JP4965153B2 - Semiconductor integrated circuit, electronic device using the same, and method for controlling semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit in which the connection between a logic circuit unit incorporated in a package and a semiconductor element electrode can be changed according to the operating state of the logic circuit unit.

  In recent years, the degree of integration of semiconductor integrated circuits has been dramatically improved by the advancement of semiconductor process miniaturization technology, and the circuit scale that can be incorporated in one semiconductor integrated circuit has increased. As a result, a system LSI in which most functions of the system are realized by a single semiconductor integrated circuit has come into practical use. Along with this, the number of connection interfaces between the system LSI and peripheral circuits has increased, and the number of external terminals of the system LSI has also increased.

  In a conventional semiconductor integrated circuit, a semiconductor element electrode incorporated in a package and an external terminal provided in the package are electrically connected to be used for communication with the outside, power supply from the outside, and the like. The connection relationship between the semiconductor element electrode and the signal line that goes out from the logic circuit portion in the package is normally fixed during operation. However, when testing a semiconductor integrated circuit, this connection relationship can be switched by an internal circuit to change a signal input / output from an external terminal.

  Patent Document 1 discloses a technique for reducing restrictions due to positions of external terminals when a packaged semiconductor integrated circuit is mounted on a substrate. In the technique disclosed in Patent Document 1, a signal line that goes out from the logic circuit portion inside the package is switched by a selection circuit and connected to a different external terminal, and a new external terminal is used to reduce restrictions due to the position of the external terminal. Is avoided.

  However, as the degree of integration of the semiconductor integrated circuit is improved, the area of the semiconductor element electrode portion for connecting the signal line extending from the logic circuit portion to the outside becomes larger than the area of the logic circuit portion in the package. This has been a major hindrance to the area reduction.

FIG. 14 is a layout diagram of a conventional packaged semiconductor integrated circuit. As shown in FIG. 14, in a conventional packaged semiconductor integrated circuit, a semiconductor element 3 is built in a package 4 having external terminals composed of pads 5 and pins 6. The semiconductor element 3 has an internal logic circuit portion 1 and peripheral semiconductor element electrodes 2. The semiconductor element electrode 2 is connected to a signal line (not shown) that exits from the logic circuit unit 1, and is wire-bonded to the pad 5 during packaging. As the semiconductor integrated circuit is highly integrated, the area occupied by the logic circuit portion 1 is reduced, but the area of the semiconductor element electrode 2 is not reduced. As a result, a useless blank portion 7 is generated in the semiconductor element 3. Further, when the logic circuit unit 1 is multi-functionalized as the semiconductor integrated circuit is highly integrated and more signal lines are required to be output from the logic circuit unit 1, the area occupied by the semiconductor element electrode 2 is increased. There is a problem that the required number of semiconductor element electrodes 2 cannot be ensured unless the number is increased.
Japanese Patent Laid-Open No. 10-313091

  Accordingly, the present invention provides a semiconductor integrated circuit capable of changing the connection between a logic circuit part and a semiconductor element electrode incorporated in a package according to the operation state of the logic circuit part, and reducing the number of necessary semiconductor element electrodes. An object is to provide a control method thereof.

  According to a first aspect of the present invention, there is provided a semiconductor integrated circuit that selects one of a logic circuit portion, a plurality of semiconductor element electrodes, and a plurality of signal lines extending from the logic circuit portion to the selected signal line. A signal selection unit electrically connected to the first semiconductor element electrode of the semiconductor element electrodes and a signal control unit for controlling the signal selection unit are provided. The signal selection unit responds to a change in the operation state of the logic circuit unit. Accordingly, the selected signal line is electrically connected to a second conductor element electrode different from the first semiconductor element electrode among the plurality of semiconductor element electrodes.

  According to this configuration, the connection between the signal line and the semiconductor element electrode that are output from the logic circuit unit to the outside can be switched in accordance with a change in the operation state of the logic circuit unit, that is, a change in processing content. As a result, one semiconductor element electrode can be shared by a plurality of signal lines, and the number of necessary semiconductor element electrodes can be reduced. As a further effect, the area of the LSI incorporating this semiconductor integrated circuit can be reduced.

  In the semiconductor integrated circuit according to the second aspect of the invention, the signal control unit connects the electrical connection between the plurality of signal lines and the plurality of semiconductor element electrodes performed by the signal selection unit in accordance with a change in the operation state of the logic circuit unit. Information is generated, and connection information is notified to the signal selection unit and simultaneously to an external semiconductor integrated circuit.

  According to this configuration, an external semiconductor integrated circuit can be accurately notified to which semiconductor element electrode a signal line extending from the logic circuit unit to the outside is connected.

  In the semiconductor integrated circuit according to the third aspect of the invention, the signal selection unit reserves a new electrical connection based on the connection information after receiving the connection information from the signal control unit until the predetermined reservation period ends.

  In the semiconductor integrated circuit according to the fourth aspect of the invention, the signal selection unit sets the semiconductor element electrode to high impedance during a predetermined retention period.

  According to these configurations, a retention period is set at the time of switching connection between the signal line and the semiconductor element electrode that are output from the logic circuit unit, and during this period, the semiconductor element electrode is set to high impedance, thereby accompanying the switching connection. Potential obstacles can be avoided.

  In the semiconductor integrated circuit according to the fifth aspect of the invention, the signal selection unit is a selector that performs a new electrical connection between one of the plurality of signal lines and one of the plurality of semiconductor element electrodes based on the connection information. And a state change detection unit that detects a change in the operation state of the logic circuit unit based on the connection information, and a new electrical connection made by the selector is reserved during a predetermined reservation period after the change in the operation state is detected. A state transition protection unit and a counter unit that measures a predetermined retention period. The state transition protection unit is a new electrical connection made by the selector after the counter unit finishes measuring the predetermined retention period. Cancel the reservation.

  According to this configuration, a certain retention period is set at the time of switching connection between the signal line and the semiconductor element electrode that are output from the logic circuit unit, and during this period, the connection between the signal line and the semiconductor element electrode can be retained. This reservation period can be measured by the counter unit.

  In the semiconductor integrated circuit according to the sixth aspect of the invention, the counter unit ends the measurement of the predetermined reservation period based on a reference value preset in the inside.

  According to this configuration, the reference value preset in the logic circuit unit is set to a time sufficient for the related external semiconductor integrated circuit to complete the setting associated with the new connection information. The semiconductor integrated circuit can reliably switch the connection between the signal line and the semiconductor element electrode.

  In the semiconductor integrated circuit according to the seventh aspect of the present invention, the signal selection unit further includes a confirmation response receiving unit that receives a confirmation response signal for the connection information from the external semiconductor integrated circuit notified of the connection information by the signal control unit. The counter unit ends the measurement of the predetermined reservation period based on the confirmation response signal received by the confirmation response receiving unit.

  According to this configuration, after receiving the confirmation response signal indicating that the setting according to the new connection information is completed from the related external semiconductor integrated circuit, the semiconductor integrated circuit connects the signal line and the semiconductor element electrode. Can be switched reliably.

  In the semiconductor integrated circuit according to the eighth aspect of the invention, the state transition protection unit sets the semiconductor element electrode to high impedance during a predetermined retention period.

  According to this configuration, it is possible to safely execute a new connection between the signal line exiting from the logic circuit unit and the semiconductor element electrode.

  An electronic device according to a ninth invention includes a plurality of semiconductor integrated circuits connected to each other and a substrate on which the plurality of semiconductor integrated circuits are mounted, and at least one of the plurality of semiconductor integrated circuits is a logic circuit Selected from the signal line and the operation state of the logic circuit unit. , A signal selection unit that performs electrical connection with the first semiconductor element electrode among the plurality of semiconductor element electrodes, and controls the signal selection unit to generate connection information regarding the electrical connection performed by the signal selection unit, A signal control unit that notifies information to other semiconductor integrated circuits among the plurality of semiconductor integrated circuits, and the signal selection unit selects a plurality of selected signal lines according to a change in the operation state of the logic circuit unit. Of the semiconductor element electrodes of the first semiconductor element And connecting different second semiconductor element electrodes and electrically.

  According to this configuration, the electronic device can switch the connection between the signal line extending from the logic circuit unit to the semiconductor element electrode in accordance with a change in the operation state of the logic circuit unit, that is, a change in processing content. Since an LSI incorporating a semiconductor integrated circuit that can be used is utilized, a highly integrated and smaller electronic device can be realized.

  A control method according to a tenth invention is a method for controlling a semiconductor integrated circuit in a semiconductor integrated circuit comprising a logic circuit portion and a plurality of semiconductor element electrodes, wherein a plurality of signal lines extending from the logic circuit portion to the outside are controlled. A selection step of selecting one of the first, a first connection step of electrically connecting the selected signal line to a first semiconductor element electrode of the plurality of semiconductor element electrodes, and an operation of the logic circuit unit A second connection step of electrically connecting the selected signal line to a second semiconductor element electrode different from the first semiconductor element electrode of the plurality of semiconductor element electrodes in response to a change in state; .

  According to this method, the connection between the signal line and the semiconductor element electrode that are output from the logic circuit unit to the outside can be switched in accordance with a change in the operation state of the logic circuit unit, that is, a change in processing content. As a result, a semiconductor integrated circuit can be realized in which one semiconductor element electrode is shared by a plurality of signal lines and the number of necessary semiconductor element electrodes is reduced.

  In the control method according to the eleventh aspect of the present invention, a generation step of generating connection information relating to the electrical connection performed in the first connection step and the electrical connection performed in the second connection step, and the generated connection information And a control step for controlling the electrical connection performed in the first connection step and the electrical connection performed in the second connection step, and the generated connection information is notified to the external semiconductor integrated circuit. A notification step.

  According to this method, it is possible to control a new connection between the signal line and the semiconductor element electrode that are output from the logic circuit unit based on the connection information, and at the same time, the external semiconductor circuit can perform signal transmission / reception based on the connection information. Settings can be made.

  In the control method according to the twelfth invention, the second connection step includes a reservation step for retaining the electrical connection between the selected signal line and the second semiconductor element electrode until the predetermined retention period ends. Including.

  In the control method according to the thirteenth invention, the second connection step includes a holding step of holding the second semiconductor element electrode at a high impedance during a predetermined holding period.

  According to these methods, a predetermined retention period is provided when a new connection between the signal line that goes out from the logic circuit portion and the semiconductor element electrode is performed, and during this retention period, the semiconductor element electrode is held high. By setting the impedance, a new electrical connection in the semiconductor integrated circuit can be executed reliably and safely.

  According to the present invention, the connection between the logic circuit part and the semiconductor element electrode incorporated in the package can be changed according to the operation state of the logic circuit part, and the number of necessary semiconductor element electrodes can be reduced. And a control method thereof.

  Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram of a semiconductor integrated circuit according to the first embodiment of the present invention. The semiconductor integrated circuit 100 of this embodiment is built in the package 10. External terminals of the package 10 are not shown.

  The semiconductor integrated circuit 100 of the present embodiment includes a logic circuit unit 20, a signal control unit 30, a first signal selection unit 41, a second signal selection unit 42, and a signal selection unit 40 including a third signal selection unit 43, a first A device electrode 51, a second device electrode 52, a third device electrode 53, and a fourth device electrode 54 are provided.

  The first signal selection unit 41 selects one of the signal lines D 1, D 2, D 3, and D 4 that are output from the logic circuit unit 20 to the outside, and is connected to the signal line D 5 that is connected to the first element electrode 51. To do.

  The second signal selection unit 42 selects one of the signal lines D4, D6, D7, and D8 that exits from the logic circuit unit 20, and is connected to the signal line D9 that is connected to the second element electrode 52. To do.

  The third signal selection unit 43 selects one of the signal lines D10, D11, D12, and D13 that exits from the logic circuit unit 20 and connects to the signal line D14 that is connected to the third element electrode 53. To do.

  When the processing content of the logic circuit unit 20 is changed, the change in the operation state is notified from the logic circuit unit 20 to the signal control unit 30 via the control signal line C1. The signal control unit 30 detects a change in the operation state of the logic circuit unit 20 and generates connection information. The signal control unit 30 notifies the generated connection information to the signal selection unit 40 through the control signal line C2, and at the same time, is connected to the fourth element electrode 54 through the control signal line C3. Notify LSI. This connection information indicates which of the signal lines D1 to D4, D6 to D8, and D10 to D13 is connected to each of the first element electrode 51, the second element electrode 52, and the third element electrode 53. .

  The first signal selection unit 41, the second signal selection unit 42, and the third signal selection unit 43. Each electrical connection is made based on the received connection information.

  An external LSI having a connection relationship with the semiconductor integrated circuit 100 performs settings for transmitting and receiving signals to and from the semiconductor integrated circuit 100 based on the received connection information.

  In the semiconductor integrated circuit 100 of this embodiment, the signal line D4 that goes out from the logic circuit unit 20 is connected to the first signal selection unit 41 and the second signal selection unit 42, and depends on the operation state of the logic circuit unit 20. Thus, the first element electrode 51 or the second element electrode 52 can be connected. As described above, one of the features of the present invention is a configuration in which a signal line extending from the logic circuit unit 20 to the outside can be connected to the plurality of element electrodes 50. The description and effect of such a configuration will be described in more detail in Embodiment 4 of the present invention.

  For example, when the logic circuit unit 20 is included in a system LSI for a mobile phone, the change in the operation state of the logic circuit unit 20 is a video shooting mode using a camera, a normal voice call mode, a television using a camera and a microphone. This means a change in an external device used by the logic circuit unit 20 or a change in signal processing content processed by the logic circuit unit 20 due to mode switching such as a telephone mode.

  FIG. 2 is a block diagram of the signal selection unit according to Embodiment 1 of the present invention. The signal selection unit 60 and the device electrode 50 of this embodiment illustrate the first signal selection unit 41 and the first device electrode 51 corresponding thereto shown in FIG. However, the signal selection unit 60 can be equally applied to the second signal selection unit 42 and the third signal selection unit 43.

  The signal selection unit 60 of this embodiment includes a selector 61, a state transition protection unit 62, a state change detection unit 63, and a counter unit 64.

  Signal lines D <b> 1 to D <b> 4 exiting from the logic circuit unit 20 of FIG. 1 are connected to the selector 61. A control signal line C 2 from the signal control unit 30 is connected to the selector 61 and the state change detection unit 63.

  FIG. 7 is a timing diagram of the signal selection unit in the first embodiment of the present invention. The horizontal axis in FIG. 7 represents time.

  The operation of the signal selection unit 60 of this embodiment will be described with reference to FIGS.

  At time t1, the CPU included in the logic circuit unit 20 informs the signal control unit 30 through the control signal line C1 that the operation state in the logic circuit unit 20 has changed from the operation state A to the operation state B. Notice. At this time, the selector 61 selects the signal of the operation state A and outputs it to the state transition protection unit 62. The state transition protection unit 62 outputs an operation state A signal to the element electrode 50.

  At time t2, the signal control unit 30 generates new connection information and sends it to the selector 61 and the state change detection unit 63 via the control signal line C2. The state change detection unit 63 detects that the operation state in the logic circuit unit 20 has changed, and notifies the state transition protection unit 62 and the counter unit 64 that the operation state has changed.

  At time t3, the state transition protection unit 62 receives the signal of the operation state A output to the device electrode 50, and sets the device electrode 50 to a high impedance state. At the same time, the counter unit 64 starts measuring the reservation period.

  At time t 4, the selector 61 switches the connection from the operation state A signal to the operation state B signal based on the connection information sent from the signal control unit 30, and outputs the connection to the state transition protection unit 62. However, the device electrode 50 is still in a high impedance state.

  At time t5, the counter unit 64 measures a predetermined time and notifies the state change detection unit 63 that the reservation period has ended. Upon receiving this notification, the state transition protection unit 62 releases the element electrode 50 from the high impedance state, and outputs an operation state B signal to the element electrode 50.

  As described above, according to the semiconductor integrated circuit 100 of the present embodiment, one of a plurality of signal lines extending from the logic circuit unit 20 to the outside is selected in accordance with the change in the operation state of the logic circuit unit 20 and is dealt with. It can be connected to the device electrode 50. Further, in this connection switching, an external LSI having a connection relationship with the semiconductor integrated circuit 100 secures a time margin for setting to properly receive a signal from the semiconductor integrated circuit 100 by the retention time. . Further, during this period, the element electrode 50 for switching the connection is set to a high impedance, and the safe connection switching is performed to prevent the occurrence of a potential failure.

  In the semiconductor integrated circuit 100 shown in FIG. 1, the number of element electrodes 50 that transmit and receive signals to and from the outside is four. However, this number is an example, and the function of the semiconductor integrated circuit 100 is required. As many device electrodes 50 and signal selectors 40 as possible can be provided.

(Embodiment 2)
FIG. 3 is a block diagram of a signal selection unit in Embodiment 2 of the present invention. In FIG. 3, the same components as those of FIG.

  The signal selection unit 60 of this embodiment further includes an acknowledgment reception unit 65 with respect to the signal selection unit 60 shown in FIG.

  The operation of the semiconductor integrated circuit 100 when the signal selection unit 60 of the present embodiment is used as the first signal selection unit 41 shown in FIG. 1 is the semiconductor integration according to the first embodiment of the present invention except for the following points. The operation is the same as that of the circuit 100.

  That is, when the processing content of the logic circuit unit 20 is changed and the operation state changes from the operation state A to the operation state B, the signal control unit 30 generates new connection information at time t2 in FIG. Notification is made to an external LSI connected to the circuit 100. After the connection information is notified, the external LSI changes the setting, and then issues an acknowledgment signal for the connection information to the semiconductor integrated circuit 100. The confirmation response receiving unit 65 receives this confirmation response signal via the control signal line C4 and notifies the counter unit 64 of the confirmation response signal. The counter unit 64 ends the measurement of the reservation period started from time t3 in FIG. 7 (corresponding to time t5).

  As described above, when the signal selection unit 60 of this embodiment is used, the reservation time measured by the selector 61 is terminated by receiving an acknowledgment signal for connection information from an external LSI connected to the semiconductor integrated circuit 100. be able to. Of course, the element electrode 50 is kept in a high impedance state during the retention period, and during that time, the selector 61 switches from the signal in the operation state A to the signal in the operation state B. As a result, safe connection switching is realized, and the occurrence of a potential failure can be prevented.

  The semiconductor integrated circuit 100 according to the present embodiment can switch the connection of the signal selection unit 40 in a shorter retention period than the semiconductor integrated circuit 100 according to the first embodiment of the present invention.

(Embodiment 3)
FIG. 4 is a block diagram of a signal control unit and a signal selection unit in Embodiment 3 of the present invention. 4, the same components as those in FIG. 2 are denoted by the same reference numerals, and the description thereof is omitted.

  4 includes a selector 61 and a state transition protection unit 62, and the signal control unit 30 includes a state change detection unit 31, a counter unit 32, and a selection instruction unit 33.

  The operation of the semiconductor integrated circuit 100 when the signal control unit 30 and the signal selection unit 60 of this embodiment are used as the signal control unit 30 and the first signal selection unit 41 shown in FIG. 1 will be described below.

  The fact that the processing content of the logic circuit unit 20 has been changed from the CPU included in the logic circuit unit 20 and the operation state has changed from the operation state A to the operation state B is sent to the signal control unit 30 via the control signal line C1. Be notified.

  Upon receiving the notification of the change in the operating state, the selection instruction unit 33 generates new connection information and notifies the selector 61 of the new connection information. At the same time, the generated new connection information is notified to an external LSI connected to the semiconductor integrated circuit 100 via the control signal line C 3 and the fourth element electrode 54.

  In response to the notification of the change in the operation state, the state change detection unit 31 detects that the operation state of the logic circuit unit 20 has changed, and informs the selection instruction unit 33 and the counter unit 32 that the reservation period starts. Notice.

  Upon receiving the start of the reservation period, the selection instruction unit 33 instructs the state transition protection unit 62 to set its output to high impedance. The state transition protection unit 62 sets the device electrode 50 to high impedance. At this time, the output to the element electrode 50 is switched from the signal of the operation state A to the high impedance.

  In response to the start of the reservation period, the counter unit 32 starts measuring the reservation period.

  The selector 61 confirms that the reservation period has started, switches the signal of the operation state A to the signal of the operation state B, and outputs the signal of the operation state B to the state transition protection unit 62.

  After measuring the predetermined time, the counter unit 32 notifies the state change detection unit 31 of the end of the reservation period. The state change detection unit 31 notifies the selection instruction unit 33 of the end of the reservation period.

  Upon receiving the notification of the end of the reservation period, the selection instruction unit 33 instructs the state transition protection unit 62 to release the output from the high impedance state. At this time, the output to the element electrode 50 is switched from the high impedance state to the signal of the operation state B.

  As described above, according to the semiconductor integrated circuit 100 of the present embodiment, one of a plurality of signal lines extending from the logic circuit unit 20 to the outside is selected in accordance with the change in the operation state of the logic circuit unit 20 and is dealt with. It can be connected to the device electrode 50. Further, in this connection switching, an external LSI having a connection relationship with the semiconductor integrated circuit 100 secures a time margin for setting to properly receive a signal from the semiconductor integrated circuit 100 by the retention time. . Further, during this period, the element electrode 50 for switching the connection is set to a high impedance so that the connection can be safely switched and the occurrence of a potential failure can be prevented.

  In the signal control unit 30 of this embodiment, the reservation period is measured with reference to a reference value preset in the counter unit 32. However, like the signal selection unit 60 of the second embodiment of the present invention shown in FIG. 3, an acknowledgment receiving unit 65 is added to the signal control unit 30 of FIG. 4 to connect to the semiconductor integrated circuit 100 of the present embodiment. It is also possible to receive an acknowledgment signal for new connection information from a related external LSI and determine the end of the reservation period.

(Embodiment 4)
FIG. 5 is a block diagram of an electronic device according to Embodiment 4 of the present invention. The electronic device 200 of this embodiment includes a first semiconductor integrated circuit 101, a second semiconductor integrated circuit 102, and a third semiconductor integrated circuit 103.

  The first semiconductor integrated circuit 101 is a semiconductor integrated circuit having the same function as that of the semiconductor integrated circuit 100 according to the first embodiment of the present invention shown in FIG. 1, and has ten external terminals T0 to T9. . These external terminals T0 to T9 are connected to the element electrodes of the first semiconductor integrated circuit 101. Details thereof will be described later.

  The second semiconductor integrated circuit 102 and the third semiconductor integrated circuit 103 are semiconductor integrated circuits corresponding to external LSIs connected to the first semiconductor integrated circuit 101, and each have seven external terminals T0 to T6. ing. The second semiconductor integrated circuit 102 and the third semiconductor integrated circuit 103 receive connection information in addition to the same functions as those of the semiconductor integrated circuit 100 according to the first embodiment of the present invention shown in FIG. It is necessary to set an acknowledgment transmission unit 66 for transmitting an acknowledgment signal after setting.

  The interconnection relationship of the electronic device 200 of this embodiment is as follows.

  That is, the external terminals T0 to T5 of the first semiconductor integrated circuit 101 are connected to the external terminals T0 to T5 of the second semiconductor integrated circuit 102, respectively, and the external terminals T3 to T8 of the first semiconductor integrated circuit 101 are connected to the third terminals. The semiconductor integrated circuit 103 is connected to the external terminals T0 to T5, respectively. The connection between these external terminals is a path for transmitting and receiving signals (data). Here, it should be noted that the external terminals T <b> 3 to T <b> 5 of the first semiconductor integrated circuit 101 are connected to the second semiconductor integrated circuit 102 and the third semiconductor integrated circuit 103.

  The external terminal T 9 of the first semiconductor integrated circuit 101 is connected to the external terminal T 6 of the second semiconductor integrated circuit 102 and the external terminal T 6 of the third semiconductor integrated circuit 103. The connection between these external terminals is a path for transmitting and receiving control signals such as connection information.

  Next, transmission / reception of signals in the electronic apparatus 200 of this embodiment will be described.

  FIG. 8 is a signal layout diagram of the first semiconductor integrated circuit according to the fourth embodiment of the present invention. That is, FIG. 8 shows the output signal arrangement of the external terminals accompanying the change of the operation state in the logic circuit unit 20 of the first semiconductor integrated circuit 101.

  FIG. 9 is a signal layout diagram of the second semiconductor integrated circuit 102 in the fourth embodiment of the present invention. That is, FIG. 9 shows an input signal arrangement of the external terminals of the second semiconductor integrated circuit 102 in accordance with a change in the operation state in the logic circuit unit 20 of the first semiconductor integrated circuit 101.

  FIG. 10 is a signal layout diagram of the third semiconductor integrated circuit 103 according to the fourth embodiment of the present invention. That is, FIG. 10 shows an input signal arrangement of the external terminals of the third semiconductor integrated circuit 103 in accordance with a change in the operation state in the logic circuit unit 20 of the first semiconductor integrated circuit 101.

  When the logic circuit unit 20 in the first semiconductor integrated circuit 101 changes to the operation state 1, the signal control unit 30 of the first semiconductor integrated circuit 101 receives the signal group A (A0 to A5) and the external terminals T0 to T8. Connection information indicating that each of the signal groups B (B0 to B2) is output is generated and notified to the second semiconductor integrated circuit 102 and the third semiconductor integrated circuit 103. At the same time, the first semiconductor integrated circuit 101 enters a reservation period. The connection information is notified via the external terminal T9 of the first semiconductor integrated circuit 101, the external terminal T6 of the second semiconductor integrated circuit 102, and the external terminal T6 of the third semiconductor integrated circuit 103.

  The signal control unit 30 of the second semiconductor integrated circuit 102 receives this connection information and sets to receive the signal group A (A0 to A5) from the external terminals T0 to T5, and the confirmation response transmission unit 66 confirms the confirmation. A response signal is sent to the first semiconductor integrated circuit 101.

  Similarly, the signal control unit 30 of the third semiconductor integrated circuit 103 receives this connection information, sets to receive the signal group B (B0 to B2) from the external terminals T3 to T5, and confirms the response transmission unit 66. Sends an acknowledgment signal to the first semiconductor integrated circuit 101.

  In the first semiconductor integrated circuit 101, the confirmation response receiver 65 receives the confirmation response signals from the second semiconductor integrated circuit 102 and the third semiconductor integrated circuit 103, the reservation period ends, and the external terminals T0 to T8 are connected. , Signal group A (A0 to A5) and signal group B (B0 to B2) are output, respectively. As a result, in the operation state 1, the signal group A (A0 to A5) is sent from the first semiconductor integrated circuit 101 to the second semiconductor integrated circuit 102, and the signal group B (B0 to B2) is sent from the first semiconductor integrated circuit 101. It is sent to the third semiconductor integrated circuit 103.

  Next, when the logic circuit unit 20 in the first semiconductor integrated circuit 101 changes to the operation state 2, the signal control unit 30 of the first semiconductor integrated circuit 101 receives a signal group C (C0 to C0) at its external terminals T0 to T8. C2), connection information indicating that the signal group D (D0 to D2) and the signal group B (B0 to B2) are output is generated and notified to the second semiconductor integrated circuit 102 and the third semiconductor integrated circuit 103. At the same time, the first semiconductor integrated circuit 101 enters a reservation period.

  The signal control unit 30 of the second semiconductor integrated circuit 102 receives this connection information, and the signal group C (C0 to C2) from the external terminals T0 to T2, and the signal group D (D0 to D2) from the external terminals T3 to T5. The confirmation response transmission unit 66 transmits the confirmation response signal to the first semiconductor integrated circuit 101.

  Similarly, the signal control unit 30 of the third semiconductor integrated circuit 103 receives this connection information, transmits the signal group D (D0 to D2) from the external terminals T0 to T2, and the signal group B (from the external terminals T3 to T5). B0 to B2) are set to be received, and the acknowledgment transmission unit 66 sends an acknowledgment signal to the first semiconductor integrated circuit 101.

  In the first semiconductor integrated circuit 101, the confirmation response receiver 65 receives the confirmation response signals from the second semiconductor integrated circuit 102 and the third semiconductor integrated circuit 103, the reservation period ends, and the external terminals T0 to T8 are connected. , Signal group C (C0 to C2), signal group D (D0 to D2), and signal group B (B0 to B2) are output. As a result, in the operation state 2, the signal group C (C0 to C2) and the signal group D (D0 to D2) are sent from the first semiconductor integrated circuit 101 to the second semiconductor integrated circuit 102, and the signal group D (D0 to D2). ), The signal group B (B0 to B2) is sent from the first semiconductor integrated circuit 101 to the third semiconductor integrated circuit 103.

  Further, when the logic circuit unit 20 in the first semiconductor integrated circuit 101 changes to the operation state 3, the signal control unit 30 of the first semiconductor integrated circuit 101 receives a signal group A (A0 to A5) at its external terminals T0 to T8. ) And signal group D (D0 to D2) are generated, and connection information is generated and notified to the second semiconductor integrated circuit 102 and the third semiconductor integrated circuit 103. At the same time, the first semiconductor integrated circuit 101 enters a reservation period. It should be noted that when the operating state 2 changes to the operating state 3, the external terminals to which the signal group D (D0 to D2) is output are changed from the external terminals T3 to T5 to the external terminals T6 to T8. It is that you are.

  The signal control unit 30 of the second semiconductor integrated circuit 102 receives this connection information and sets to receive the signal group A (A0 to A5) from the external terminals T0 to T5, and the confirmation response transmission unit 66 confirms the confirmation. A response signal is sent to the first semiconductor integrated circuit 101.

  Similarly, the signal control unit 30 of the third semiconductor integrated circuit 103 receives this connection information, sets to receive the signal group D (D0 to D2) from the external terminals T3 to T5, and confirms the response transmission unit 66. Sends an acknowledgment signal to the first semiconductor integrated circuit 101.

  In the first semiconductor integrated circuit 101, the confirmation response receiver 65 receives the confirmation response signals from the second semiconductor integrated circuit 102 and the third semiconductor integrated circuit 103, the reservation period ends, and the external terminals T0 to T8 are connected. , Signal group A (A0 to A5) and signal group D (D0 to D2) are output, respectively. As a result, in the operation state 3, the signal group A (A0 to A5) is sent from the first semiconductor integrated circuit 101 to the second semiconductor integrated circuit 102, and the signal group D (D0 to D2) is sent from the first semiconductor integrated circuit 101. It is sent to the third semiconductor integrated circuit 103.

  It should be noted in the operation of the electronic device 200 of the present embodiment described above that the external terminals to which the signal group D (D0 to D2) is output from the external terminals T3 to T5 when the operation state 2 changes to the operation state 3. That is, the external terminals T6 to T8 are changed. As a result, the number of external terminals required in the first semiconductor integrated circuit 101 of this embodiment can be reduced to nine terminals, that is, the external terminals T0 to T8.

  FIG. 11 is a signal layout diagram of a semiconductor integrated circuit according to the prior art. The semiconductor integrated circuit according to the prior art does not have a function of connecting one of a plurality of signal lines coming out from the logic circuit unit 20 to the plurality of element electrodes 50 (and thus a plurality of external terminals). As a result, in order to output the signal group A (A0 to A5), the signal group B (B0 to B2), the signal group C (C0 to C2), and the signal group D (D0 to D2), the first semiconductor integrated circuit As shown in FIG. 11, the 101 needs to include 12 signal (data) transmission / reception external terminals T0 to TB. Here, it is assumed that the signal group A (A0 to A5) and the signal group C (C0 to C2) are not output at the same time and can share an external terminal.

  From the above description, it is apparent that the semiconductor integrated circuit 100 of the present invention can reduce the number of external terminals required.

  FIG. 6 is an explanatory diagram of the signal selection unit of the first semiconductor integrated circuit according to the fourth embodiment of the present invention. FIG. 6 shows the connection between the signal line and the signal selection unit 40 that are output from the logic circuit unit 20 to realize transmission and reception of signals in the electronic device 200 of FIG.

As shown in FIG. 6, the logic circuit unit 20 outputs a signal group A (A0 to A5), a signal group B (B0 to B2), a signal group C (C0 to C2), and a signal group D (D0 to D2). In order to do so, it has 15 signal lines A0 to D2 that go outside. (Signal lines for sending connection information and other control signals are provided separately and excluded from this description.)
The signal selection unit 40 has nine selection units S0 to S8, and each output terminal is connected to the element electrodes E0 to E8, and further connected to the external terminals T0 to T8.

  The selection unit S0 selects the signal line A0 or C0 of the logic circuit unit 20 and outputs it to the element electrode E0. The selection unit S1 selects the signal line A1 or C1 of the logic circuit unit 20 and outputs it to the element electrode E1. The same applies hereinafter.

  However, the signal line D0 of the logic circuit unit 20 is connected to the selection unit S3 and the selection unit S6, the signal line D1 is connected to the selection unit S4 and the selection unit S7, and the signal line D2 is connected to the selection unit S5 and the selection unit. Connected to S8.

  With this configuration, as described above, when the logic circuit unit 20 changes from the operation state 2 to the operation state 3, the external terminals to which the signal group D (D0 to D2) is output are connected from the external terminals T3 to T5 to the external terminals. It is possible to change to T6 to T8.

(Embodiment 5)
FIG. 12 is a block diagram of a semiconductor integrated circuit according to the fifth embodiment of the present invention. In FIG. 12, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

  A semiconductor integrated circuit 100 shown in FIG. 12 includes a logic circuit unit 20, a signal control unit 30, a signal selection unit 40, a ROM 70, and an element electrode 50. The logic circuit unit 20 includes various functional circuits (not shown). The CPU 21 controls the entire semiconductor integrated circuit 100. In FIG. 12, the device electrode 50 represents a plurality of device electrodes, and the signal selection unit 40 represents a plurality of signal selection units.

  The ROM 70 stores a program for controlling the semiconductor integrated circuit 100, and the CPU 21 reads and executes this program.

  FIG. 13 is a flowchart of the semiconductor integrated circuit according to the fifth embodiment of the present invention. A program for executing this flowchart is stored in the ROM 70.

  The operation of the semiconductor integrated circuit 100 according to the present embodiment when the signal selection unit 60 according to the first embodiment of the present invention shown in FIG. 2 is used as the signal selection unit 40 will be described with reference to the flowchart of FIG.

  In FIG. 13, the control program starts in step S0.

  In step S1, the signal control unit 30 determines whether the operation state of the logic circuit unit 20 has changed. If the determination result is “NO” (a change in the operating state is not detected), step S1 is repeated. If the determination result is “YES” (a change in the operating state is detected), the control proceeds to step S2.

  In step S <b> 2, the signal control unit 30 generates connection information related to the connection between the signal line that goes out of the logic circuit unit 20 and the element electrode 50, and notifies the signal selection unit 40 of the connection information. At the same time, the signal control unit 30 notifies the connection information to an external LSI connected to the semiconductor integrated circuit 100.

  In step S3, the state change detection unit 63 in FIG. 2 receives the connection information and instructs the state transition protection unit 62 to set the element electrode 50 to high impedance.

  In step S4, the counter unit 64 starts measuring the reservation period. While the counter unit 64 is measuring the reservation period, the selector 61 selects a signal line of the logic circuit unit 20 according to the connection information and connects to the state transition protection unit 62. The external LSI is set to receive a signal (data) according to the connection information.

  In step S5, the counter unit 64 determines whether a predetermined reservation period has been measured. When the determination result is “YES” (measurement of a predetermined reservation period), the counter unit 64 notifies the state change detection unit 63 that the predetermined reservation period has ended. Then, the control moves to step S6.

  In step S <b> 6, the state change detection unit 63 receives the notification of the end of the retention period, instructs the state transition protection unit 62 to release the element electrode 50 from the high impedance setting, and the selector 61 is connected to the element electrode 50. Send the signal of the already selected signal line. In this way, a new signal is transmitted from the element electrode 50 to the external LSI according to the change in the operation state of the logic circuit unit 20.

  In step S <b> 7, a series of processes accompanying the change in the operation state of the logic circuit unit 20 is completed. Thereafter, the control may return to step S1 again.

  In the above-described flowchart, the reservation period is measured using the reference value that the counter unit 64 has internally. However, when the confirmation response signal for the connection information is received from the external LSI, the reservation period ends. Also good. When there are many external LSIs connected to the semiconductor integrated circuit 100, it is generally possible to set the retention period shorter by receiving an acknowledgment signal for the connection information from the external LSI and ending the reservation period. .

  In each of the above-described embodiments of the present invention, the operation is described assuming that a signal (data) is transmitted from the semiconductor integrated circuit 100 to an external LSI connected to the semiconductor integrated circuit 100. did. However, the signal can be transmitted in both directions.

  For example, in the electronic device 200 according to the fourth embodiment of the present invention shown in FIG. 5, when the first semiconductor integrated circuit 101 is in the operation state 1, as shown in FIGS. A5) is sent from the first semiconductor integrated circuit 101 to the second semiconductor integrated circuit 102 via the external terminals T0 to T5 of the first semiconductor integrated circuit 101 and the external terminals T0 to T5 of the second semiconductor integrated circuit 102. The signal group B (B0 to B2) is transmitted from the first semiconductor integrated circuit 101 via the external terminals T6 to T8 of the first semiconductor integrated circuit 101 and the external terminals T3 to T5 of the third semiconductor integrated circuit 103. It is sent to the third semiconductor integrated circuit 103.

  At the same time, in this connection state, for example, from the second semiconductor integrated circuit 102, the external terminals T0 to T5 of the second semiconductor integrated circuit 102, the external terminals T0 to T5 of the first semiconductor integrated circuit 101, and the first semiconductor integrated circuit It is also possible to send signals to the signal lines A0 to A5 of the first semiconductor integrated circuit 101 via the selection units S0 to S4 of 101.

  In other words, in any of the embodiments of the present invention, the semiconductor integrated circuit 100 and an external LSI connected to the semiconductor integrated circuit 100 can bidirectionally transmit signals as necessary. In addition, in this case, the number of element electrodes required for the semiconductor integrated circuit 100 can be reduced as compared with the conventional technique.

  As described above, the gist of the present invention is that the connection between the logic circuit part built in the package and the semiconductor element electrode can be changed according to the operation state of the logic circuit part, and the number of necessary semiconductor element electrodes Therefore, various modifications are possible without departing from the spirit of the present invention.

  The semiconductor integrated circuit according to the present invention can be used in a semiconductor device having a plurality of functions such as a mobile phone and requiring high integration and miniaturization and its application fields.

1 is a block diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. The block diagram of the signal selection part in Embodiment 1 of this invention The block diagram of the signal selection part in Embodiment 2 of this invention The block diagram of the signal control part and signal selection part in Embodiment 3 of this invention Block diagram of an electronic device according to Embodiment 4 of the present invention Explanatory drawing of the signal selection part of the 1st semiconductor integrated circuit in Embodiment 4 of this invention Timing diagram of signal selection section in Embodiment 1 of the present invention Signal arrangement diagram of first semiconductor integrated circuit according to the fourth embodiment of the present invention Signal arrangement diagram of second semiconductor integrated circuit according to the fourth embodiment of the present invention Signal arrangement diagram of third semiconductor integrated circuit in the fourth embodiment of the present invention Signal arrangement diagram of conventional semiconductor integrated circuit Block diagram of a semiconductor integrated circuit according to a fifth embodiment of the present invention Flowchart of Semiconductor Integrated Circuit in Embodiment 5 of the Present Invention Layout of conventional packaged semiconductor integrated circuit

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 20 Logic circuit part 2 Semiconductor element electrode 3 Semiconductor element 4, 10 Package 5 Pad 6 Pin 21 CPU
22 Signal line terminal 30 Signal control unit 31 State change detection unit 32 Counter unit 33 Selection instruction unit 40, 41, 42, 43, 60 Signal selection unit 44 Selection unit 50, 51, 52, 53, 54, 55 Element electrode 61 Selector 62 state transition protection unit 63 state change detection unit 64 counter unit 65 confirmation response reception unit 66 confirmation response transmission unit 70 ROM
81, 82, 83 External terminals 100, 101, 102, 103 Semiconductor integrated circuit 200 Electronic device

Claims (17)

A logic circuit section;
A plurality of semiconductor element electrodes;
A signal selection unit that selects one of a plurality of signal lines that exits from the logic circuit unit and electrically connects the selected signal line to a first semiconductor element electrode of the plurality of semiconductor element electrodes. When,
A signal control unit for controlling the signal selection unit,
The signal selection unit is configured in accordance with a change in the operation state of the logic circuit portion, the selected signal line, the first semiconductor element electrode different from the second half conductor elements of said plurality of semiconductor element electrodes A semiconductor integrated circuit that is electrically connected to an electrode . The signal control unit generates connection information regarding electrical connection between the plurality of signal lines and the plurality of semiconductor element electrodes performed by the signal selection unit according to a change in an operation state of the logic circuit unit, The semiconductor integrated circuit according to claim 1, wherein connection information is notified to an external semiconductor integrated circuit at the same time as the signal selection unit is notified. 3. The semiconductor integrated circuit according to claim 2, wherein, after receiving the connection information from the signal control unit, the signal selection unit reserves a new electrical connection based on the connection information until a predetermined reservation period ends. circuit. The semiconductor integrated circuit according to claim 3, wherein the signal selection unit sets the second semiconductor element electrode to a high impedance during the predetermined retention period. The signal selector is
A selector for performing a new electrical connection between one of the plurality of signal lines and one of the plurality of semiconductor element electrodes based on the connection information;
Based on the connection information, a state change detection unit that detects a change in the operation state of the logic circuit unit;
A state transition protection unit that reserves a new electrical connection made by the selector in a predetermined retention period after detecting a change in the operating state;
A counter unit for measuring the predetermined retention period;
3. The semiconductor integrated circuit according to claim 2, wherein the state transition protection unit releases the reservation of a new electrical connection performed by the selector after the counter unit finishes measuring the predetermined reservation period. The semiconductor integrated circuit according to claim 5, wherein the counter unit ends the measurement of the predetermined retention period based on a reference value preset in the inside. The signal selection unit further includes a confirmation response reception unit that receives a confirmation response signal for the connection information from an external semiconductor integrated circuit notified of the connection information by the signal control unit,
6. The semiconductor integrated circuit according to claim 5, wherein the counter unit ends the measurement of the predetermined reservation period based on the confirmation response signal received by the confirmation response receiving unit. The semiconductor integrated circuit according to claim 5, wherein the state transition protection unit sets the second semiconductor element electrode to a high impedance during the predetermined retention period. A plurality of semiconductor integrated circuits connected to each other;
A board on which the plurality of semiconductor integrated circuits are mounted,
At least one of the plurality of semiconductor integrated circuits is:
A logic circuit section;
A plurality of semiconductor element electrodes;
Selecting one of a plurality of signal lines coming out of the logic circuit unit, and selecting the selected signal line and the plurality of semiconductor element electrodes selected in accordance with a change in an operation state of the logic circuit unit; A signal selection unit for making electrical connection with the first semiconductor element electrode
A signal control unit that controls the signal selection unit, generates connection information related to the electrical connection performed by the signal selection unit, and notifies the connection information to another semiconductor integrated circuit among the plurality of semiconductor integrated circuits. And
A second semiconductor element different from the first semiconductor element electrode among the plurality of semiconductor element electrodes, wherein the signal selection unit is configured to change the selected signal line according to a change in an operation state of the logic circuit unit; An electronic device that is electrically connected to an electrode. The signal selection unit retains electrical connection between the selected signal line and the second semiconductor element electrode until a predetermined retention period ends after detecting a change in the operation state of the logic circuit unit. The electronic device according to claim 9. The signal selection unit receives an acknowledgment signal indicating that the connection information has been confirmed from an external semiconductor integrated circuit notified of the connection information from the signal control unit, and based on the received acknowledgment signal, The electronic device according to claim 10, wherein measurement of the predetermined retention period is terminated. The electronic device according to claim 10, wherein the signal selection unit ends the measurement of the predetermined reservation period based on a reference value preset in the interior. The electronic device according to claim 10 , wherein the signal selection unit sets the second semiconductor element electrode to high impedance in the predetermined retention period. A method for controlling a semiconductor integrated circuit in a semiconductor integrated circuit comprising a logic circuit section and a plurality of semiconductor element electrodes,
A selection step of selecting one of a plurality of signal lines coming out of the logic circuit unit;
A first connection step of electrically connecting the selected signal line to a first semiconductor element electrode of the plurality of semiconductor element electrodes;
The selected signal line is electrically connected to a second semiconductor element electrode different from the first semiconductor element electrode among the plurality of semiconductor element electrodes in accordance with a change in an operation state of the logic circuit portion. And a second connection step. A method for controlling a semiconductor integrated circuit. A generation step of generating connection information relating to the electrical connection performed in the first connection step and the electrical connection performed in the second connection step;
A control step for controlling the electrical connection performed in the first connection step and the electrical connection performed in the second connection step based on the generated connection information;
15. The method of controlling a semiconductor integrated circuit according to claim 14, further comprising a notification step of notifying the generated connection information to an external semiconductor integrated circuit. The second connection step includes a reservation step of retaining an electrical connection between the selected signal line and the second semiconductor element electrode until a predetermined retention period ends. A method for controlling a semiconductor integrated circuit. 17. The method of controlling a semiconductor integrated circuit according to claim 16, wherein the second connection step includes a holding step of holding the second semiconductor element electrode at a high impedance during the predetermined retention period.

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