JPH1062493A - Integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the problem of I/O terminals in the functional test of an integrated circuit. SOLUTION: Output data signals O1, O2, and O3 of a logic circuit 13 are connected to the input sides of selectors 151 , 152 , and 153 , respectively. Verification signals S1, S2,..., S18 in the functional test of the logic circuit 13 are similarly connected to the input sides of the selectors 151 ,..., 153 . When an enable signal EN as well as a mode selection signal MD are fed to a shift register 14, the mode selection signal MD is shifted and retained in synchronization with a clock signal CLK and a mode control signal is fed to a control terminal S of the selectors 151 ,..., 153 . The selectors 151 ,..., 153 selects the output data signals O1, O2, and O3 or the verification signals S1, S2,..., S18 based on the mode control signal and output them to output terminals 161 , 162 , and 163 .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit (Integr
ated circuit (hereinafter referred to as “IC”), and more particularly to an IC having a test function of outputting a signal for verifying the function of an internal logic gate.

[0002]

2. Description of the Related Art An IC is a circuit formed by integrating a plurality of logic gates on a semiconductor substrate. It is necessary to perform a functional test on whether or not an IC has a designed logic function at the time of manufacture. In this functional test, input signals of all logical combinations are sequentially applied to a plurality of input terminals of the IC, and a response state of a logic level of an output signal appearing at the plurality of output terminals is tested. In a large-scale IC (Large Scale IC, hereinafter referred to as “LSI”) in which the degree of integration of the IC has increased, the functions that can be realized by one LSI increase.
In such an LSI, it is necessary to perform a dynamic function test in accordance with the actual use state by sufficiently considering not only the logic level of the input signal applied to the input terminal but also the input sequence and timing of the input signal. . In an LSI, the degree of integration increases and the number of internal logic gates that are not connected to external input / output terminals increases. Therefore, the number of gates that cannot be directly measured from the input / output terminals increases. Even if it contains unstable elements, it cannot be detected,
It may be judged as good. Therefore, an LSI as shown in FIG. 2 has been proposed.

FIG. 2 shows a conventional LSI having a test function.
FIG. This LSI has a plurality of input terminals 1 ₁ ,
1 _2, 1 _3, has a ..., these input terminals 1 _1, ..., the
Each is connected to the input side of the logic circuit 2. The output side of the logic circuit 2 has output terminals 3 ₁ , 3 ₂ , 3 ₃ ,
…It is connected to the. Further, the output side of the internal gate (not shown) of the logic circuit 2 are respectively connected to a plurality of input terminals DI of the selector 4 _1, 4 _2. The selectors 4 ₁ and 4 ₂ select one of the plurality of input terminals DI and output it to the output terminal DO according to a selection signal given to the selection terminal SEL. These selectors 4 _1, 4 ₂ selection terminal SEL is connected to the control terminal 5 _1, 5 ₂ of LSI. Also, the selectors 4 ₁ , 4
Output terminal DO of the ₂ is connected to the test terminal 6 ₁ and 6 ₂ of the LSI, respectively. In such a LSI, by applying a selection signal to the control terminal 5 _1, 5 _2, the signal of the internal logic gates that are not directly connected to the input and output terminals, and output from the test terminal 6 _and 62 to the outside, these The state of the internal logic gate can be tested.

[0004]

However, the conventional LSI has the following problems. To validate the output signal of the internal logic gate of the logic circuit 2 of LSI, a control terminal 5 _1, 5 _2, using the test terminal 6 ₁ and 6 _2. However, as the function of the LSI increases, the number of internal logic gates to be verified increases, and the number of necessary control terminals and test terminals also increases. On the other hand, as the functions of the LSI increase, the original input / output signals also tend to increase, and it becomes difficult to secure terminals for functional tests. As a result, there is a problem that it is not possible to secure sufficient terminals necessary for verifying the function of the LSI. An object of the present invention is to provide an IC such as an LSI capable of solving the problem of the related art and securing more terminals for function verification.

[0005]

According to a first aspect of the present invention, there is provided an IC such as an LSI, comprising: a plurality of input terminals for receiving a plurality of bits of a data signal; M output terminals for outputting a data signal, a control terminal to which a control signal is input, and a multi-bit mode for selecting one of a normal operation mode and a plurality of operation verification modes A mode terminal to which a selection signal is input in series, and a plurality of logic gates for performing logic processing of a data signal input from the input terminal, and outputting a plurality of bits of an output data signal as a processing result; A logic circuit that outputs a plurality of verification signals for operation verification at the gate, and a mode selection signal input from the mode terminal according to a control signal input from the control terminal. Converted to a serial-parallel conversion means for outputting a mode control signal, N-number (where, N ≦ M) and selection means is provided on a semiconductor substrate.

The selecting means is provided with a specific output data signal among the output data signals of the logic circuit and the verification signal corresponding to the operation verification mode, and based on the mode control signal, In the mode, the specific output data signal is selected and output to the output terminal, and in the plurality of operation verification modes, the output data signal or the verification signal corresponding to the operation verification mode is selected and output to the output terminal. It is. According to a second aspect of the present invention, in an IC such as an LSI, a plurality of input terminals to which a plurality of bits of a data signal are input, M output terminals to output a plurality of bits of a data signal, and a header section having a specific bit pattern A mode terminal to which a mode selection signal composed of a mode selection unit having a plurality of bits for selecting any one of a normal operation mode and a plurality of operation verification modes is sequentially input in series; A plurality of logic gates for performing logic processing of a data signal input from an input terminal, outputting a plurality of bits of an output data signal as a processing result to the output terminal, and a plurality of verifications for verifying operation of the logic gate; A logic circuit for outputting a signal, serial-parallel conversion means,
N selection means (where N ≦ M) are provided on the semiconductor substrate.

The serial-parallel conversion means detects a header of a mode selection signal input from the mode terminal and outputs a detection signal, and a latch signal generator for generating a latch signal based on the detection signal. A data holding unit that holds a mode selection unit of the mode selection signal based on the latch signal and outputs the mode selection signal as a mode control signal. Further, the selection means is provided with a specific output data signal among the output data signals of the logic circuit and the verification signal corresponding to the operation verification mode, and the normal operation is performed based on the mode control signal. In the mode, the specific output data signal is selected and output to the output terminal, and in the plurality of operation verification modes, the output data signal or the verification signal corresponding to the operation verification mode is selected and output to the output terminal. It is. According to the first aspect, since the IC is configured as described above, the following operation is performed.

When a control signal is input from the control terminal of the IC, the mode selection signal given to the mode terminal is converted into a parallel signal by the serial / parallel conversion means, and given as a mode control signal to the N selection means. Can be On the other hand, IC
The data signals input to the plurality of input terminals are logically processed by a logic circuit composed of a plurality of logic gates,
The M output data signals resulting from the processing are output, and a plurality of verification signals for verifying the operation of the logic gate are output. The N output data signals and the plurality of verification signals among the output data signals are supplied to the input sides of the N selection means. Then, in the N selection means, an output data signal and a verification signal corresponding to the verification mode are respectively selected by the mode control signal and output to the output terminal. According to the second aspect, when the mode selection signal is input to the mode terminal of the IC, the header detection section of the serial / parallel conversion means detects the header portion in the mode selection signal. When the header section is detected, the data holding section of the serial / parallel conversion means holds the mode selection section in the mode selection signal following the header section as the mode selection signal. This mode selection signal is provided as a mode control signal for the N selection means. The functions of the logic circuit and the N selecting means in the IC are the same as those of the first invention.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram of an LSI showing a first embodiment of the present invention. This LSI includes a plurality of input signals IN1, IN
A plurality of input terminals 1 to which 2,.
1 _1, 11 _2, ..., 11 _m, a clock terminal 12 ₁ of the clock signal CLK is input, the mode selection signal mode pin 12 ₂ MD is input, and the input control signals (e.g.,
And a control terminal 12 ₃ of the enable signal) EN is input. Input terminal 11 _1, ..., and the clock terminal 12
₁ is connected to the input side of the logic circuit 13 respectively. The logic circuit 13 is constituted by a plurality of logic gates (not shown), and the input signal IN inputted to the input terminals 11 ₁ ,.
1, ..., and performs logic processing of a particular function based on the clock signal CLK input to clock terminal 12 _1, the output signal O1 and the processing result, O2, ..., and outputs as On. The logic circuit 13 has a function of outputting output signals of specific logic gates other than the output signals O1,... As function verification signals S1, S2,.

[0010] The clock terminal 12 _1, the mode terminals 12 ₂ and the control terminal 12 ₃ is connected parallel conversion means (e.g., a shift register) 14. Shift register 14
Are an enable terminal E, a clock terminal C, an input terminal D,
And a plurality of output terminals Q1, Q2, Q3. While the enable terminal E is activated by the enable signal EN, the shift register 14 is provided with a mode selection signal applied to the input terminal D in synchronization with the rising timing of the clock signal CLK applied to the clock terminal C. M
This is a circuit for holding and shifting D. Shift register 1
A mode selection signal MD converted into a parallel signal of three bits (for example, bits A, B, and C) is output to the output terminals Q1, Q2, and Q3. The output side of the shift register 14 has a plurality of selection means (for example, selectors) 15 ₁ , 1
5 _2, 15 ₃ of the selection terminal S, are commonly connected. The selector 15 _{1-15 3} has eight input terminals respectively, and outputs the signal selected by the output side of which is supplied to an input terminal selected by 3 bits of the mode selection signal MD. The eight input terminals from the first selector 15 ₁ to 8 th, for example, the output signal O1 of the logic circuit 13,
Function verification signals S1, S2, S3, S4, S5, S6, S
7 are connected in this order. Further, in the same manner as the eight input terminals of the selector 15 _2, the output signal O2, O2 of the logic circuit 13, the function verification signal S8, S9, S10, S1
1, S12 and S13 are connected in this order. Moreover, the eight input terminals of the selector 15 _3, logic circuit 1
3, the output signals O3, O3, O3, the function verification signal S14,
S15, S16, S17, and S18 are connected in this order.

The output sides of the selectors 15 ₁ , 15 ₂ , 15 ₃ are connected to output terminals 16 ₁ , 16 ₂ , 16 ₃ of the LSI, respectively. Also, the output signal O of the logic circuit 13
4,... On are output terminals 16 ₄ ,.
_n , respectively. Figure 3 is a time chart showing the operation of the shift register 14 of FIG. 1, FIG. 4 showing the relationship between the mode selection signal MD output signal OUT1~OUT3 inputted to the selector 15 ₁ to 15 ₃ in FIG. 1 It is. The operation in the case where “101” is given as the mode selection signal MD during the function verification test of the LSI in FIG. 1 will be described below with reference to FIGS. FIG.
At time t1, the enable signal EN becomes logic "1" indicating the activated state, and the shift register 14 of FIG.
Becomes operable. Then, at the timing of the rise of the clock signal CLK at time t2, the signal “1” of the mode selection signal MD is held, and “1” is output as the bit A of the mode selection signal MD to the output terminal Q1.

At time t3, after the mode selection signal MD is changed to logic "0", the output terminal Q2 has been output to the output terminal Q1 at the rising timing of the clock signal CLK at time t4. The signal of "1" is shifted, and the mode selection signal MD is output to the output terminal Q1.
Is held and output. Similarly, time t
5, after the mode selection signal MD is changed to "1", the output terminals Q3 and Q2 have been output to the output terminals Q2 and Q1 at the rising timing of the clock signal CLK at time t6. The signals "1" and "0" are shifted, and the signal "1" of the mode selection signal MD is held and output to the output terminal Q1. Thereafter, at time t7, when the enable signal EN becomes “0” indicating an inactive state, the shift register 14 shown in FIG.
Is in an operation stop state. As a result, shift register 1
4 output bits A, B, and C are “1”,
It becomes “0” and “1” and is determined. At this point, the LSI
Output terminals 16 ₁ , 16 ₂ , 16 ₃
1, OUT2, the OUT3, as shown in FIG. 4, the selector 15 _1, 15 _2, 15 the selected function in ₃ verification signal S5, S11, S16 are outputted respectively.

As described above, the mode selection signal MD is "10
1 ", the output signals OUT1, OUT2, O
Although the UT 3 has been described, as shown in FIG. 4, by changing the mode selection signal MD, other function verification signals S1,... And output signals O1, O2, O3 can be selected and output. For example, assuming that the mode selection signal MD is "000", the output signals O1, O2, and O3 are selected, and a normal operation mode is set. Further, for example, when the mode selection signal MD is "100", the function verification signal S1 is selected instead of the output signal O1, and the other output signals O2 to On are output in the same manner as in the normal operation mode. As described above, the LSI of the present embodiment includes the following (1) to (3)
There are advantages such as: (1) Since the shift register 14 is provided, it is possible to input the mode selection signal MD as a serial signal, and it is not necessary to increase the number of terminals for inputting control signals even if the number of selection modes increases. (2) Since a function terminal for outputting a test signal during verification is shared with the output terminal 16 ₁ to 16 ₃ in the normal operation mode, it is not necessary to provide a dedicated terminal for the test signal output, the terminal neck There is little fear. (3) the selector 15 ₁ to 15 having a plurality of input terminals
_Since it has ₃ , a plurality of function verification modes can be set. Thus, the function verification can be efficiently performed by incorporating in advance the function verification mode for selecting the function verification signals S1,... Optimal for the function verification.

Second Embodiment FIG. 5 shows a second embodiment of the present invention.
2 is a configuration diagram of the serial-parallel conversion means in FIG. 1, and elements common to the elements in FIG. 1 are denoted by common reference numerals. The serial / parallel conversion means in FIG. 5 is an alternative to the shift register 14 in FIG. 1, and includes an eight-stage shift register 21 to which a clock signal CLK and a mode selection signal MDA having a different configuration from FIG. It has a register 22. These shift registers 21 and 22 are provided with a clock signal CLK.
Mode selection signal M in synchronization with the rising timing of
This is a circuit that holds and shifts DA. The data held in each stage of the shift registers 21 and 22 is output as a parallel signal. The header detection unit 23 is connected to the output side of the shift register 21. The header detector 23 is a circuit that checks whether the 8-bit data output from the shift register 21 has a specific bit pattern, and outputs a detection signal DS when the 8-bit data has the specific bit pattern. is there. The latch pulse generator 24 is connected to the output side of the header detector 23. The latch pulse generator 24 is a circuit that receives the detection signal DS and the clock signal CLK, and outputs the latch pulse LP at the rising timing of the third clock signal CLK after the detection signal DS is applied.

The output side of the shift register 22 and the output side of the latch pulse generation section 24 are connected to a data holding section 25. The data holding unit 25 includes the latch pulse generation unit 2
4 holds the 3-bit parallel output data of the shift register 22 at the timing of the latch pulse LP given from 4 and outputs the mode selection signal MD converted to the 3-bit parallel signal of bits A, B and C. is there. FIG.
6 is a time chart illustrating an operation of the serial-parallel conversion unit in FIG. 5. As shown in FIG. 6, the mode selection signal MDA is, for example, an 8-bit specific pattern (for example, “101001”).
01 ″) is a serial signal composed of a header HDR and 3-bit data of the mode selector MOD following the header HDR. The mode selection signal MDA is synchronized with the falling timing of the clock signal CLK. Then, the data bits are sequentially changed to form a serial signal as a serial signal.
1, 22. This mode selection signal MDA is
The data is held and shifted by the shift registers 21 and 22 in synchronization with the rising timing of the clock signal CLK. At time t11 in FIG. 6, when the output signal of the shift register 21 has a specific pattern of the header part HDR, the detection signal DS is output from the header detection part 23 to the latch pulse generation part 24.

The latch pulse generator 24 detects the detection signal DS
, The counting of the clock signal CLK is started, and the latch pulse LP is output to the data holding unit 25 in synchronization with the rising of the third clock signal at time t12. At time t12, 3-bit data of the mode selection unit MOD of the mode selection signal MDA is output to the output side of the shift register 22. Thereby, the data “101” of the mode selection unit MOD is stored in the data holding unit 25.
Are converted to a 3-bit parallel signal of bits A, B, and C and output as a mode selection signal MD. The operation of the selector and the like based on the mode selection signal MD is described in FIG.
Is the same as the above LSI. As described above, in the second embodiment, since the header detecting section 23 is provided, the header section HDR of the mode selection signal MDA can be detected, and the data of the mode selecting section MOD can be input. This is advantageous in that the control terminal 12 ₃ is not required for the enable signal EN in FIG. Note that the present invention is not limited to the above embodiment, and various modifications are possible. As this modified example, for example, the following (a) to (d)
There is something like

(A) The mode selection signal MD has a 3-bit configuration. However, the mode selection signal MD is not limited to the 3-bit configuration, but can have a larger number of bits. With a large number of bit configurations, various function verification modes can be set, and a function verification test can be performed efficiently. (B) the selector 15 ₁ to 15 _3, the use of the 8-input of the selector, the number of bits k of the mode selection signal MD
If it is a bit, a ^2k input selector must be used. (C) Although the configuration is such that three selectors 15 ₁ ,... Are used, a configuration using more selectors 15 ₁ ,. By using a large number of selectors, a large number of function verification signals can be tested simultaneously, and a function verification test can be performed more efficiently. (D) The header part HDR in FIGS. 5 and 6 has an 8-bit configuration, but need not be limited to 8-bit. As long as the bit configuration is not confused with the data of the mode selection unit MOD, any configuration can be similarly applied.

[0018]

As described above in detail, according to the first aspect, a specific output data signal in an output data signal of a logic circuit and an operation verification signal are provided, and an output is provided by a mode control signal. Since the selection means for selecting the data signal or the operation verification signal and outputting the selected signal to the output terminal is provided, the output terminal in the normal operation and the verification signal output terminal in the operation verification mode can be shared, and the terminal neck is reduced. Never be. Further, since the mode selection signal is input as serial data using the control terminal and the mode terminal, the number of mode control terminals can be covered by two regardless of the number of bits of the mode selection signal. According to the second aspect, in the serial-parallel conversion means, the header detection section for detecting the header section in the mode selection signal and the data holding section for holding the mode selection section following the header section are provided. A mode control signal can be input by only one. This allows
Further, the terminals can be effectively used.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an LSI showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional LSI having a test function.

FIG. 3 is a time chart illustrating an operation of the shift register of FIG. 1;

FIG. 4 is a diagram showing a relationship between a mode selection signal and an output signal of FIG. 1;

FIG. 5 is a configuration diagram of an LSI serial-parallel conversion unit according to a second embodiment of the present invention;

FIG. 6 is a time chart showing the operation of the serial-parallel conversion means of FIG. 5;

[Description of Signs] 11 ₁ ,..., 11 _m input terminal 12 ₁ clock terminal 12 ₂ mode terminal 12 ₃ control terminal 13 logic circuit 14, 21, 22 shift register 15 ₁ , 15 ₂ , 15 ₃ selector 16 ₁ ,. 16 _n output terminal 23 header detection unit 24 latch pulse generation unit 25 data holding unit EN enable signal HDR header unit MOD mode selection unit MD, MDA mode selection signal S1 to S18 Function verification signal

Claims (2)

[Claims] A plurality of input terminals to which a plurality of bits of a data signal are input; M output terminals to output a plurality of bits of a data signal; a control terminal to which a control signal is input; A mode terminal to which a multi-bit mode selection signal for selecting any one of the operation verification modes is input in series; and a plurality of logic terminals for performing logical processing of a data signal input from the input terminal. A logic circuit having a logic gate, outputting a plurality of bits of output data signals as a processing result, and outputting a plurality of verification signals for operation verification in the logic gate; and a logic circuit according to a control signal input from the control terminal. Serial-parallel conversion means for converting a mode selection signal input from a mode terminal into a parallel signal and outputting the signal as a mode control signal; and an output data signal of the logic circuit The specific output data signal and the verification signal corresponding to the operation verification mode are given, and based on the mode control signal, the specific output data signal is selected during the normal operation mode, and the output terminal is selected. At the time of the plurality of operation verification modes, an output data signal or a verification signal corresponding to the operation verification mode is selected and output to the output terminal (where N ≦ M).
An integrated circuit, wherein the selecting means is provided on a semiconductor substrate. 2. A plurality of input terminals to which a plurality of bits of a data signal are input, M number of output terminals for outputting a plurality of bits of a data signal, a header having a specific bit pattern, and a plurality of normal operation modes. A mode terminal to which a mode selection signal composed of a plurality of mode selection units for selecting any one of the operation verification modes is sequentially input in series; and data input from the input terminal. A logic circuit having a plurality of logic gates for performing logic processing of signals, outputting a plurality of bits of output data signals as a processing result, and outputting a plurality of verification signals for operation verification in the logic gates; Header detection unit for detecting a header portion of a mode selection signal input from the device and outputting a detection signal, and a latch for generating a latch signal based on the detection signal Serial-parallel conversion means having a signal generation unit, and a data holding unit that holds a mode selection unit of the mode selection signal based on the latch signal and outputs the mode selection signal as a mode control signal; Output data signal and the verification signal corresponding to the operation verification mode are respectively provided, and based on the mode control signal, select the specific output data signal in the normal operation mode and output the selected output data signal to the output terminal. In the plurality of operation verification modes, N output data signals or verification signals corresponding to the operation verification mode are selected and output to the output terminal (where
(N ≦ M) is provided on a semiconductor substrate.