JP4937444B2 - 半導体デバイスを動作させる方法 - Google Patents

半導体デバイスを動作させる方法 Download PDF

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Publication number
JP4937444B2
JP4937444B2 JP2000375551A JP2000375551A JP4937444B2 JP 4937444 B2 JP4937444 B2 JP 4937444B2 JP 2000375551 A JP2000375551 A JP 2000375551A JP 2000375551 A JP2000375551 A JP 2000375551A JP 4937444 B2 JP4937444 B2 JP 4937444B2
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Japan
Prior art keywords
dielectric layer
potential
memory cell
discontinuous storage
storage elements
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Expired - Lifetime
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JP2000375551A
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English (en)
Japanese (ja)
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JP2001217328A5 (enExample
JP2001217328A (ja
Inventor
ブルース・イー・ホワイト
ボー・ジャング
ラマチャンドラン・ムラリドハー
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NXP USA Inc
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NXP USA Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/687—Floating-gate IGFETs having more than two programming levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
JP2000375551A 2000-02-01 2000-12-11 半導体デバイスを動作させる方法 Expired - Lifetime JP4937444B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/495,354 US6172905B1 (en) 2000-02-01 2000-02-01 Method of operating a semiconductor device
US495354 2000-02-01

Publications (3)

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JP2001217328A JP2001217328A (ja) 2001-08-10
JP2001217328A5 JP2001217328A5 (enExample) 2008-01-31
JP4937444B2 true JP4937444B2 (ja) 2012-05-23

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JP (1) JP4937444B2 (enExample)

Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3999900B2 (ja) * 1998-09-10 2007-10-31 株式会社東芝 不揮発性半導体メモリ
US6479862B1 (en) * 2000-06-22 2002-11-12 Progressant Technologies, Inc. Charge trapping device and method for implementing a transistor having a negative differential resistance mode
ATE458249T1 (de) * 2001-03-15 2010-03-15 Halo Inc Doppelbit monos speicherzellgebrauch für breite programbandbreite
WO2002097821A1 (en) * 2001-05-25 2002-12-05 Fujitsu Limited Nonvolatile semiconductor storage device
US6512701B1 (en) * 2001-06-21 2003-01-28 Advanced Micro Devices, Inc. Erase method for dual bit virtual ground flash
DE10140758A1 (de) 2001-08-20 2003-04-24 Infineon Technologies Ag Speicherelement für eine Halbleiterspeichereinrichtung
JP2003068891A (ja) * 2001-08-24 2003-03-07 Hitachi Ltd 半導体記憶素子、半導体装置及びその制御方法
US20030151077A1 (en) * 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
JP3745297B2 (ja) * 2002-03-27 2006-02-15 Ｎｅｃエレクトロニクス株式会社 不揮発性半導体記憶装置の製造方法
TW533588B (en) * 2002-04-24 2003-05-21 Nanya Technology Corp Flash memory and its manufacturing method
US6853587B2 (en) * 2002-06-21 2005-02-08 Micron Technology, Inc. Vertical NROM having a storage density of 1 bit per 1F2
US7221586B2 (en) 2002-07-08 2007-05-22 Micron Technology, Inc. Memory utilizing oxide nanolaminates
CN1319149C (zh) * 2002-07-19 2007-05-30 哈娄利公司 用于宽编程的双金属/多晶硅氧化物氮化物氧化物硅存储器单元
FR2846795A1 (fr) * 2002-11-05 2004-05-07 St Microelectronics Sa Procede de memorisation d'une donnee binaire dans une cellule-memoire d'un circuit integre de memoire, circuit integre correspondant et procede de fabrication
US7259984B2 (en) * 2002-11-26 2007-08-21 Cornell Research Foundation, Inc. Multibit metal nanocrystal memories and fabrication
US6967143B2 (en) * 2003-04-30 2005-11-22 Freescale Semiconductor, Inc. Semiconductor fabrication process with asymmetrical conductive spacers
US6903967B2 (en) * 2003-05-22 2005-06-07 Freescale Semiconductor, Inc. Memory with charge storage locations and adjacent gate structures
US7192876B2 (en) * 2003-05-22 2007-03-20 Freescale Semiconductor, Inc. Transistor with independent gate structures
US6831310B1 (en) 2003-11-10 2004-12-14 Freescale Semiconductor, Inc. Integrated circuit having multiple memory types and method of formation
US7098502B2 (en) * 2003-11-10 2006-08-29 Freescale Semiconductor, Inc. Transistor having three electrically isolated electrodes and method of formation
KR100601943B1 (ko) * 2004-03-04 2006-07-14 삼성전자주식회사 고르게 분포된 실리콘 나노 도트가 포함된 게이트를구비하는 메모리 소자의 제조 방법
JP4223427B2 (ja) * 2004-03-30 2009-02-12 株式会社ルネサステクノロジ 不揮発性半導体記憶装置及びそのデータ書き換え方法
US7018876B2 (en) * 2004-06-18 2006-03-28 Freescale Semiconductor, Inc. Transistor with vertical dielectric structure
US20060054963A1 (en) * 2004-09-10 2006-03-16 Qian Rong A Non-volatile and non-uniform trapped-charge memory cell structure and method of fabrication
US7518179B2 (en) * 2004-10-08 2009-04-14 Freescale Semiconductor, Inc. Virtual ground memory array and method therefor
US20060197140A1 (en) * 2005-03-04 2006-09-07 Freescale Semiconductor, Inc. Vertical transistor NVM with body contact structure and method
US7314798B2 (en) * 2005-07-25 2008-01-01 Freescale Semiconductor, Inc. Method of fabricating a nonvolatile storage array with continuous control gate employing hot carrier injection programming
US7256454B2 (en) * 2005-07-25 2007-08-14 Freescale Semiconductor, Inc Electronic device including discontinuous storage elements and a process for forming the same
US7394686B2 (en) * 2005-07-25 2008-07-01 Freescale Semiconductor, Inc. Programmable structure including discontinuous storage elements and spacer control gates in a trench
US7205608B2 (en) * 2005-07-25 2007-04-17 Freescale Semiconductor, Inc. Electronic device including discontinuous storage elements
US7262997B2 (en) * 2005-07-25 2007-08-28 Freescale Semiconductor, Inc. Process for operating an electronic device including a memory array and conductive lines
US7619275B2 (en) * 2005-07-25 2009-11-17 Freescale Semiconductor, Inc. Process for forming an electronic device including discontinuous storage elements
US7250340B2 (en) * 2005-07-25 2007-07-31 Freescale Semiconductor, Inc. Method of fabricating programmable structure including discontinuous storage elements and spacer control gates in a trench
US7619270B2 (en) * 2005-07-25 2009-11-17 Freescale Semiconductor, Inc. Electronic device including discontinuous storage elements
US7582929B2 (en) * 2005-07-25 2009-09-01 Freescale Semiconductor, Inc Electronic device including discontinuous storage elements
US20070020840A1 (en) * 2005-07-25 2007-01-25 Freescale Semiconductor, Inc. Programmable structure including nanocrystal storage elements in a trench
US7285819B2 (en) * 2005-07-25 2007-10-23 Freescale Semiconductor, Inc. Nonvolatile storage array with continuous control gate employing hot carrier injection programming
US7211858B2 (en) * 2005-07-25 2007-05-01 Freescale Semiconductor, Inc. Split gate storage device including a horizontal first gate and a vertical second gate in a trench
US7642594B2 (en) * 2005-07-25 2010-01-05 Freescale Semiconductor, Inc Electronic device including gate lines, bit lines, or a combination thereof
US7211487B2 (en) * 2005-07-25 2007-05-01 Freescale Semiconductor, Inc. Process for forming an electronic device including discontinuous storage elements
US7226840B2 (en) * 2005-07-25 2007-06-05 Freescale Semiconductor, Inc. Process for forming an electronic device including discontinuous storage elements
US7112490B1 (en) 2005-07-25 2006-09-26 Freescale Semiconductor, Inc. Hot carrier injection programmable structure including discontinuous storage elements and spacer control gates in a trench
US7364970B2 (en) * 2005-09-30 2008-04-29 Freescale Semiconductor, Inc. Method of making a multi-bit non-volatile memory (NVM) cell and structure
KR100690925B1 (ko) * 2005-12-01 2007-03-09 삼성전자주식회사 나노 크리스탈 비휘발성 반도체 집적 회로 장치 및 그 제조방법
US7622349B2 (en) * 2005-12-14 2009-11-24 Freescale Semiconductor, Inc. Floating gate non-volatile memory and method thereof
US7432122B2 (en) * 2006-01-06 2008-10-07 Freescale Semiconductor, Inc. Electronic device and a process for forming the electronic device
US20070212832A1 (en) * 2006-03-08 2007-09-13 Freescale Semiconductor Inc. Method for making a multibit transistor
US7535060B2 (en) * 2006-03-08 2009-05-19 Freescale Semiconductor, Inc. Charge storage structure formation in transistor with vertical channel region
US7592224B2 (en) 2006-03-30 2009-09-22 Freescale Semiconductor, Inc Method of fabricating a storage device including decontinuous storage elements within and between trenches
KR100735534B1 (ko) * 2006-04-04 2007-07-04 삼성전자주식회사 나노 크리스탈 비휘발성 반도체 집적 회로 장치 및 그 제조방법
US7838922B2 (en) * 2007-01-24 2010-11-23 Freescale Semiconductor, Inc. Electronic device including trenches and discontinuous storage elements
US7572699B2 (en) * 2007-01-24 2009-08-11 Freescale Semiconductor, Inc Process of forming an electronic device including fins and discontinuous storage elements
US7651916B2 (en) * 2007-01-24 2010-01-26 Freescale Semiconductor, Inc Electronic device including trenches and discontinuous storage elements and processes of forming and using the same
US7416945B1 (en) * 2007-02-19 2008-08-26 Freescale Semiconductor, Inc. Method for forming a split gate memory device
US8300461B2 (en) * 2010-08-24 2012-10-30 Yield Microelectronics Corp. Area saving electrically-erasable-programmable read-only memory (EEPROM) array

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0655788B1 (en) * 1993-11-29 1998-01-21 STMicroelectronics S.A. A volatile memory cell
US5408115A (en) 1994-04-04 1995-04-18 Motorola Inc. Self-aligned, split-gate EEPROM device
JP3588376B2 (ja) * 1994-10-21 2004-11-10 新日本製鐵株式会社 強誘電体メモリ
US5714766A (en) 1995-09-29 1998-02-03 International Business Machines Corporation Nano-structure memory device
US5852306A (en) * 1997-01-29 1998-12-22 Micron Technology, Inc. Flash memory with nanocrystalline silicon film floating gate
US5740104A (en) * 1997-01-29 1998-04-14 Micron Technology, Inc. Multi-state flash memory cell and method for programming single electron differences
US6060743A (en) * 1997-05-21 2000-05-09 Kabushiki Kaisha Toshiba Semiconductor memory device having multilayer group IV nanocrystal quantum dot floating gate and method of manufacturing the same
US6768165B1 (en) * 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
JP3951443B2 (ja) * 1997-09-02 2007-08-01 ソニー株式会社 不揮発性半導体記憶装置及びその書き込み方法
JPH11163173A (ja) * 1997-09-26 1999-06-18 Sony Corp 不揮発性半導体記憶装置と、その読み出し方法、及び書き込み方法
JP3727449B2 (ja) * 1997-09-30 2005-12-14 シャープ株式会社 半導体ナノ結晶の製造方法
US6232643B1 (en) * 1997-11-13 2001-05-15 Micron Technology, Inc. Memory using insulator traps
JP4045011B2 (ja) * 1998-04-09 2008-02-13 株式会社ルネサステクノロジ 半導体記憶装置

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US6172905B1 (en) 2001-01-09
JP2001217328A (ja) 2001-08-10
US6330184B1 (en) 2001-12-11

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