JP4910335B2 - Printed wiring board and semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a printed wiring board capable of reducing EMI due to resonance of a conductor layer without increasing transmission loss in a signal layer, and to provide a semiconductor integrated circuit device. <P>SOLUTION: The printed wiring board has a first conductor layer and a second conductor layer which are arranged in substantially parallel with an insulation layer sandwiched, and a signal layer. Out of the first and second conductor layers, one conductor layer adjacent to the signal layer has a low-loss conductor and a high-loss conductor having a plane resistivity of loss performance. The low-loss conductor has an overlap pattern arranged so as to overlap on at least one part of the wiring pattern of the signal layer. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a printed wiring board and a semiconductor integrated circuit device in which generation of unnecessary electromagnetic interference (EMI) is suppressed.

  In an electronic device such as a mobile phone equipped with an electronic component such as an IC or LSI, electromagnetic noise (EMI) generated inside the electronic device is a problem. One source of EMI is an electromagnetic field resonance phenomenon between a parallel plate of a power supply surface and a ground surface of a printed circuit board on which electronic components are mounted.

  1 to 2 show schematic views of a general printed wiring board. 1 is a top view of the printed wiring board 51, and FIG. 2 is a cross-sectional view taken along the line AA of FIG. The printed wiring board shown in FIG. 1 has a structure in which signal layers 52a and 52b, a power supply layer 56, and a ground layer 57 are laminated, and an insulating layer 53 is interposed between the layers. The printed wiring board 51 is formed with through holes 54 for electrically connecting the respective layers and / or for connecting the terminals of the electronic component 55 and the respective layers. A conductor 58 is disposed.

  Here, what is regarded as a problem as a generation source of EMI is a noise current that flows into the power supply layer 56 and the ground layer 57 when power is supplied to the electronic component 55 disposed on the printed wiring board 51. For example, when a current flows through the interlayer connection conductor 58 to supply current to the electronic component 55, an electromagnetic field is generated between the power supply layer 56 and the ground layer 57, and this electromagnetic field is generated between the power supply layer 56 and the ground layer 57. Resonance between parallel plates results in large EMI.

  Therefore, printed wiring boards as shown in Patent Documents 1 to 3 are known as printed wiring boards that reduce EMI. In the printed wiring board described in Patent Document 1, by providing a nickel plating layer or a chromium plating layer as a loss layer around the power supply layer and the ground layer, a high-frequency current due to resonance between the periphery of the power supply layer and the ground layer is generated. It is attenuated.

  In the printed wiring board described in Patent Document 2, in a sandwich structure in which an insulating layer is sandwiched between a power supply layer and a ground layer, loss layers are inserted between the power supply layer and the insulating layer and between the ground layer and the insulating layer, that is, the power supply The high frequency current is attenuated by laminating the layers, the loss layer, the insulating layer, the loss layer, and the ground layer in this order.

  In the printed wiring board described in Patent Document 3, in addition to the structure described in Patent Document 2, a loss layer (high resistance conductor) and a power supply layer (low resistance conductor) are not laminated, but the same layer. A printed wiring board in which a high resistance conductor is formed around a low resistance conductor is disclosed.

  As another problem, the signal layer of the printed wiring board may be subjected to EMI due to external noise such as a nearby high electromagnetic field generation source. Therefore, a printed wiring board 51 in which a shield layer 59 made of a solid pattern of conductors as shown in FIG. 3 is arranged to shield external noise is also known.

JP-A-10-27987 US Pat. No. 6,873,219 JP 2003-283073 A

  In the printed wiring boards described in Patent Document 1 and Patent Document 2, a high loss conductor (loss layer) that gives a loss (resistance) and a low loss conductor (power supply layer, ground layer) that are good conductors are overlapped. As a result, the loss effect of the high loss conductor is nullified by the influence of the low loss conductor. Therefore, it is necessary to form the thickness of the high loss conductor at least 1.4 times the skin thickness of the skin effect. The following expression 1 is an expression for obtaining the skin depth d. For example, when a nickel-phosphorus alloy is used as a high loss conductor to reduce the resonance of a parallel plate of about 1 GHz, the skin depth d of the nickel-phosphorus alloy is 49 μm according to the equation (1). Therefore, in this case, in order to obtain sufficient loss, the thickness of the high loss conductor must be 70 μm or more. Usually, since the thickness of the low loss conductor is about 10 μm, the thickness of the high loss conductor is too thick with respect to the thickness of the low loss conductor. Therefore, when a high-loss conductor having a large effect of reducing EMI is used in printed wiring boards as described in Patent Document 1 and Patent Document 2, the skin depth of the skin effect is deepened, and thus a high-loss conductor is necessary. The problem arises that the thickness becomes too thick.

ｄ：表皮深さ（ｍ）、ｆ：周波数（Ｈｚ）、μ_０：真空の透磁率（Ｈ／ｍ）、σ：導電率（Ω^−１ｍ^−１）

d: skin depth (m), f: frequency (Hz), μ ₀ : vacuum permeability (H / m), σ: conductivity (Ω ⁻¹ m ⁻¹ )

  As in Patent Document 3, when a high loss conductor is formed adjacent to a low loss conductor and a return current is passed through the high loss conductor, there is a problem that the high loss conductor causes a large transmission loss. is there.

  In a printed wiring board that shields external noise using the shield layer 59 as shown in FIG. 3, when the shield layer 59 is formed of a low-loss conductor, the shield layer 59 and the ground layer 57 are parallel flat plates. EMI occurs due to electromagnetic resonance of the parallel plate. Therefore, if the shield layer 59 is formed of a high-loss conductor in order to eliminate resonance that causes EMI, there arises a problem that transmission loss of the signal layer 52 increases.

  An object of the present invention is to provide a printed wiring board and a semiconductor integrated circuit device that reduce EMI due to resonance of a conductor layer without increasing transmission loss of a signal layer.

According to a first aspect of the present invention, in a printed wiring board having a first conductor layer, a second conductor layer, and a signal layer arranged in parallel via an insulating layer, the first conductor layer and the second conductor layer One conductor layer adjacent to the signal layer includes a low loss conductor and a high loss conductor having a lossy surface resistivity, and the low loss conductor is at least a wiring pattern of the signal layer. Provided is a printed wiring board having an overlapping pattern arranged to overlap a part. The dimension of the resonance current direction in which EMI occurs in the first conductor layer or the second conductor layer is L, the distance between the first conductor layer and the second conductor layer is t, and the insulating layer interposed between the first conductor layer and the second conductor layer When the relative permittivity is ε _r , the vacuum permeability is μ ₀ = 4π × 10 ⁻⁷ H / m, and the vacuum permittivity is ε ₀ = 8.84 × 10 ⁻¹² F / m, high loss The surface resistivity ρ (Ω / □) of the conductive conductor satisfies the following formula (3).

  According to a preferred form of the first aspect, when the through-hole electrically connecting each layer is provided, the low-loss conductor has an annular pattern surrounding the through-hole.

  According to a preferred form of the first aspect, the width of the overlapping pattern is equal to or greater than the width of the wiring pattern of the signal layer.

  According to the preferred form of the first aspect, the ratio of the area of the low-loss conductor to the area of one conductor layer is 60% or less.

  According to a preferred embodiment of the first aspect, the surface resistivity of the low loss conductor is 0.25Ω / □ or less.

  According to a preferred form of the first aspect, the outer diameter of the annular pattern is in the range of 2 to 7 times the hole diameter of the through hole.

  According to a preferred form of the first aspect, one of the first conductor layer and the second conductor layer is a power supply layer connected to a power supply, and the other conductor layer is a ground layer. According to another preferred embodiment, one of the first conductor layer and the second conductor layer is a shield layer that shields the signal layer from external noise.

  According to a preferred form of the first aspect, the electronic component is mounted. According to a more preferred embodiment, one conductor layer adjacent to the signal layer is disposed in the lower region of the electronic component.

  According to a preferred embodiment of the first aspect, the electronic component is built in between the first conductor layer and the second conductor layer.

According to a second aspect of the present invention, in a semiconductor integrated circuit device having a first conductor layer, a second conductor layer, and a signal layer arranged in parallel via an insulating layer, the first conductor layer and the second conductor Of the layers, one conductor layer adjacent to the signal layer has a low-loss conductor and a high-loss conductor having a lossy surface resistivity, and the low-loss conductor is a signal layer wiring pattern. Provided is a semiconductor integrated circuit device having an overlapping pattern arranged to overlap at least a part. The dimension of the resonance current direction in which EMI occurs in the first conductor layer or the second conductor layer is L, the distance between the first conductor layer and the second conductor layer is t, and the insulating layer interposed between the first conductor layer and the second conductor layer When the relative permittivity is ε _r , the vacuum permeability is μ ₀ = 4π × 10 ⁻⁷ H / m, and the vacuum permittivity is ε ₀ = 8.84 × 10 ⁻¹² F / m, high loss The surface resistivity ρ (Ω / □) of the conductive conductor satisfies the following formula (3).

  According to a preferred form of the second aspect, when the through-hole electrically connecting each layer is provided, the low-loss conductor has an annular pattern surrounding the through-hole.

  According to a preferred form of the second aspect, the width of the overlapping pattern is equal to or greater than the width of the wiring pattern of the signal layer.

  According to a preferred form of the second aspect, the ratio of the area of the low-loss conductor to the area of one conductor layer is 60% or less.

  According to a preferred embodiment of the second aspect, the surface resistivity of the low loss conductor is 0.25Ω / □ or less.

  According to a preferred form of the second aspect, the outer diameter of the annular pattern is in the range of 2 to 7 times the hole diameter of the through hole.

  According to the present invention, EMI due to resonance of a conductor layer can be reduced by arranging a high-loss conductor in the conductor layer, and transmission loss of the signal layer can be reduced by arranging an overlapping pattern made of low-loss conductors. be able to. Further, the transmission loss of the interlayer connection conductor can be reduced by arranging the annular pattern.

  1st Embodiment of the printed wiring board of this invention is shown in FIGS. 4 shows a top view of the printed wiring board 1, FIG. 5 shows a cross-sectional view along the line BB in FIG. 4, and FIGS. 6 to 9 show planes of each layer surface of the printed wiring board 1. The printed wiring board 1 includes a first signal layer 2a, a power supply layer 6, a ground layer 7, and a second signal layer 2b, and an insulating layer 3 is interposed between each layer (see FIGS. 4 and 5). . An electronic component 5 is mounted on the first signal layer 2a. In the printed wiring board 1, through holes 4 for electrically connecting the respective layers are formed, and interlayer connection conductors 8 are arranged in the through holes 4. The clearance 3 a is a part of the insulating layer 3 and is provided in a portion that insulates the power supply layer 6 or the ground layer 7 from the interlayer connection conductor 8.

  The first signal layer 2a and the second signal layer 2b have a desired wiring pattern made of a low-loss conductor, and the wiring pattern is connected to the interlayer connection conductor 8 (see FIGS. 6 and 9). The ground layer 7 has a low-loss conductor extending on one surface excluding the peripheral portion, the through hole 4 and the clearance 3a (see FIG. 8).

  The power supply layer 6 is formed of a low loss conductor 6a and a high loss conductor 6b (see FIG. 7). First, in order to reduce EMI due to resonance with the ground layer 7, the high-loss conductor 6b is provided on one side of the lower surface side (the ground layer 7 side) of the power supply layer 6 (excluding the peripheral portion, the through hole 4 and the clearance 3a). It extends to. Next, the low-loss conductor 6a is formed on the high-loss conductor 6b layer (the upper surface side (the first signal layer 2 side) of the power supply layer 6). The low-loss conductor 6a overlaps (coincides) with the three patterns, the current supply pattern 6a (1) for supplying current from the power source to the electronic component 5, and the shape and position of the wiring pattern of the first signal layer 2a. The overlapping pattern 6a (2) arranged in this manner and the annular pattern 6a (3) arranged so as to surround the through hole 4 (and the clearance 3a) are formed. FIG. 10 shows a view of the low-loss conductor 6a portion of the power supply layer 6 divided into patterns for each pattern 6a (1) to (3).

  The overlapping pattern 6a (2) is a pattern for flowing a current in the opposite direction to the current flowing in the wiring pattern of the adjacent signal layer 2a. By forming the overlapping pattern 6a (2) at a position overlapping the wiring pattern of the signal layer 2a when viewed from above (or below) the printed wiring board 1, the transmission loss of the signal layer 2a due to the high loss conductor 6b is reduced. Can do. The overlapping pattern 6a (2) is preferably formed to have the same shape as the wiring pattern of the first signal layer 2a. The width of the overlapping pattern 6a (2) is preferably at least the same width as the wiring pattern of the first signal layer 2a, and more preferably wider than the wiring pattern of the first signal layer 2a.

  The annular pattern 6a (3) is arranged to reduce the transmission loss of the current flowing through the interlayer connection conductor 8 caused by the high loss conductor 6b, and is used for electrical connection between the low loss conductor 6a and the interlayer connection conductor 8. They can be arranged regardless of the presence or absence (presence or absence of clearance 3a). The annular pattern 6a (3) may have a shape that partially surrounds the through hole 4 (or the interlayer connection conductor 8), but preferably has an annular shape that can be completely surrounded. The outer diameter (or outer periphery diagonal line) of the annular pattern 6a (3) is preferably about 2 to 7 times, more preferably about 4 to 5 times the diameter (or diagonal line) of the through hole 4. The shape of the annular pattern 6a (3) is not limited to a circular shape or an elliptical shape, and may be a polygonal shape.

  A desirable ratio of the low loss conductor 6a occupying the power supply layer 6 is 60% or less with respect to the surface area of the power supply layer 6. The smaller the area ratio of the low loss conductor 6a, the better the EMI reduction effect. Therefore, the length and width of the current supply pattern 6a (1), the overlapping pattern 6a (2), and the annular pattern 6a (3) are appropriately set according to the total area of the low loss conductor 6a. For example, when the wiring pattern of the first signal layer 2a is wired with high density, the width of the overlapping pattern 6a (2) is the same as the width of the wiring pattern, and the area of the low loss conductor 6a is set to the power supply layer. 6 or less is preferably 60% or less. In addition, when a region where the wiring pattern of the first signal layer 2a is wired at a high density and a region where the wiring pattern is wired at a low density are mixed, a wiring bundle in which the wiring pattern is wired at a high density is used. Overlapping pattern 6a (2) having almost the same width as the wiring bundle is formed in the power supply region overlapping with the formed region, and the region of high loss conductor 6b without the low loss conductor pattern is formed in the other region. Thus, the area of the low loss conductor 6a may be 60% or less of the power supply layer 6. The low-loss conductor 6a can be arranged so as to overlap the high-loss conductor 6b or can be arranged so as not to overlap. In the case of the form as shown in FIG. 5, the portion where the low loss conductor 6a and the high loss conductor 6b overlap in the power supply layer 6 can be regarded as the low loss conductor 6a.

  In the first embodiment, the high loss conductor 6b is arranged in the power supply layer 6, but it can be arranged in the ground layer 7 instead of the power supply layer. In this case, the overlapping pattern 6a (2) and the annular pattern 6a (3) are provided on the low-loss conductor of the ground layer 7.

Next, a formula for obtaining a preferable sheet resistivity of the high loss conductor will be described. The dimension in the resonance current direction of the conductor layer (power supply layer, ground layer) that generates EMI is L, the distance between the conductor layers (thickness of the insulating layer) is t, and the relative dielectric constant of the insulating layer interposed between the conductor layers is ε _r , In this case, the optimum sheet resistivity ρ (Ω / □) of the high-loss conductor disposed in one conductor layer is obtained by the following equation (2). Note that μ ₀ is the vacuum permeability, and ε ₀ is the vacuum dielectric constant.

μ_０＝４π×１０^−７Ｈ／ｍ、ε_０＝８．８４×１０^−１２Ｆ／ｍ

μ ₀ = 4π × 10 ⁻⁷ H / m, ε ₀ = 8.84 × 10 ⁻¹² F / m

For example, when ε _r = 4.5, L = 150 mm, and t = 0.2 mm, the optimum sheet resistivity of the high-loss conductor is about 1.6Ω / □. Equation 2 was derived from the optimum surface resistivity ρ obtained from the simulation results of the example .

  There may be a plurality of parallel flat plates made of conductor layers on one printed wiring board. In that case, the optimum sheet resistance of the high-loss conductor given by the equation (2) for each shape of each conductor layer. There is a rate.

  Further, if the sheet resistivity of the high loss conductor is in the range of 0.1 to 160 times the optimum sheet resistivity derived from the equation (2), EMI can be effectively reduced. Therefore, in the printed wiring board according to the present invention, the preferable range of the surface resistivity of the high loss conductor can be derived from the following equation (3). The basis of “0.1 to 160 times” is obtained from the electromagnetic field simulation, and the model and result of the simulation will be described in the following examples.

  Here, when there are parallel flat plates of a plurality of conductor layers on the printed wiring board, for example, when the conductor layers form a rectangular surface, each conductor layer has a length Ls in the short direction and a length Ln in the longitudinal direction. Although it exists, the direction of the resonance current can be short or long. When the frequency of electromagnetic resonance in each direction falls within the frequency band where EMI should be suppressed, it is necessary to suppress the resonance. In this case, in order to obtain a suitable sheet resistivity ρ, the lengths Ls and / or Ln that resonate at the frequency at which EMI is generated are substituted into L in the equations (2) and (3). At this time, since it is more effective to suppress the lowest resonance frequency, the length Ln in the longitudinal direction that gives the lowest resonance frequency of the conductor layer is preferably substituted for L in the equation. Further, when the shape of the power supply layer is significantly different from the rectangle, for example, in the case of L shape, C shape, etc., ρ can be obtained by setting the width Ls and / or the length Ln of the region as L.

For example, when t = 1 mm, √ε _r = 2 and Ls = 100 mm and Ln = 200 mm in the rectangular conductor layer, the half-wave resonance frequency in the short direction is 750 MHz, and the half-wave resonance frequency in the longitudinal direction is 375 MHz. It becomes. In this case, L giving the lowest resonance frequency is Ln, and therefore, a preferable range of the surface resistivity ρ is 0.625Ω / □ ≦ ρ ≦ 1000Ω / □ from the equation (3). In order to suppress both directions of resonance, the range of ρ obtained from Ln and the range of ρ obtained by substituting Ls into Equation 3 are 1.25Ω / □ ≦ ρ ≦ 2000Ω / □. Therefore, a suitable surface resistivity ρ for suppressing resonance in both directions is 1.25Ω / □ ≦ ρ ≦ 1000Ω / □. The resonance frequency (Hz) is obtained from the following equation (4).

  Here, in the present invention, the “low loss conductor” means a conductor pattern having a surface resistivity of 0.25Ω / □ or less, and the “high loss conductor” means a surface resistivity of 0.25Ω. This indicates a conductor pattern exceeding / □. Further, the surface resistivity (Ω / □) indicates a resistivity per unit length of a conductor surface having a thickness, a resistivity per unit width, that is, an effect of thickness.

The surface resistivity of the low loss conductor is 0.25Ω / □ or less, preferably 0.1Ω / □ or less, and more preferably 0.05Ω / □ or less. Further, the surface resistivity of the high loss conductor is more than 0.25Ω / □, but is preferably not less than a value obtained by substituting the maximum dimension L _max in the left side of Equation 3 among all the conductor layers, and more preferably. The second largest dimension L _2nd of all the conductor layers is equal to or greater than the value assigned to the left side of Equation 3.

  As a material of the low-loss conductor used in the signal layer, the power supply layer, or the ground layer, a metal having good conductivity, preferably copper, gold, silver, aluminum, tungsten, molybdenum, or the like is used. In addition, copper, gold, silver, aluminum, tungsten, and molybdenum having good conductivity can be used as the material for the high loss conductor. Preferably, the metal is 4 to 1000 times the electrical resistivity of copper. Form with. For example, nickel, iron, tin, nickel-chromium alloy, nickel-phosphorus alloy, copper-nickel alloy, Pb-Sn eutectic solder alloy, or the like is used. The material used for the low-loss conductor and the high-loss conductor is not limited to metal, but polyphenylene vinylene, indium tris 2,4-pentanedionate (or trisacetoacetonato indium), indium trishexafluoropentanedio An organic metal compound such as narate or methyltrimethylacetoxyindium, or a semiconductor material such as ITO (Indium Tin Oxide), GaP, or AlGaAs may be used.

  The insulating layer can be formed of glass epoxy resin, polyimide resin, glass, ceramics mainly composed of alumina, silicon nitride, silicon carbide, mullite, etc., or a silicon substrate, and has a desired dielectric constant. An optimal insulator is appropriately selected according to the rate.

  According to the equation (5) obtained by modifying the equation (3), the applicable range of the dimension L of the printed wiring board can also be obtained from the surface resistivity ρ of the high-loss conductor to be used. For example, a high-loss conductor with a surface resistivity ρ = 5Ω / □ using a nickel-phosphorus alloy with a thickness of 2 μm is applied to a conductor layer of 0.5 mm ≦ L ≦ 700 mm when the parallel plate interval t = 0.02 mm. In the case of t = 0.4 mm, it is applicable to a conductor layer of 9 mm ≦ L ≦ 15,000 mm.

Here, the applicable resonance frequency can also be calculated from the surface resistivity of the high-loss loss conductor to be used from the equations (4) and (5). A high loss conductor having a surface resistivity ρ = 1Ω / □ using a 23% nickel-copper alloy film having a thickness of 0.3 μm is 2.5 mm ≦ L ≦ 3500 mm when the parallel plate interval t = 0.02 mm. In the case where the parallel plate interval t = 0.1 mm, the present invention can be applied to a conductor layer of 11 mm ≦ L ≦ 19,000 mm. Here, the resonance frequency of the parallel plate when ε _r = 4.5, the parallel plate interval t = 0.1 mm, and the conductor layer dimension L = 11 mm is 6.4 GHz. That is, even if there is a parallel plate having a dimension of 11 mm or less, it has a resonance frequency higher than 6.4 GHz. Therefore, under this condition, a high loss conductor having a surface resistivity ρ = 1Ω / □ can be used practically sufficiently because it can reduce resonance at a frequency of 6.4 GHz or less. On the other hand, when using a highly lossy conductor with a surface resistivity ρ = 50Ω / □, a parallel plate spacing t = 0.02 mm can be applied up to 0.05 mm ≦ l ≦ 75 mm. If the flat plate interval t = 0.1 mm, it is applicable up to 0.25 mm ≦ L ≦ 350 mm. Therefore, it is considered that a high-loss conductor having a surface resistivity ρ = 50Ω / □ is sufficiently practical. Therefore, under this condition, the high-loss conductor can cope with a wide range of resonances if it has a surface resistivity in the range of at least 1Ω / □ ≦ ρ ≦ 50Ω / □. Note that the preferable range of the surface resistivity depends on the relative dielectric constant ε _{r of} the insulating layer, the distance t between the conductor layers, and the dimension L of the conductor layer, as shown in the equation (3). It is necessary to set appropriately from the equation (3).

  Table 1 shows data such as film thicknesses of various metals for obtaining a sheet resistivity of 1 to 50Ω / □.

For example, in the first embodiment, when copper is used for the low-loss conductor 6a, in order to set the surface resistivity of the high-loss conductor 6b to 1Ω / □, the mass of the high-loss conductor 6b is 30 mass. When a nickel-phosphorus alloy containing 1% phosphorus is used, the nickel-phosphorus alloy has a resistivity of 10 ⁻⁵ Ωm. Therefore, the surface resistivity of 1 Ω / □ should be formed by forming the nickel-phosphorus alloy to a thickness of about 10 μm. Can do. The nickel-phosphorus alloy has an advantage that it can be easily handled, for example, it can be dissolved without generating an undissolved residue (smut) by subsequent etching. When a 23% nickel-copper alloy is used as the material of the high loss conductor 6b, the resistivity of the nickel-copper alloy is 303 nΩm, so that the thickness is about 1 μm / □ when formed to a thickness of about 0.3 μm. The sheet resistivity can be made as follows. Further, when nickel is used as the material of the high loss conductor 6b, the resistivity of nickel is 78 nΩm. Therefore, the surface resistivity of about 1Ω / □ can be obtained by forming the thickness of nickel to 0.08 μm. it can.

  Moreover, the high loss conductor 6b can be formed integrally with the low loss conductor 6a by forming the high loss conductor 6b with the same material as the low loss conductor 6a. For example, when the low loss conductor 6a is formed by copper plating having a thickness of 10 μm, the surface resistivity of about 1Ω / □ can be obtained by forming the high loss conductor 6b by copper plating having a thickness of about 0.02 μm. it can. Thus, if both conductors are made of copper, the manufacturing cost can be reduced.

  A method of manufacturing the printed wiring board 1 as shown in FIGS. 4 to 10 according to the first embodiment will be described. First, the high loss conductor 6 b is formed on the insulating substrate that forms the insulating layer 3 between the power supply layer 6 and the ground layer 7. As the material of the insulating layer 3, a material having a desired relative dielectric constant is appropriately selected. Next, a low loss conductor (current supply pattern 6a (1), overlapping pattern 6a (2), annular pattern 6a (3), ground layer 7) is formed by electroless plating of copper. Next, an insulating substrate with a metal foil is laminated on the power supply layer 6 and the ground layer 7 via a prepreg. Next, the through-hole 4 is opened, and the interlayer connection conductor 8 is formed by plating the inner surface of the through-hole with copper or the like, or filling the through-hole 4 with a conductor. Next, the signal layers 2a and 2b are formed by etching the metal foils on both sides of the laminate.

  Each conductor layer and insulating layer can also enhance adhesion by utilizing an anchor effect. For example, when a copper-nickel-phosphorus alloy is used as the material of the high loss conductor 6b, the anchor effect can be obtained by depositing acicular metal on the surface. Further, when nickel is used for the high loss conductor 6b, needle-like nickel can be deposited by electroless nickel plating using hydrazine as a reducing agent and glycine as a complexing agent, and the anchor effect can be obtained.

  A second embodiment of the printed wiring board of the present invention is shown in FIGS. 11 is a top view of the printed wiring board 1, FIG. 12 is a sectional view taken along the line CC of FIG. 11, and FIG. 13 is a plan view of the signal layer surface shown in FIG. In the first embodiment, the printed wiring board that reduces the EMI due to the resonance of the parallel plate composed of the power supply layer and the ground layer is shown. In the second embodiment, the parallel wiring composed of the ground layer 7 and the shield layer 9 is shown. 1 shows a printed wiring board that reduces EMI due to resonance of a flat plate, that is, a parallel flat plate formed by two ground layers. The printed wiring board of the second embodiment is used for a flexible printed wiring board having a wiring pattern for connecting an in-circuit emulator and a CPU mounting board, for example.

  In the second embodiment, the solid pattern ground layer 7 and the signal layer 2 are arranged via the insulating layer 3, and the signal layer 2 and the shield layer 9 are arranged via the insulating layer 3. Thereby, the ground layer 7 and the shield layer 9 are configured to form parallel flat plates via the insulating layer 3 and the signal layer 2. The shield layer 9 shields extraneous noise and reduces EMI due to resonance with the ground layer 7, and a low-loss conductor 9a that reduces transmission loss of the signal layer 2 due to the high-loss conductor 9b. It is composed of The low loss conductor 9a is arranged so that the shape and position of the signal layer 2 overlap with each other when viewed from above the printed wiring board 1 (see FIGS. 11 to 13), and the overlapping pattern referred to in the first embodiment is the same. Forming. The high loss conductor 9b is formed in a solid pattern on the low loss conductor 9a. The high loss conductor 9b can be formed by printing a tin paste, a conductive adhesive, or a conductive paste such as a silver paste or a copper paste.

  According to the second embodiment, even when the signal layer 2 is disposed between the ground layer 7 and the shield layer 9, the shield layer 9 is composed of the high loss conductor 9b and the low loss conductor (overlapping pattern). By comprising from 9a, EMI by resonance of the ground layer 7 and the shield layer 9 can be reduced, and the transmission loss of the signal layer 2 can also be reduced. Further, according to the second embodiment, even when two signal layers are present in the printed wiring board 1 (not shown), mutual electromagnetic noise between the signal layers can be reduced (Example) 9).

  As another structure of the second embodiment, an intermediate such as an adhesive can be interposed between the high loss conductor 9b and the low loss conductor 9a (not shown). For example, when the high loss conductor 9b and the low loss conductor 9a are bonded via an adhesive having a thickness of several tens of μm or less, the high loss conductor 9b and the low loss conductor 9a are directly connected to each other. Although it is not electrically connected, it is indirectly electrically connected by capacitive coupling via an adhesive.

  A third embodiment of the printed wiring board of the present invention is shown in FIGS. In the third embodiment, similarly to the second embodiment, the printed wiring board 1 has a shield layer 9 composed of a low-loss conductor 9a and a high-loss conductor 9b on the upper surface of the printed wiring board 1, and the low-loss conductor 9a includes: The overlapping pattern is arranged so as to overlap the signal layer 2 arranged in the insulating layer 3. The third embodiment is different from the second embodiment in that the shield layer 9 covers only a part of the printed wiring board 1 instead of the entire surface. When this 3rd Embodiment is used, it is a case where the electronic component 5 which has the wide conductor board 5a is mounted in the printed wiring board 1, etc., for example. In the printed wiring board 1 shown in FIGS. 14 to 18, when the conductor plate 5 a of the electronic component 5 is installed close to the surface of the printed wiring board 1, the conductor plate 5 a affects the signal transmission characteristics of the signal layer 2. Therefore, in the lower region of the electronic component 5, a shield layer 9 composed of a high loss conductor 9b having an EMI shielding effect and an overlapping pattern 9a for reducing transmission loss is formed. In the third embodiment, the overlapping pattern 9a does not overlap the entire signal layer 2 but partially overlaps the signal layer 2 (see FIGS. 16 and 17).

  In the printed wiring board 1 according to the second and third embodiments, for example, the signal layer 2 of the analog circuit of the printed wiring board 1 is shielded from external noise, or the signal layer 2 from a nearby high electromagnetic field generation source. It can also be used for shielding.

A fourth embodiment of the printed wiring board of the present invention is shown in FIG. In the fourth embodiment, the principle of the present invention is applied to a semiconductor integrated circuit device. Also in the semiconductor integrated circuit device 21, the high loss conductor 23 is disposed in the power supply layer 32 in order to shield the signal layer 22 a from external noise. An overlapping pattern 22c is disposed below the high loss conductor 23 so as to correspond to the signal layer 22a and the arrangement, thereby reducing transmission loss.

  In the semiconductor integrated circuit device shown in FIG. 19, a source semiconductor film 26 and a drain semiconductor film 27 are formed on a silicon substrate 25, and a gate electrode pattern separated by an oxide film insulating layer 30 on a current path 28 therebetween. 29 is formed. An interlayer connection conductor 22 d is connected on the source semiconductor film 26 and the drain semiconductor film 27. The interlayer connection conductor 22d is formed by being embedded in an insulating layer 24 made of polyimide or the like, and is connected to the signal layer 22a, the power supply layer 32, and the ground layer 22b.

  Here, for example, in the case where a parallel plate having a dimension of the power supply layer 32 and the ground layer 22b of about 2 mm is configured, resonance occurs at a frequency of about 100 GHz on the parallel plate. In this case, in order to reduce resonance, a high loss conductor 23 having a surface resistivity of about 1 Ω / □ may be formed in the power supply layer 32. For this purpose, as shown in Table 1, a high-loss conductor 23 having a surface resistivity of 1 Ω / □ formed of copper having a thickness of 17 nm is formed on the power supply layer 32. When the signal layer 22a adjacent to the power supply layer 32 exists, an overlapping pattern 22c corresponding to the arrangement of the signal layer 22a is formed in the power supply layer 32 with copper having a thickness of 70 nm or more. Similarly, when the power supply layer 32 is made of aluminum, the high-loss conductor 23 having a thickness of 27 nm may be formed as shown in Table 1.

  A fifth embodiment of the printed wiring board of the present invention is shown in FIGS. 20 is a cross-sectional view of the printed wiring board 1, FIG. 21 is a plan view of the power supply layer 6, FIG. 22 is a plan view of the ground layer 7, and FIG. 23 is a plan view of the second signal layer 2b. In the fifth embodiment, the electronic component 5 is built in an insulating layer between the power supply layer 6 and the ground layer 7. As a method for connecting the electronic component 5, the power supply layer 6, and the ground layer 7, a suitable form can be selected as appropriate. For example, in the form shown in FIGS. 20 to 22, the ground terminal 5 c of the electronic component 5 is metal-bonded to the low-loss conductor 7 a of the ground layer 7 through the joint portion 33. Further, the power supply terminal 5 b of the electronic component 5 is connected to the recess of the power supply layer 6.

  In the first embodiment, the high loss conductor 6a for reducing the EMI is disposed on the surface of the power supply layer 6 (see FIG. 5). In the fifth embodiment, the high loss conductor 6a is disposed. 7b is arranged on the surface of the ground layer 7. Accordingly, an overlapping pattern 7a (2) and an annular pattern 7a (3) for reducing transmission loss are also arranged on the surface of the ground layer 7. The overlapping pattern 7a (2) is formed at least as wide as the wiring pattern of the signal layer 2b so as to follow the wiring pattern of the signal layer 2b. The annular pattern 7a (3) is formed to surround the through hole 4 (interlayer connection conductor 8, clearance 3a).

  Next, the 1st manufacturing method of the printed wiring board 1 shown in FIGS. 20-23 is demonstrated using FIG. First, in the process shown in FIG. 24 (a), the high loss conductor 7b is plated on the periphery of the insulation substrate 3b, the low loss conductor 7a portion, the region on the insulation substrate 3b excluding the clearance 3a and the through hole 4 or the like. To form. Thereafter, the low loss conductor 7a is formed at a predetermined position. Next, a metal paste that becomes the joint portion 33 is disposed in the region of the low-loss conductor 7a where the electronic component 5 is to be installed. In this metal paste, metal particles such as silver ultrafine particles dispersed in a solvent such as tetradecane using a dispersant such as alkylamine can be used. The metal paste is a method such as ink jet printing. Can be arranged.

  Next, in the step shown in FIG. 24B, the electronic component 5 is placed on the metal paste. For example, the electronic component 5 shown in FIG. 24 has a power supply terminal 5b and a ground terminal 5c covering a region excluding the vicinity of the power supply terminal 5b on a part of the upper surface. When using the silver ultrafine metal paste exemplified above, the electronic component 5 is placed so that the surface of the ground terminal 5c is in contact with the metal paste, and then the whole is heated to about 200 ° C. The ground terminal 5c and the low-loss conductor 7a are metal-bonded by decomposing the dispersant, evaporating the solvent, and sintering the silver ultrafine particles. In this way, when the joint portion 33 is formed by metal bonding, the joint portion 33 can withstand even when heated to about 300 ° C. during the soldering heat treatment.

  Next, in the steps shown in FIGS. 24C to 24D, the insulating layer 3 is disposed in a region excluding the electronic component 5, and the fluid insulating layer 3 is supplied around the electronic component 5, An insulating layer 3 that covers the electronic component 5 is formed. For example, as shown in FIG. 24C, a resin (insulating layer 3) with a metal foil 35 such as a copper foil cut through the region of the electronic component 5 is disposed on the insulating substrate 3b. Next, as shown in FIG. 24D, the insulating layer 3 disposed via the metal foil 35 is heated and pressurized by the heating / pressurizing means 36 such as a mirror plate, so that the fluid around the electronic component 5 is fluidized. The insulating layer 3c is eluted. Alternatively, the fluid insulating layer 3c can be filled around the electronic component 5 by a dispenser or the like.

  Next, in the step shown in FIG. 24 (e), after the fluid insulating layer 3c is cured, the metal foil 35 is removed by etching, and the exposed insulating layer 3 is polished to obtain an insulating layer having a certain thickness. 3 is formed.

  Next, in the step shown in FIG. 24F, a hole reaching the power supply terminal 5b of the electronic component 5 is formed in the insulating layer 3 by a carbon dioxide laser or the like. Thereafter, the power source layer 6 is formed by forming a low-loss conductor in the hole and in a predetermined region on the insulating layer 3 by plating or the like.

  Next, the printed wiring board 1 as shown in FIG. 20 is formed by forming the insulating layer 3, the first signal layer 2a, the through hole 4 and the interlayer connection conductor 8 on the power supply layer 6. The through hole can be opened, for example, by means of a drill, a laser, or the like, and the interlayer connection conductor 8 can be formed by, for example, plating in the through hole, filling the through hole with a metal material, or the like. Moreover, the solder resist 34 is printed on the 1st signal layer 2a as needed.

  The printed wiring board 1 can also be manufactured by manufacturing a printed wiring board having a plurality of desired printed wiring boards 1 in a single process and further adding a cutting process.

  FIG. 25 shows a second manufacturing method of the printed wiring board 1 according to the fifth embodiment. First, in the process shown in FIG. 25A, a high-loss conductor 7b and a soluble filler 38 are disposed on a metal substrate 37 such as copper. The soluble filler 38 is soluble in an inorganic solution or an organic solvent, for example, calcium carbonate soluble in an acidic aqueous solution, and is disposed by ink jet printing, dispenser printing, or the like.

  In the step shown in FIG. 25 (b), the electronic component 5 is disposed on the soluble filler 38, and a resin (insulating layer 3) with a metal foil 35 that penetrates the region of the electronic component 5 is disposed. In addition, a soluble filler 38 is disposed on the power supply terminal 5 b of the electronic component 5.

  In the step shown in FIG. 25 (c), the resin is melted from above the metal foil 35 by the heating / pressurizing means 36, and the fluid insulating layer 3c is supplied around the electronic component 5 and cured.

  In the step shown in FIG. 25D, the metal foil 35 and the metal substrate 37 are removed by etching, and the soluble filler 38 is removed with an appropriate liquid. Next, the exposed insulating layer 3 is mechanically polished to form the insulating layer 3 having a predetermined thickness.

  In the step shown in FIG. 25E, the low-loss conductors of the power supply layer 6 and the ground layer 7 are arranged by plating or the like. At this time, the low loss conductors of the power supply layer 6 and the ground layer 7 are brought into contact with the electronic component 5.

  In the step shown in FIG. 25 (f), the insulating layer 3 having a predetermined thickness is disposed above the power supply layer 6 and below the ground layer 7, and then the first signal layer 2a, the second signal layer 2b, and the through hole. 4. The interlayer connection conductor 8 is formed, and a solder resist 34 is formed on the first signal layer as necessary.

  According to the printed wiring board 1 according to the fifth embodiment, since the electronic component 5 and the power supply layer 6 and the ground layer 7 are joined almost directly, the inductance of the electronic component 5 can be reduced. Moreover, according to the 1st manufacturing method of the printed wiring board 1 as shown in FIG. 24, the electronic component 5 and the power supply layer 6 or the ground layer 7 can be metal-bonded at low temperature. Further, according to the second manufacturing method as shown in FIG. 25, the conductor and the insulating layer can be disposed from both surfaces of the electronic component 5. According to the second manufacturing method, the printed wiring board 1 can also be made thinner than in the first manufacturing method.

  In the following examples, an electromagnetic field simulation of the printed wiring board of the present invention will be described. In the electromagnetic field simulation, the EMI or the transmission loss of the printed wiring board was calculated using Sonnet which is an electromagnetic field simulator of the moment method.

In Example 1, the calculation for calculating the magnification for obtaining the suitable range of the surface resistivity of the high loss conductor from the optimum surface resistivity was performed. FIG. 26 is a model of electromagnetic field simulation of the printed wiring board of the present invention. The model of FIG. 26 has a power supply layer 43 in which a lattice-like low-loss conductor 43a is incorporated in a high-loss conductor 43b with a = 150 mm and b = 150 mm on the upper surface, and a ground layer 44 on the lower surface. . Other conditions are that the width of the low-loss conductor is 10 mm, the distance t between the power supply layer 43 and the ground layer is 0.2 mm, and the relative dielectric constant ε _r of the insulating layer 42 is 4.5. 27 and 28 show the results of calculating EMI by electromagnetic field simulation for this model. FIG. 27 shows each EMI when the sheet resistivity ρ (Ω / □) = 0, 0.16, 0.4, 0.8, 1.6 of the high loss conductor 43b, and FIG. Each EMI when the surface resistivity ρ (Ω / □) of the lossy conductor 43b = 1.6, 3.2, 6.4, 16, 32, 64, 128, 256, 1000,> 100 × 10 ³ Show. According to FIG. 27, it is recognized that the surface resistivity ρ giving the minimum value of EMI is about 1.6Ω / □. Further, according to FIG. 28, it is recognized that the surface resistivity ρ giving the minimum value of EMI is 1.6 to 6.4Ω / □. Therefore, according to the conditions of Example 1, the optimum value of the surface resistivity ρ is considered to be 1.6Ω / □. 27 and 28, the difference between the maximum value and the minimum value of EMI is about 50 dB. That is, under the minimum value condition, for example, the surface resistivity ρ = 1.6Ω / □, the EMI can be reduced to about 1/1000.

Further, according to FIG. 27, even when the surface resistivity ρ = 0.16Ω / □, the EMI of the surface resistivity ρ = 0Ω / □ at which the EMI becomes maximum can be reduced by about 20 dB. According to FIG. 28, even when the surface resistivity ρ = 256Ω / □, the EMI when the surface resistivity ρ> 100 × 10 ³ Ω / □ at which the EMI is maximized can be reduced by about 20 dB. Therefore, according to FIGS. 27 and 28, even if the surface resistivity is a value within a range from 0.16Ω / □, which is 1/10 of 1.6Ω / □, to 256Ω / □, which is 160 times greater. It can be seen that the effect of reducing EMI is sufficient.

  This EMI calculation is obtained by observing the strength of the potential of the low-loss conductor in the power supply region, and does not consider the potential of the high-loss conductor. Therefore, when the surface resistivity is high, for example, ρ = 256Ω / □, EMI is observed to be high. Therefore, if the potentials of the low loss conductor and the high loss conductor are averaged, the EMI at ρ = 256Ω / □ is considered to be further reduced.

In Example 2, the influence of the direction of the resonance current on the preferred sheet resistivity was examined. FIG. 29 is a model in which the length a of the power supply layer 43 is approximately half that of the model of the first embodiment, a = 70 mm, and b = 150 mm. Other conditions are the same as those of the model of the first embodiment. . FIG. 30 and FIG. 31 show the results of calculating EMI by electromagnetic field simulation for this model. FIG. 30 shows each EMI when the surface resistivity ρ (Ω / □) = 0, 0.2, 0.5, 1, 2, 4 and FIG. 31 shows the surface resistivity ρ (Ω / □). Each EMI is shown for = 4, 8, 16, 32, 64, 128, 256, 1000,> 100 × 10 ³ . According to FIG. 30, the EMI of ρ = 0.2 Ω / □ is about 20 dB lower than the EMI peak of ρ = 0 Ω / □ near 450 GHz, and the entire graph is gentle. Therefore, even if ρ = 0.2Ω / □, it is considered that there is an effect of reducing EMI. Further, according to FIG. 31, the EMI of ρ = 256Ω / □ is about 20 dB lower than the EMI peak of ρ> 100 × 10 ³ Ω / □ in the vicinity of 400 GHz, and the entire graph is gentle. Therefore, even if ρ = 256Ω / □, it is considered that there is an effect of reducing EMI.

  Therefore, the preferable range of the surface resistivity having the effect of reducing the EMI is the same as that of the model of FIG. From the above, it can be seen that the preferred sheet resistivity ρ is inversely proportional to the dimension L in the resonance current direction of the power supply layer (in this case, the dimension Ln in the longitudinal direction) and is not affected by the dimension Ls in the direction perpendicular to that direction. It was.

In Example 3, the influence of the thickness t of the insulating layer between the power supply layer and the ground layer on the preferred sheet resistivity was examined. 32 and 33 are simulation results of a model in which the thickness t of the insulating layer 42 of the model of the first embodiment is increased by 10 times and the other conditions are the same as those of the first embodiment. FIG. 32 shows EMI when the surface resistivity ρ (Ω / □) = 0, 1.6, 4, 8, 16 and FIG. 33 shows the surface resistivity ρ (Ω / □) = 16, 40. , 80, 160, 320, 640, 1280, 2560, 10 × 10 ³ , and> 100 × 10 ³ . According to FIG. 32, the surface resistivity ρ showing the minimum EMI is 16Ω / □. On the other hand, according to FIG. 33, the sheet resistivity ρ showing the minimum EMI is 16 to 40Ω / □.

  Therefore, in this model, the optimum sheet resistivity is considered to be ρ = 16Ω / □, and the optimum sheet resistivity of this model is 10 times the optimum sheet resistivity of the model of Example 1. It was. From this, it was derived that the optimum sheet resistivity ρ is proportional to the thickness t of the insulating layer.

In Example 4, the influence of the relative dielectric constant ε _r of the insulating layer on the preferred sheet resistivity was examined. 34 and 35 show simulation results of a model in which the relative dielectric constant ε _r of the insulating layer 42 in the model of the first embodiment is set to 18 which is four times, and the other conditions are the same as those in the first embodiment. FIG. 34 shows each EMI when the surface resistivity ρ (Ω / □) = 0, 0.1, 0.2, 0.4, and 0.8, and FIG. 35 shows the surface resistivity ρ (Ω / □). □) = 0.8, 1.6, 4, 8, 16, 32,> 100 × 10 ³ EMI is shown. According to FIG. 34, the sheet resistivity ρ showing the minimum EMI is 0.8Ω / □. On the other hand, according to FIG. 35, the sheet resistivity ρ showing the minimum EMI is 0.8 to 4Ω / □.

Therefore, in this model, the optimum sheet resistivity is considered to be ρ = 0.8Ω / □, and the optimum sheet resistivity of this model is one half of the optimum sheet resistivity of the model of Example 1. Became. From this, it has been derived that the optimum sheet resistivity is inversely proportional to the square root of the dielectric constant ε _r of the insulating layer.

In Example 5, the influence of the ratio of the area of the low-loss conductor on the preferred sheet resistivity was examined. FIGS. 36A to 36F are electromagnetic field simulation models as shown in FIG. 26, and show only the low-loss conductor 43a and the high-loss conductor 43b. In each model, the dimensions of the power supply layer 43 are a = 150 mm, b = 150 mm, the thickness t of the insulating layer 42 is 0.2 mm, the relative dielectric constant ε _r of the insulating layer 42 is 4.5, and the high-loss conductor 43b The surface resistivity ρ is 1.6Ω / □, the low-loss conductor 43a is copper having a thickness of 20 μm, and the length of one side of the entire region of the low-loss conductor 43a is 130 mm. 36 (A) to 36 (C) are models in which a low-loss conductor 43a having a width of 5 mm is assembled in a lattice shape of 5 × 5, 7 × 7, and 13 × 13, and (D) in FIG. The model (F) is a model in which low-loss conductors 43a having a width of 10 mm are assembled in a lattice shape with 3 × 3, 5 × 5, and 7 × 7. Each of the pairs (A) and (D), (B) and (E), and (C) and (F) in the figure has a value with a close area of the low-loss conductor.

FIG. 37 shows the EMI calculation results of the models (A) to (C), and FIG. 38 shows the EMI calculation results of the models (D) to (F). 37 and 38 also show the calculation results when the surface resistivity ρ of the high loss conductor 43b is 0Ω / □ as a (G) comparative model. Comparing FIG. 37 and FIG. 38, the models having a value close to the area of the low loss conductor 43a show almost the same EMI, and the effect of reducing the EMI is smaller as the model of the area of the low loss conductor 43a is larger. It has become. Thus, the upper limit of the area of the low-loss conductor 43a that can effectively reduce EMI is given by the ratio of the maximum area of the low-loss conductor 43a to the area of the power supply layer 43. Both models (C) and (F) where the area of the low-loss conductor 43a is large can reduce EMI by about 20 dB, and the area ratio of the low-loss conductor 43a included in the models (C) and (F) is less than the area ratio. If it exists, it is thought that EMI can be reduced effectively. The area of the low-loss conductor 43a in both models is about 13,000 mm ³ and the area of the power supply layer 43 is 150 mm × 150 mm = 22,500 mm ³ , so the low-loss conductor 43a occupying the power supply layer 43 is The percentage is about 58%. Therefore, in order to efficiently reduce EMI, it is considered that the area of the low-loss conductor 43a is preferably 60% or less of the area of the power supply layer 43.

  An electromagnetic field simulation was performed on the effect of the overlapping pattern of the printed wiring board according to the first embodiment on the transmission loss of the signal layer. In the printed wiring board model, the size of the power supply layer is 150 mm long × 150 mm wide, the distance between the power supply layer and the signal layer is 0.2 mm, and the relative dielectric constant of the insulating layer between the power supply layer and the signal layer is 4.5. The width of the wiring pattern of the signal layer made of copper is set to 0.374 mm so that the characteristic impedance is 50Ω.

  Under this condition, when the wiring pattern length of the signal layer is 200 mm and (i) the width of the overlapping pattern is the same as the width of the wiring pattern, (ii) the width of the overlapping pattern is three times the width of the wiring pattern. In the case of (iii) when there is no overlapping pattern, the comparison result is shown in FIG. According to this, the transmission loss of the signal layer wiring pattern is greatly reduced due to the presence of the overlapping pattern. The reason for this is that when there is no overlapping pattern, the magnetic field generated by the current flowing in the wiring pattern generates eddy currents in the high-loss conductor due to electromagnetic induction, and the eddy current is converted into thermal energy by the resistance of the high-loss conductor. It is thought to change. Moreover, since the electromagnetic induction is larger as the signal frequency is higher, it is considered that the transmission loss increases as the frequency increases. On the other hand, when an overlapping pattern exists, electromagnetic induction of the magnetic field generated by the current flowing in the signal layer wiring pattern generates a return current in the direction opposite to the wiring pattern current in the overlapping pattern, and the overlapping pattern has a low resistivity. Therefore, it is considered that the return current is not lost, and as a result, the transmission loss is reduced.

  As another example of the sixth embodiment, the distance between the power supply layer and the signal layer is 1/4 of the fourth embodiment, 0.04 mm, and the width of the wiring pattern made of copper is 50Ω. FIG. 40 shows the results of the same conditions (i) to (iii) as in Example 6 for the case where 0.076 mm is set and the other conditions are the same as in Example 7. According to this, the transmission loss of the wiring pattern of the signal layer is effectively reduced due to the presence of the overlapping pattern. Here, the transmission loss of the condition (ii) was not greatly reduced compared to the transmission loss of the condition (i). This is because the wiring pattern has a narrow width of 0.076 mm, and thus the resistance value of the wiring pattern itself. This is considered to be due to a major transmission loss.

  For the printed wiring board according to the second embodiment of the present invention, the transmission loss of the signal layer was calculated by electromagnetic field simulation. A model of the printed wiring board is shown in FIG. As shown in FIG. 41, the printed wiring board 41 includes a ground layer 44, a signal layer 45, and a shield layer (a low loss conductor 46 and a high loss conductor 47). The dimensions of the printed wiring board 41 are a = 200 mm, b = 190 mm, and c = 1 mm, and the distance t between the ground layer 44 and the signal layer 45 and the distance between the signal layer 45 and the shield layer are 0.5 mm, respectively. . The shield layer is composed of a low-loss conductor (overlapping pattern) 46 made of copper having a length of lm, a width Wm, and a thickness of 10 to 20 μm, and a high-loss conductor 47 having a surface resistivity of 1Ω / □. Further, the width of the signal layer 45 is Ws, and the relative dielectric constant of the insulating layer 42 is 4.5.

  When the width Ws of the signal layer 45 is 10 mm (characteristic impedance 4.2Ω) and the length lm of the overlapping pattern 46 is 140 mm, (i) the width Wm = 0 mm of the overlapping pattern 46, that is, the overlapping pattern 46 does not exist and is shielded. When the layer is composed only of the high loss conductor 47, the magnitude of the transmission loss was analyzed by electromagnetic field simulation for (ii) Wm = 10 mm and (iii) Wm = 130 mm. FIG. 42 shows the calculation result of the transmission loss of the signal layer 45. According to FIG. 42, the transmission loss of the signal layer 45 is generally small when the width of the overlapping pattern 46 is 10 mm, which is the same as the width of the signal layer 45. When the width of the overlapping pattern 46 is 130 mm, the area ratio of the overlapping pattern 46 to the shield layer is about 48%, but the transmission loss is smaller than when the overlapping pattern 46 does not exist. However, the transmission loss increases rapidly at a specific frequency. This is considered to be caused by the fact that the current flowing through the signal layer 45 causes electromagnetic field resonance in the parallel plate formed by the shield layer and the ground layer 44 and supplies the energy.

  Next, when the width Ws of the signal layer 45 is 2 mm (characteristic impedance 19Ω), (i) the width Wm = 0 mm of the overlapping pattern 46, that is, the overlapping pattern 46 does not exist, and the shield layer is formed only from the high loss conductor 47. (Ii) When the length of the overlapping pattern 46 is lm = 140 mm and the width Wm = 2 mm, (iii) When the length of the overlapping pattern 46 is lm = 200 mm, and the width Wm = 170 mm, and (iv) The shield layer When the entire surface was made of a copper pattern, the magnitude of transmission loss was analyzed by electromagnetic field simulation. FIG. 43 shows the calculation result of the transmission loss of the signal layer 45. According to FIG. 43, in the case of the condition (iv), that is, when there is no high loss conductor 47, the current flowing through the signal layer 45 gives the electromagnetic resonance energy to the parallel plate composed of the shield layer and the ground layer 44. A large transmission loss occurred at a specific frequency for delivery. However, as shown in the graphs of the conditions (i) to (iii), the electromagnetic resonance could be suppressed by installing the high loss conductor 47 in the shield layer. Comparing the conditions (i) to (iii), when the condition (ii), that is, when the width of the overlapping pattern 46 is 2 mm, which is the same as the width of the signal layer 45, the transmission loss was the smallest as a whole. In the case of condition (iii), the area ratio of the overlapping pattern 46 to the shield layer is about 90%. However, since the ratio of the overlapping pattern 46 exceeds 60%, a large transmission loss occurs at a specific frequency. It is considered that this is because the current flowing through the signal layer 45 causes a large electromagnetic resonance in the parallel plate composed of the shield layer and the ground layer 44 and the energy is supplied.

  Next, it is shown by the electromagnetic field simulation that the transmission loss of the signal layer also occurs when another signal layer generates an electromagnetic resonance in the parallel plate. FIG. 44 shows a model of the printed wiring board. In this model, the printed wiring board has a first signal layer 45 a and a second signal layer 45 b, and the shield layer (not shown) includes the first signal layer 45 a and the second signal layer 45 b through the insulating layer 42. Covering. Therefore, the influence between the signal layers 45a and 45b of this model was analyzed by electromagnetic field simulation. As a result, when the electromagnetic resonance frequency of the parallel plate composed of the shield layer and the ground layer 44 is 350 MHz, the second signal layer 45b has a voltage V3 as shown in FIG. 46 according to the value of the termination resistance Rs2. Induced. The equivalent circuit is shown in FIG. 45, and a voltage proportional to the voltage V1 of the electric signal transmitted to the first signal layer 45a is generated in the voltage source. When the width Wm of the overlapping pattern is 2 mm, the induced voltage generated in this voltage source is compared with the case where the width Wm of the overlapping pattern is 170 mm, that is, the ratio of the overlapping pattern to the shield layer is 90%. It became small to about 1/5. Thus, electromagnetic induction noise was generated in the second signal layer 45b because the first signal layer 45a caused electromagnetic field resonance in the parallel plates. This electromagnetic induction noise is reduced by forming a parallel flat shield layer from a high loss conductor and a low loss conductor (overlapping pattern), and reducing the ratio of the low loss conductor to the shield layer to 60% or less. be able to.

  For the printed wiring board according to the fifth embodiment of the present invention, EMI was calculated by electromagnetic field simulation. (I) The model according to the fifth embodiment used in the electromagnetic field simulation is shown in FIG. 20 to FIG. 23. The dielectric constant of the insulating layer 3 is 4.5, and the parallel structure including the power source layer 6 and the ground layer 7 The vertical and horizontal dimensions of the flat plate are 8 mm, the distance between the power supply layer 6 and the ground layer 7 is 0.24 mm, the material of the low loss conductor is copper, the surface resistivity of the high loss conductor 7 b is 2Ω / □, and the electronic component 2 is a 180 pF capacitor. In addition, as a comparison model to be compared with this model (ii), an electromagnetic field simulation was performed on a model having an 8 mm square ground layer 7 made of copper entirely instead of the ground layer 7 having the high loss conductor 7b. The simulation result is shown in FIG. In each model, the parallel plate TM10 mode resonance occurs around 8.7 GHz and the resonance caused by the built-in capacitor element around 4 GHz. (I) In the model according to the fifth embodiment, (ii ) Resonance strength could be reduced by about 30 dB compared to the comparative model. Thus, according to the present invention, it has been shown that EMI can be effectively reduced even for a printed wiring board incorporating an electronic component.

  The matters described above regarding the printed wiring board, such as a suitable surface efficiency range of the high-loss conductor, an area ratio of the low-loss conductor, and the like can be similarly applied to the semiconductor integrated circuit device.

  The concept of the present invention in which a high loss conductor is disposed to reduce EMI and a low loss conductor is disposed to reduce transmission loss is not limited to the printed wiring board and the semiconductor integrated circuit device as described above, Needless to say, the present invention can be applied to other devices and apparatuses having parallel conductor layers.

Schematic of the printed wiring board for demonstrating background art. AA sectional drawing of the printed wiring board shown in FIG. Schematic of the printed wiring board for demonstrating background art. 1 is a top view of a printed wiring board according to a first embodiment of the present invention. BB sectional drawing of the printed wiring board shown in FIG. The top view of the 1st signal layer surface of the printed wiring board shown in FIG.4 and FIG.5. The top view of the power supply layer surface of the printed wiring board shown in FIG.4 and FIG.5. The top view of the ground layer surface of the printed wiring board shown in FIG.4 and FIG.5. The top view of the 2nd signal layer surface of the printed wiring board shown in FIG.4 and FIG.5. The figure which divided the low-loss layer conductor of the power supply layer shown in FIG. The top view of the printed wiring board which concerns on the 2nd Embodiment of this invention. CC sectional drawing of the printed wiring board shown in FIG. The top view of the signal layer surface of the printed wiring board shown in FIG. The top view of the printed wiring board which concerns on the 3rd Embodiment of this invention. DD sectional drawing of the printed wiring board shown in FIG. The top view of the shield layer surface of the printed wiring board shown in FIG.14 and FIG.15. The top view of the signal layer surface of the printed wiring board shown in FIG. The top view of the ground layer surface of the printed wiring board shown in FIG. Sectional drawing of the semiconductor integrated circuit device which concerns on the 4th Embodiment of this invention. The top view of the printed wiring board which concerns on the 5th Embodiment of this invention. The top view of the power supply layer surface of the printed wiring board shown in FIG. The top view of the ground layer surface of the printed wiring board shown in FIG. The top view of the 2nd signal layer surface of the printed wiring board shown in FIG. The figure explaining the 1st manufacturing method of the printed wiring board concerning the 5th Embodiment of this invention. The figure explaining the 2nd manufacturing method of the printed wiring board concerning the 5th Embodiment of this invention. The top view (upper) and EE sectional drawing (lower) of the model of the electromagnetic field simulation in Example 1. FIG. 6 is a graph showing a simulation result in Example 1. 6 is a graph showing a simulation result in Example 1. The top view (upper) and FF sectional drawing (lower) of the model of the electromagnetic field simulation in Example 2. FIG. 6 is a graph showing a simulation result in Example 2. 6 is a graph showing a simulation result in Example 2. 10 is a graph showing simulation results in Example 3. 10 is a graph showing simulation results in Example 3. 10 is a graph showing simulation results in Example 4. 10 is a graph showing simulation results in Example 4. FIG. 10 is a partial top view of an electromagnetic field simulation model in Embodiment 5. 10 is a graph showing simulation results in Example 5. 10 is a graph showing simulation results in Example 5. 10 is a graph showing simulation results in Example 6. 10 is a graph showing simulation results in Example 7. FIG. 10 is a perspective view of an electromagnetic field simulation model according to an eighth embodiment. 10 is a graph showing simulation results in Example 8. 10 is a graph showing simulation results in Example 8. FIG. 10 is a perspective view of an electromagnetic field simulation model in Embodiment 9. FIG. 10 is a schematic diagram showing a simulation result in Example 9. 10 is a graph showing simulation results in Example 9. 10 is a graph showing simulation results in Example 10.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Printed wiring board 2a 1st signal layer 2b 2nd signal layer 3 Insulating layer 3a Clearance 3b Insulating board 3c Fluid-like insulating layer 4 Through hole 5 Electronic component 5a Conductor plate 5b Power supply terminal 5c Ground terminal 6 Power supply layer 6a Low loss conductor 6a (1) Current supply pattern 6a (2) Overlapping pattern 6a (3) Ring pattern 6b High loss conductor 6c Recess 7 Ground layer 7a Low loss conductor 7a (2) Overlapping pattern 7a (3) Ring pattern 7b High loss Conductor 7c Recess 8 Interlayer connection conductor 9 Shield layer 9a Low loss conductor 9b High loss conductor 10 Conductor 11 Junction 21 Semiconductor integrated circuit device 22 Low loss conductor 22a Signal layer 22b Ground layer 22c Overlapping pattern 22d Interlayer connection conductor 23 High Lossy conductor 24 insulating layer 25 silicon substrate 26 source semiconductor film 27 drain semiconductor film 28 current Passage 29 Gate electrode pattern 30 Oxide film insulating layer 31 Etching stopper layer 32 Power supply layer 33 Junction 34 Solder resist 35 Metal foil 36 Heating / pressurizing means 37 Metal substrate 38 Soluble filler 41 Printed wiring board 42 Insulating layer 43 Power supply layer 43a Low loss conductor 43a (1) Port 1
43b (2) Port 2
43b High loss conductor 44 Ground layer 45 Signal layer 45a First signal layer 45b Second signal layer 46 Low loss conductor 47 High loss conductor 51 Printed wiring boards 52a and 52b Signal layer 53 Insulating layer 54 Through hole 55 Electronic component 56 Power supply layer 57 Ground layer 58 Interlayer connection conductor 59 Shield layer

Claims (17)

In a printed wiring board having a first conductor layer, a second conductor layer, and a signal layer arranged in parallel via an insulating layer,
Of the first conductor layer and the second conductor layer, one conductor layer adjacent to the signal layer has a low loss conductor and a high loss conductor having a lossy surface resistivity,
The low loss conductor, have a duplicate pattern are arranged so as to overlap with at least a portion of the wiring pattern of the signal layer,
The dimension of the resonance current direction in which EMI occurs in the first conductor layer or the second conductor layer is L, the distance between the first conductor layer and the second conductor layer is t, and the first conductor layer and the second conductor. The dielectric constant of the insulating layer interposed between the layers is ε _r , the vacuum permeability is μ ₀ = 4π × 10 ⁻⁷ H / m, and the vacuum dielectric constant is ε ₀ = 8.84 × 10 ⁻¹² F / m. , And when
The printed wiring board according to claim 1, wherein the sheet resistivity ρ (Ω / □) of the high loss conductor satisfies the following equation (1) .

When it has a through hole that electrically connects each layer,
The printed wiring board according to claim 1, wherein the low loss conductor has an annular pattern surrounding the through hole.   The printed wiring board according to claim 2, wherein an outer diameter of the annular pattern is in a range of 2 to 7 times a hole diameter of the through hole. The width of the overlapping patterns is the same as the width of the wiring pattern of the signal layer or printed circuit board according to claim 1, characterized in that more. The printed wiring board according to any one of claims 1 to 4 , wherein a ratio of the area of the low-loss conductor to the area of the one conductor layer is 60% or less.   The printed wiring board according to claim 1, wherein the low-loss conductor has a sheet resistivity of 0.25Ω / □ or less. Among the first conductive layer and the second conductive layer, one conductor layer is a power layer connected to a power source, according to claim 1 to 6 in which the other conductive layer, characterized in that a ground layer The printed wiring board as described in any one of Claims. Among the first conductive layer and the second conductive layer, one conductor layer, according to any one of claims 1 to 6, characterized in that a shielding layer that shields the signal layer from external noise Printed wiring board. Printed wiring board according to any one of claims 1-8, characterized in that the electronic component is mounted. The printed wiring board according to claim 9, wherein the one conductor layer adjacent to the signal layer is disposed in a lower region of the electronic component. The printed wiring board according to any one of claims 1 to 10 , wherein an electronic component is built in between the first conductor layer and the second conductor layer. In a semiconductor integrated circuit device having a first conductor layer, a second conductor layer, and a signal layer arranged in parallel via an insulating layer,
Of the first conductor layer and the second conductor layer, one conductor layer adjacent to the signal layer has a low loss conductor and a high loss conductor having a lossy surface resistivity,
The low loss conductor, have a duplicate pattern are arranged so as to overlap with at least a portion of the wiring pattern of the signal layer,
The dimension of the resonance current direction in which EMI occurs in the first conductor layer or the second conductor layer is L, the distance between the first conductor layer and the second conductor layer is t, and the first conductor layer and the second conductor. The dielectric constant of the insulating layer interposed between the layers is ε _r , the vacuum permeability is μ ₀ = 4π × 10 ⁻⁷ H / m, and the vacuum dielectric constant is ε ₀ = 8.84 × 10 ⁻¹² F / m. , And when
The semiconductor integrated circuit device characterized in that the sheet resistivity ρ (Ω / □) of the high loss conductor satisfies the following equation (2) .

When it has a through hole that electrically connects each layer,
13. The semiconductor integrated circuit device according to claim 12 , wherein the low-loss conductor has an annular pattern surrounding the through hole.   14. The semiconductor integrated circuit device according to claim 13, wherein an outer diameter of the annular pattern is in a range of 2 to 7 times a hole diameter of the through hole. 15. The semiconductor integrated circuit device according to claim 12 , wherein a width of the overlapping pattern is equal to or greater than a width of the wiring pattern of the signal layer. 16. The semiconductor integrated circuit device according to claim 12 , wherein a ratio of the area of the low-loss conductor to the area of the one conductor layer is 60% or less. The semiconductor integrated circuit device according to claim 12 , wherein the low-loss conductor has a surface resistivity of 0.25Ω / □ or less.

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