JP6028297B2 - Transmission line structure, multilayer wiring board, semiconductor device, and semiconductor system - Google Patents

Description

  The present invention relates to a transmission line structure, and more particularly to a transmission line structure that exhibits excellent characteristics for high-speed signal transmission. The present invention also relates to a multilayer wiring board including the transmission line structure, or a semiconductor device and a semiconductor system in which a semiconductor integrated circuit is mounted on the multilayer wiring board.

  There is no end to the demand for downsizing and high functionality of electronic devices. In order to meet this demand, semiconductor devices mounted on electronic devices are required to be downsized and highly functional. Note that the semiconductor device refers to an assembly including an integrated circuit and a mounting member (for example, a lead frame, a multilayer wiring board, and a CSP rewiring unit) on which the integrated circuit is mounted.

  High functionality of the semiconductor device is realized by improving the processing speed of the integrated circuit constituting the semiconductor device. An integrated circuit that operates at high speed inputs and outputs a large amount of data in a short time, and the semiconductor device must also cope with this. Specifically, a transmission line structure corresponding to higher-speed signal transmission is required. In many cases, it is necessary to incorporate a capacitor in a semiconductor device including a high-speed IC.

First, a transmission line corresponding to high-speed signal transmission will be described.
A transmission line structure for transmitting a high-speed signal requires two characteristics: that the characteristic impedance is controlled to a value within a certain range in the entire path and that the loss during signal transmission is small.

  An example of a conventional transmission line structure is shown in the sectional view of FIG. The transmission line structure 1000 is formed in a multilayer wiring board 1010. A conductor pattern (first wiring) 1021 and a conductor pattern (second wiring) 1022 for signal transmission are composed of a plurality of conductor layers 1030 and an insulator layer. It is a structure surrounded by 1040. Part or all of the conductor layer 1030 is connected to a power supply potential or a ground potential, and is used as a reference electrode for controlling the characteristic impedance of the transmission line structure. An electromagnetic wave as a high-speed signal is transmitted through the transmission line structure 1000. In the multilayer wiring board, since the reference electrode having a larger area than the signal transmission pattern can be easily arranged, the characteristic impedance is excellently controlled.

  On the other hand, in the transmission line structure in the multilayer wiring board, the signal conductor and the surrounding conductor are farther away or the conductors that are electrically coupled to the signal transmission conductor pattern are smaller in number. Transmission efficiency is improved.

While a signal is transmitted through the transmission line structure, a return current or an eddy current is generated on the surface of the conductor that is electrically coupled to the signal transmission conductor pattern. When these currents flow through the conductor surface, power is consumed by the resistance of the conductor surface, and the power source is the signal power. Therefore, signal loss increases as return current and eddy current occur.
Since the return current and eddy current decrease rapidly in the conductor far from the conductor pattern, the signal transmission efficiency improves as the conductor pattern and the surrounding conductor are further away.
However, moving the signal transmission conductor pattern away from the surrounding electrodes is nothing but moving the reference electrode for controlling the characteristic impedance of the transmission line structure away from the conductor pattern. Therefore, careful consideration is required for the design of the transmission line structure.

Next, incorporation of a capacitor into a semiconductor device will be described.
Supplying a stable power supply is indispensable for stable operation of an IC. Therefore, a capacitor for power supply decoupling is mounted in many semiconductor devices for the purpose of stabilizing the power supply voltage. In some semiconductor devices and mounting members, a capacitor for forming a filter may be mounted.

One suitable method for mounting a capacitor on a semiconductor device is to form a parallel plate capacitor having a MIM (Metal-Insulator-Metal) structure. The MIM structure is a structure in which metal and dielectric thin films are alternately stacked.
The MIM structure capacitor has a smaller parasitic inductance and equivalent series resistance than a discrete component capacitor. For this reason, there are advantages such as an improvement in power supply stabilization performance and a highly accurate filter circuit. In addition, the multilayer wiring board and the MIM structure suitable for the formation of the transmission line structure both have a structure in which metal and dielectric layers are alternately laminated, and it is advantageous that the process has affinity.

As a transmission line structure excellent in high-speed signal transmission characteristics, many inventions that achieve both control of characteristic impedance and reduction of peripheral conductors have been disclosed.
Patent Document 1 is given as one of the inventions. FIG. 18 shows a structure exemplified in Patent Document 1. In the present invention, when forming the transmission line structure 1060 for transmitting a differential signal with the conductor patterns 1021 and 1022 on the multilayer wiring board 1050, the conductor pattern 1021 of the surface layer or the inner conductor layer 1030 of the multilayer wiring board 1050 is formed. An opening 1031 is provided in a portion immediately above and below 1022. The multilayer wiring board 1050 has a base material 1066 made of silicon or the like, and a via 1068 is formed in the insulator layer 1040.
The width of the opening 1031 is also defined from the pattern widths of the conductor patterns 1021 and 1022. By forming the opening 1031, the two conductor patterns 1021 and 1022 are strongly and electrically coupled to each other, but are hardly coupled to the surrounding conductor layer 1030. In this transmission line structure 1060, the characteristic impedance is controlled by strong coupling between the conductor patterns 1021 and 1022, and transmission loss is reduced by suppressing coupling with other conductors.

On the other hand, an invention that attempts to achieve both the formation of a transmission line structure and the incorporation of an MIM capacitor has been disclosed.
One example is the invention disclosed in Patent Document 2. FIG. 19 shows an embodiment of the invention disclosed in Patent Document 2. A high-frequency circuit unit 1080 in which conductor layers 1032 and dielectric insulating layers (insulator layers) 1042 are alternately stacked is added to the surface of the multilayer wiring board 1070. Using this high-frequency circuit unit 1080, a transmission line structure 1090 and an MIM capacitor 1100 are formed.

JP 2007-174075 A JP 2003-264348 A

  However, in the transmission line structure based on the inventions described in Patent Documents 1 and 2, (1) the characteristic impedance is controlled to a value within a certain range over the entire path, and (2) the loss during signal transmission. It was difficult to satisfy all three conditions of being small and (3) having a built-in MIM capacitor.

In general, the strength of the electromagnetic field is inversely proportional to the square of the distance. If the strength of the electromagnetic field of a pair of wirings is less than 1/10 of the other wiring, the other wiring It is considered that the crosstalk (effect due to electromagnetic field coupling between wirings) can be ignored. Therefore, the other conductor layer is separated from the pair of wirings in a direction along the surface of each layer to be stacked at least three times the distance between the pair of wirings.
For this reason, if an MIM capacitor having a sufficient desired capacity is incorporated while satisfying the above-described crosstalk, there is a problem that the transmission line structure becomes large.

  The present invention has been made in view of such problems, and is capable of forming a transmission line applicable to high-speed signal transmission, improving the wiring accommodation density, and maintaining the electrical characteristics of the built-in MIM capacitor while maintaining the outer shape. It is an object of the present invention to provide a transmission line structure capable of realizing an increase in capacitance, and a multilayer wiring board, a semiconductor device, and a semiconductor system including the transmission line structure.

In order to solve the above problems, the present invention proposes the following means.
The transmission line structure of the present invention comprises a base material formed in a plate shape, a power supply conductor layer connected to a power supply potential, a first dielectric layer, and a ground potential provided on one surface of the base material. A first laminated portion in which a GND conductor layer and a second dielectric layer are laminated in this order, and a second laminated layer in which conductor layers and insulator layers are alternately laminated on the second dielectric layer. And a first wiring used for signal transmission formed on the first wiring conductor layer that is one of the plurality of conductor layers, and the one conductor layer of the plurality of conductor layers. A wiring pair formed on the second wiring conductor layer and providing a reference potential to the first wiring, and the power supply conductor layer, the first dielectric layer, and In the cross section that constitutes the MIM capacitor with the GND conductor layer and is orthogonal to the longitudinal direction of the first wiring, The distance between the first wiring and the second wiring is S, the width of the first wiring is W1, the width of the second wiring is W2, the thickness of the first wiring is t1, and the thickness of the second wiring T2 and the length of the first axis along the parallel direction parallel to the one surface is a value obtained by the equation (6S + W1), and the length of the second axis along the thickness direction of the substrate is A value obtained by the equation (2S + t1), and an intersection of the first axis and the second axis passes through the center of gravity of the first wiring and extends in the thickness direction, and the first wiring conductor A first ellipse positioned at the intersection with a straight line that equally divides the layer in the thickness direction, a value of the length of the third axis along the parallel direction determined by the formula (6S + W2), along the thickness direction The length of the fourth axis is a value obtained by the formula (2S + t2), and the intersection of the third axis and the fourth axis is the second alignment. A second ellipse located at the intersection of a straight line that passes through the center of gravity of the second wiring conductor layer and a straight line that equally divides the second wiring conductor layer in the thickness direction. A first boundary line spaced 3S from one end in the parallel direction of the wiring and the second wiring to one side in the parallel direction, and the other end in the parallel direction of the first wiring and the second wiring When the second boundary line separated by 3S from the other in the parallel direction is defined, the first wiring conductor layer is the conductor layer not sandwiched between the first wiring conductor layer and the second wiring conductor layer. And the second laminated portion proximity point closest to the first wiring in the conductor layer excluding the second wiring conductor layer, and the closest distance to the first wiring in the power supply conductor layer Power supply conductor proximity point and the GND All of the GND conductor layer proximity points closest to the first wiring in the conductor layer are arranged outside the first ellipse and the second ellipse, respectively, and the second stacked portion proximity point , At least one of the power conductor layer proximity point and the GND conductor layer proximity point is disposed between the first boundary line and the second boundary line.

In addition, another transmission line structure of the present invention includes a base material formed in a plate shape, a power conductor layer provided on one surface of the base material, connected to a power source potential, a first dielectric layer, a ground A conductor layer and an insulator layer are alternately laminated on the first laminate part in which the GND conductor layer connected to the electric potential and the second dielectric layer are laminated in this order, and the second dielectric layer. A second wiring portion, a first wiring conductor layer that is one of the plurality of conductor layers, the first wiring used for inversion signal transmission, and the plurality of the conductor layers. A wiring pair for differential signal transmission, comprising: a second wiring that is formed in a second wiring conductor layer that is one of the conductor layers and that provides a reference potential to the first wiring; The conductor layer, the first dielectric layer, and the GND conductor layer constitute an MIM capacitor, and the length of the first wiring In a cross section orthogonal to the direction, the distance between the first wiring and the second wiring is S, the width of the first wiring is W1, the width of the second wiring is W2, and the thickness of the first wiring is t1, The thickness of the second wiring is t2, and the length of the first axis along the parallel direction parallel to the one surface is a value obtained by the formula (6S + W1), along the thickness direction of the substrate. The length of the second axis is a value obtained by the expression (2S + t1), and the intersection of the first axis and the second axis passes through the center of gravity of the first wiring and extends in the thickness direction. And the first ellipse located at the intersection of the first wiring conductor layer and the straight line equally dividing in the thickness direction, and the value of the length of the third axis along the parallel direction is obtained by the formula (6S + W2) The length of the fourth axis along the thickness direction is a value obtained by the formula (2S + t2), and the third axis and the front A second ellipse whose intersection with the fourth axis is located at the intersection of a straight line that passes through the center of gravity of the second wiring and extends in the thickness direction and a straight line that equally divides the second wiring conductor layer in the thickness direction , When viewed in the thickness direction, a first boundary line spaced 3S from one end in the parallel direction of the first wiring and the second wiring to one in the parallel direction, and the first wiring and the When a second boundary line separated by 3S from the other end of the second wiring in the parallel direction to the other in the parallel direction is defined, the second wiring is not sandwiched between the first wiring conductor layer and the second wiring conductor layer A second laminated portion proximity point closest to the first wiring among the conductor layers excluding the first wiring conductor layer and the second wiring conductor layer, the conductor layer; Among them, the power supply conductor closest to the first wiring is All of the body layer proximity points and the GND conductor layer proximity points that are closest to the first wiring in the GND conductor layer are disposed outside the first ellipse and the second ellipse, And at least one of said 2nd lamination | stacking part proximity | contact point, said power supply conductor layer proximity | contact point, and said GND conductor layer proximity | contact point is arrange | positioned between said 1st boundary line and said 2nd boundary line. It is said.

In the above transmission line structure, it is more preferable that the width of the portion where the first wiring and the second wiring overlap when viewed in parallel with the thickness direction is zero.
In the above transmission line structure, when viewed in parallel with the thickness direction, the first wiring and the second wiring overlap, and the distance in the parallel direction between the first wiring and the second wiring is More preferably 0.
In the above transmission line structure, the first wiring and the second wiring are arranged on the same conductor layer, and the distance in the thickness direction between the first wiring and the second wiring is zero. It is more preferable.

In the above transmission line structure, it is more preferable that the dielectric constant of the first dielectric layer is larger than the dielectric constants of the second dielectric layer and the insulator layer.
The transmission line structure may further include a through electrode formed in the base material and penetrating in the thickness direction to electrically connect the one surface and the other surface of the base material. preferable.
In the above transmission line structure, it is more preferable that the through electrode is electrically connected to at least one of the first wiring and the second wiring.

Further, in the above transmission line structure, the second conductor layer is provided with a third laminated portion obtained by alternately laminating a second conductor layer and a second insulator layer on the other surface of the base material. More preferably, at least one of is electrically connected to the through electrode on the other surface.
In the above transmission line structure, it is more preferable that the base material is formed of a semiconductor material and an insulating film is provided on the one surface.
In the above transmission line structure, the conductivity of the base material is more preferably 0.001 Ω · cm to 100 Ω · cm.

A multilayer wiring board according to the present invention includes any of the transmission line structures described above.
In the multilayer wiring board, it is more preferable that the first laminated portion is a power supply decoupling capacitor.
Further, in the multilayer wiring board, a surface mounting pad exposed to the outside is provided on the conductor layer which is an outermost layer of the second laminated portion, and at least a part of the surface mounting pad is a first conductor. More preferably, it is electrically connected to the pattern or the second conductor pattern.

In the above-described multilayer wiring substrate, the second conductive layer serving as the outermost layer of the third laminated portion formed by laminating a second conductive layer and a second insulating layer alternately exposed to the outside two More preferably, a next mounting pad is provided.
According to another aspect of the present invention, there is provided a semiconductor device according to any one of the above-described aspects, wherein at least one of the multilayer wiring boards is provided via a surface mounting pad exposed to the outside of the conductor layer that is the outermost layer of the second stacked portion . It is characterized by mounting a semiconductor integrated circuit.
According to another aspect of the present invention, there is provided a semiconductor system including at least one semiconductor integrated circuit connected to the multilayer wiring board described above via a surface mounting pad exposed to the outside of the conductor layer that is the outermost layer of the second laminated portion. A semiconductor device is configured by mounting the semiconductor device, and the semiconductor device is mounted on a second semiconductor device or a second multilayer wiring board via the secondary mounting pad.

  According to the transmission line structure, multilayer wiring board, semiconductor device, and semiconductor system of the present invention, formation of a transmission line applicable to high-speed signal transmission, improvement in wiring accommodation density, and built-in MIM capacitor while maintaining the outer shape An increase in the electric capacity can be realized.

It is sectional drawing of the front of the multilayer wiring board of 1st Embodiment of this invention. It is sectional drawing of cutting line A1-A1 in FIG. It is sectional drawing of the front of the multilayer wiring board of 2nd Embodiment of this invention. FIG. 4 is a cross-sectional view taken along a cutting line A2-A2 in FIG. It is sectional drawing of the side surface of the semiconductor device comprised using the same multilayer wiring board. It is sectional drawing of the front of the multilayer wiring board of 3rd Embodiment of this invention. It is sectional drawing of the cutting line A3-A3 in FIG. It is sectional drawing of the side surface of the semiconductor device comprised using the same multilayer wiring board. It is sectional drawing of the side surface of the semiconductor system comprised using the same multilayer wiring board. It is sectional drawing of the front of the multilayer wiring board of 4th Embodiment of this invention. It is a schematic diagram of the model used for the simulation of the transmission line structure of the multilayer wiring board. It is a figure which shows the result of the simulation of the transmission line structure. It is a schematic diagram of the model used for the simulation of the transmission line structure. It is a figure which shows the result of the simulation of the transmission line structure. It is a schematic diagram of the model used for the simulation of the transmission line structure. It is a figure which shows the result of the simulation of the transmission line structure. It is sectional drawing of the principal part which shows an example of the conventional transmission line structure. It is sectional drawing of the principal part which shows the other example of the conventional transmission line structure. It is sectional drawing of the principal part which shows the other example of the conventional transmission line structure.

  Hereinafter, a transmission line structure according to the present invention, a multilayer wiring board using the transmission line structure, a semiconductor device, a semiconductor system, and manufacturing methods thereof will be described. The embodiment described below is taken up for convenience in order to explain the concept of the invention, and does not limit the embodiment of the invention.

(First embodiment)
As shown in FIG. 1, the multilayer wiring board 1 of the present embodiment includes a base material 10 formed in a plate shape, a first stacked portion 20 provided on one surface 10 a of the base material 10, and a first stacked layer. The second laminated part 30 provided in the part 20 and the third laminated part 40 provided on the other surface 10 b of the base material 10 are provided.
1 has a cross section orthogonal to the longitudinal direction of conductor patterns 35a and 35b described later.

As shown in FIG. 2, the base material 10 is formed with a through electrode 11 that penetrates in the thickness direction D1 of the base material 10 and electrically connects the one surface 10a and the other surface 10b.
As shown in FIG. 1, the first stacked unit 20 includes a power conductor layer 21 connected to a power source potential, a first dielectric layer 22, a GND conductor layer 23 connected to a ground potential, and a second dielectric layer. 24, the power supply conductor layer 21, the first dielectric layer 22, the GND conductor layer 23, and the second dielectric layer 24 are laminated in this order from the one surface 10a side.
Note that the power conductor layer 21, the first dielectric layer 22, and the GND conductor layer 23 of the first stacked unit 20 constitute an MIM capacitor 26 (see FIG. 2).
Two sets of conductor layers 31 and insulator layers 32 are alternately stacked in the second stacked portion 30. That is, the second dielectric layer 24 includes a conductor layer 33, an insulator layer 34, a conductor layer (first wiring conductor layer, second wiring conductor layer) 35, and an insulator layer 36. The conductor layer 33, the insulator layer 34, the conductor layer 35, and the insulator layer 36 are laminated in this order from the side.

The conductor layer 35 is formed with a conductor pattern (first wiring) 35a used for signal transmission and a conductor pattern (second wiring) 35b for providing a reference potential to the conductor pattern 35a. That is, the conductor patterns 35a and 35b are arranged on the same conductor layer 35 so as to extend substantially in parallel with each other, and are used as wiring. In other words, when viewed in parallel with the thickness direction D1, the width of the portion where the conductor pattern 35a and the conductor pattern 35b overlap is set to zero.
The cross sections orthogonal to the longitudinal direction of the conductor patterns 35a and 35b are each formed in a rectangular shape. The thickness of the conductor patterns 35 a and 35 b is equal to the thickness of the conductor layer 35.
The conductor pattern 35a and the conductor pattern 35b constitute a wiring pair 51. The conductor patterns 35a and 35b together with the insulator layer 32 around the conductor patterns 35a and 35b constitute a transmission line structure 52.
The transmission line structure 52 is used as a single-ended transmission line having a characteristic impedance of 50Ω (ohms) (tolerance 10%). The conductor pattern 35a is used for signal transmission, and the conductor pattern 35b is connected to the ground potential.
In addition to the conductor patterns 35a and 35b, conductor patterns 35c and 35d are formed on the conductor layer 35.

  As shown in FIG. 2, an opening 36 a is formed in the insulator layer 36 so as to expose a part of the conductor layer 35. The portion of the conductor layer 35 exposed to the outside from the opening 36a can be used as the surface mounting pad 35e.

As shown in FIG. 1, the second conductor layer 41 and the second insulator layer 42 are alternately stacked in the third stacked portion 40 in pairs. That is, in the third laminated portion 40, the second conductor layer 43, the second insulator layer 44, the second conductor layer 45, and the second insulator layer 46 are arranged from the other surface 10b side to the second conductor layer 43, The second insulator layer 44, the second conductor layer 45, and the second insulator layer 46 are laminated in this order.
As shown in FIG. 2, an opening 46 a is formed in the second insulator layer 46 so as to expose a part of the second conductor layer 45. The portion of the second conductor layer 45 exposed to the outside from the opening 46a can be used as the secondary mounting pad 45a.

  The first laminated portion 20, the second laminated portion 30, and the third laminated portion 40 are electrically connected by the through electrode 11, the via hole 53, and another through electrode (not shown) shown in FIG. Specifically, the conductor pattern 35a is electrically connected to the surface mounting pad 35e, the second conductor layer 43, and the secondary mounting pad 45a via the through electrode 11 or the like.

Next, the characteristic impedance of the multilayer wiring board 1 configured as described above was verified by simulation.
Table 1 shows the physical properties and thickness of each layer.

When a single-ended transmission line using the conductor pattern 35a as a reference electrode was designed under the conditions of Table 1, the width W1 of the conductor pattern 35a and the width W2 of the conductor pattern 35b shown in FIG. The distance S between the pattern 35a and the conductor pattern 35b was calculated to be 40 μm.
As a result, the shape of the conductor placement prohibited area around the conductor patterns 35a and 35b in the cross section shown in FIG. 1 of the transmission line structure 52 is defined as an ellipse having a major axis of 433 μm and a minor axis of 98 μm.
As a result of the optimization of the opening, it was found that there is no need to provide an opening in the first stacked portion 20. As a comparative example, it was calculated that an opening with a width of 338.2 μm was required in the first stacked portion when a configuration without opening optimization was taken.

  The method for realizing the multilayer wiring board 1 according to the first embodiment of the present invention by using a material that seems to be common to those skilled in the art has been described above. However, no matter what material or method is adopted, the present invention can be carried out while maintaining the nature of optimization of the shape of the opening, which is the essence of the present invention.

The conductor patterns 35a and 35b are arranged on the same conductor layer 35, and the width of the portion where the conductor pattern 35a and the conductor pattern 35b overlap when viewed in parallel with the thickness direction D1 is set to zero. For this reason, the conductor patterns 35a and 35b can be configured to be thin in the thickness direction D1.
Since the number of conductor layers 31 and insulator layers 32 necessary for the configuration of the transmission line structure 52 can be reduced, the manufacturing cost can be reduced.

Since the through electrode 11 is formed on the base material 10, wiring for signal transmission and the like can be arranged on one surface 10a and the other surface 10b of the base material 10. Further, when the third laminated portion 40 is formed on the other surface 10b of the base material 10, not only signal transmission wiring but also a large number of conductor patterns for supplying power and ground potential are formed on the third laminated portion 40. it can.
Since the through electrode 11 is electrically connected to the conductor pattern 35 a, a signal transmitted by the conductor pattern 35 a can be transmitted to the other surface 10 b of the substrate 10.
The multilayer wiring board 1 includes a third laminated portion 40, and the second conductor layer 43 is electrically connected to the through electrode 11. For this reason, the lamination | stacking part which has the 2nd conductor layer 41 can be provided not only in the one surface 10a of the base material 10 but in the other surface 10b. And the 2nd conductor layer 43 of the 3rd lamination | stacking part 40 can be electrically connected with one side 10a of the base material 10, and signal transmission etc. can be performed.

  In the present embodiment, for the base material 10, an organic material such as a liquid crystal polymer or a fluororesin, or an inorganic material such as glass can be freely selected. In addition, the electrical connection between the layers can be ensured not by via holes or conformal through holes but by conductive paste vias, and even when they are connected by a mechanical non-contact method such as electromagnetic coupling, when manufacturing multilayer wiring boards No problem occurred in the function of the multilayer wiring board. Also in the formation of the first laminated portion 20, it was possible to use sputtering, low-temperature CVD, or the like for the formation of the conductor layer / dielectric layer.

  In the present embodiment, it is preferable that the dielectric constant of the first dielectric layer 22 is larger than the dielectric constants of the second dielectric layer 24 and the insulator layer 32. With this configuration, it is possible to increase the capacity when the first stacked unit 20 is used as the MIM capacitor 26, more preferably as a power supply decoupling capacitor.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. 3 to FIG. 5, but the same parts as those of the above-described embodiment will be denoted by the same reference numerals, and the description thereof will be omitted. explain.
As shown in FIG. 3, the multilayer wiring board 2 of the present embodiment has a base material instead of the base material 10, the second laminated portion 30, and the third laminated portion 40 of the multilayer wiring board 1 of the first embodiment. 70, and a second laminated portion 80.

The base material 70 has a base 71 made of a semiconductor material such as silicon, an active element region 72 formed on the surface of the base 71, and an insulating film (film) 73 that covers and protects the active element region 72. doing.
The active element region 72 includes an active element and a passive element (not shown), and wiring for connecting the active element and the passive element.

The second laminated portion 80 has a configuration in which a conductor layer 81 and an insulating layer 82 are laminated on the insulator layer 36 of the second laminated portion 30.
In the vicinity of the conductor patterns 35a and 35b, a conductor arrangement prohibition region for prohibiting the arrangement of the conductor layers 31 other than the conductor patterns 35a and 35b is set. When the width of the conductor pattern 35a is W1, the distance between the conductor patterns 35a and 35b is S, and the thickness of the conductor patterns 35a and 35b is t, the conductor placement prohibited area is “the cross section of the first and second conductor patterns. The center of gravity is the focal point, and the lengths of the two axes are respectively defined as the value obtained by the expression (6S + W1) and the elliptical region having the value obtained by the expression (2S + t).
The transmission line structure 52 is used as a single-ended transmission line having a characteristic impedance of 85Ω (tolerance 10%). The conductor pattern 35a is used for signal transmission, and the conductor pattern 35b is connected to the power supply potential.

  In addition to the transmission line structure 52 and the MIM capacitor 26 shown in FIG. 4, an inductor 91 is formed using the conductor layer 35 and a stub 92 is formed using the conductor layer 81 on the multilayer wiring board 2. Yes. These passive components such as the transmission line structure 52 bear a part of the function of the multilayer wiring board 2. In the insulator layer 82, an opening 82a is formed at a position near the ends of the conductor patterns 35a and 35b. A portion of the conductor layer 81 exposed to the outside from the opening 82a is a surface mounting pad 81a.

Next, the characteristic impedance of the multilayer wiring board 2 configured as described above was verified by simulation.
Table 2 shows the thickness and physical properties of each layer.

When a single-ended transmission line was designed under the conditions shown in Table 2, the width W1 of the conductor pattern 35a and the width W2 of the conductor pattern 35b were 5.7 μm, respectively, and the distance S between the conductor pattern 35a and the conductor pattern 35b was 4. It was calculated as 7 μm.
As a result, the shape of the conductor placement prohibited area around the conductor patterns 35a and 35b in the cross section shown in FIG. 3 of the transmission line structure 52 is defined as an ellipse having a major axis of 44.3 μm and a minor axis of 10.9 μm.
As a result of the opening optimization, the width of the opening provided in the first stacked portion 20 was 29.8 μm. On the other hand, in the configuration that does not perform the opening optimization as the comparative example, it was calculated that 33.6 μm was required as the opening width of the first stacked portion. That is, it was confirmed that the opening width of the first stacked portion 20 can be reduced to about 88% by performing the opening optimization.

  In addition, as shown in FIG. 5, the multilayer wiring board 2 of this embodiment separately prepares a multilayer wiring auxiliary board 7 corresponding to the multilayer wiring board 2, and the multilayer wiring board 2 is lead-free on this multilayer wiring auxiliary board 7. The semiconductor device 3 can be configured by connecting and mounting with bumps 97 made of solder.

As described above, according to the multilayer wiring board 2 of the present embodiment, an increase in the electric capacity of the built-in MIM capacitor 26 can be realized.
Further, by forming the insulating film 73 that covers the base 71, it is possible to ensure the insulation of the base material 70 against the direct current. Since the conductivity of the semiconductor substrate 70 does not matter, the conductor layers 21 and 23 of the first laminated portion 20 can block the electromagnetic field associated with signal transmission. This eliminates the need to use an expensive high-resistance wafer, thereby reducing the manufacturing cost of the transmission line structure 52.

As described above, the method for realizing the second embodiment of the present invention by using materials that are considered to be general to those skilled in the art has been described. However, no matter what material or construction method is used, it was possible to carry out the invention while maintaining the characteristics of optimization of the shape of the opening, which is the essence of the present invention.
For example, a single semiconductor material such as silicon or a compound semiconductor material such as gallium nitride can be used as the base material 70 on which the active element is formed, and a transistor made of an organic semiconductor material is formed instead of the base material 70. An organic substrate can also be used.
Moreover, in the 1st lamination | stacking part 20 and the 2nd lamination | stacking part 80, it is also possible to form a conductor layer by screen printing or an inkjet system, and to form a dielectric material layer and an insulator layer by various printing methods.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIGS. 6 to 9, but the same parts as those of the above-described embodiment are denoted by the same reference numerals, and the description thereof will be omitted. explain.
As shown in FIG. 6, the multilayer wiring board 4 of the present embodiment includes a second laminated portion 100 instead of the second laminated portion 30 of the multilayer wiring board 1 of the first embodiment.

In the second stacked unit 100, the conductor pattern 81 b is formed on the conductor layer 81, and the conductor pattern 35 b is formed on the conductor layer 35. That is, the conductor patterns 81b and 35b are arranged on different conductor layers. When viewed in parallel to the thickness direction D1 of the substrate 10, the conductor pattern 81b and the conductor pattern 35b are formed so as to overlap each other.
The cross section orthogonal to the longitudinal direction of the conductor pattern 81b is formed in a rectangular shape. The thickness of the conductor pattern 81 b is equal to the thickness of the conductor layer 81.
The conductor pattern 81b and the conductor pattern 35b constitute a wiring pair 111, and the conductor patterns 81b and 35b together with the insulator layer around the conductor patterns 81b and 35b constitute a transmission line structure 112.

In the vicinity of the conductor patterns 81b and 35b, a conductor arrangement prohibition region for prohibiting the arrangement of conductors other than the conductor pattern is set. The width of the conductor pattern 81b is defined as W1, the thickness is defined as t1, the width of the conductor pattern 35b is defined as W2, the thickness is defined as t2, and the thickness of the insulator layer 36 is defined as t11. At this time, the conductor placement prohibited area is “a value obtained by the expression (2t11 + t1) and the value obtained by the expression (6t11 + W1) with the center of gravity of the cross section of the conductor pattern 81b as the focal point and the lengths of the two axes, respectively. "Oval area" and "Oval shape with the center of gravity of the cross section of the conductor pattern 35b as the focal point, and the lengths of the two axes obtained by the expression (6t11 + W2) and the values obtained by the expression (2t11 + t2), respectively. Are defined as
The conductor pattern 35b is used for inverted signal transmission with respect to the conductor pattern 81b to which a predetermined signal is transmitted. The transmission line structure 112 is used as a differential signal transmission line having a differential impedance of 100Ω (tolerance 10%).

As shown in FIG. 7, a through electrode 14 that electrically connects the first stacked unit 20, the second stacked unit 100, and the third stacked unit 40 is formed in the base material 10.
An opening 82 a is formed in the insulator layer 82 so as to expose a part of the conductor layer 81. Similarly, an opening 46 a is formed in the second insulator layer 46 so as to expose a part of the second conductor layer 45.
The exposed portions of the conductor layer 81 include a surface mounting pad 81c electrically connected to the conductor patterns 81b and 35b, a power supply mounting pad 81d connected to the power supply conductor layer 21, and a GND connected to the GND conductor layer 23. The mounting pad 81e is used. The exposed portion of the second conductor layer 45 can be used as a secondary mounting pad 45a.

Next, the characteristic impedance of the multilayer wiring board 4 configured as described above was verified by simulation.
Table 3 shows the thickness and physical properties of each layer.

When the differential transmission line was designed under the conditions of Table 3, the width W1 of the conductor pattern 81b shown in FIG. 6 was calculated to be 10 μm, and the width W2 of the conductor pattern 35b was calculated to be 8 μm.
As a result, the shape of the conductor placement prohibited area is defined as an ellipse having a major axis of 80 μm and a minor axis of 46 μm.
As a result of the optimization of the opening, the width of the opening provided in the first laminated portion 20 was 28.6 μm. On the other hand, it was calculated that the opening width of the first laminated portion was 70 μm in the configuration in which the opening optimization as in Patent Document 1 as a comparative example was not performed. That is, it was confirmed that the opening width of the first stacked portion 20 can be reduced to about 40% by performing the opening optimization.

In the multilayer wiring board 4 of this embodiment, the semiconductor device 5 can be configured by mounting the semiconductor integrated circuit 8 with gold bumps 117 as shown in FIG.
In this case, the signal pin 121 of the semiconductor integrated circuit 8 is connected to the surface mounting pad 81c, the power supply pin 122 is connected to the power supply mounting pad 81d, and the GND pin 123 is connected to the GND mounting pad 81e. By mounting in this way, the first stacked unit 20 can function as a power supply decoupling capacitor for the semiconductor integrated circuit 8.

  Furthermore, as shown in FIG. 9, the semiconductor device 5 is mounted on another multilayer wiring board (second multilayer wiring board) 9 having a pattern corresponding thereto, with a secondary mounting pad 45a and lead-free solder. The semiconductor system 6 can be configured by mounting via the bumps 118.

The method for realizing the third embodiment of the present invention using the materials considered to be common for those skilled in the art has been described above. However, no matter what material or construction method is used, it was possible to carry out the invention while maintaining the characteristics of optimization of the shape of the opening, which is the essence of the present invention. According to the multilayer wiring board 4 of the present embodiment, an increase in the electric capacity of the built-in MIM capacitor can be realized.
The conductor pattern 81b and the conductor pattern 35b are formed so as to overlap each other when viewed in parallel to the thickness direction D1, so that the conductor patterns 81b and 35b are parallel to the one surface 10a of the substrate 10. While forming in D2 compactly, wiring arrangement density can be raised.

In the present embodiment, a mechanical grade silicon wafer having a conductivity of 0.14 Ω · cm is used as the substrate 10. However, the substrate having a desired conductivity of 0.001 Ω · cm or more and 100 Ω · cm or less can be suitably used.
In addition, for example, the formation of the first stacked unit 20 may be performed not by a vacuum process but by a damascene method or a printing process. Also for the base material 10, a semiconductor silicon wafer is used in this embodiment, but any resin base material or high-resistance semiconductor wafer can naturally be used. The formation of the through electrode 14 is not essential, although it is suitable for mounting on another multilayer wiring board 9. A semiconductor device having a function equivalent to that of the present embodiment can also be obtained by providing a secondary mounting pad on the conductor layer 81 and connecting the secondary mounting pad and the multilayer wiring board 9 by wire bonding.

In the present embodiment, the semiconductor device 5 is configured by mounting one semiconductor integrated circuit 8 on the multilayer wiring substrate 4, but the semiconductor device is configured by mounting two or more semiconductor integrated circuits on the multilayer wiring substrate 4. Also good.
The semiconductor system 5 is configured by mounting the semiconductor device 5 on the multilayer wiring board 9. However, the semiconductor system is configured by mounting the semiconductor device 5 on a semiconductor device (second semiconductor device) different from the semiconductor device 5. May be.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to FIGS. 10 to 16. However, the same parts as those of the above embodiment are denoted by the same reference numerals, and the description thereof will be omitted. Only differences will be described. explain.
As shown in FIG. 10, the multilayer wiring board 2 </ b> A of this embodiment includes a second laminated portion 130 instead of the second laminated portion 80 of the multilayer wiring board 2 of the second embodiment.
The second laminated portion 130 of the present embodiment includes a conductor pattern (first wiring) 81b formed on the conductor layer (first wiring conductor layer) 81 and a conductor formed on the conductor layer (second wiring conductor layer) 35. Pattern (second wiring) 35b.
In this example, the conductor pattern 81b and the conductor pattern 35b are arranged so as not to overlap with the thickness direction D1 of the base material 70 but shifted in a parallel direction D2 parallel to one surface 70a of the base material 70.
The conductor pattern 81b is used for signal transmission, and the conductor pattern 35b provides a reference potential to the conductor pattern 81b.

Here, as will be described below, some rules are made.
First, the width of the conductor pattern 81b is W1, the thickness is t1, the width of the conductor pattern 35b is W2, and the thickness is t2. The distance in the thickness direction D1 between the conductor pattern 81b and the conductor pattern 35b is Sx, the distance in the parallel direction D2 between the conductor pattern 81b and the conductor pattern 35b is Sy, and the square of Sx and Sy obtained by the following equation (1) The average (the square root of the sum of the square of Sx and the square of Sy) is defined as S.

  At this time, the distance between the conductor pattern 81b and the conductor pattern 35b (the distance between the outer periphery of the conductor pattern 81b and the outer periphery of the conductor pattern 35b) is also S.

  Subsequently, a first ellipse E10, a second ellipse E20, a first boundary line R11, a second boundary line R12, a second laminated portion proximity point P1, a power supply conductor layer proximity point P2, and a GND conductor layer proximity point P3 are defined. .

The first ellipse E10 is set to have a first axis E11 along the parallel direction D2 and a second axis E12 along the thickness direction D1. That is, generally, one of the first axis E11 and the second axis E12 is the major axis of the first ellipse E10, and the other is the minor axis.
The length of the first axis E11 is a value obtained by the equation (6S + W1), and the length of the second axis E12 is a value obtained by the equation (2S + t1).
In the first ellipse E10, the intersection point E13 of the first axis E11 and the second axis E12 passes through the center of gravity of the conductor pattern 81b and extends in the thickness direction D1, and the conductor layer 81 is equally divided into two in the thickness direction D1. It arrange | positions so that it may be located in the intersection with the straight line M7 to do. In the present embodiment, the thickness of the conductor pattern 81b is equal to the thickness of the conductor layer 81 other than the conductor pattern 81b, and the cross section of the conductor pattern 81b is formed in a rectangular shape. Therefore, the intersection point E13 is the center of gravity of the conductor pattern 81b. Placed in.

Similarly, the second ellipse E20 is set to have a third axis E21 along the parallel direction D2 and a fourth axis E22 along the thickness direction D1. That is, generally, one of the third axis E21 and the fourth axis E22 is the major axis of the second ellipse E20, and the other is the minor axis.
The length of the third axis E21 is a value obtained by the equation (6S + W2), and the length of the fourth axis E22 is a value obtained by the equation (2S + t2).
In the second ellipse E20, the intersection point E23 of the third axis E21 and the fourth axis E22 passes through the center of gravity of the conductor pattern 35b and extends in the thickness direction D1, and the conductor layer 35 is divided into two in the thickness direction D1. It arrange | positions so that it may be located in the intersection with the straight line M9. In the present embodiment, the thickness of the conductor pattern 35b is equal to the thickness of the conductor layer 35 other than the conductor pattern 35b, and the cross section of the conductor pattern 35b is formed in a rectangular shape, so the intersection E23 is the center of gravity of the conductor pattern 35b. Placed in.

The first boundary line R11 is defined at a position 3S away from the end of one D21 in the parallel direction D2 of the conductor pattern 81b and the conductor pattern 35b as viewed in the thickness direction D1. In this example, since the conductor pattern 81b is disposed on the one D21 side than the conductor pattern 35b, the first boundary line R11 is defined at a position 3S away from the end of the one D21 of the conductor pattern 81b to the one D21. Is done.
Similarly, the second boundary line R12 is defined at a position spaced 3S from the end of the other D22 in the parallel direction D2 of the conductor pattern 81b and the conductor pattern 35b to the other D22 when viewed in the thickness direction D1. In this example, since the conductor pattern 35b is arranged on the other D22 side than the conductor pattern 81b, the second boundary line R12 is defined at a position 3S away from the end of the other D22 of the conductor pattern 81b to the other D22. Is done.

The second stacked portion proximity point P1 is a point having the shortest distance from the conductor pattern 81b in the conductor layer 81 and the conductor layer 31 not sandwiched between the conductor layers 35 except for the conductor patterns 81b and 35b. It is.
Here, the conductor layer 81 and the conductor layer 31 not sandwiched between the conductor layers 35 are arranged outside the conductor layer 81 and the conductor layer 35 in the conductor layer 31 except for the conductor layer 81 and the conductor layer 35. It means the conductor layer 31 to be formed.
In this embodiment, since the conductor layer 31 that is not sandwiched between the conductor layer 81 and the conductor layer 35 is only the conductor layer 33, the second stacked portion proximity point P1 is a distance from the conductor pattern 81b in the conductor layer 33. Is defined as the closest point.

The power conductor layer proximity point P2 is a point in the power conductor layer 21 that is closest to the conductor pattern 81b.
The GND conductor layer proximity point P3 is a point in the GND conductor layer 23 that is closest to the conductor pattern 81b.
The first ellipse E10, the second ellipse E20, the first boundary line R11, the second boundary line R12, the second laminated portion proximity point P1, the power supply conductor layer proximity point P2, and the GND conductor layer proximity point defined as described above. In contrast to P3, in the multilayer wiring board 2A, all the proximity points P1, P2, and P3 are arranged outside the first ellipse E10 and the second ellipse E20, respectively, and all the proximity points P1, P2, and P3 are arranged. Is disposed between the first boundary line R11 and the second boundary line R12.

The wiring accommodation density of the multilayer wiring board 2A configured and manufactured as described above and the electric capacity of the built-in MIM capacitor were examined by electromagnetic field simulation.
In the multilayer wiring board 2A of the present embodiment, the conductor pattern 81b and the conductor pattern 35b are arranged in different conductor layers 31, but in the following, these conductor patterns 81b and 35b are arranged in the same conductor layer 31. The case will be explained.

As a first stage of the simulation, a threshold value of the electric field strength generated on the conductor surface other than the conductor patterns 81b and 35b was determined.
FIG. 11 is a schematic diagram of a model of the transmission line structure 141 used for calculation of the threshold value of the electric field strength. A copper wiring pair composed of conductor patterns 81b and 35b and a conductor layer 31 are provided on the surface of the base material 10 (relative dielectric constant 3.1, thickness 1 mm). In this model, the conductor patterns 81 b and 35 b are formed on the same conductor layer 31. The conductor pattern 81b is used for signal transmission, and the conductor pattern 35b and the conductor layer 31 are used for supplying the installation potential. As a result, the transmission line structure 141 serves as a single-ended transmission line. The widths of both the conductor patterns 81b and 35b were 152 μm, and the distance S between the conductor pattern 81b and the conductor pattern 35b was 25 μm.

  Under this condition, the characteristic impedance of the transmission line structure 141 and the maximum value of the electric field strength on the surface of the conductor layer 31 when the distance d between the conductor layer 31 and the conductor pattern 81b was changed were calculated. The analysis results are shown in FIG. The horizontal axis of the plot is a value obtained by normalizing the distance d by the distance S of the conductor patterns 81b and 35b (a value obtained by dividing the distance d by the distance S), and the vertical axis is the electric field strength on the surface of the conductor layer 31 (left side). , And characteristic impedance (right side). It can be seen that as the conductor layer 31 and the conductor pattern 81b come close to each other and the distance d decreases, the electric field strength increases and the characteristic impedance decreases.

  The threshold value of the electric field strength is determined to be the electric field strength when the distance d is three times the distance S. As a known technique, when a plurality of transmission line structures having a distance between conductor patterns of S are brought close to each other, the distance between the transmission line structures is set to 3S in order to suppress crosstalk due to induced current. (See High Speed Board Layout Layout Guidelines (Altera literature) and Characteristic Impedance Board Manufacturing Standards (Inflow Corporation literature).) This is because a high-speed signal induces a sufficiently small current in a conductor separated from the conductor pattern by three times the distance S or more.

With reference to this threshold value, the minimum distance that a conductor other than the wiring pair can approach is determined with respect to the conductor pattern 81b.
FIG. 13 is a schematic diagram of the transmission line structure 143 used when obtaining the minimum distance that the conductor arranged in the thickness direction can approach the conductor pattern from the simulation. The transmission line structure 141 in FIG. 11 is provided with a conductor layer 31a on the condition that the distance d is three times the distance S. The distance in the thickness direction between the conductor pattern 81b and the conductor layer 31a was defined as h.

FIG. 14 shows the result of calculating the maximum value of the electric field strength on the surface of the conductor layer 31a and the characteristic impedance when the distance h is changed in the model shown in FIG. 14 is the same as that shown in FIG. 12, and the surface electric field strength of the conductor layer 31 when the distance d is three times the distance S in the model of the transmission line structure 141 shown in FIG. Indicated. As shown in FIG. 14, the electric field generated on the surface of the conductor layer 31 a reaches the value indicated by the broken line α when the distance h becomes equal to the distance S. That is, even if the conductor layer 31a adjacent to the conductor pattern 81b in the thickness direction is brought close to the distance h until it becomes equal to the distance S, the loss of the high-speed signal can be sufficiently suppressed.
At this time, the characteristic impedance of the transmission line structure 143 was 45.1Ω, and the fluctuation of the characteristic impedance due to the proximity of the conductor could be suppressed to less than 10% of the initial value.

  FIG. 15 shows a model of the transmission line structure 145 used for calculating the minimum value of the distance between the conductor pattern 81b and the conductor adjacent to the conductor pattern 81b in the direction between the thickness direction and the parallel direction. It is a schematic diagram. The transmission line structure 145 has a distance h equal to the distance S in the transmission line structure 143 shown in FIG. 13, and further includes a conductor layer 31b at a position between the conductor pattern 81b and the conductor layer 31a in the thickness direction. Yes. When the transmission line structure 145 is seen through in the thickness direction of the base material 10, the conductor layer 31b protrudes to the conductor pattern 81b side from the conductor layer 31, and the length of the protrusion is determined to be L.

FIG. 16 shows the length L of the conductor layer 31b installed at a certain position in the thickness direction and the maximum value of the electric field strength generated on the surface of the conductor layer 31b in the transmission line structure 145 shown in FIG. It is an example of a simulation result. On the plot, the surface electric field strength of the conductor layer 31 when the distance d is three times the distance S in the model of the transmission line structure 141 of FIG.
As a result of repeating the above simulation by providing a plurality of levels for the position in the thickness direction of the conductor layer 31b and the protruding length L, the inventors found that the conductor layer 31 has an elliptical first shape with respect to the conductor pattern 81b. It has been found that it is possible to approach the ellipse E10.

The high-speed signal transmission characteristics can be improved by forming the conductor patterns 81b and 35b forming the wiring pair as the conductors closest to each other. At this time, the conductor patterns 81b and 35b are electrically strongly coupled, and the electrical coupling with the conductors included in the first laminated portion 20 and the second laminated portion 130 is weakened.
In the multilayer wiring board 2A of the present embodiment, the second stacked portion proximity point P1, the power supply conductor layer proximity point P2, and the GND conductor layer proximity point P3 are disposed outside the first ellipse E10 and the second ellipse E20, All the proximity points P1, P2, and P3 are arranged between the first boundary line R11 and the second boundary line R12. As a first effect obtained by such a configuration, since the characteristic impedance of the transmission line structure is stabilized, reflection of signals in the transmission line structure is suppressed, and signal transmission efficiency is improved.
As a second effect, crosstalk from the conductor patterns 81b and 35b can be suppressed, and radiation noise from the transmission line structure can be suppressed. Since strong electrical coupling exists between the wiring pairs, the electromagnetic field of the high-speed signal can be confined in a narrow region between the wiring pairs, and leakage of the electromagnetic field to the outside of the transmission line structure can be prevented.
As a third effect, high-speed signal loss can be suppressed. This is induced in these conductors because the electrical coupling with the power source conductor layer 21, the GND conductor layer 23, and the conductor layer 31 which are conductors included in the first laminated portion 20 and the second laminated portion 130 is weakened. This is because the return current and eddy current are suppressed.

  On the other hand, since the range of the distance to be provided between the conductor patterns 81b and 35b forming the wiring pair and the conductors included in the first laminated portion 20 and the second laminated portion 130 is clearly shown, the power supply conductor layer is more than necessary. 21, the GND conductor layer 23 and the conductor layer 31 can be prevented from being separated from the wiring pair. As a result, the area required to form one transmission line structure can be suppressed, so that the wiring density of the multilayer wiring board, the semiconductor device, and the semiconductor system is improved and the area of the MIM capacitor is increased (that is, the electric capacity is increased). Is possible.

Further, the above configuration satisfies all three requirements of (1) control of characteristic impedance of the transmission line structure, (2) improvement of transmission efficiency, and (3) formation of an MIM capacitor having a sufficient capacity. be able to.
The characteristic impedance control of the transmission line structure of (1) is realized by bringing the wiring pairs of the conductor pattern 81b and the conductor pattern 35b used for signal transmission close to each other and having a close electrical coupling.
The improvement of the transmission characteristics of (2) and the formation of the MIM capacitor having a sufficient capacity of (3) are achieved by the conductor layers 81 and 35 belonging to the second laminated portion 100 and the conductor layers sandwiched between the conductor layers 81 and 35. In FIG. 31, the other conductors are sufficiently separated from the signal transmission conductor pattern 81b. On the other hand, in the conductor layers 31 other than the above, the distance between the conductor pattern 81b and the other conductors is set as a transmission characteristic. It is possible to achieve both by shortening within a range where there is no influence.

In the present embodiment, all proximity points P1, P2, and P3 are arranged outside the first ellipse E10 and the second ellipse E20 and between the first boundary line R11 and the second boundary line r12. However, the present invention is not limited to this, and it is sufficient that at least one of the second laminated portion proximity point P1, the power supply conductor layer proximity point P2, and the GND conductor layer proximity point P3 is arranged in this region.
In addition, the multilayer wiring board 2A can constitute a semiconductor device or a semiconductor system, similarly to the multilayer wiring boards of the second embodiment and the third embodiment.

In the present embodiment, originally, in the cross section orthogonal to the longitudinal direction of the conductor patterns 81b and 35b, instead of the ellipses E10 and E20, ellipses (hereinafter referred to as “inclined ellipses”) whose focal points are the centers of gravity of the conductor patterns 81b and 35b, respectively. The transmission line structure can be made more compact if it is defined that all adjacent points P1, P2, and P3 are arranged outside the inclined ellipse. However, in order to make the design easy and to prevent the inclined ellipse from protruding to the first laminated portion, the provisions of the present invention were made.
The conductor patterns 81b and 35b may be used as differential signal transmission lines by transmitting an inverted signal to the conductor pattern 35b with respect to the conductor pattern 81b to which a predetermined signal is transmitted.

  The first to fourth embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and the configuration does not depart from the gist of the present invention. Changes are also included. Furthermore, it goes without saying that the configurations shown in the embodiments can be used in appropriate combinations.

1, 2, 2A, 4 Multilayer wiring board 3, 5 Semiconductor device 6 Semiconductor system 8 Semiconductor integrated circuit 9 Multilayer wiring board (second multilayer wiring board)
DESCRIPTION OF SYMBOLS 10, 70 Base material 10a One side 10b The other side 11, 14 Through electrode 20 First laminated part 21 Power supply conductor layer 22 First dielectric layer 23 GND conductor layer 24 Second dielectric layer 30, 80, 130 Second Laminated portion 31, 33, 81 Conductor layer 32, 34, 36, 82 Insulator layer 35 Conductor layer (first wiring conductor layer, second wiring conductor layer)
35a, 81b Conductor pattern (first wiring)
35b Conductor pattern (second wiring)
40 3rd laminated part 41, 43, 45 2nd conductor layer 42, 44, 46 2nd insulator layer 45a Pad for secondary mounting 51 Wiring pair 52, 141, 143, 145 Transmission line structure 73 Insulation film (film)
81a, 81c Surface mounting pad D1 Thickness direction D2 Parallel direction E10 First ellipse E11 First axis E12 Second axis E13, E23 Intersection E20 Second ellipse E21 Third axis E22 Fourth axis P1 Second stacked portion proximity point P2 Power supply conductor proximity point P3 GND conductor layer proximity point R11 First boundary line R12 Second boundary line

Claims (17)

A base material formed in a plate shape;
A power supply conductor layer, a first dielectric layer, a GND conductor layer connected to a ground potential, and a second dielectric layer, which are provided on one surface of the substrate and are connected to a power supply potential, are laminated in this order. A first laminated portion;
On the second dielectric layer, a second laminated portion formed by alternately laminating conductor layers and insulator layers;
A first wiring formed in a first wiring conductor layer that is one of the plurality of conductor layers and used for signal transmission; and a first wiring layer that is one of the plurality of conductor layers. A wiring pair formed of two wiring conductor layers and comprising a second wiring that provides a reference potential to the first wiring;
With
The power supply conductor layer, the first dielectric layer, and the GND conductor layer constitute an MIM capacitor,
In a cross section orthogonal to the longitudinal direction of the first wiring,
The distance between the first wiring and the second wiring is S, the width of the first wiring is W1, the width of the second wiring is W2, the thickness of the first wiring is t1, and the thickness of the second wiring. Is t2,
The length of the first axis along the parallel direction parallel to the one surface is a value obtained by the formula (6S + W1), and the length of the second axis along the thickness direction of the base material is (2S + t1). And the intersection of the first axis and the second axis passes through the center of gravity of the first wiring and extends in the thickness direction, and the thickness of the first wiring conductor layer A first ellipse located at the intersection with a straight line equally dividing in the vertical direction,
The length of the third axis along the parallel direction is a value obtained by the equation (6S + W2), the length of the fourth axis along the thickness direction is a value obtained by the equation (2S + t2), and The intersection of the third axis and the fourth axis is a straight line that passes through the center of gravity of the second wiring and extends in the thickness direction, and a straight line that equally divides the second wiring conductor layer in the thickness direction. A second ellipse located at the intersection,
As viewed in the thickness direction, a first boundary line spaced 3S from one end in the parallel direction of the first wiring and the second wiring to one in the parallel direction, and the first wiring and the first wiring When defining a second boundary line separated by 3S from the other end of the two wires in the parallel direction to the other in the parallel direction,
The first wiring in the conductor layer that is not sandwiched between the first wiring conductor layer and the second wiring conductor layer, excluding the first wiring conductor layer and the second wiring conductor layer. The second laminated part proximity point with the closest distance to
Power supply conductor layer proximity point that is closest to the first wiring in the power supply conductor layer,
And all of the GND conductor layer proximity points that are closest to the first wiring in the GND conductor layer are arranged outside the first ellipse and the second ellipse, respectively, and the second At least one of a laminated part proximity point, the power supply conductor layer proximity point, and the GND conductor layer proximity point is disposed between the first boundary line and the second boundary line. . A base material formed in a plate shape;
A power supply conductor layer, a first dielectric layer, a GND conductor layer connected to a ground potential, and a second dielectric layer, which are provided on one surface of the substrate and are connected to a power supply potential, are laminated in this order. A first laminated portion;
On the second dielectric layer, a second laminated portion formed by alternately laminating conductor layers and insulator layers;
A first wiring formed on a first wiring conductor layer, which is one of the plurality of conductor layers, and used for inversion signal transmission; and one of the plurality of conductor layers. A second wiring that is formed in the second wiring conductor layer and provides a reference potential to the first wiring, and a wiring pair for differential signal transmission,
With
The power supply conductor layer, the first dielectric layer, and the GND conductor layer constitute an MIM capacitor,
In a cross section orthogonal to the longitudinal direction of the first wiring,
The distance between the first wiring and the second wiring is S, the width of the first wiring is W1, the width of the second wiring is W2, the thickness of the first wiring is t1, and the thickness of the second wiring. T2
The length of the first axis along the parallel direction parallel to the one surface is a value obtained by the formula (6S + W1), and the length of the second axis along the thickness direction of the base material is (2S + t1). And the intersection of the first axis and the second axis passes through the center of gravity of the first wiring and extends in the thickness direction, and the thickness of the first wiring conductor layer A first ellipse located at the intersection with a straight line equally dividing in the vertical direction,
The length of the third axis along the parallel direction is a value obtained by the equation (6S + W2), the length of the fourth axis along the thickness direction is a value obtained by the equation (2S + t2), and The intersection of the third axis and the fourth axis is a straight line that passes through the center of gravity of the second wiring and extends in the thickness direction, and a straight line that equally divides the second wiring conductor layer in the thickness direction. A second ellipse located at the intersection,
As viewed in the thickness direction, a first boundary line spaced 3S from one end in the parallel direction of the first wiring and the second wiring to one in the parallel direction, and the first wiring and the first wiring When defining a second boundary line separated by 3S from the other end of the two wires in the parallel direction to the other in the parallel direction,
The first wiring in the conductor layer that is not sandwiched between the first wiring conductor layer and the second wiring conductor layer, excluding the first wiring conductor layer and the second wiring conductor layer. The second laminated part proximity point with the closest distance to
Power supply conductor layer proximity point that is closest to the first wiring in the power supply conductor layer,
And all of the GND conductor layer proximity points that are closest to the first wiring in the GND conductor layer are arranged outside the first ellipse and the second ellipse, respectively, and the second At least one of a laminated part proximity point, the power supply conductor layer proximity point, and the GND conductor layer proximity point is disposed between the first boundary line and the second boundary line. .   The transmission line structure according to claim 1 or 2, wherein a width of a portion where the first wiring and the second wiring overlap when viewed in parallel with the thickness direction is zero. Construction. In the transmission line structure according to claim 1 or 2,
When viewed in parallel to the thickness direction, the first wiring and the second wiring overlap,
The transmission line structure, wherein a distance between the first wiring and the second wiring in the parallel direction is zero. In the transmission line structure according to any one of claims 1 to 3,
The first wiring and the second wiring are arranged on the same conductor layer,
A transmission line structure, wherein a distance between the first wiring and the second wiring in the thickness direction is zero.   6. The transmission line structure according to claim 1, wherein a dielectric constant of the first dielectric layer is larger than a dielectric constant of the second dielectric layer and the insulator layer. Transmission line structure.   The transmission line structure according to any one of claims 1 to 6, wherein the transmission line structure is formed in the base material and penetrates in the thickness direction to electrically connect the one surface and the other surface of the base material. A transmission line structure comprising a through electrode to be connected.   The transmission line structure according to claim 7, wherein the through electrode is electrically connected to at least one of the first wiring and the second wiring. The transmission line structure according to claim 7 or 8, further comprising a third laminated portion formed by alternately laminating a second conductor layer and a second insulator layer on the other surface of the base material,
At least one of said 2nd conductor layers is electrically connected with the said penetration electrode in said other surface, The transmission line structure characterized by the above-mentioned. In the transmission line structure according to any one of claims 1 to 9,
The substrate is formed of a semiconductor material;
A transmission line structure comprising an insulating film on the one surface.   The transmission line structure according to claim 10, wherein the base material has a conductivity of 0.001 Ω · cm to 100 Ω · cm.   A multilayer wiring board comprising the transmission line structure according to any one of claims 1 to 11.   13. The multilayer wiring board according to claim 12, wherein the first laminated portion is a power supply decoupling capacitor. In the multilayer wiring board according to claim 12 or 13,
A surface mounting pad exposed to the outside is provided on the conductor layer which is the outermost layer of the second laminated portion,
A multilayer wiring board, wherein at least a part of the surface mounting pads is electrically connected to the first wiring or the second wiring.   The multilayer wiring board according to claim 14, wherein the second conductor layer that is the outermost layer of the third laminated portion in which the second conductor layers and the second insulator layers are alternately laminated is exposed to the outside. A multilayer wiring board comprising a secondary mounting pad.   16. The multilayer wiring board according to claim 12, wherein at least one semiconductor integrated circuit is provided via a surface mounting pad exposed to the outside on the conductor layer which is the outermost layer of the second laminated portion. A semiconductor device characterized by mounting. A semiconductor device is mounted by mounting at least one semiconductor integrated circuit on the multilayer wiring board according to claim 15 through a surface mounting pad exposed to the outside on the conductor layer which is the outermost layer of the second laminated portion. Configure
A semiconductor system comprising the semiconductor device mounted on a second semiconductor device or a second multilayer wiring board via the secondary mounting pad.

Images