JP4909384B2 - プロトコルスタックのタイミングの管理 - Google Patents

プロトコルスタックのタイミングの管理 Download PDF

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Publication number
JP4909384B2
JP4909384B2 JP2009165061A JP2009165061A JP4909384B2 JP 4909384 B2 JP4909384 B2 JP 4909384B2 JP 2009165061 A JP2009165061 A JP 2009165061A JP 2009165061 A JP2009165061 A JP 2009165061A JP 4909384 B2 JP4909384 B2 JP 4909384B2
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JP
Japan
Prior art keywords
protocol stack
timing
stack
tunneling
protocol
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Expired - Fee Related
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JP2009165061A
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English (en)
Japanese (ja)
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JP2010088106A (ja
Inventor
ジェイ． ハリマン、デービット
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Intel Corp
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Intel Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/08—Protocols for interworking; Protocol conversion
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46—Interconnection of networks
    • H04L12/4633—Interconnection of networks using encapsulation techniques, e.g. tunneling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/28—Timers or timing mechanisms used in protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/323—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the physical layer [OSI layer 1]

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
JP2009165061A 2008-07-15 2009-07-13 プロトコルスタックのタイミングの管理 Expired - Fee Related JP4909384B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/218,410 US8218580B2 (en) 2008-07-15 2008-07-15 Managing timing of a protocol stack
US12/218,410 2008-07-15

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012004950A Division JP5422005B2 (ja) 2008-07-15 2012-01-13 プロトコルスタックのタイミングの管理

Publications (2)

Publication Number Publication Date
JP2010088106A JP2010088106A (ja) 2010-04-15
JP4909384B2 true JP4909384B2 (ja) 2012-04-04

Family

ID=41057862

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2009165061A Expired - Fee Related JP4909384B2 (ja) 2008-07-15 2009-07-13 プロトコルスタックのタイミングの管理
JP2012004950A Expired - Fee Related JP5422005B2 (ja) 2008-07-15 2012-01-13 プロトコルスタックのタイミングの管理

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2012004950A Expired - Fee Related JP5422005B2 (ja) 2008-07-15 2012-01-13 プロトコルスタックのタイミングの管理

Country Status (6)

Country Link
US (1) US8218580B2 (enExample)
JP (2) JP4909384B2 (enExample)
CN (1) CN101630301B (enExample)
DE (1) DE102009032581B4 (enExample)
GB (1) GB2461802B (enExample)
TW (1) TWI424317B (enExample)

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US9946683B2 (en) 2014-12-24 2018-04-17 Intel Corporation Reducing precision timing measurement uncertainty

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EP2506920B1 (en) 2009-12-01 2016-07-13 Ecole Polytechnique Fédérale de Lausanne Microfabricated surface neurostimulation device and method of making the same
JP5927176B2 (ja) 2010-04-01 2016-06-01 エコーレ ポリテクニーク フェデラーレ デ ローザンヌ （イーピーエフエル） 神経組織と相互作用するためのデバイス、ならびにそれを作製および使用する方法
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US8856420B2 (en) * 2011-12-27 2014-10-07 Intel Corporation Multi-protocol I/O interconnect flow control
US8782321B2 (en) 2012-02-08 2014-07-15 Intel Corporation PCI express tunneling over a multi-protocol I/O interconnect
US8880923B2 (en) 2012-03-29 2014-11-04 Intel Corporation Link power management in an I/O interconnect
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US8549205B1 (en) * 2012-05-22 2013-10-01 Intel Corporation Providing a consolidated sideband communication channel between devices
US8446903B1 (en) * 2012-05-22 2013-05-21 Intel Corporation Providing a load/store communication protocol with a low power physical unit
US8437343B1 (en) 2012-05-22 2013-05-07 Intel Corporation Optimized link training and management mechanism
US8924611B2 (en) 2012-06-26 2014-12-30 Intel Corporation Providing a serial protocol for a bidirectional serial interconnect
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US8972640B2 (en) 2012-06-27 2015-03-03 Intel Corporation Controlling a physical link of a first protocol using an extended capability structure of a second protocol
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US9292039B2 (en) * 2012-09-18 2016-03-22 Amazon Technologies, Inc. Adaptive service timeouts
US9261934B2 (en) 2013-03-15 2016-02-16 Intel Corporation Dynamic response improvement of hybrid power boost technology
US9612643B2 (en) 2014-03-29 2017-04-04 Intel Corporation Controlling the CPU slew rates based on the battery state of charge
CN110585588A (zh) 2014-05-16 2019-12-20 阿莱瓦神经治疗股份有限公司 可植入式微电极装置
US11311718B2 (en) 2014-05-16 2022-04-26 Aleva Neurotherapeutics Sa Device for interacting with neurological tissue and methods of making and using the same
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Publication number Priority date Publication date Assignee Title
US9946683B2 (en) 2014-12-24 2018-04-17 Intel Corporation Reducing precision timing measurement uncertainty

Also Published As

Publication number Publication date
US20100014541A1 (en) 2010-01-21
CN101630301A (zh) 2010-01-20
TW201009585A (en) 2010-03-01
GB0912137D0 (en) 2009-08-26
US8218580B2 (en) 2012-07-10
DE102009032581B4 (de) 2012-05-31
GB2461802B (en) 2012-04-11
GB2461802A (en) 2010-01-20
CN101630301B (zh) 2013-03-13
JP2012105344A (ja) 2012-05-31
JP2010088106A (ja) 2010-04-15
TWI424317B (zh) 2014-01-21
JP5422005B2 (ja) 2014-02-19
DE102009032581A1 (de) 2010-02-04

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