JP4906734B2 - ビデオ処理 - Google Patents

ビデオ処理 Download PDF

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Publication number
JP4906734B2
JP4906734B2 JP2007541436A JP2007541436A JP4906734B2 JP 4906734 B2 JP4906734 B2 JP 4906734B2 JP 2007541436 A JP2007541436 A JP 2007541436A JP 2007541436 A JP2007541436 A JP 2007541436A JP 4906734 B2 JP4906734 B2 JP 4906734B2
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Japan
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execution unit
vector
scalar
stream
data
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Japanese (ja)
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JP2008521097A (ja
Inventor
シリッシュ ガドレ，
アシッシュ カランディカー，
スティーヴン リュウ，
クリストファー， ティー． チェン，
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エヌヴィディア コーポレイション
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Priority claimed from US11/267,700 external-priority patent/US8698817B2/en
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Publication of JP2008521097A publication Critical patent/JP2008521097A/ja
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/85—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
  • Image Analysis (AREA)
JP2007541436A 2004-11-15 2005-11-14 ビデオ処理 Active JP4906734B2 (ja)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US62841404P 2004-11-15 2004-11-15
US60/628,414 2004-11-15
US11/267,875 2005-11-04
US11/267,700 US8698817B2 (en) 2004-11-15 2005-11-04 Video processor having scalar and vector components
US11/267,599 US8416251B2 (en) 2004-11-15 2005-11-04 Stream processing in a video processor
US11/267,638 2005-11-04
US11/267,599 2005-11-04
US11/267,875 US8687008B2 (en) 2004-11-15 2005-11-04 Latency tolerant system for executing video processing operations
US11/267,700 2005-11-04
US11/267,638 US8493396B2 (en) 2004-11-15 2005-11-04 Multidimensional datapath processing in a video processor
PCT/US2005/041329 WO2006055546A2 (fr) 2004-11-15 2005-11-14 Traitement video

Publications (2)

Publication Number Publication Date
JP2008521097A JP2008521097A (ja) 2008-06-19
JP4906734B2 true JP4906734B2 (ja) 2012-03-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007541436A Active JP4906734B2 (ja) 2004-11-15 2005-11-14 ビデオ処理

Country Status (5)

Country Link
EP (1) EP1812928A4 (fr)
JP (1) JP4906734B2 (fr)
KR (5) KR101030174B1 (fr)
CA (1) CA2585157A1 (fr)
WO (1) WO2006055546A2 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0519597D0 (en) * 2005-09-26 2005-11-02 Imagination Tech Ltd Scalable multi-threaded media processing architecture
WO2015035327A1 (fr) * 2013-09-06 2015-03-12 Futurewei Technologies, Inc. Procédé et appareil pour un processeur asynchrone avec un mode rapide et un mode lent
US10275370B2 (en) * 2015-01-05 2019-04-30 Google Llc Operating system dongle
KR102067714B1 (ko) * 2016-11-17 2020-01-17 주식회사 엘지화학 배터리 모듈 및 이를 포함하는 배터리 팩
WO2019173075A1 (fr) * 2018-03-06 2019-09-12 DinoplusAI Holdings Limited Processeur d'intelligence artificielle critique à la mission avec prise en charge de tolérance aux pannes dans de multiples couches
KR102067128B1 (ko) * 2018-06-07 2020-01-16 코츠테크놀로지주식회사 헬스 모니터링 장치 및 이를 포함하는 대화면 시현기
WO2022220835A1 (fr) * 2021-04-15 2022-10-20 Zeku, Inc. Registre partagé pour fichier de registre vectoriel et fichier de registre scalaire

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JPH08153032A (ja) * 1994-11-29 1996-06-11 Matsushita Electric Ind Co Ltd ネットワーク経由データ先読みバッファ方法
JPH08297605A (ja) * 1995-04-26 1996-11-12 Hitachi Ltd データ処理装置、及びそれを用いたシステム
US5574944A (en) * 1993-12-15 1996-11-12 Convex Computer Corporation System for accessing distributed memory by breaking each accepted access request into series of instructions by using sets of parameters defined as logical channel context
JPH09325759A (ja) * 1995-11-22 1997-12-16 Nintendo Co Ltd 高速高効率３ｄグラフィックス及びデジタル音声信号処理を提供するコプロセッサを備える高性能低コストビデオゲームシステム
JPH10222476A (ja) * 1996-10-15 1998-08-21 Samsung Electron Co Ltd Ｍｐｅｇオーディオデコーディング装置およびそのデコーディング方法
US5949410A (en) * 1996-10-18 1999-09-07 Samsung Electronics Company, Ltd. Apparatus and method for synchronizing audio and video frames in an MPEG presentation system
JP2000148695A (ja) * 1998-11-09 2000-05-30 Mitsubishi Electric Corp 幾何学処理プロセッサ、浮動小数点べき乗計算装置およびデータの出力制御装置
JP2001022638A (ja) * 1999-07-05 2001-01-26 Hitachi Ltd 情報処理システム
US20020144061A1 (en) * 1998-12-31 2002-10-03 Cray Inc. Vector and scalar data cache for a vector multiprocessor
JP2003178294A (ja) * 2001-12-12 2003-06-27 Sony Corp 画像処理装置およびその方法
US20030204673A1 (en) * 2002-04-26 2003-10-30 Suresh Venkumahanti Data prefetching apparatus in a data processing system and method therefor
US20040073771A1 (en) * 2002-10-10 2004-04-15 Yen-Kuang Chen Apparatus and method for facilitating memory data access with generic read/write patterns
JP2004252990A (ja) * 2001-03-22 2004-09-09 Sony Computer Entertainment Inc コンピュータ・プロセッサ及び処理装置

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US5574944A (en) * 1993-12-15 1996-11-12 Convex Computer Corporation System for accessing distributed memory by breaking each accepted access request into series of instructions by using sets of parameters defined as logical channel context
JPH0877347A (ja) * 1994-03-08 1996-03-22 Texas Instr Inc <Ti> 画像／グラフィックス処理用のデータ処理装置およびその操作方法
JPH08153032A (ja) * 1994-11-29 1996-06-11 Matsushita Electric Ind Co Ltd ネットワーク経由データ先読みバッファ方法
JPH08297605A (ja) * 1995-04-26 1996-11-12 Hitachi Ltd データ処理装置、及びそれを用いたシステム
US6239810B1 (en) * 1995-11-22 2001-05-29 Nintendo Co., Ltd. High performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing
JPH09325759A (ja) * 1995-11-22 1997-12-16 Nintendo Co Ltd 高速高効率３ｄグラフィックス及びデジタル音声信号処理を提供するコプロセッサを備える高性能低コストビデオゲームシステム
JPH10222476A (ja) * 1996-10-15 1998-08-21 Samsung Electron Co Ltd Ｍｐｅｇオーディオデコーディング装置およびそのデコーディング方法
US5949410A (en) * 1996-10-18 1999-09-07 Samsung Electronics Company, Ltd. Apparatus and method for synchronizing audio and video frames in an MPEG presentation system
JP2000148695A (ja) * 1998-11-09 2000-05-30 Mitsubishi Electric Corp 幾何学処理プロセッサ、浮動小数点べき乗計算装置およびデータの出力制御装置
US20020144061A1 (en) * 1998-12-31 2002-10-03 Cray Inc. Vector and scalar data cache for a vector multiprocessor
JP2001022638A (ja) * 1999-07-05 2001-01-26 Hitachi Ltd 情報処理システム
JP2004252990A (ja) * 2001-03-22 2004-09-09 Sony Computer Entertainment Inc コンピュータ・プロセッサ及び処理装置
JP2003178294A (ja) * 2001-12-12 2003-06-27 Sony Corp 画像処理装置およびその方法
US20030204673A1 (en) * 2002-04-26 2003-10-30 Suresh Venkumahanti Data prefetching apparatus in a data processing system and method therefor
US20040073771A1 (en) * 2002-10-10 2004-04-15 Yen-Kuang Chen Apparatus and method for facilitating memory data access with generic read/write patterns

Also Published As

Publication number Publication date
KR20100093141A (ko) 2010-08-24
KR20090020715A (ko) 2009-02-26
EP1812928A4 (fr) 2010-03-31
KR100880982B1 (ko) 2009-02-03
KR100917067B1 (ko) 2009-09-15
KR101002485B1 (ko) 2010-12-17
KR101084806B1 (ko) 2011-11-21
WO2006055546A9 (fr) 2007-09-27
KR101030174B1 (ko) 2011-04-18
KR20080080419A (ko) 2008-09-03
WO2006055546A2 (fr) 2006-05-26
EP1812928A2 (fr) 2007-08-01
KR20110011758A (ko) 2011-02-08
JP2008521097A (ja) 2008-06-19
WO2006055546A3 (fr) 2008-06-19
CA2585157A1 (fr) 2006-05-26
KR20070063580A (ko) 2007-06-19

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