EP1812928A4 - Traitement video - Google Patents

Traitement video

Info

Publication number
EP1812928A4
EP1812928A4 EP05851664A EP05851664A EP1812928A4 EP 1812928 A4 EP1812928 A4 EP 1812928A4 EP 05851664 A EP05851664 A EP 05851664A EP 05851664 A EP05851664 A EP 05851664A EP 1812928 A4 EP1812928 A4 EP 1812928A4
Authority
EP
European Patent Office
Prior art keywords
video processing
video processor
processing
video
multidimensional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05851664A
Other languages
German (de)
English (en)
Other versions
EP1812928A2 (fr
Inventor
Shirish Gadre
Ashish Karandikar
Stephen Lew
Christopher T Cheng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nvidia Corp
Original Assignee
Nvidia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/267,700 external-priority patent/US8698817B2/en
Application filed by Nvidia Corp filed Critical Nvidia Corp
Publication of EP1812928A2 publication Critical patent/EP1812928A2/fr
Publication of EP1812928A4 publication Critical patent/EP1812928A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/85—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
  • Image Analysis (AREA)
EP05851664A 2004-11-15 2005-11-14 Traitement video Withdrawn EP1812928A4 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US62841404P 2004-11-15 2004-11-15
US11/267,700 US8698817B2 (en) 2004-11-15 2005-11-04 Video processor having scalar and vector components
US11/267,599 US8416251B2 (en) 2004-11-15 2005-11-04 Stream processing in a video processor
US11/267,875 US8687008B2 (en) 2004-11-15 2005-11-04 Latency tolerant system for executing video processing operations
US11/267,638 US8493396B2 (en) 2004-11-15 2005-11-04 Multidimensional datapath processing in a video processor
PCT/US2005/041329 WO2006055546A2 (fr) 2004-11-15 2005-11-14 Traitement video

Publications (2)

Publication Number Publication Date
EP1812928A2 EP1812928A2 (fr) 2007-08-01
EP1812928A4 true EP1812928A4 (fr) 2010-03-31

Family

ID=36407688

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05851664A Withdrawn EP1812928A4 (fr) 2004-11-15 2005-11-14 Traitement video

Country Status (5)

Country Link
EP (1) EP1812928A4 (fr)
JP (1) JP4906734B2 (fr)
KR (5) KR101030174B1 (fr)
CA (1) CA2585157A1 (fr)
WO (1) WO2006055546A2 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0519597D0 (en) * 2005-09-26 2005-11-02 Imagination Tech Ltd Scalable multi-threaded media processing architecture
WO2015035327A1 (fr) * 2013-09-06 2015-03-12 Futurewei Technologies, Inc. Procédé et appareil pour un processeur asynchrone avec un mode rapide et un mode lent
US10275370B2 (en) * 2015-01-05 2019-04-30 Google Llc Operating system dongle
KR102067714B1 (ko) * 2016-11-17 2020-01-17 주식회사 엘지화학 배터리 모듈 및 이를 포함하는 배터리 팩
WO2019173075A1 (fr) * 2018-03-06 2019-09-12 DinoplusAI Holdings Limited Processeur d'intelligence artificielle critique à la mission avec prise en charge de tolérance aux pannes dans de multiples couches
KR102067128B1 (ko) * 2018-06-07 2020-01-16 코츠테크놀로지주식회사 헬스 모니터링 장치 및 이를 포함하는 대화면 시현기
WO2022220835A1 (fr) * 2021-04-15 2022-10-20 Zeku, Inc. Registre partagé pour fichier de registre vectoriel et fichier de registre scalaire

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US5978838A (en) * 1996-08-19 1999-11-02 Samsung Electronics Co., Ltd. Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor
US6239810B1 (en) * 1995-11-22 2001-05-29 Nintendo Co., Ltd. High performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing

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US4541046A (en) * 1981-03-25 1985-09-10 Hitachi, Ltd. Data processing system including scalar data processor and vector data processor
US4985848A (en) * 1987-09-14 1991-01-15 Visual Information Technologies, Inc. High speed image processing system using separate data processor and address generator
US4965716A (en) * 1988-03-11 1990-10-23 International Business Machines Corporation Fast access priority queue for managing multiple messages at a communications node or managing multiple programs in a multiprogrammed data processor
US4958303A (en) * 1988-05-12 1990-09-18 Digital Equipment Corporation Apparatus for exchanging pixel data among pixel processors
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JPH0795766B2 (ja) * 1989-06-30 1995-10-11 株式会社日立製作所 デジタル・データ通信装置及びそれに使用するデータ通信アダプタ
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JPH0877347A (ja) * 1994-03-08 1996-03-22 Texas Instr Inc <Ti> 画像／グラフィックス処理用のデータ処理装置およびその操作方法
JPH08153032A (ja) * 1994-11-29 1996-06-11 Matsushita Electric Ind Co Ltd ネットワーク経由データ先読みバッファ方法
JP3619565B2 (ja) * 1995-04-26 2005-02-09 株式会社ルネサステクノロジ データ処理装置、及びそれを用いたシステム
KR100262453B1 (ko) * 1996-08-19 2000-08-01 윤종용 비디오데이터처리방법및장치
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US6239810B1 (en) * 1995-11-22 2001-05-29 Nintendo Co., Ltd. High performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing
US5978838A (en) * 1996-08-19 1999-11-02 Samsung Electronics Co., Ltd. Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor

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Also Published As

Publication number Publication date
KR20100093141A (ko) 2010-08-24
KR20090020715A (ko) 2009-02-26
KR100880982B1 (ko) 2009-02-03
KR100917067B1 (ko) 2009-09-15
KR101002485B1 (ko) 2010-12-17
KR101084806B1 (ko) 2011-11-21
WO2006055546A9 (fr) 2007-09-27
KR101030174B1 (ko) 2011-04-18
KR20080080419A (ko) 2008-09-03
WO2006055546A2 (fr) 2006-05-26
EP1812928A2 (fr) 2007-08-01
JP4906734B2 (ja) 2012-03-28
KR20110011758A (ko) 2011-02-08
JP2008521097A (ja) 2008-06-19
WO2006055546A3 (fr) 2008-06-19
CA2585157A1 (fr) 2006-05-26
KR20070063580A (ko) 2007-06-19

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