EP1812928A4 - Video processing - Google Patents

Video processing

Info

Publication number
EP1812928A4
EP1812928A4 EP05851664A EP05851664A EP1812928A4 EP 1812928 A4 EP1812928 A4 EP 1812928A4 EP 05851664 A EP05851664 A EP 05851664A EP 05851664 A EP05851664 A EP 05851664A EP 1812928 A4 EP1812928 A4 EP 1812928A4
Authority
EP
European Patent Office
Prior art keywords
video processing
video processor
processing
video
scalar
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05851664A
Other languages
German (de)
French (fr)
Other versions
EP1812928A2 (en
Inventor
Shirish Gadre
Ashish Karandikar
Stephen Lew
Christopher T Cheng
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nvidia Corp
Original Assignee
Nvidia Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US62841404P priority Critical
Priority to US11/267,599 priority patent/US8416251B2/en
Priority to US11/267,875 priority patent/US8687008B2/en
Priority to US11/267,700 priority patent/US8698817B2/en
Priority to US11/267,638 priority patent/US8493396B2/en
Application filed by Nvidia Corp filed Critical Nvidia Corp
Priority to PCT/US2005/041329 priority patent/WO2006055546A2/en
Publication of EP1812928A2 publication Critical patent/EP1812928A2/en
Publication of EP1812928A4 publication Critical patent/EP1812928A4/en
Application status is Withdrawn legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/20Processor architectures; Processor configuration, e.g. pipelining
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3887Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by a single instruction, e.g. SIMD
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/60Memory management
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/436Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/44Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/85Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression

Abstract

A latency tolerant system for executing video processing operations is described. So too is a stream processing in a video processor, a video processor having scalar and vector components and multidimensional datapath processing in a video processor.
EP05851664A 2004-11-15 2005-11-14 Video processing Withdrawn EP1812928A4 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US62841404P true 2004-11-15 2004-11-15
US11/267,599 US8416251B2 (en) 2004-11-15 2005-11-04 Stream processing in a video processor
US11/267,875 US8687008B2 (en) 2004-11-15 2005-11-04 Latency tolerant system for executing video processing operations
US11/267,700 US8698817B2 (en) 2004-11-15 2005-11-04 Video processor having scalar and vector components
US11/267,638 US8493396B2 (en) 2004-11-15 2005-11-04 Multidimensional datapath processing in a video processor
PCT/US2005/041329 WO2006055546A2 (en) 2004-11-15 2005-11-14 A video processor having a scalar component controlling a vector component to implement video processing

Publications (2)

Publication Number Publication Date
EP1812928A2 EP1812928A2 (en) 2007-08-01
EP1812928A4 true EP1812928A4 (en) 2010-03-31

Family

ID=36407688

Family Applications (1)

Application Number Title Priority Date Filing Date
EP05851664A Withdrawn EP1812928A4 (en) 2004-11-15 2005-11-14 Video processing

Country Status (5)

Country Link
EP (1) EP1812928A4 (en)
JP (1) JP4906734B2 (en)
KR (5) KR101002485B1 (en)
CA (1) CA2585157A1 (en)
WO (1) WO2006055546A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0519597D0 (en) * 2005-09-26 2005-11-02 Imagination Tech Ltd Scalable multi-threaded media processing architecture
US10042641B2 (en) 2013-09-06 2018-08-07 Huawei Technologies Co., Ltd. Method and apparatus for asynchronous processor with auxiliary asynchronous vector processor
US20160196220A1 (en) * 2015-01-05 2016-07-07 Google Inc. Operating system dongle
KR20180055407A (en) * 2016-11-17 2018-05-25 주식회사 엘지화학 Battery module and battery pack including the same

Citations (2)

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US5978838A (en) * 1996-08-19 1999-11-02 Samsung Electronics Co., Ltd. Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor
US6239810B1 (en) * 1995-11-22 2001-05-29 Nintendo Co., Ltd. High performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing

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US4101960A (en) * 1977-03-29 1978-07-18 Burroughs Corporation Scientific processor
US4541046A (en) * 1981-03-25 1985-09-10 Hitachi, Ltd. Data processing system including scalar data processor and vector data processor
US4985848A (en) * 1987-09-14 1991-01-15 Visual Information Technologies, Inc. High speed image processing system using separate data processor and address generator
US4965716A (en) * 1988-03-11 1990-10-23 International Business Machines Corporation Fast access priority queue for managing multiple messages at a communications node or managing multiple programs in a multiprogrammed data processor
US4958303A (en) * 1988-05-12 1990-09-18 Digital Equipment Corporation Apparatus for exchanging pixel data among pixel processors
US5210834A (en) * 1988-06-01 1993-05-11 Digital Equipment Corporation High speed transfer of instructions from a master to a slave processor
US5040109A (en) * 1988-07-20 1991-08-13 Digital Equipment Corporation Efficient protocol for communicating between asychronous devices
JPH0795766B2 (en) * 1989-06-30 1995-10-11 日立エンジニアリング株式会社 Digital data communication apparatus and data communication adapter to be used with it
US5179530A (en) * 1989-11-03 1993-01-12 Zoran Corporation Architecture for integrated concurrent vector signal processor
US5418973A (en) * 1992-06-22 1995-05-23 Digital Equipment Corporation Digital computer system with cache controller coordinating both vector and scalar operations
EP0607988B1 (en) * 1993-01-22 1999-10-13 Matsushita Electric Industrial Co., Ltd. Program controlled processor
US5574944A (en) * 1993-12-15 1996-11-12 Convex Computer Corporation System for accessing distributed memory by breaking each accepted access request into series of instructions by using sets of parameters defined as logical channel context
JPH0877347A (en) * 1994-03-08 1996-03-22 Texas Instr Inc <Ti> Data processor for processing image/graphics and operating method therefor
JPH08153032A (en) * 1994-11-29 1996-06-11 Matsushita Electric Ind Co Ltd Data look-ahead buffer method via network
JP3619565B2 (en) * 1995-04-26 2005-02-09 株式会社ルネサステクノロジ Data processing apparatus, and a system using the same
KR100262453B1 (en) * 1996-08-19 2000-08-01 윤종용 Method and apparatus for processing video data
US5812147A (en) * 1996-09-20 1998-09-22 Silicon Graphics, Inc. Instruction methods for performing data formatting while moving data between memory and a vector register file
US5893066A (en) * 1996-10-15 1999-04-06 Samsung Electronics Co. Ltd. Fast requantization apparatus and method for MPEG audio decoding
US5949410A (en) * 1996-10-18 1999-09-07 Samsung Electronics Company, Ltd. Apparatus and method for synchronizing audio and video frames in an MPEG presentation system
JP3983394B2 (en) * 1998-11-09 2007-09-26 株式会社ルネサステクノロジ Geometry processor
US6496902B1 (en) * 1998-12-31 2002-12-17 Cray Inc. Vector and scalar data cache for a vector multiprocessor
JP3639464B2 (en) * 1999-07-05 2005-04-20 株式会社ルネサステクノロジ Information processing system
US7093104B2 (en) * 2001-03-22 2006-08-15 Sony Computer Entertainment Inc. Processing modules for computer architecture for broadband networks
JP3840966B2 (en) * 2001-12-12 2006-11-01 ソニー株式会社 Image processing apparatus and method
US7305540B1 (en) * 2001-12-31 2007-12-04 Apple Inc. Method and apparatus for data processing
US6785772B2 (en) * 2002-04-26 2004-08-31 Freescale Semiconductor, Inc. Data prefetching apparatus in a data processing system and method therefor
US6957317B2 (en) * 2002-10-10 2005-10-18 Intel Corporation Apparatus and method for facilitating memory data access with generic read/write patterns
US20060064517A1 (en) * 2004-09-23 2006-03-23 Honeywell International Inc. Event-driven DMA controller

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6239810B1 (en) * 1995-11-22 2001-05-29 Nintendo Co., Ltd. High performance low cost video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing
US5978838A (en) * 1996-08-19 1999-11-02 Samsung Electronics Co., Ltd. Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor

Also Published As

Publication number Publication date
WO2006055546A2 (en) 2006-05-26
KR101002485B1 (en) 2010-12-17
CA2585157A1 (en) 2006-05-26
KR100880982B1 (en) 2009-02-03
KR101030174B1 (en) 2011-04-18
KR20070063580A (en) 2007-06-19
KR20080080419A (en) 2008-09-03
KR20100093141A (en) 2010-08-24
KR20110011758A (en) 2011-02-08
KR20090020715A (en) 2009-02-26
KR101084806B1 (en) 2011-11-21
EP1812928A2 (en) 2007-08-01
JP2008521097A (en) 2008-06-19
WO2006055546A9 (en) 2007-09-27
WO2006055546A3 (en) 2008-06-19
KR100917067B1 (en) 2009-09-15
JP4906734B2 (en) 2012-03-28

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RIC1 Classification (correction)

Ipc: G06F 12/02 20060101AFI20080724BHEP

Ipc: G09G 5/36 20060101ALI20080724BHEP

Ipc: G09G 5/39 20060101ALI20080724BHEP

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Ipc: G06F 15/00 20060101ALI20100225BHEP

Ipc: G06F 12/02 20060101AFI20080724BHEP

Ipc: G06T 1/20 20060101ALI20100225BHEP

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