JP4902511B2 - High-speed testing of semiconductor integrated circuits - Google Patents

Description

  The present invention relates to a high-speed test of a semiconductor integrated circuit, and more particularly to a test leak detection means for a high-speed test between flip-flops.

  An LSI tester is used to confirm whether the logic of the semiconductor integrated circuit operates correctly at a desired frequency. The LSI tester verifies the operation by executing a test pattern prepared in advance. Specifically, a path from one flip-flop to another flip-flop is operated at a desired frequency, and if the data can be transferred correctly, it is determined that the path has operated normally.

  This is performed for all the paths in the semiconductor integrated circuit, and when all the paths operate normally, the tested semiconductor integrated circuit is determined to be a non-defective product.

  A test pattern is separately created by a designer, and is loaded into an LSI tester for execution. In general, the test pattern is created so as to include a path (critical path) having a large delay time and close to the limit frequency of the product. In order to perform the test more efficiently, for example, Patent Document 1 proposes a method for extracting a critical path based on physical information and performing the test without excess or deficiency. By limiting the critical path, an efficient test pattern is generated, and an improvement effect is expected in terms of quality, development schedule, and cost.

JP 2005-308471 A

  Usually, a test pattern is created so that a path considered to be a critical path is always tested. A path that is not considered to be a critical path is not necessarily included in the test pattern. However, if it is determined that the path is a critical path, the path to be tested may not be tested. Even if it is considered that the test pattern includes a critical path, there is a possibility that the path is not actually tested. If such an untested path does not reach the desired operating frequency, it is erroneously determined to be a good product even if it is inspected by the LSI tester.

  In the unlikely event that the path to be tested is not tested, a defect will be detected for the first time by the user after the shipment of the semiconductor integrated circuit product. Finding a new path is not always easy.

  For example, in FIG. 2, there are paths from flip-flops 201 to 208, 209, and 210, and there are two paths from 201 to 208, so there are a total of four paths. If it is determined that only the path from 201 to 208 via the gate 205 is a critical path, the test pattern is created to activate this path, but the other paths are not necessarily activated. If the path from 201 to 210 is not tested despite the critical path, a defect will be detected under the user after the product is shipped. However, since there is no means for detecting an untested path, it may take time to find a defective path.

  The present invention provides a means for extracting a path that has not been tested, regardless of whether it is a critical path. By feeding this information back to the designer, the designer is given an opportunity to correct the test pattern before shipping the product, and the problem of reliably testing the critical path is solved.

  Each flip-flop in the semiconductor integrated circuit is provided with a terminal called a determination terminal, which is different from a normal data output terminal. The determination terminal continues to output “1” when the data output terminal is inverted from “0” to “1” or “1” to “0” after the test is started. In a path between certain flip-flops, if both the determination terminals of the start and end flip-flops output “1”, it is determined that the path has been tested. If it remains “0” after the end of the test, it means that no data inversion has occurred at the data output terminal of the flip-flop, and it is determined that the path including the flip-flop has not been tested.

  In addition, when the start point flip-flop and the end point flip-flop are the same and there are a plurality of paths, each wiring is drawn out from the input terminal of the gate where the paths merge, and each wiring is input to a separate counter. Each counter outputs “1” if the input data is inverted from “0” to “1” or “1” to “0” at least once. As with the determination terminal of the flip-flop, if “1” is output, it is determined that the wiring has been tested.

  If the decision terminal of each flip-flop or the wiring from the counter output is distributed and input to several NAND gates and all NAND gate outputs are “0”, all paths in the semiconductor integrated circuit are tested. Judge that If the output of the NAND gate is “1”, it means that there is a path that is not tested because the data is not inverted between the flip-flops. In this case, it is possible to prevent test leakage by adding a test pattern so as to activate the path. If the path is not a critical path and does not require testing, no action is required.

  According to the present invention, when a high-speed test pattern is executed on a certain semiconductor integrated circuit, it can be determined where all paths have been tested or where there are untested paths. If it is determined that the test is missing, the designer adds a pattern that activates the path to the test pattern. As a result, all the paths that need to be tested can be tested, and the quality of the semiconductor integrated circuit can be improved.

  Below, the form for implementing this invention is shown.

  FIG. 1 shows an embodiment of a test between flip-flops according to the present invention. In FIG. 1, if the flip-flop 101 is the start point of the test path, there are three flip-flops 108, 109, and 110 as end points. Since there are two paths to the end point 108, there are a total of four test paths in FIG. A method for confirming whether all four paths have been tested when an operation test is performed on an actual semiconductor integrated circuit will be described.

  In addition to data output, determination terminals 151, 152, 153, and 154 are prepared for the flip-flops 101, 108, 109, and 110, and wirings 128, 129, 130, and 131 are connected thereto, respectively. These four wirings are input to the NAND gate 111. Each flip-flop outputs data in synchronization with the clock, but the clock terminal is omitted in the flip-flop of FIG. The determination terminals 151 to 154 output “1” when the data output terminals 141 to 144 of the flip-flops are switched from “0” to “1” or “1” to “0”, respectively. When the data output terminals 141 to 144 are fixed to “0” or “1”, the corresponding determination terminals 151 to 154 output “0”. When all of the output terminals 151 to 154 are “1”, “1” is transmitted to the wirings 128 to 131, and thus “0” is output to the output-side wiring 132 of the NAND gate 111. At this time, since all flip-flops are used and data is inverted, it is determined that all flip-flops have been tested. On the other hand, when “0” is output from at least one of the determination terminals 151 to 154, “0” is transmitted to the corresponding wiring among the wirings 128 to 131. “1” is output to 132. At this time, since the data is not inverted by at least one flip-flop, it is considered that the flip-flop continues to output the same data regardless of the clock frequency. Therefore, it is determined that the flip-flop has not been tested.

  In FIG. 1, there are two paths from the flip-flops 101 to 108, a path through the gate 102 and a path through the gates 103 and 105. In the above logic, even if only one path is tested, the decision terminal 152 of the flip-flop 108 outputs “1”. In order to prevent this, in FIG. 1, the wires 133 and 134 are drawn out immediately before the gate 106 and connected to the counters 112 and 113, respectively. The counters 112 and 113 count the number of times the wirings 133 and 134 are switched from “0” to “1” or “1” to “0”, respectively. 1 "is output. When “1” is transmitted to both the wirings 135 and 136, “0” is output to the output-side wiring 137 of the NAND gate 114. At this time, it is determined that both of the two paths from the flip-flops 101 to 108 have been tested. On the other hand, when “0” is transmitted to at least one of the wirings 135 and 136, “1” is output to the output-side wiring 137 of the NAND gate 114. At this time, at least one of the two paths from the flip-flops 101 to 108 has no data inversion, so it is determined that the test has not been performed.

  In FIG. 1, when both NAND gates 132 and 137 output “0”, it is determined that they have been normally tested. When a plurality of such NAND gates are arranged in the semiconductor integrated circuit and all of them output “0”, it is determined that the test of the entire semiconductor integrated circuit has been performed normally.

  After the test is completed, by inputting a reset signal to the reset input terminals 161 to 166 of each flip-flop and counter, the results so far are reset, and another test pattern can be continuously executed.

  FIG. 3 shows a second embodiment.

  FIG. 3 shows a waveform in which a serial identification signal is added before the transfer data. This serial identification signal is different in each flip-flop path. For example, the flip-flop 201 in FIG. 2 outputs a data signal including this identification signal, and the flip-flop 208 receives these signals. If the identification signal received at 208 matches the identification signal output at 201, it is determined that the flip-flops 201-208 have been tested. Similarly, different identification signals are given between 201 to 209 and 201 to 210, respectively, and if the identification signals match at the start and end flip-flops after the test is completed, the test between these flip-flops is performed. Judge that it was implemented.

  In FIG. 2, there are two paths between 201 and 208. Also in such a case, different identification signals are given to the respective paths, and when 208 receives both identification signals, it is determined that both paths have been tested. When the identification signal designates a path passing through the wiring 222, the path passing through the wiring 223 is not opened.

  Since the identification signal is not a test pattern, one bit does not need to be one cycle. In order to reliably transfer the identification signal, for example, as shown in FIG.

  The present invention is particularly useful as a means for detecting an untested path between flip-flops in a high-speed test of a semiconductor integrated circuit.

It is the figure which showed the characteristic of this invention provided with the path | pass between flip-flops, the determination terminal of the flip-flop, the counter, and the NAND gate. It is the figure which showed the conventional path | pass between flip-flops. It is a figure which shows the waveform which added the identification signal of the path | pass between flip-flops before the transfer data.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101,108-110 ... Flip-flop, 102-107 ... Gate, 111, 114 ... NAND gate, 112-113 ... Counter, 121-138 ... Wiring, 141-144 ... Data output terminal, 151-154 ... Determination terminal, 161 ˜166, reset input terminal, 201, 208-210, flip-flop, 202-207, gate, 221-227, wiring.

Claims (4)

In high-speed testing of semiconductor integrated circuits,
When the data output terminal of each flip-flop is inverted from “0” to “1” or “1” to “0” at least once after the test starts, “1” continues to be output. If there is no change, continue to output “0”.
A high-speed test of a semiconductor integrated circuit, wherein each flip-flop has another output terminal (referred to as a determination terminal). Each wiring taken out from the determination terminal of each flip-flop according to claim 1 is input to one or a plurality of NAND gates,
If the output of the NAND gate is “0” after the high-speed test, the corresponding flip-flop means that the data output has been inverted,
A high-speed test of a semiconductor integrated circuit, characterized in that it can be determined that a high-speed test is performed between flip-flops. If there are multiple paths between flip-flops with the same start and end points,
In order to determine whether all of the paths have been tested, separate wirings are drawn from immediately before the input terminals of the gates where the paths merge.
If the wiring input to each counter is inverted from “0” to “1” or “1” to “0” at least once after the test starts, the counter outputs “1”. Continue
A high-speed test of a semiconductor integrated circuit characterized in that it can be determined whether or not all paths between the same flip-flops have been tested by continuing to output “0” when there is no data inversion in the input wiring. In the determination terminal of the flip-flop in claim 1 and the output terminal of the counter in claim 3,
A high-speed test of a semiconductor integrated circuit, wherein each flip-flop and counter are provided with reset input terminals in order to return the output data to “0” after completion of the high-speed test.

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