JP5803561B2 - Logic circuit failure detection method, test circuit insertion method, test circuit insertion device, and semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a failure detection method for a logic circuit, a test circuit insertion method, a test circuit insertion device, and a semiconductor integrated circuit.

  In a semiconductor integrated circuit including a logic circuit such as a logic LSI (Large Scale Integration), an observation point or a control point, which is a test circuit, is inserted into the logic circuit in order to improve the failure detection rate. The observation point is inserted into the logic circuit in order to observe the signal value of the predetermined node, and the control point is inserted into the logic circuit to give the signal value to the predetermined node. For example, a method has been proposed in which a failure detection rate when inserting an observation point or a control point is obtained, and a test circuit having a high effect of improving the failure detection rate per unit area is inserted into the logic circuit (for example, a patent Reference 1).

  In full-scan design in which all flip-flops in a logic circuit are replaced with scan flip-flops, a method has been proposed in which observation points and control points are inserted into circuit blocks in which the number of test patterns exceeds a predetermined value (for example, patents) Reference 2). In order to detect a delay fault between the macro and the user logic, a method of adding a function of performing a toggle operation to a control point connected to an input terminal of the macro has been proposed (for example, see Patent Document 3).

JP 2006-84427 A JP 2001-31529 A JP 2009-205414 A

  If the output of a user logic is connected to one input of a logic gate and the output of another user logic is connected to the other input of the logic gate via a control point, a delay failure in the signal path containing one input The delay failure of the signal path including the other input cannot be detected using one control point. Specifically, when providing a control point having a function of fixing the output logic in order to detect a delay fault of a signal path including one input, since different logics cannot be continuously output from the control point, the other The delay fault of the signal path including the input cannot be detected. In addition, when a control point having a function of sequentially changing the output logic is provided in order to detect a delay fault of a signal path including the other input, the same logic cannot be output continuously from the control point. The delay failure of the signal path including it cannot be detected.

  SUMMARY OF THE INVENTION An object of the present invention is to detect a fault in a logic circuit that can detect a delay fault of a signal path including one input of a logic gate and a delay fault of a signal path including the other input of the logic gate by one control point. A test circuit insertion method, a test circuit insertion device, and a semiconductor integrated circuit are provided.

According to one aspect of the logic circuit failure detection method of the present invention, a first user logic including a plurality of first scan flip-flops having a data input and a scan input, and a second user logic including at least one first scan flip-flop. A first logic gate having a first input connected to the output of the first user logic, and a third user logic including at least one first scan flip-flop and connected to the output of the first logic gate; and a inserted control point between the second user logic and the first logic gate, control points, one data output of the first scan flip flop of the second user logic or the third user logic data input A second scan flip-flop connected to the pair of inputs and a data output of the second scan flip-flop as a pair of inputs And a second logic gate connected to an output of the second user logic, the output of which is connected to the second input of the first logic gate, wherein the scan input is enabled, In the scan shift period in which the first and second scan flip-flops operate as a shift register, the same logic is set in one of the first scan flip-flop and the second scan flip-flop of the second user logic or the third user logic . Different logics are set in a pair of first scan flip-flops of the first user logic connected in series to one input, and two clocks are supplied to the first and second scan flip-flops in a capture period in which data input is enabled. Supply a pulse and keep it in the first scan flip-flop of the third user logic Wherein the logic is to detect a delay fault of the signal paths including a first input when no change.

In one form of the test circuit insertion method of the logic circuit of the present invention, the first user logic including a plurality of flip -flops, the second user logic including at least one first scan flip-flop, and the output of the first user logic A first logic gate having a first input connected and a second input connected to an output of the second user logic; a third user logic connected to the output of the first logic gate and including at least one flip-flop; A test circuit insertion method for a logic circuit having a process of replacing a flip-flop with a first scan flip-flop having a data input and a scan input, a second scan flip-flop having a data input and a scan input, The input is the data output of the second scan flip-flop and the second user A process of inserting a control point having a second logic gate connected to the output of the logic and having an output connected to the second input between the second user logic and the first logic gate; and a second scan flip-flop And connecting one data output of the first scan flip-flop of the second user logic or the third user logic to the data input of the second user logic .

In one form of the test circuit insertion device for a logic circuit of the present invention, the first user logic including a plurality of flip -flops, the second user logic including at least one first scan flip-flop, and the output of the first user logic A first logic gate having a first input connected and a second input connected to an output of the second user logic; a third user logic connected to the output of the first logic gate and including at least one flip-flop; A test circuit insertion device for a logic circuit having a process of replacing a flip-flop with a first scan flip-flop having a data input and a scan input, a second scan flip-flop having a data input and a scan input, The input is the data output of the second scan flip-flop and the second user A process of inserting a control point having a second logic gate connected to the output of the logic and having an output connected to the second input between the second user logic and the first logic gate; and a second scan flip-flop And a process of connecting one data output of the first scan flip-flop of the second user logic or the third user logic to the data input of the second user logic .

In one form of the semiconductor integrated circuit of the present invention, a first user logic including a plurality of first scan flip-flops each having a data input and a scan input, a second user logic including at least one first scan flip-flop , a first logic gate having a first input connected to the output of the first user logic comprises at least one first scan flip-flop, a third user logic which is connected to the output of the first logic gate, a second test showing a second scan flip-flop in which one data output of the first scan flip-flop of the user logic or the third user logic is connected to a data input, a pair of input data output and a test mode of the second scan flip-flop A mask circuit connected to the mode terminal and a pair of inputs And a control point having a second logic gate connected to the output of the first logic gate and the second user logic, respectively, the output being connected to the second input of the first logic gate, wherein the mask circuit is in a test mode. In addition, the output signal from the second scan flip-flop is transmitted to the second logic gate, and during the period other than the test mode, the transmission of the output signal to the second logic gate is masked, and the output signal from the second user logic Is output to the second logic gate through the second logic gate.

  The delay fault of the signal path including the first input of the first logic gate and the delay fault of the signal path including the second input of the first logic gate can be detected by one control point.

1 shows an embodiment of a logic circuit failure detection method, a logic circuit test circuit insertion method, and a logic circuit test circuit insertion device. 2 shows an example of a failure detection method for a logic circuit in which the test circuit shown in FIG. 1 is inserted. 3 shows another embodiment of a logic circuit failure detection method, a logic circuit test circuit insertion method, a logic circuit test circuit insertion device, and an embodiment of a semiconductor integrated circuit. 4 shows an example of a logic circuit before a test circuit is inserted into the logic circuit shown in FIG. 5 shows an example of a test circuit insertion device that generates the logic circuit shown in FIG. 3 from the logic circuit shown in FIG. 6 shows an example of the operation of the test circuit insertion device shown in FIG. 4 shows an example of a test system for testing a semiconductor integrated circuit having the logic circuit shown in FIG. 4 shows an example of a test for detecting a delay fault in the logic circuit shown in FIG. 4 shows another example of a test for detecting a delay fault in the logic circuit shown in FIG. 3 shows another embodiment of a logic circuit failure detection method, a logic circuit test circuit insertion method, a logic circuit test circuit insertion device, and a semiconductor integrated circuit. 11 shows an example of a test for detecting a delay fault in the logic circuit shown in FIG. 11 shows another example of a test for detecting a delay fault in the logic circuit shown in FIG. 3 shows another embodiment of a logic circuit failure detection method, a logic circuit test circuit insertion method, a logic circuit test circuit insertion device, and a semiconductor integrated circuit. 14 shows an example of a test for detecting a delay fault in the logic circuit shown in FIG. 14 shows another example of a test for detecting a delay fault in the logic circuit shown in FIG. 3 shows another embodiment of a logic circuit failure detection method, a logic circuit test circuit insertion method, a logic circuit test circuit insertion device, and a semiconductor integrated circuit. 17 shows an example of a test for detecting a delay fault in the logic circuit shown in FIG. 17 shows another example of a test for detecting a delay fault in the logic circuit shown in FIG. 3 shows another embodiment of a logic circuit failure detection method, a logic circuit test circuit insertion method, a logic circuit test circuit insertion device, and a semiconductor integrated circuit. 19 shows an example of a test for detecting a delay fault of the logic circuit shown in FIG. 20 shows another example of a test for detecting a delay fault in the logic circuit LOGICT shown in FIG.

  Hereinafter, embodiments will be described with reference to the drawings. In the figure, the same reference numerals as signal names are used for signal lines through which signals are transmitted.

  FIG. 1 shows an embodiment of a logic circuit failure detection method, a logic circuit test circuit insertion method, and a logic circuit test circuit insertion device. The left side of FIG. 1 shows an example of a logic circuit LOGIC designed by the user. The right side of FIG. 1 shows an example of a logic circuit LOGICT generated by inserting a test circuit into the logic circuit LOGIC.

The logic circuit LOGIC includes user logic UL1, UL2, UL3 and a logic gate L1. The user logic UL1 includes a plurality of flip-flops FF (FF1, FF2). The user logic UL3 includes at least one flip-flop FF3. The flip-flops FF1 to FF3 operate by receiving a common clock at a clock input indicated by “>”. Note that the clock wiring is omitted in order to avoid complication of the drawing.

  The outputs of the user logics UL1 and UL2 are connected to the inputs I1 and I2 of the logic gate L1, respectively. The output of the logic gate L1 is connected to the input of the user logic UL3. The logic gate L1 is not limited to an OR gate, and may be an AND gate, a NOR gate, a NAND gate, or the like.

  For example, the data output Q of the flip-flop FF1 is connected to the data input D of the flip-flop FF2. The data output Q of the flip-flop FF2 is connected to the input I1 of the logic gate L1. That is, the flip-flops FF1 and FF2 are connected in series. Note that the data output Q of the flip-flop FF1 may be connected to the data input D of the flip-flop FF2 via a combinational circuit. The data output Q of the flip-flop FF2 may be connected to the input I1 through a combinational circuit. The output of the logic gate L1 is connected to the data input D of the flip-flop FF3. Note that the output of the logic gate L1 may be connected to the data input D of the flip-flop FF3 via a combinational circuit.

  In this example, it is assumed that the output of the user logic UL2 (that is, the input I2 of the logic gate L1) is likely to be logic 1. Therefore, in order to detect a stuck-at fault or delay fault in the signal path including the input node I1, or to detect a stuck-out fault or delay fault in the signal path including the input node I2, as shown on the right side of FIG. A test circuit is inserted.

  The logic circuit LOGICT has a scan flip-flop SFF (SFF1, SFF2, SFF3) replaced from the flip-flop FF, and a control point CP inserted between the output of the user logic UL2 and the input I2 of the logic gate L1. doing. The control point CP is an example of a test circuit for controlling the logic value of the input I2 of the logic gate L1, and includes a scan flip-flop SFF4 and a logic gate L2.

  Each of the scan flip-flops SFF1 to SFF4 has a scan input SIN and a scan mode input SM in addition to the data input D. In order to avoid complication of the drawing, the wiring connected to the scan mode input SM is omitted. The scan flip-flops SFF1 to SFF4 latch the logic received at the data input D in synchronization with the clock during the capture period in which the first logic (for example, logic 0) is received at the scan mode input SM, and the latched logic is data Output from output Q.

  The scan flip-flops SFF1 to SFF4 latch the logic received by the scan input SIN in synchronization with the clock during the scan shift period in which the second logic (for example, logic 1) is received by the scan mode input SM, and the latched logic is Output from data output Q. Each scan flip-flop SFF1-SFF4 may be formed by connecting a multiplexer that selects either the data input D or the scan input SIN to the data input D of each flip-flop FF1-FF4.

  A signal line indicated by a thick line in the logic circuit LOGICT indicates a path of a signal transmitted to the scan flip-flops SFF1 to SFF4 during the scan shift period. The scan input SIN of each scan flip-flop SFF is connected to the data output Q of another scan flip-flop SFF. With the thick signal lines, the scan flip-flops SFF1 to SFF4 operate as shift registers during the scan shift period. Note that the signal transmission path during the scan shift period may not be in the order of the scan flip-flops SFF1 to SFF4. In order to improve the testability, replacing a normal flip-flop FF with a scan flip-flop SFF operable as a shift register as described above is referred to as scan design.

  In this example, since the output of the user logic UL2 is likely to be logic 1, an AND gate is used as the logic gate L2. For example, when the output of the user logic UL2 is likely to become logic 0, an OR gate is used as the logic gate L2. As the logic gate L2, a NAND gate may be used instead of the AND gate, and a NOR gate may be used instead of the OR gate. For example, in the logic circuit LOGIC, when inverting logic such as an inverter is arranged between the user logic UL2 and the input I2 of the logic gate L1, in the logic circuit LOGICT, between the user logic UL2 and the inverting logic, a NAND gate or A NOR gate is arranged.

  The control point CP is provided to enable the input I2 of the logic gate L1 to be set to logic 0 when the output of the user logic UL2 is set to logic 1. This type of control point CP is referred to as a “0 control point”. On the other hand, a control point including an OR gate that is inserted when the output of the user logic UL2 is likely to become logic 0 is referred to as “1 control point”. By inserting the control point CP, the logic of the input node I2 can be arbitrarily set by the scan flip-flop SFF4, and the failure detection rate can be improved.

  A common scan mode input signal SM is supplied to the scan mode inputs SM of the scan flip-flops SFF1 to SFF4. A common clock is supplied to clock inputs indicated by “>” in the scan flip-flops SFF1 to SFF4. Note that the description of the signal line and the clock wiring of the scan mode signal SM is omitted in order to avoid complication of the drawing.

  The data input D of the scan flip-flop SFF4 formed at the control point CP is connected to one of the data outputs Q of the scan flip-flops SFF1-SFF3 formed other than the control point CP. In this example, the data input D of the scan flip-flop SFF4 is connected to the data output Q of the scan flip-flop SFF3.

  For example, a test circuit is inserted into a logic circuit LOGIC designed by a user by a computer system such as a workstation executing a test circuit insertion program. In other words, the computer system that inserts the test circuit into the logic circuit LOGIC by executing the test circuit insertion program functions as a test circuit insertion device. Then, a test circuit insertion method for inserting a test circuit into the logic circuit LOGIC is performed by the operation of the test circuit insertion device.

By executing the test circuit insertion program, the test circuit insertion device performs at least three processes 1 to 3 described below, and inserts the test circuit into the logic circuit LOGIC to generate the logic circuit LOGICT. Note that the test circuit insertion device may perform the processing 1 and the processing 2 in this order or in the reverse order. Further, the test circuit insertion device may perform the processing 1 and the processing 2 at the same time.
(Process 1) The flip-flops FF1-FF3 of the logic circuit LOGIC are replaced with scan flip-flops SFF1-SFF3 each having a data input D and a scan input SIN in order to function as a shift register.
(Process 2) A node that requires insertion of a control point CP to facilitate the test and the logic of the control point CP to be inserted are obtained. In this example, the control point CP is inserted between the user logic UL2 and the logic gate L1, and includes a scan flip-flop SFF4 having a data input D and a scan input SIN, and a logic gate L2. The logic gate L2 has a pair of inputs connected to the data output Q of the scan flip-flop SFF4 and the output of the user logic UL2, respectively.
(Process 3) The data outputs Q of the scan flip-flops SFF1-SFF3 formed other than the control point CP are connected to the data input D of the scan flip-flop SFF4. In this example, the data input D of the scan flip-flop SFF4 is connected to the data output Q of the scan flip-flop SFF3.

  FIG. 2 shows an example of a failure detection method for the logic circuit LOGICT in which the test circuit shown in FIG. 1 is inserted. For example, the failure detection method shown in FIG. 2 uses a test device such as an LSI (Large Scale Integration) tester to distinguish between non-defective products and defective products in a test process in the manufacturing process of a semiconductor integrated circuit including a logic circuit LOGICT. To be implemented. The logical values shown in parentheses in the scan flip-flops SFF1, SFF2, SFF3, and SFF4 are logical values set during a scan shift period in which the scan input SIN is validated and the scan flip-flops SFF1-SFF4 are operated as shift registers. Is shown.

  The left side of FIG. 2 shows a method for detecting a delay fault in a signal path including the input node I1 of the logic gate L1 (signal path after the data output Q of the scan flip-flop SFF2). The right side of FIG. 2 shows a method for detecting a delay fault in a signal path (a signal path after the output of the logic gate L2) including the input node I2 of the logic gate L1.

  Note that symbols F1 and F2 marked with X indicate the presence of a delay fault. However, the X mark does not necessarily indicate the position where the delay faults F1 and F2 have occurred. For example, the delay fault F1 occurs locally in any of signal paths from the data output Q of the scan flip-flop SFF2 to the data input D of the scan flip-flop SFF3. Alternatively, the delay fault F1 occurs in a distributed manner on the signal path from the data output Q of the scan flip-flop SFF2 to the data input D of the scan flip-flop SFF3.

  Similarly, the delay fault F2 occurs locally in any of signal paths from the output of the logic gate L2 to the data input D of the scan flip-flop SFF3. Alternatively, the delay fault F2 occurs in a distributed manner on the signal path from the output of the logic gate L2 to the data input D of the scan flip-flop SFF3. Generally, a delay fault that occurs locally is referred to as a transition delay fault, and a delay fault that occurs in a distributed manner is referred to as a path delay fault.

  On the left side of the figure, when detecting a delay fault of a signal path including the input I1 not connected to the control point CP, the test apparatus sets the scan mode input SM to the second logic in order to shift to the scan shift period. In the scan shift period, each of the scan flip-flops SFF1 to SFF4 latches the logic received by the scan input SIN in synchronization with the clock, and outputs the latched logic from the data output Q.

  The test apparatus shifts the scan flip-flops SFF1 to SFF4 during the scan shift period, and sets logic 1, logic 0, logic 0, and logic 0 to the scan flip-flops SFF1, SFF2, SFF3, and SFF4, respectively. That is, the test apparatus sets different logics to the pair of scan flip-flops SFF1 and SFF2 connected in series to the input I1, and sets the same logic to the scan flip-flops SFF3 and SFF4.

  Here, the scan flip-flops SFF1 and SFF2 may be set to logic 0 and logic 1, respectively. The logic 0 set in the scan flip-flops SFF3 and SFF4 does not depend on the logic output from the user logic UL2, and is necessary to fix the input I2 of the logic gate L1 to the logic 0. By fixing the input I2 to logic 0, the logic 0 and logic 1 set in the scan flip-flops SFF2 and SFF1 can be sequentially transmitted to the output of the logic gate L1.

  Next, the test apparatus sets the scan mode input SM to the first logic in order to shift from the scan shift period to the capture period. In the capture period, each of the scan flip-flops SFF1 to SFF4 sequentially latches the logic received at the data input D in synchronization with the clock, and outputs the latched logic from the data output Q. The test device generates two clock pulses during the capture period. The input I1 of the logic gate L1 changes from logic 0 to logic 1 by the first clock pulse.

  In the logic circuit without the delay fault F1, the scan flip-flop SFF3 latches the logic 0 initially set in the scan flip-flop SFF2 in synchronization with the first clock pulse, and the scan flip-flop in synchronization with the second clock pulse. Latches the initial logic 1 in SFF1.

  On the other hand, in the logic circuit having the delay fault F1, the transition from the logic 0 to the logic 1 of the data output Q of the scan flip-flop SFF2 is transmitted to the scan flip-flop SFF3 with a delay. Therefore, the scan flip-flop SFF3 cannot latch the logic 1 initialized in the scan flip-flop SFF1 in synchronization with the second clock pulse, and latches the logic 0 initialized in the scan flip-flop SFF2 again.

  Thereafter, the test apparatus shifts from the capture period to the scan shift period, and reads the logic held in the scan flip-flop SFF3. Then, the test apparatus detects that the delay fault F1 does not exist when the logic 1 is held in the scan flip-flop SFF3, and the delay fault F1 when the logic 0 is held in the scan flip-flop SFF3. Detect that exists. That is, when the logic held in the scan flip-flop SFF3 does not change before and after the second clock pulse, the delay fault F1 of the signal path including the input I1 is detected.

  On the other hand, on the right side of the figure, when detecting the delay fault F2 of the signal path including the input I2 connected to the control point CP, the test apparatus sets logic 0, logic 0, logic 1, and logic 0 during the scan shift period. , And scan flip-flops SFF1, SFF2, SFF3, and SFF4, respectively. That is, the test apparatus sets the same logic to the pair of scan flip-flops SFF1 and SFF2 connected in series to the input I1, and sets different logics to the scan flip-flops SFF3 and SFF4.

  Here, the scan flip-flops SFF3 and SFF4 may be set to logic 0 and logic 1, respectively. The logic 0 set in the scan flip-flops SFF1 and SFF2 is necessary for sequentially transmitting the logic 0 and logic 1 set in the scan flip-flops SFF4 and SFF3 to the output of the logic gate L1.

  Next, during the capture period, the test device changes the input I2 of the logic gate L1 from logic 0 to logic 1, and generates two clock pulses to latch the output value of the logic gate L1 in the scan flip-flop SFF3. To do. Similar to the operation on the left side of FIG. 2, in the logic circuit without the delay fault F2, the scan flip-flop SFF3 latches the logic 1 initialized in the scan flip-flop SFF1 in synchronization with the second clock pulse. On the other hand, in the logic circuit having the delay fault F2, the scan flip-flop SFF3 cannot latch the logic 1 initialized in the scan flip-flop SFF1 in synchronization with the second clock pulse, and is initialized in the scan flip-flop SFF2. Latch the logic 0 again.

  Thereafter, the test apparatus reads the logic held in the scan flip-flop SFF3 during the capture period, as in the operation on the left side of FIG. Then, the test apparatus detects that the delay fault F2 does not exist when the logic 1 is held in the scan flip-flop SFF3, and the delay fault F2 when the logic 0 is held in the scan flip-flop SFF3. Detect that exists. That is, when the logic held in the scan flip-flop SFF3 does not change before and after the second clock pulse, the delay fault F2 of the signal path including the input I2 is detected.

  In addition, by implementing the fault detection method on the left side of FIG. 2, not only the delay fault F1 but also the stuck-at fault of the signal path including the input I1 can be detected. By implementing the fault detection method on the right side of FIG. 2, not only the delay fault F2 but also the stuck-at fault of the signal path including the input I2 can be detected. In addition, the setting of the logical values to the scan flip-flops SFF1 to SFF4 and the detection of the delay faults F1 and F2 are not used in the test apparatus, but the BIST (Built-In Self Test) mounted on the semiconductor integrated circuit including the logic circuit LOGICT. ) It may be implemented by a circuit or the like.

  As described above, in this embodiment, the logic of the output of the control point CP can be fixed or changed in the capture period according to the positions of the delay faults F1 and F2 to be detected. Thereby, the logic change of the input I1 of the logic gate L1 can be transmitted to the subsequent logic, or the logic change of the input I2 of the logic gate L1 can be transmitted to the subsequent logic. As a result, the delay fault F1 of the signal path including the input I1 of the logic gate L1 and the delay fault F2 of the signal path including the input I2 of the logic gate L1 can be detected by one control point CP. That is, it is possible to provide a logic circuit fault detection method, a test circuit insertion method, and a test circuit insertion device that can detect the delay faults F1 and F2 by one control point CP.

  FIG. 3 shows another embodiment of a logic circuit failure detection method, a logic circuit test circuit insertion method, a logic circuit test circuit insertion device, and an embodiment of a semiconductor integrated circuit. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. FIG. 3 shows a logic circuit LOGICT into which a control point CP, which is an example of a test circuit, is inserted. The logic circuit LOGIC before the test circuit is inserted is shown in FIG.

  In this embodiment, the logic circuit LOGICT has user logic UL1, UL2, UL3, an OR gate OR1, and a control point CP. The output of the user logic UL1 is connected to the input I1 of the OR gate OR1. The output of the user logic UL2 is connected to the input I2 of the OR gate OR1 via the control point CP. The output of the OR gate OR1 is connected to the user logic UL3.

  The OR gate OR1 may be an AND gate, NOR gate, NAND gate, or the like. In the case of the AND gate and the NAND gate, the delay I of the signal path including the input I1 can be detected by fixing the input I2 to logic 1 and changing the logic of the input I1. Further, by fixing the input I1 to logic 1 and changing the logic of the input I2, it is possible to detect the delay fault F2 of the signal path including the input I2. In the case of the NOR gate, similarly to the OR gate OR1, by fixing the input I2 to logic 0 and changing the logic of the input I1, the delay fault F1 of the signal path including the input I1 can be detected. Further, by fixing the input I1 to logic 0 and changing the logic of the input I2, it is possible to detect the delay fault F2 of the signal path including the input I2. A method for detecting a delay fault will be described with reference to FIGS.

  For example, the user logic UL1 includes a plurality of scan flip-flops SFF (SFFa, SFFb). The data output Q of the scan flip-flop SFFa is connected to the data input D and the scan input SIN of the scan flip-flop SFFb via the node NDa. The data output Q of the scan flip-flop SFFb is connected to the input I1 of the OR gate OR1 and the scan input SIN of the scan flip-flop SFFc via the node NDb. Note that the data output Q of the scan flip-flop SFFb may be connected to the input I1 through a combinational circuit.

  For example, the user logic UL2 includes a plurality of scan flip-flops SFF (SFFc, SFFc) and a circuit CC1 such as a combinational circuit. In this example, it is assumed that the output of the circuit CC1 (that is, the node NDe) is likely to be logic 1. In other words, during the operation of the user logic UL2, the probability that the node NDe becomes logic 1 is sufficiently higher than the probability that the node NDe becomes logic 0. For this reason, the control point CP is inserted in order to enable the input I2 of the OR gate OR1 to be set to an arbitrary logic when the node NDe is a logic 1.

  The data output Q of the scan flip-flop SFFc is connected to the data input D and the scan input SIN of the scan flip-flop SFFd via the node NDc. The data output Q of the scan flip-flop SFFd is connected to the scan input SIN of the scan flip-flop SFFf, and is connected to the node NDe via the circuit CC1.

  For example, the user logic UL3 includes a circuit CC2 such as a combinational circuit and at least one scan flip-flop SFFe. The input of the circuit CC2 is connected to the output of the OR gate OR1 through the node NDh. For example, the circuit CC2 inverts the logic of the node NDh and outputs it to the node NDi. The data input D of the scan flip-flop SFFe is connected to the output of the circuit CC2 via the node NDi. The scan input SIN of the scan flip-flop SFFe is connected to the data output Q of the scan flip-flop SFFf. The data output Q of the scan flip-flop SFFe is connected to the node SOUT and the data input D of the scan flip-flop SFFf.

  The control point CP is an example of a test circuit, and includes a scan flip-flop SFFf, a NAND gate NAND1, and an AND gate AND1. The data output Q of the scan flip-flop SFFf is connected to one input of the NAND gate NAND1 and the scan input SIN of the scan flip-flop SFFe. The other input of the NAND gate NAND1 is connected to a test mode terminal TM that receives a test mode signal. The output of the NAND gate NAND1 is connected to one input of the AND gate AND1 through the node NDf. The other input of the AND gate AND1 is connected to the output of the circuit CC1 via the node NDe. The output of the AND gate AND1 is connected to the input I2 of the OR gate OR1 through the node NDg.

  In this example, the test mode terminal TM is set to logic 1 during the test mode for detecting a delay fault, and is set to logic 0 during the system mode in which the logic circuit LOGICT operates as part of the user system. The signal transmission function of the NAND gate NAND1 is enabled by the logic 1 of the test mode terminal TM, and the NAND gate NAND1 inverts the logic of the output Q of the scan flip-flop SFFf and outputs it to the AND gate AND1. On the other hand, the logic 0 of the test mode terminal TM disables the signal transmission function of the NAND gate NAND1, and the node NDf that is the output of the NAND gate NAND1 is fixed to the logic 1.

  This prevents the logic of the data output Q of the scan flip-flop SFFf operating according to the logic received at the data input D during the system mode (TM = logic 0) from being transmitted to the AND gate AND1. Malfunctions such as UL3 can be prevented. When the NAND gate NAND1 outputs the logic 1 to the node NDf, the logic of the node NDe, which is the output of the circuit CC1, is transmitted to the OR gate OR1 via the AND gate AND1. In this manner, by connecting the scan flip-flop SFFf to the AND gate AND1 via the NAND gate NAND1 controlled by the test mode signal TM, malfunction due to the operation of the scan flip-flop SFFf in the system mode can be prevented.

  Similar to FIG. 1, signal lines indicated by bold lines indicate paths of signals transmitted to the scan flip-flops SFFa, SFFb, SFFc, SFFd, SFFf, and SFFe during the scan shift period. Symbols F1 and F2 marked with X indicate the presence of a delay fault. However, the delay faults F1 and F2 are treated as not occurring at the same time stochastically. Further, as described with reference to FIG. 2, the mark X does not necessarily indicate the position where the delay faults F1 and F2 are generated.

  Each of the scan flip-flops SFFa to SFFf may be formed by connecting a multiplexer that selects either a data input or a scan input to the data input of the flip-flop.

  FIG. 4 shows an example of the logic circuit LOGIC before the test circuit is inserted into the logic circuit LOGICT shown in FIG. The logic circuit LOGIC is a circuit designed by the user. In the logic circuit LOGIC, flip-flops FFa, FFb, FFc, FFd, and FFe are arranged instead of the scan flip-flops SFFa, SFFb, SFFc, SFFd, and SFFe in FIG. The logic circuit LOGIC does not include the control point CP. For this reason, in the logic circuit LOGIC, the output of the user logic UL2 is directly connected to the input I2 of the OR gate OR1.

  FIG. 5 shows an example of a test circuit insertion device CAD that generates the logic circuit LOGICT shown in FIG. 3 from the logic circuit LOGIC shown in FIG. For example, the test circuit insertion device CAD is realized by a computer system such as a workstation.

  The test circuit insertion device CAD has a memory device MEM for storing a test circuit insertion program for inserting a test circuit such as the control point CP shown in FIG. 3, and a processor CPU for executing the test circuit insertion program. . The memory device MEM is, for example, a semiconductor memory device or a hard disk drive device. The test circuit insertion device CAD includes a display DISP, an input device INPUT such as a keyboard and a mouse, a disk drive device DRV, and an input / output device INOUT.

  The display DISP displays information input from the input device INPUT and the disk drive DRV, a logic diagram of the logic circuit LOGICT generated by the test circuit insertion program, a net list, and the like. A recording medium such as a CD-ROM or DVD in which a test circuit insertion program or a netlist of the logic circuit LOGIC shown in FIG. 4 is recorded is set in the disk drive DRV. The test circuit insertion program and the net list are downloaded to the memory device MEM via the disk drive device DRV.

  Then, the test circuit insertion method is performed by the processor CPU executing the test circuit insertion program, and the logic circuit LOGICT (net list) in FIG. 3 is generated from the logic circuit LOGIC in FIG. The generated netlist is written from the memory device MEM to an input / output device INOUT such as a silicon disk such as a memory card, a magnetic tape device, or a hard disk drive device.

  Note that the test circuit insertion program and the net list may be transferred to the memory device MEM using the input / output device INOUT instead of the disk drive device DRV. Alternatively, the test circuit insertion program and the net list may be input / output to / from the memory device MEM via the network.

  FIG. 6 shows an example of the operation of the test circuit insertion device CAD shown in FIG. FIG. 6 shows the flow of the test circuit insertion method, which is realized by the test circuit insertion device CAD executing the test circuit insertion program.

  First, in step S10, the test circuit insertion device CAD analyzes the net list of the logic circuit LOGIC designed by the user, and obtains a node where the control point CP needs to be inserted and the logic of the control point CP to be inserted. The test circuit insertion device CAD obtains the node to be inserted and the logic of the observation point to be inserted as necessary. The observation point is a kind of test circuit, such as a scan flip-flop that needs to be inserted in order to obtain a logical value for detecting a delay fault. The obtained control point CP information and observation point information are written in the memory device MEM or the like as information of the inserted test circuit.

  Next, in step S20, the test circuit insertion device CAD, based on the obtained information on the control point CP, scan scan flip-flop connected to the data input D of the scan flip-flop SFF (for example, SFFf in FIG. 3) of the control point CP. Select SFF. For example, in step S20, the downstream side (output side) of the control point CP is searched in order, and the scan flip-flop SFF having the smallest number of logical stages from the control point CP is selected. Alternatively, the upstream side (input side) of the control point CP is searched in order, and the scan flip-flop SFF having the smallest number of logic stages from the control point CP is selected. Thereby, the data input D of the scan flip-flop SFF at the control point CP is connected to one of the data outputs Q of the scan flip-flop SFF formed other than the control point CP. Information of the selected scan flip-flop SFF is written in the memory device MEM or the like.

  Next, in step S30, the test circuit insertion device CAD replaces the flip-flop FF on the net list with the scan flip-flop SFF using the net list of the logic circuit LOGIC. Next, the test circuit insertion device CAD inserts the control point CP on the net list using the information of the control point CP. Further, the test circuit insertion device CAD uses the information of the scan flip-flop SFF selected in step S20 to input the selected scan flip-flop to the data input D of the scan flip-flop SFF (SFFf in FIG. 3) of the inserted control point CP. Connect the data output Q of the SFF. Then, the logic circuit LOGICT (net list) shown in FIG. 3 is generated.

  The test circuit insertion device CAD inserts observation points on the netlist based on observation point information as necessary. The test circuit insertion device CAD generates a net list of the logic circuit LOGICT in which the test circuit is inserted. Then, using the generated netlist, a program for executing arrangement of elements such as transistors and wiring between elements is executed, and photomask data for manufacturing the semiconductor integrated circuit LSI is generated. The element layout, wiring, and photomask data generation may be performed by the test circuit insertion device CAD executing another program, or may be performed using a large computer or the like.

  Thereafter, a photomask is manufactured using the photomask data, a semiconductor manufacturing process is performed using the photomask, and a semiconductor integrated circuit LSI having the logic circuit LOGICT shown in FIG. 3 is manufactured. The manufactured semiconductor integrated circuit LSI is tested by the test system TSYS shown in FIG. 7, and the presence or absence of a delay fault is detected.

  FIG. 7 shows an example of a test system TSYS that tests the semiconductor integrated circuit LSI having the logic circuit LOGICT shown in FIG. In the embodiment described later, the same test system TSYS as in FIG. 7 is used. The test system TSYS is used in a test process in the manufacturing process of the semiconductor integrated circuit LSI.

  First, a plurality of semiconductor integrated circuits LSI are formed on a semiconductor wafer WAF by a semiconductor manufacturing process. The semiconductor integrated circuit LSI is tested by a test apparatus such as a tester TEST before being cut out from the wafer WAF. A failure detection method for the logic circuit LOGICT is realized by testing the semiconductor integrated circuit LSI by the test system TSYS. That is, the tester TEST operates as a failure detection device for the logic circuit LOGICT.

  The semiconductor integrated circuit LSI is connected to the tester TEST via, for example, a probe card probe PRB. In FIG. 7, one semiconductor integrated circuit LSI is connected to the tester TEST, but a plurality of semiconductor integrated circuit LSIs may be connected to the tester TEST at a time. The number of semiconductor integrated circuit LSIs connected to the tester TEST at a time depends on the number of terminals of the tester TEST and the number of terminals of the semiconductor integrated circuit LSI.

  For example, the tester TEST executes a failure detection program for detecting a delay failure in the logic circuit LOGICT, and outputs a clock CLK, a test mode signal TM, a scan mode input signal SM, and a scan input signal SIN to the semiconductor integrated circuit LSI. . The tester TEST reads the logic held in a predetermined scan flip-flop SFF (for example, SFFe in FIG. 3) in the logic circuit LOGICT through the scan-out terminal SOUT, and detects the presence or absence of a delay fault. The semiconductor integrated circuit LSI in which the delay fault is detected is treated as a defective product. Note that the tester TEST may be used to test the packaged semiconductor integrated circuit LSI.

  FIG. 8 shows an example of a test for detecting a delay fault of the logic circuit LOGICT shown in FIG. The operation of FIG. 8 is realized by the tester TEST illustrated in FIG. 7 executing the failure detection program, and is performed to detect the delay failure F1 illustrated in FIG. In other words, FIG. 8 shows a fault detection method for a delay fault in the logic circuit LOGICT, and shows a method for manufacturing the semiconductor integrated circuit LSI.

  In FIG. 8 and the subsequent waveform diagrams, the first to sixth clock cycles and the ninth clock cycle indicate scan shift periods in which the scan mode input SM is set to logic 1. The seventh and eighth clock cycles indicate the capture period in which the scan mode input SM is set to logic zero. The length of the seventh clock cycle is set in accordance with the delay time of the signal path for determining the delay fault F1 or F2. In other words, the occurrence of the delay fault F1 or F2 is detected when the delay time of the signal path is longer than the length of the seventh clock cycle. Here, the length of the seventh clock cycle is a period from the rising edge of the seventh clock CLK to the rising edge of the eighth clock CLK. Further, in order to transmit the logic (transition edge) output from the scan flip-flop SFFf to the OR gate OR1, the test mode terminal TM is set to logic 1 during the test mode. In the seventh to ninth clock cycles, a waveform indicated by a broken line indicates an operation when there is a delay fault.

  In this example, in order to set a desired logic in the scan flip-flops SFFe, SFFf, SFFd, SFFc, Sffb, and Sffa, in the first to sixth clock cycles, the scan input SIN is set to logic 1, logic 1, logic 0, Logic 0, logic 0, and logic 1 are supplied in order. The name of the scan flip-flop shown on the waveform of the scan input SIN indicates the correspondence with the logic set in the sixth clock cycle. In the sixth clock cycle immediately before the capture period, the scan flip-flops SFFb, SFFa, SFFf, and SFFe are set to logic 0, logic 1, logic 1, and logic 1, respectively.

  That is, in the sixth clock cycle, the scan flip-flops SFFb and SFFa connected in series via the data input D to the input I1 of the OR gate OR1 hold different logics. Thus, in the seventh clock cycle of the capture period, the logic held in the scan flip-flop SFFb can be changed from logic 0 to logic 1, and the input I1 of the OR gate OR1 can be changed from logic 0 to logic 1.

  In the sixth clock cycle, the scan flip-flops SFFf and SFFe connected in series to the input I2 of the OR gate OR1 via the NAND gate NAND1 and the AND gate AND1 and via the data input D hold the same logic. Thereby, in the seventh clock cycle of the capture period, the logic held in the scan flip-flop SFFf can be maintained at the logic 1 using the logic held in the scan flip-flop SFFe one clock cycle before. Therefore, the input I2 of the OR gate OR1 connected to the output node of the scan flip-flop SFFf can be maintained at logic zero. The logic held in the scan flip-flop SFFf is inverted by the NAND gate NAND1 and transmitted to the node NDf and the input I2 of the OR gate OR1.

  When the delay fault F1 does not exist, the logical change of the scan flip-flop SFFb is immediately transmitted to the input I1 of the OR gate OR1 and the output node NDh of the OR gate OR1. The circuit CC2 immediately changes the output node NDi from logic 1 to logic 0 in response to the change of the output node NDh from logic 0 to logic 1. Therefore, the scan flip-flop SFFe latches the logic 0 in the eighth clock cycle of the capture period, and outputs the latched logic 0 to the scan-out terminal SOUT. Then, in the ninth clock cycle of the scan shift period, the tester TEST shown in FIG. 7 detects that the delay fault F1 does not exist by reading the logic 0 of the scan-out terminal SOUT.

  In an actual circuit, the output of the scan flip-flop SFFe is often connected to the scan-out terminal SOUT via a plurality of scan flip-flops. In this case, the scan-out terminal SOUT is connected to, for example, the output Q of the last scan flip-flop constituting the shift register, and the presence or absence of the delay fault F1 is determined in a clock cycle after the ninth clock cycle.

  On the other hand, when the delay fault F1 exists, the logical change of the scan flip-flop SFFb is delayed with respect to the input I1 of the OR gate OR1, the output node NDh of the OR gate OR1, or the output node NDi of the circuit CC2, as indicated by a broken line. . When the scan flip-flop SFFe cannot latch the logic 0 of the node NDi in the eighth clock cycle of the capture period due to the signal delay, the scan-out terminal SOUT is maintained at the logic 1. The tester TEST shown in FIG. 7 detects the presence of the delay fault F1 by reading the logic 1 of the scan-out terminal SOUT in the ninth clock cycle of the scan shift period.

  FIG. 9 shows another example of a test for detecting a delay fault in the logic circuit LOGICT shown in FIG. The operation of FIG. 9 is realized by the tester TEST shown in FIG. 7 executing the fault detection program, and is executed to detect the delay fault F2 shown in FIG. In other words, FIG. 9 shows a fault detection method for delay faults in the logic circuit LOGICT, and shows a method for manufacturing a semiconductor integrated circuit LSI. Detailed descriptions of the same operations as those in FIG. 8 are omitted.

  In this example, logic 0, logic 1, logic 0, logic 0, logic 0, and logic 0 are sequentially supplied to the scan input SIN in the first to sixth clock cycles. In the sixth clock cycle, the scan flip-flops SFFb, SFFa, SFFf, SFFe are set to logic 0, logic 0, logic 1, and logic 0, respectively. That is, in the sixth clock cycle, the scan flip-flops SFFb and SFFa connected in series to the input I1 of the OR gate OR1 hold the same logic. The scan flip-flops SFFf and SFFe connected in series to the input I2 of the OR gate OR1 through the NAND gate NAND1 and the AND gate AND1 hold different logics.

  This changes the logic held in the scan flip-flop SFFf from the logic 1 to the logic 0 using the logic held in the scan flip-flop SFFe one clock cycle before the seventh clock cycle of the capture period. it can. The logic held in the scan flip-flop SFFe is inverted by the NAND gate NAND1. That is, in the seventh clock cycle, the input I2 of the OR gate OR1 can be changed from the logical 0 to the logical 1 while the input I1 of the OR gate OR1 is maintained at the logical 0.

  When there is no delay fault F2, the logic change of the scan flip-flop SFFf is immediately transmitted to the input I2 and the output node NDh of the OR gate OR1. Similarly to FIG. 8, the scan flip-flop SFFe latches a logic 0 in the eighth clock cycle, and the tester TEST reads the logic 0 of the scan-out terminal SOUT in the ninth clock cycle. Thereby, it is detected that the delay fault F2 does not exist.

  On the other hand, when the delay fault F2 exists, as indicated by a broken line, the logical change of the scan flip-flop SFFf is transmitted with a delay to the input I1 of the OR gate OR1, the output node NDh of the OR gate OR1, or the output node NDi of the circuit CC2. . Then, in the eighth clock cycle, when the scan flip-flop SFFe cannot latch the logic 0 of the node NDi, the scan-out terminal SOUT is maintained at the logic 1. The tester TEST shown in FIG. 7 detects the presence of the delay fault F2 by reading the logic 1 of the scan-out terminal SOUT in the ninth clock cycle of the scan shift period.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, it is possible to provide a semiconductor integrated circuit LSI that can detect the delay fault F1 of the signal path including the input I1 of the logic gate L1 and the delay fault F2 of the signal path including the input I2 of the logic gate L1 by one control point CP. . Further, by connecting the data output Q of the scan flip-flop SFFf to the AND circuit AND1 through the NAND gate NAND1 controlled by the test mode signal TM, the logic of the data output Q of the scan flip-flop SFFf is ANDed during the system mode. Transmission to the gate AND1 can be prevented. As a result, it is possible to prevent the logic circuit LOGICT from malfunctioning.

  FIG. 10 shows another embodiment of a logic circuit failure detection method, a logic circuit test circuit insertion method, a logic circuit test circuit insertion device, and a semiconductor integrated circuit. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

  The logic circuit LOGICT of this embodiment has a circuit CC3 instead of the circuit CC1 of FIG. The control point CP has an AND gate AND2 instead of the NAND gate NAND1 shown in FIG. 3, and has an OR gate OR2 instead of the AND gate AND1 shown in FIG. Other configurations of the logic circuit LOGICT are the same as those in FIG. The logic circuit LOGIC in FIG. 10 is generated when the test circuit insertion device CAD shown in FIG. 5 executes the test circuit insertion program and performs the processing shown in FIG.

  In this embodiment, it is assumed that the output of the circuit CC3 (that is, the node NDe) is likely to be logic zero. In other words, during the operation of the user logic UL2, the probability that the node NDe becomes logic 0 is sufficiently higher than the probability that the node NDe becomes logic 1. Therefore, a control point CP different from that shown in FIG. 3 is inserted so that the input I2 of the OR gate OR1 can be set to an arbitrary logic and the failure detection rate is improved. The OR gate OR2 of the control point CP is provided to enable the input I2 of the OR gate L1 to be set to logic 1 when the output of the circuit CC3 is set to logic 0.

  During the test mode (TM = logic 1), the signal transmission function of the AND gate AND2 is enabled, and the AND gate AND2 outputs the logic of the output Q of the scan flip-flop SFFf to the OR gate OR2. On the other hand, during the system mode (TM = logic 0), the signal transmission function of the AND gate AND2 is disabled, and the node NDf which is the output of the AND gate AND2 is fixed to logic 0. This prevents the logic of the data output Q of the scan flip-flop SFFf that operates according to the logic received at the data input D during the system mode from being transmitted to the OR gate OR2, and prevents the user logic UL3 and the like from malfunctioning. . When the AND gate AND2 outputs the logic 0 to the node NDf, the logic of the node NDe, which is the output of the circuit CC3, is transmitted to the OR gate OR1 via the OR gate OR2. In this way, by connecting the scan flip-flop SFFf to the OR gate OR2 via the AND gate AND2 controlled by the test mode signal TM, malfunction due to the operation of the scan flip-flop SFFf in the system mode can be prevented.

  FIG. 11 shows an example of a test for detecting a delay fault of the logic circuit LOGICT shown in FIG. The operation of FIG. 11 is realized by the tester TEST illustrated in FIG. 7 executing the failure detection program, and is performed to detect the delay failure F1 illustrated in FIG. In other words, FIG. 11 shows a fault detection method for a delay fault in the logic circuit LOGICT, and shows a method for manufacturing a semiconductor integrated circuit LSI. Detailed descriptions of the same operations as those in FIG. 8 are omitted.

  In this example, logic 0, logic 0, logic 0, logic 0, logic 0, and logic 1 are sequentially supplied to the scan input SIN in the first to sixth clock cycles. In the sixth clock cycle, the scan flip-flops SFFb, SFFa, SFFf, and SFFe are set to logic 0, logic 1, logic 0, and logic 0, respectively. That is, in the sixth clock cycle, the scan flip-flops SFFb and SFFa connected in series to the input I1 of the OR gate OR1 hold different logics. Thus, as in FIG. 8, in the seventh clock cycle of the capture period, the logic held in the scan flip-flop SFFb can be changed from logic 0 to logic 1, and the input I1 of the OR gate OR1 is changed from logic 0 to logic 1. Can change.

  In the sixth clock cycle, the scan flip-flops SFFf and SFFe connected in series to the input I2 of the OR gate OR1 via the AND gate AND2 and the OR gate OR2 hold the same logic. As a result, in the seventh clock cycle of the capture period, the logic held in the scan flip-flop SFFf can be maintained at logic 0 using the logic held in the scan flip-flop SFFe one clock cycle before. Here, since the control point CP of FIG. 10 has an AND gate AND2 instead of the NAND gate NAND1 (FIG. 3), in order to operate the control point CP as a “0 control point”, the scan flip-flop SFFf, SFFe is set to logic zero. With the control point CP, the input I2 of the OR gate OR1 connected to the output node of the scan flip-flop SFFf can be maintained at logic zero.

  When the delay fault F1 does not exist, the logical change of the scan flip-flop SFFb immediately appears as the logical change of the output node NDi, as in FIG. The scan flip-flop SFFe latches logic 0 in the eighth clock cycle, and outputs the latched logic 0 to the scan-out terminal SOUT. The tester TEST shown in FIG. 7 detects that the delay fault F1 does not exist by reading the logic 0 of the scan-out terminal SOUT.

  On the other hand, when the delay fault F1 exists, the logic change of the scan flip-flop SFFb is transmitted to the output node NDi with a delay, as in FIG. In the eighth clock cycle, when the scan flip-flop SFFe cannot latch the logic 0 of the node NDi, the scan-out terminal SOUT is maintained at the logic 1. The tester TEST shown in FIG. 7 detects the presence of the delay fault F1 by reading the logic 1 of the scan-out terminal SOUT.

  FIG. 12 shows another example of a test for detecting a delay fault of the logic circuit LOGICT shown in FIG. The operation of FIG. 12 is realized by the tester TEST illustrated in FIG. 7 executing the failure detection program, and is performed to detect the delay failure F2 illustrated in FIG. In other words, FIG. 12 shows a fault detection method for delay faults in the logic circuit LOGICT, and shows a method for manufacturing a semiconductor integrated circuit LSI. Detailed descriptions of the same operations as those in FIGS. 8 and 9 are omitted.

  In this example, logic 1, logic 0, logic 0, logic 0, logic 0, and logic 0 are sequentially supplied to the scan input SIN in the first to sixth clock cycles. In the sixth clock cycle, the scan flip-flops SFFb, SFFa, SFFf, and SFFe are set to logic 0, logic 0, logic 0, and logic 1, respectively. That is, in the sixth clock cycle, the scan flip-flops SFFb and SFFa connected in series to the input I1 of the OR gate OR1 hold the same logic. The scan flip-flops SFFf and SFFe connected in series to the input I2 of the OR gate OR1 via the AND gate AND2 and the OR gate OR2 hold different logics.

  As a result, in the seventh clock cycle of the capture period, the logic held in the scan flip-flop SFFf is changed from logic 0 to logic 1 using the logic held in the scan flip-flop SFFe one clock cycle before. it can. That is, in the seventh clock cycle, the input I2 of the OR gate OR1 can be changed from the logical 0 to the logical 1 while the input I1 of the OR gate OR1 is maintained at the logical 0.

  When there is no delay fault F2, the logical change of the scan flip-flop SFFf is immediately transmitted to the input I2 of the OR gate OR1 and the nodes NDh and NDi. Similarly to FIG. 9, the scan flip-flop SFFe latches the logic 0 in the eighth clock cycle, and the tester TEST reads the logic 0 of the scan-out terminal SOUT in the ninth clock cycle. Thereby, it is detected that the delay fault F2 does not exist.

  On the other hand, when the delay fault F2 exists, the logical change of the scan flip-flop SFFf is transmitted with a delay to the input node I2 of the OR gate OR1, the output node NDh of the OR gate OR1, or the output node NDi of the circuit CC2. Similarly to FIG. 9, in the eighth clock cycle, when the scan flip-flop SFFe cannot latch the logic 0 of the node NDi, the scan-out terminal SOUT is maintained at the logic 1. The tester TEST shown in FIG. 7 detects the presence of the delay fault F2 by reading the logic 1 of the scan-out terminal SOUT in the ninth clock cycle of the scan shift period. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 13 shows another embodiment of a logic circuit failure detection method, a logic circuit test circuit insertion method, a logic circuit test circuit insertion device, and a semiconductor integrated circuit. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In the logic circuit LOGICT of this embodiment, the data input D of the scan flip-flop SFFf at the control point CP is connected to the data output Q of the scan flip-flop SFFd instead of the data output Q of the scan flip-flop SFFe shown in FIG. ing. Other configurations of the logic circuit LOGICT are the same as those in FIG. The logic circuit LOGIC in FIG. 13 is generated when the test circuit insertion device CAD shown in FIG. 5 executes the test circuit insertion program and performs the processing shown in FIG.

  FIG. 14 shows an example of a test for detecting a delay fault in the logic circuit LOGICT shown in FIG. The operation of FIG. 14 is realized by the tester TEST illustrated in FIG. 7 executing the failure detection program, and is performed to detect the delay failure F1 illustrated in FIG. In other words, FIG. 14 shows a fault detection method for a delay fault in the logic circuit LOGICT, and shows a method for manufacturing the semiconductor integrated circuit LSI. Detailed descriptions of the same operations as those in FIG. 8 are omitted.

  In this example, logic 1, logic 1, logic 1, logic 1, logic 1, logic 0, and logic 1 are sequentially supplied to the scan input SIN in the first to sixth clock cycles. In the sixth clock cycle, the scan flip-flops SFFb, SFFa, SFFf, and SFFd are set to logic 0, logic 1, logic 1, and logic 1, respectively. Then, when there is no delay fault F1, as in FIG. 8, the logical change of the scan flip-flop SFFb immediately appears as the logical change of the output node NDi, and the scan flip-flop SFFe has a logical 0 in the eighth clock cycle. Latch. When the delay fault F1 exists, the scan flip-flop SFFe cannot latch the logic 0 of the node NDi in the eighth clock cycle as in FIG. The tester TEST shown in FIG. 7 detects the presence or absence of the delay fault F1 by reading the logic of the scan-out terminal SOUT in the ninth clock cycle of the scan shift period.

  FIG. 15 shows another example of a test for detecting a delay fault in the logic circuit LOGICT shown in FIG. The operation of FIG. 15 is realized by the tester TEST illustrated in FIG. 7 executing the failure detection program, and is performed in order to detect the delay failure F2 illustrated in FIG. In other words, FIG. 15 shows a fault detection method for delay faults in the logic circuit LOGICT, and shows a method for manufacturing a semiconductor integrated circuit LSI. Detailed descriptions of the same operations as those in FIGS. 8 and 9 are omitted.

  In this example, logic 1, logic 1, logic 0, logic 0, logic 0, and logic 0 are sequentially supplied to the scan input SIN in the first to sixth clock cycles. In the sixth clock cycle, the scan flip-flops SFFb, SFFa, SFFf, and SFFd are set to logic 0, logic 0, logic 1, and logic 0, respectively. Then, when there is no delay fault F2, as in FIG. 9, the logical change of the scan flip-flop SFFf immediately appears as the logical change of the output node NDi, and the scan flip-flop SFFe has a logical 0 in the eighth clock cycle. Latch. When the delay fault F2 exists, the scan flip-flop SFFe cannot latch the logic 0 of the node NDi in the eighth clock cycle as in FIG. The tester TEST shown in FIG. 7 detects the presence or absence of the delay fault F2 by reading the logic of the scan-out terminal SOUT in the ninth clock cycle of the scan shift period. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 16 shows another embodiment of a logic circuit failure detection method, a logic circuit test circuit insertion method, a logic circuit test circuit insertion device, and a semiconductor integrated circuit. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In the logic circuit LOGICT of this embodiment, the data input D of the scan flip-flop SFFf at the control point CP is connected to the data output Q of the scan flip-flop SFFd instead of the data output Q of the scan flip-flop SFFe shown in FIG. ing. Other configurations of the logic circuit LOGICT are the same as those in FIG. The logic circuit LOGIC in FIG. 16 is generated when the test circuit insertion device CAD shown in FIG. 5 executes the test circuit insertion program and performs the processing shown in FIG.

  FIG. 17 shows an example of a test for detecting a delay fault in the logic circuit LOGICT shown in FIG. The operation of FIG. 17 is realized by the tester TEST illustrated in FIG. 7 executing the failure detection program, and is performed to detect the delay failure F1 illustrated in FIG. In other words, FIG. 17 shows a fault detection method for a delay fault in the logic circuit LOGICT, and shows a method for manufacturing a semiconductor integrated circuit LSI. Detailed descriptions of the same operations as those in FIGS. 8 and 11 are omitted.

  In this example, logic 0, logic 0, logic 0, logic 0, logic 0, and logic 1 are sequentially supplied to the scan input SIN in the first to sixth clock cycles. In the sixth clock cycle, the scan flip-flops SFFb, SFFa, SFFf, and SFFd are set to logic 0, logic 1, logic 0, and logic 0, respectively. Then, when the delay fault F1 does not exist, the logical change of the scan flip-flop SFFb immediately appears as the logical change of the output node NDi, as in FIG. 11, and the scan flip-flop SFFe has a logical 0 in the eighth clock cycle. Latch. When the delay fault F1 exists, the scan flip-flop SFFe cannot latch the logic 0 of the node NDi in the eighth clock cycle as in FIG. The tester TEST shown in FIG. 7 detects the presence or absence of the delay fault F1 by reading the logic of the scan-out terminal SOUT in the ninth clock cycle of the scan shift period.

  FIG. 18 shows another example of a test for detecting a delay fault of the logic circuit LOGICT shown in FIG. The operation of FIG. 18 is realized by the tester TEST illustrated in FIG. 7 executing the failure detection program, and is performed to detect the delay failure F2 illustrated in FIG. In other words, FIG. 15 shows a fault detection method for delay faults in the logic circuit LOGICT, and shows a method for manufacturing a semiconductor integrated circuit LSI. Detailed description of the same operations as those in FIGS. 8, 9 and 12 will be omitted.

  In this example, logic 0, logic 0, logic 1, logic 1, logic 0, and logic 0 are sequentially supplied to the scan input SIN in the first to sixth clock cycles. In the sixth clock cycle, the scan flip-flops SFFb, SFFa, SFFf, and SFFd are set to logic 0, logic 0, logic 0, and logic 1, respectively. Then, when there is no delay fault F2, as in FIG. 12, the logical change of the scan flip-flop SFFf immediately appears as the logical change of the output node NDi, and the scan flip-flop SFFe has a logical 0 in the eighth clock cycle. Latch. When the delay fault F2 exists, the scan flip-flop SFFe cannot latch the logic 0 of the node NDi in the eighth clock cycle as in FIG. The tester TEST shown in FIG. 7 detects the presence or absence of the delay fault F2 by reading the logic of the scan-out terminal SOUT in the ninth clock cycle of the scan shift period. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 19 shows another embodiment of a logic circuit failure detection method, a logic circuit test circuit insertion method, a logic circuit test circuit insertion device, and a semiconductor integrated circuit. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In the logic circuit LOGICT of this embodiment, the data input D of the scan flip-flop SFFf at the control point CP is connected to the data output Q of the scan flip-flop SFFc instead of the data output Q of the scan flip-flop SFFe shown in FIG. ing. Other configurations of the logic circuit LOGICT are the same as those in FIG. The logic circuit LOGIC in FIG. 19 is generated when the test circuit insertion device CAD shown in FIG. 5 executes the test circuit insertion program and performs the processing shown in FIG.

  FIG. 20 shows an example of a test for detecting a delay fault of the logic circuit LOGICT shown in FIG. The operation of FIG. 20 is realized by the tester TEST illustrated in FIG. 7 executing the failure detection program, and is performed to detect the delay failure F1 illustrated in FIG. In other words, FIG. 20 shows a fault detection method for a delay fault in the logic circuit LOGICT, and shows a method for manufacturing a semiconductor integrated circuit LSI. Detailed descriptions of the same operations as those in FIGS. 8 and 14 are omitted.

  In this example, logic 1, logic 1, logic 1, logic 1, logic 1, logic 0, and logic 1 are sequentially supplied to the scan input SIN in the first to sixth clock cycles. In the sixth clock cycle, the scan flip-flops SFFb, SFFa, SFFf, and SFFc are set to logic 0, logic 1, logic 1, and logic 1, respectively. Then, when there is no delay fault F1, as in FIG. 14, the logical change of the scan flip-flop SFFb immediately appears as the logical change of the output node NDi, and the scan flip-flop SFFe has a logical 0 in the eighth clock cycle. Latch. When the delay fault F1 exists, the scan flip-flop SFFe cannot latch the logic 0 of the node NDi in the eighth clock cycle as in FIG. The tester TEST shown in FIG. 7 detects the presence or absence of the delay fault F1 by reading the logic of the scan-out terminal SOUT in the ninth clock cycle of the scan shift period.

  FIG. 21 shows another example of a test for detecting a delay fault of the logic circuit LOGICT shown in FIG. The operation of FIG. 21 is realized by the tester TEST illustrated in FIG. 7 executing the failure detection program, and is performed to detect the delay failure F2 illustrated in FIG. In other words, FIG. 21 shows a fault detection method for a delay fault of the logic circuit LOGICT, and shows a method for manufacturing a semiconductor integrated circuit LSI. Detailed descriptions of the same operations as those in FIGS. 8, 9 and 15 are omitted.

  In this example, logic 1, logic 1, logic 0, logic 0, logic 0, and logic 0 are sequentially supplied to the scan input SIN in the first to sixth clock cycles. In the sixth clock cycle, the scan flip-flops SFFb, SFFa, SFFf, and SFFc are set to logic 0, logic 0, logic 1, and logic 0, respectively. Then, when there is no delay fault F2, as in FIG. 15, the logic change of the scan flip-flop SFFf immediately appears as the logic change of the output node NDi, and the scan flip-flop SFFe has a logic 0 in the eighth clock cycle. Latch. When the delay fault F2 exists, the scan flip-flop SFFe cannot latch the logic 0 of the node NDi in the eighth clock cycle as in FIG. The tester TEST shown in FIG. 7 detects the presence or absence of the delay fault F2 by reading the logic of the scan-out terminal SOUT in the ninth clock cycle of the scan shift period. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and changes, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  CAD, test circuit insertion device; CC1, CC2, circuit; CP, control point, CPU, processor, DISP, display; DRV, disk drive device; FF1-FF4, FFa-FFf, flip-flop; INOUT, input / output device; Input device; L1, L2 Logic gate; LSI Semiconductor integrated circuit; LOGIC, LOGICT Logic circuit; MEM Memory device; PRB Probe; SFF1-SFF4, SFFa-SFFf Scan flip-flop; SM Scan mode input; TEST Tester; TSYS Test system; UL1, UL2, UL3 User logic; WAF Semiconductor wafer

Claims (8)

A first user logic including a plurality of first scan flip-flops having a data input and a scan input; a second user logic including at least one first scan flip-flop; and a first user logic connected to an output of the first user logic. A first logic gate having one input; a third user logic including at least one first scan flip-flop connected to an output of the first logic gate; the second user logic; and the first logic gate; and a inserted control point between the control point, a second one of the data output of the first scan flip-flop of the second user logic or the third user logic is connected to the data input A scan flip-flop and a pair of inputs are connected to the data output of the second scan flip-flop and the previous Is connected to the output of the second user logic, the output is a fault detection method for a logic circuit and a second logic gate connected to the second input of the first logic gate,
The one of the first scan flip-flops of the second user logic or the third user logic and the scan shift period in which the scan input is enabled and the first and second scan flip-flops operate as a shift register. Setting the same logic to the second scan flip-flop, setting different logics to a pair of the first scan flip-flops of the first user logic connected in series to the first input;
When two clock pulses are supplied to the first and second scan flip-flops during the capture period for enabling the data input, and the logic held in the first scan flip-flop of the third user logic does not change And detecting a delay fault in a signal path including the first input. In the scan shift period, different logics are set in the first scan flip-flop and the second scan flip-flop of the second user logic or the third user logic, and the pair of first scan flip-flops Are set to the same logic, two clock pulses are supplied to the first and second scan flip-flops during the capture period, and the logic held in the first scan flip-flop of the third user logic does not change. 2. The logic circuit fault detection method according to claim 1, wherein a delay fault of a signal path including the second input is sometimes detected. The control point is disposed between a data output of the second scan flip-flop and the second logic gate, and an output signal from the second scan flip-flop is supplied to the second logic gate during the test mode. And transmitting the output signal to the second logic gate during a period excluding the test mode, and outputting the output signal from the second user logic via the second logic gate to the first logic gate. A mask circuit for outputting a logic value to be transmitted to the gate to the second logic gate;
3. The logic circuit failure detection method according to claim 1, wherein the scan shift period and the capture period are performed during the test mode. A first user logic including a plurality of flip-flops; a second user logic including at least one first scan flip-flop; and a first input connected to an output of the first user logic and an output of the second user logic. A test circuit insertion method for a logic circuit comprising: a first logic gate having a second input connected; and a third user logic connected to an output of the first logic gate and including at least one flip-flop,
Replacing the flip-flop with a first scan flip-flop each having a data input and a scan input;
A second scan flip-flop having a data input and a scan input, a pair of inputs connected to the data output of the second scan flip-flop and the output of the second user logic, respectively, and an output connected to the second input Inserting a control point having a second logic gate between the second user logic and the first logic gate;
And a process for connecting one data output of the first scan flip-flop of the second user logic or the third user logic to a data input of the second scan flip-flop. Insertion method. During the test mode, the output signal from the second scan flip-flop is transmitted to the second logic gate, and during the period other than the test mode, the transmission of the output signal to the second logic gate is masked. A mask circuit that outputs a logic value for transmitting an output signal from the second user logic to the first logic gate via the second logic gate is provided in the second scan flip-flop. The method for inserting a test circuit of a logic circuit according to claim 4, further comprising a process of arranging between a data output and the second logic gate. A first user logic including a plurality of flip-flops; a second user logic including at least one first scan flip-flop; and a first input connected to an output of the first user logic and an output of the second user logic. A test circuit insertion device for a logic circuit, comprising: a first logic gate having a second input connected; and a third user logic connected to the output of the first logic gate and including at least one flip-flop,
Replacing the flip-flop with a first scan flip-flop each having a data input and a scan input;
A second scan flip-flop having a data input and a scan input, a pair of inputs connected to the data output of the second scan flip-flop and the output of the second user logic, respectively, and an output connected to the second input Inserting a control point having a second logic gate between the second user logic and the first logic gate;
A process for connecting one data output of the first scan flip-flop of the second user logic or the third user logic to a data input of the second scan flip-flop. Circuit insertion device. During the test mode, the output signal from the second scan flip-flop is transmitted to the second logic gate, and during the period excluding the test mode, the transmission of the output signal to the second logic gate is masked, and A mask circuit for outputting a logic value for transmitting an output signal from a second user logic to the first logic gate through the second logic gate to the second logic gate. The logic circuit test circuit insertion device according to claim 6, wherein a process of arranging between an output and the second logic gate is performed. First user logic including a plurality of first scan flip-flops having a data input and a scan input;
A second user logic including at least one first scan flip-flop ;
A first logic gate having a first input connected to the output of the first user logic;
A third user logic including at least one first scan flip-flop and connected to an output of the first logic gate;
Data output of the second user logic or the third second scan flip-flop and said pair of input second scan flip-flop in which one data output of the first scan flip-flop of the user logic is connected to the data input And a mask circuit connected to a test mode terminal indicating a test mode, a pair of inputs connected to an output of the mask circuit and an output of the second user logic, respectively, and an output to a second input of the first logic gate A control point having a second logic gate connected thereto,
The mask circuit transmits an output signal from the second scan flip-flop to the second logic gate during the test mode, and outputs the output signal to the second logic gate during a period other than the test mode. The transmission is masked, and a logic value for transmitting an output signal from the second user logic to the first logic gate through the second logic gate is output to the second logic gate. Semiconductor integrated circuit.

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