JP4888242B2 - Manufacturing method of silicon epitaxial wafer - Google Patents

Description

  The present invention relates to a method for manufacturing a silicon epitaxial wafer in which a silicon epitaxial layer is vapor-phase grown on a silicon wafer.

  In the field of semiconductor manufacturing, a silicon epitaxial wafer (hereinafter referred to as epitaxial) in which a silicon epitaxial layer (hereinafter also referred to as epitaxial layer) is grown on a silicon single crystal substrate (hereinafter also referred to as silicon wafer). Conventionally known as “wafer”. An epitaxial wafer can form an epitaxial layer having an arbitrary thickness and resistance on a silicon single crystal substrate, and can also eliminate the grow-in defect problem that hinders device fabrication. It is used for bipolar circuits and CMOS circuits.

In recent years, the demand for miniaturization of semiconductor devices has increased, and the quality of epitaxial wafers used has been demanded accordingly. In particular, the uniformity of the thickness of the epitaxial layer is an important requirement and greatly affects the photolithography process and the like. Vapor phase epitaxy is generally used for epitaxial growth of silicon wafers, and a silane-based gas is used as a silicon source gas (hereinafter sometimes referred to as source gas), and H ₂ gas is used as a carrier gas. Often to do.

  More specifically, the epitaxial wafer is manufactured by the following process.

For example, as shown in FIG. 1, first, a silicon single crystal substrate is charged into a reaction vessel set to a charging temperature (for example, about 650 ° C.) (charging step S7).
Next, the inside of the reaction vessel is heated (heated) to a hydrogen heat treatment temperature (for example, about 1100 ° C. to 1180 ° C.) (temperature raising step S8), and the hydrogen heat treatment is performed to etch the oxide film on the silicon substrate surface with hydrogen. (Hydrogen treatment step S9).
Next, the inside of the reaction vessel is set to a growth temperature (for example, about 1060 ° C. to 1150 ° C.), and a silicon source gas (for example, trichlorosilane) is supplied onto the main surface of the silicon single crystal substrate. Thus, an epitaxial layer is vapor-grown on the main surface of the silicon single crystal substrate to manufacture an epitaxial wafer (vapor-phase growth step S10). Specifically, the hydrogen heat treatment is performed until just before the start of vapor phase growth.
Next, the inside of the reaction vessel is cooled (cooled down) to a take-out temperature (for example, about 650 ° C. as in the above-described charging temperature) (temperature drop step S11), and the epitaxial wafer is taken out from the reaction vessel (take-out step S12).

  Moreover, an epitaxial wafer can be manufactured sequentially by repeating the above steps (S7 to S12).

As an apparatus for vapor-phase growing an epitaxial layer on a silicon wafer, FIG. In this apparatus, the silicon wafers W placed one by one in a reaction vessel 1 made of transparent quartz are subjected to vapor deposition of a thin film while being radiatively heated from above and below using infrared lamps 9a and 9b. . The infrared lamps 9a and 9b are arranged in a double concentric shape, and the infrared lamp 9a constitutes one set on the outside and the infrared lamp 9b constitutes one set on the inside. The inside of the reaction vessel 1 is divided into an upper space 1a and a lower space 1b by a susceptor 5 on which the silicon wafer W is placed. In this upper space 1a, the silicon source gas introduced together with the carrier gas H ₂ gas from the upper gas supply port 2 flows in the direction of arrow A in the figure while forming a substantially laminar flow on the surface of the silicon wafer W, and on the opposite side Are discharged from the exhaust port 4. The lower space 1b is supplied with H ₂ gas, which is a purge gas, at a pressure higher than that of the silicon source gas from the lower gas supply port 3. The reason why the purge gas is set to high pressure is to prevent the raw material gas from entering the lower space 1b through the gap between the reaction vessel 1 and the susceptor 5.

  The lower space 1b incorporates support means made of quartz for supporting the susceptor 5 from the back surface and lift pins 8 for attaching and detaching the silicon wafer W on the susceptor 5. The support means can be moved up and down as indicated by an arrow B in the figure, and includes a rotating shaft 6 and a plurality of spokes 7 that diverge radially from the rotating shaft 6. A vertical pin 7 b is provided at the end of the spoke 7, and the tip of the vertical pin 7 b is supported by being fitted into recesses 5 c and 5 d provided on the back surface of the susceptor 5. . The rotating shaft 6 can be rotated in the direction of arrow C in the drawing by a driving means (not shown).

  The lift pin 8 has an enlarged head portion, and the head portion is suspended from a tapered side wall portion of a through hole 5b provided on the bottom surface of the countersink portion 5a of the susceptor 5 on which the silicon wafer W is placed. Yes. The shaft portion of the lift pin 8 is inserted into a through hole 7a formed in the middle portion of the spoke 7 so that the lift pin 8 is stably suspended.

  The silicon wafer W is attached to and detached from the susceptor 5 by raising and lowering the support means. For example, when removing the silicon wafer W from the susceptor 5, the support means is lowered and the lower end portion of the lift pin 8 is brought into contact with the inner wall of the lower space 1 b of the reaction vessel 1. The lift pins 8 biased thereby collide with the back surface of the silicon wafer W at the head, and the silicon wafer W is floated above the countersink portion 5a. Thereafter, a hand (not shown) is inserted into the space between the susceptor 5 and the silicon wafer W, and the silicon wafer W is transferred and transported.

  As the constituent material of the susceptor 5, a graphite base material coated with a SiC (silicon carbide) film is usually used. The reason why graphite is selected as the base material is related to the fact that the main heating method of the vapor-phase thin film growth equipment at the beginning of development was high-frequency induction heating, but it is also easy to obtain high-purity products. This is because there are merits such as easy processing, excellent thermal conductivity, and less damage.

  However, because graphite is a porous material, there is a possibility of releasing occluded gas during the process, and in the course of vapor phase thin film growth, the surface of the susceptor changes to SiC due to the reaction of graphite and source gas. The structure which covers the surface with a SiC film from the beginning is generalized. The SiC film is usually formed by CVD (Chemical Vapor Deposition). Similarly to the susceptor 5, the constituent material of the lift pin 8 is a SiC-based graphite-coated material. The vapor phase growth apparatus is disclosed in, for example, Japanese Patent Laid-Open No. 2000-103696.

  However, when an epitaxial layer is grown on a silicon wafer using the above vapor phase growth apparatus, the metal that appears to have been generated from the inner wall of the lower chamber or the susceptor rotation mechanism adheres to the growth surface, and crystal defects, metal There was a problem of causing contamination.

JP 2000-103696 A

  In order to solve the above-described problems, an object of the present invention is to provide an epitaxial wafer manufacturing method with less metal contamination on a wafer.

In order to achieve the above object, the present invention provides a silicon wafer placed on a rotating susceptor horizontally supported in a reaction vessel, and a silicon epitaxial layer is vapor-phased on the silicon wafer while heating the silicon wafer. A method for producing a silicon epitaxial wafer to be grown, wherein an H ₂ gas that is a carrier gas is supplied from an upper gas supply port together with a raw material gas into an upper space with respect to the susceptor of the reaction vessel. In a method of vapor-growing a silicon epitaxial layer by supplying H ₂ gas as a purge gas from a lower gas supply port to a lower space, before the production of a product, the upper gas supply port is used in advance of actual product manufacturing conditions. The ratio of the supplied carrier gas flow rate to the purge gas flow rate supplied from the lower gas supply port is changed. Then, a flow rate change test for vapor-phase growth of the silicon epitaxial layer is performed, and a metal contamination level in the silicon epitaxial layer is measured to obtain a relationship between the ratio of the gas flow rate and the metal contamination level. The gas flow rate ratio condition in which the metal contamination on the wafer is in a relatively low contamination level is determined, and the silicon epitaxial layer is evaporated on the silicon wafer under the condition within the determined gas flow rate ratio range. A silicon epitaxial wafer manufacturing method characterized by manufacturing a silicon epitaxial wafer as a product by phase growth.

  Thus, before manufacturing a silicon epitaxial wafer as a product, among actual product manufacturing conditions, the carrier gas flow rate supplied from the upper gas supply port to the susceptor of the reaction vessel on which the silicon wafer is placed in advance. And a flow rate change test for vapor phase growth of the silicon epitaxial layer by changing the ratio of the flow rate of the purge gas supplied from the lower gas supply port to the susceptor, and measuring the metal contamination level in the silicon epitaxial layer Then, by obtaining the relationship between the ratio of the gas flow rate and the metal contamination level, the condition of the gas flow rate ratio in which the metal contamination on the silicon wafer falls within a relatively low contamination level can be obtained. . Based on the obtained conditions, when actually manufacturing the product, the ratio of the upper and lower gas flow rate is controlled within the found range, and if the operation for manufacturing the product is performed, a silicon epitaxial layer with a low metal contamination level can be formed. Vapor phase growth is possible, and as a result, a silicon epitaxial wafer with a low metal contamination level can be obtained.

  Further, it is preferable that the ratio of the gas flow rate is changed by changing only the lower gas flow rate.

  Thus, by changing only the lower gas flow rate and changing the ratio of the upper and lower gas flow rates without changing the upper gas flow rate, an epitaxial layer with a relatively low metal contamination level on the silicon wafer has a uniform thickness. Thus, it is possible to find a range of the upper and lower gas flow ratios that can be vapor-phase grown without impairing the properties.

  The method for producing a silicon epitaxial wafer according to the present invention is a method for producing a silicon epitaxial wafer obtained by vapor-phase-growing a silicon epitaxial layer on the silicon wafer. A silicon epitaxial wafer manufacturing method capable of obtaining a silicon epitaxial wafer having a sufficiently reduced metal contamination level without impairing thickness uniformity and improving product quality level and productivity. Can be provided.

  As described above, in the conventional technique, when an epitaxial layer is grown on a silicon wafer, metal that appears to be generated from the inner wall of the lower chamber or the susceptor rotation mechanism adheres to the growth surface, causing crystal defects and metal contamination. There was a problem of generating.

As a result of intensive studies to solve the above problems, the present inventor is supplied from the upper gas supply port to the susceptor of the reaction vessel on which the silicon wafer is placed in the single wafer vapor phase growth apparatus. The ratio of the upper H ₂ gas flow rate (carrier gas flow rate) and the lower H ₂ gas flow rate (purge gas flow rate) supplied from the lower gas supply port to the susceptor (hereinafter referred to as the upper and lower gas flow rate ratio) is metal. It has been found that it has an important role in pollution. Therefore, the relationship between the upper and lower gas flow rate ratio and the metal contamination level is obtained in advance by experiments before manufacturing the product, and the range of the upper and lower gas flow rate ratio where the level of metal contamination generated on the silicon wafer is relatively low is found. If the gas flow ratio in the upper and lower gas flow ratio is controlled within this range when the product is manufactured, an epitaxial layer with less metal contamination can be vapor-phase grown, and the occurrence of metal contamination on the silicon wafer is reduced. It will be.

  However, this upper and lower gas flow ratio varies depending on the conditions for stacking the epitaxial layer, that is, the diameter of the silicon wafer, conductivity type, growth temperature, growth rate, reaction vessel, susceptor shape, etc. Except for changing, it is necessary to conduct experiments under the same conditions as the actual one and to individually find the range of the upper and lower gas flow rate ratios in which metal contamination hardly occurs. After that, if the upper and lower gas flow ratios are controlled and operated within the found range, the occurrence of metal contamination on the silicon wafer can be surely reduced.

In addition, when changing the upper and lower gas flow ratio, it is preferable to adjust the upper and lower gas flow ratio by changing only the lower H ₂ gas flow without changing the upper H ₂ gas flow. This is because the upper H ₂ gas flow rate may be specified in order to adjust the uniformity of the epitaxial layer thickness. By changing the upper and lower gas flow ratios, the range of the upper and lower gas flow ratios allows vapor phase growth of an epitaxial layer having a relatively low metal contamination level on a silicon wafer without impairing the thickness uniformity. Can be found.

  As described above, the upper and lower gas flow ratios depend on manufacturing conditions. That is, if the range of the upper and lower gas flow ratio in which the level of metal contamination generated on the silicon wafer is relatively low is found in advance, the same applies by applying the upper and lower gas flow ratio in the same manufacturing conditions. An epitaxial layer having a relatively low metal contamination level can be vapor-phase grown on the silicon wafer without impairing the uniformity of the thickness, and a silicon epitaxial wafer with a sufficiently reduced metal contamination level can be obtained. Product quality level and productivity can be improved.

  Hereinafter, embodiments of the present invention will be described in detail, but the present invention is not limited thereto.

Using the single-wafer vapor phase thin film growth apparatus 10 shown in FIG. 2, the flow rate of gas supplied from the upper gas supply port 2 in the upper space 1a on the upper space 1a with respect to the susceptor 5 of the reaction vessel 1 on which the silicon wafer W is placed. and among H ₂ carrier gas flow consisting of gas (upper H ₂ gas flow rate), the purge gas consisting of H ₂ gas is a gas flow supplied from the lower gas supply port 3 at the lower side of the lower space 1b with respect to the susceptor 5 The ratio of the flow rate (lower H ₂ gas flow rate), that is, the upper and lower H ₂ gas flow rate ratio (upper H ₂ gas flow rate / lower H ₂ gas flow rate) is set to about 5 levels between 0.5 and 5. The upper H ₂ gas flow rate, the raw material gas flow rate, and the reaction temperature are the same as the actual product manufacturing conditions.

  Next, a silicon wafer W to be a substrate is placed in the reaction vessel 1 at 700 to 950 ° C., and vapor phase growth of the epitaxial layer is performed as follows using one of the set five levels. In this case, the reaction temperature is varied between 1060 and 1180 ° C., and the epitaxial layer thickness is about 2 to 20 μm.

The inside of the reaction vessel 1 is heated (heated up) to a hydrogen heat treatment temperature (for example, about 1100 ° C. to 1180 ° C.), and the hydrogen oxide heat treatment is performed to remove the oxide film on the silicon substrate surface by etching with hydrogen. Next, the inside of the reaction vessel is set to a growth temperature (for example, about 1060 ° C. to 1150 ° C.), and H is a carrier gas together with a silicon source gas from the gas supply port 2 in the upper space 1a onto the main surface of the silicon wafer W. _Two gases are supplied. Further, H ₂ gas, which is a purge gas, is supplied from the gas supply port 3 in the lower space 1b at a pressure higher than that of the silicon source gas. At this time, the gas flow rate of the purge gas supplied from the lower gas supply port 3 is adjusted to be a ratio of a set level with respect to the gas flow rate of the carrier gas supplied from the upper gas supply port 2. In this manner, an epitaxial layer is vapor-grown on the main surface of the silicon wafer W to manufacture an epitaxial wafer. Next, the inside of the reaction vessel 1 is cooled (cooled down) to the take-out temperature (for example, about 700 ° C. as in the above-described charging temperature), and the epitaxial wafer is taken out from the inside of the reaction vessel 1. Next, a new silicon wafer W is put into the reaction vessel 1 and epitaxial growth is performed using all the levels set by changing the upper and lower gas flow ratio.

  Thereafter, the metal contamination level is measured in all the produced epitaxial wafers, and the metal contamination level and the upper and lower gas flow ratio are graphed to find the upper and lower gas flow ratio with a relatively low metal contamination level.

  The above-described upper and lower gas flow ratio range where the metal contamination level is low is applied to the conditions for manufacturing an actual product to manufacture an epitaxial wafer as a product. In this case, it is naturally preferable to manufacture the product at the ratio of the upper and lower gas flow rates at which the metal contamination level is lowest. This appropriate upper and lower gas flow ratio depends on other manufacturing conditions. Therefore, the above relationship needs to be obtained for each manufacturing condition. On the other hand, if the other manufacturing conditions do not change, the relationship between the upper and lower gas flow ratio and the metal contamination level does not change. Therefore, once this ratio is clarified before manufacturing the product, it is not necessary to conduct an experiment again.

  Examples of the present invention will be described in more detail below, but the present invention is not limited thereto.

(Example)
As described above, H ₂ out of the gas flow rate in the upper space 1a above the susceptor 5 of the reaction vessel 1 on which the silicon wafer W is placed, using the single wafer vapor phase thin film growth apparatus 10 shown in FIG. a carrier gas flow consisting of gas (upper H ₂ gas flow rate), the ratio of the purge gas flow rate (lower H ₂ gas flow rate) consisting of H ₂ gas is a gas flow rate in the lower side of the lower space 1b with respect to the susceptor 5, i.e. The upper and lower gas flow rate ratio (upper H ₂ gas flow rate / lower H ₂ gas flow rate) was set to 8 levels between 0.5 and 5. In this case, the upper H ₂ gas flow rate was not changed from the product manufacturing conditions, but only the lower H ₂ gas flow rate was changed and adjusted so as to have a ratio of each set level.

Next, the silicon wafer W to be the substrate was put into the reaction vessel 1 at 900 ° C., and vapor phase growth of the epitaxial layer was performed as described above using all of the set eight levels to obtain a total of eight epitaxial wafers. . In this case, the upper H ₂ gas flow rate was 50 liters / minute, trichlorosilane was used as the source gas, and the flow rate was 12 liters / minute. The reaction temperature was 1130.degree. C. for hydrogen heat treatment, 1130.degree. C. for growth, and 900.degree. C. for extraction. The film thickness of the epitaxial layer for vapor phase growth was about 10 .mu.m. Thereafter, the metal contamination level was measured in all eight epitaxial wafers fabricated using these levels, respectively, and the metal contamination level and the upper and lower gas flow ratio were graphed (FIG. 3). Here, the metal contamination level is represented by the Fe concentration (atoms / cm ³ ), and as a measurement method, a method obtained by calculation from a diffusion length measurement value of the SPV method was used.

  As shown in FIG. 3, the metal contamination level was stable when the upper and lower gas flow ratio ≧ 3. However, it was found that the metal contamination level in the epitaxial layer was worse when manufactured under the condition of the upper and lower gas flow rate ratio ≦ 2, compared with the case where the upper and lower gas flow rate ratio ≧ 3. Therefore, when the product manufacturing conditions are set in the range of 3 ≦ upper and lower gas flow ratio ≦ 5, and an epitaxial wafer that is actually a product is manufactured under the upper and lower gas flow ratio conditions, the metal contamination level is low and the thickness is reduced. It was possible to vapor-phase grow an epitaxial layer having a uniform thickness, and to obtain an epitaxial wafer having a sufficiently low metal contamination level.

  From the above results, in the manufacturing method according to the present invention, before manufacturing the product, the actual product manufacturing conditions are adjusted to a plurality of level values set by changing only the upper and lower gas flow rate ratios, and the respective levels are used. Then, a flow rate change test for vapor phase growth of the silicon epitaxial layer is performed, and the relationship between the upper and lower gas flow rate ratio and the metal contamination level is obtained, and as a result, the metal contamination on the silicon wafer has a relatively low contamination level. By clarifying the range of the upper and lower gas flow ratio conditions, it becomes possible to produce silicon epitaxial wafers as products without sacrificing thickness uniformity while maintaining metal contamination at a good level even at the production site. I understood.

  The present invention is not limited to the above embodiment. The above embodiment is an exemplification, and the technical scope of the present invention is anything that has substantially the same configuration as the technical idea described in the claims of the present invention and has the same effect. Is included.

  For example, in the above, in order to change the upper and lower gas flow rate ratio, only the lower gas flow rate is changed to change the flow rate ratio, but this is because the upper gas flow rate cannot be changed due to the uniformity of the epitaxial layer thickness. In other words, the present invention is not limited to this. When the upper gas flow rate can be changed, such as when the thickness uniformity does not deteriorate, the gas flow rate ratio may be changed by changing the upper gas flow rate, or the gas flow rate may be changed both in the upper and lower directions. You may make it adjust.

It is an example of the manufacturing method of a general epitaxial wafer. 1 is a schematic view of a general single-wafer vapor phase thin film growth apparatus. In the Example of this invention, a metal contamination level and the upper and lower gas flow ratio are graphed.

Explanation of symbols

S7 ... charging step, S8 ... temperature rising step, S9 ... hydrogen heat treatment step,
S10: Vapor phase growth step, S11: Temperature lowering step, S12 ... Extraction step,
DESCRIPTION OF SYMBOLS 10 ... Single wafer type vapor-phase thin film growth apparatus, 1 ... Reaction container, 1a ... Upper space,
1b ... lower space, 2 ... upper gas supply port, 3 ... lower gas supply port,
4 ... exhaust port, 5 ... susceptor, 5a ... counterbore part, 5b ... through hole,
5c ... (recessed on the back side of the susceptor), 5d ... (recessed on the back side of the susceptor),
6 ... Rotating shaft, 7 ... Spoke, 7a ... Through hole, 7b ... Vertical pin,
8 ... Lift pin, 9a ... Infrared lamp (outside),
9b: Infrared lamp (inside) W: Silicon wafer,
A: Flow direction of the upper gas, B: Operation direction of the support means, C: Direction of rotation of the rotating shaft 6.

Claims (2)

A silicon epitaxial wafer manufacturing method in which a silicon wafer is placed on a rotary susceptor horizontally supported in a reaction vessel, and a silicon epitaxial layer is vapor-phase grown on the silicon wafer while heating the silicon wafer. The H ₂ gas as a carrier gas is supplied from the upper gas supply port to the upper space with respect to the susceptor of the reaction vessel, and the purge gas is supplied to the lower space with respect to the susceptor from the lower gas supply port. In the method of vapor-phase-growing the silicon epitaxial layer by supplying H ₂ gas, the carrier gas flow rate supplied from the upper gas supply port and the lower gas supply among the actual product manufacturing conditions in advance before manufacturing the product Change the ratio to the purge gas flow rate supplied from the port to change the silicon epitaxial layer A flow rate change test for phase growth is performed, and the metal contamination level in the silicon epitaxial layer is measured to determine the relationship between the ratio of the gas flow rate and the metal contamination level. As a result, the metal contamination on the silicon wafer is relatively The condition for the ratio of the gas flow rate in which the contamination level is low is obtained, and a silicon epitaxial layer is vapor-phase grown on the silicon wafer under the condition within the determined gas flow rate ratio. A method for producing a silicon epitaxial wafer, comprising producing an epitaxial wafer. 2. The method of manufacturing a silicon epitaxial wafer according to claim 1, wherein the change of the gas flow rate ratio is performed by changing only the lower gas flow rate.

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