JP4839263B2 - Semiconductor switch device - Google Patents

Description

  The present invention relates to a semiconductor switch device which is applied to, for example, a high-frequency amplifier tube (klystron) and which applies a high voltage, for example, a 10 KV class voltage, and cuts off a large current, for example, about 2000 A.

  Conventionally, for example, as a semiconductor switch device that is applied to an excimer laser device and is suitable for high-voltage / high-current high-speed switching operation, and reduces the inductance of semiconductor elements connected in multiple series, as follows: The configuration is described in Patent Document 1. That is, a series circuit in which a plurality of semiconductor switch elements and radiating fins are alternately stacked, a first switch module in which a plurality of conductors arranged in a cylindrical shape around the semiconductor circuit are connected in series at one end, and the polarity of the first switch module Are connected between the second switch module of a series circuit in which semiconductor switch elements and radiating fins are alternately stacked and the conductor ends of each switch module arranged in a cylindrical shape. Specifically, the return-side conductor has a coaxial structure and cancels out the magnetic flux, thereby reducing the inductance and reducing the insulation resistance at half the total length of the switch.

As described above, since the invention of Patent Document 1 is connected with the polarity of the first switch module and that of the second switch module reversed, it is possible to provide a compact semiconductor switch device suitable for high voltage and high speed switching operation. .
JP-A-8-242149

  However, there are some technical problems in developing and putting the invention of Patent Document 1 described above into practical use, and one of them exists in the circuit when the circuit current between the power source and the load is cut off. Even a semiconductor switch device in which a snubber capacitor that absorbs the energy of the total inductance is connected to each semiconductor element can make the whole compact and reduce the round-trip inductance and unbalance the voltage jump of each semiconductor element. It is necessary to suppress.

  Furthermore, since the invention of Patent Document 1 uses a thyristor as each semiconductor element, a gate drive circuit for turning off each thyristor is not necessary. However, when a self-extinguishing element is used as a semiconductor element, In addition, it is necessary to provide a snubber circuit and a gate drive circuit for each semiconductor element, and it is difficult to make the whole compact when a semiconductor switch device in which these are integrated.

  The present invention can reduce the total inductance by reducing the total inductance by reducing the total inductance, and can suppress the voltage jump generated at both ends of the switch when the current is interrupted, and can also imbalance the voltage jump of each semiconductor element. An object of the present invention is to provide a semiconductor switch device that can be suppressed.

In order to achieve the above object, the invention corresponding to claim 1 includes a snubber capacitor in which at least two flat semiconductor elements are electrically connected in series and electrically connected to both ends of each of the semiconductor elements, A semiconductor laminated structure in which a plurality of flat semiconductors with a snubber capacitor are press-contacted so as to be connected in series is connected between one of a positive bus or a negative bus of a DC power source and a load terminal, and the DC power source In the semiconductor switch device that cuts off the current flowing between the load and the load,
The semiconductor multilayer structure is disposed substantially parallel to an arbitrary position on an installation surface, and each of the snubber capacitors is in a direction perpendicular to the axial direction of the semiconductor multilayer structure, and at least one of the snubber capacitors is installed in the installation plane. The semiconductor multilayer structure is disposed in an upper position and a lower position in a direction perpendicular to the surface and parallel to the semiconductor multilayer structure on the side where the snubber capacitor is not disposed in the semiconductor multilayer structure. The negative side bus or the positive side bus other than the positive side bus or the negative side bus connected to the
The input side connection conductor and the output side connection conductor that connect the input side terminal and output side terminal of each snubber capacitor and the anode, collector, cathode, or emitter of each semiconductor element, respectively, are substantially parallel to each other, and This is a semiconductor switch device in which the magnetic flux generated in each of the side connection conductor and the output side connection conductor is canceled.

  According to the present invention, the whole can be made compact and the total inductance is reduced, thereby suppressing the voltage jump generated at both ends of the switch at the time of current interruption and suppressing the voltage jump unbalance of each semiconductor element. The semiconductor switch device which can be provided can be provided.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a main circuit of a first embodiment according to the semiconductor switch device of the present invention, which is at least two (here, six) self-extinguishing type flat semiconductor elements E1, E2. , E3, E4, E5, E6 (collectively E) are electrically connected in series, and between each of the semiconductor elements E1 to E6 and at the end thereof, a refrigerant-type, for example, a water-cooled, for example, copper radiating fin F1, F2, F3, F4, F5, F6, F7, and a semiconductor laminated structure in which springs (not shown) for applying a pressure contact force are provided between the semiconductor elements E1 to E6, and these are integrated with a connecting rod (not shown) Pressure contact type semiconductor stack) PS and at least two (here, six) snubber capacitors C1, C2, C3, C4, C5, C6 (in this case, electrically connected in parallel to the collector and emitter of each of the semiconductor elements E1 to E6) Collectively For example, a DC power source S is connected to the input terminal PI which is one terminal of the semiconductor stacked structure PS (for example, also serving as the positive bus P) and the input terminal NI which is one terminal of the negative bus N A load L such as a high-frequency amplifier tube is connected to the output terminal PO, which is the other terminal of the semiconductor multilayer structure PS, and the output terminal NO, which is the other terminal of the negative bus N.

  Further, between the output terminal PO and the output terminal NO, a reflux circuit K for returning the current flowing through the inductances up to the output terminals PO and NO and the load L when the switch is shut off and suppressing the voltage generated at both ends of the switch. Is provided.

  Note that the DC power source S includes a capacitor and a charger that charges the capacitor.

  Next, a characteristic configuration of the present invention will be described with reference to FIGS. An insulator is provided on the installation plate B disposed on the installation surface, and the semiconductor multilayer structure PS is disposed on the insulator approximately parallel to the installation plate B, and will be described later on one side of the semiconductor multilayer structure PS. A rack R for supporting at least two (six in this case) snubber capacitors C is arranged, and the rack R is fixed to the installation plate B via insulators G.

  The rack R has a connecting plate r3 arranged in the vertical direction, and an upper capacitor mounting plate r2 and a lower capacitor mounting plate r1 connected in the horizontal direction at the upper end and the lower end of the connecting plate r3, respectively. Snubber capacitors C2, C4, C6 (shown by solid lines in FIG. 2) are arranged and fixed at intervals on the upper capacitor mounting plate r2, and snubber capacitors C1, C3 are placed on the lower capacitor mounting plate r1. , C5 (shown by a two-dot chain line in FIG. 2) are arranged and fixed at intervals. As shown in FIG. 2, when the upper snubber capacitors C2, C4, and C6 and the lower snubber capacitors C1, C3, and C5 are stacked in the vertical direction (paper surface direction in FIG. 2), each snubber capacitor In FIG. 2, the width dimension in the lateral direction of FIG.

  And each of the snubber capacitors C2, C4, C6, C1, C3, and C5 (generally referred to as C) has an input terminal and an output terminal, and collectors or anodes and emitters of the semiconductor elements E1 to E6, or The L input side connection conductor IC and the output side connection conductor OC that connect the cathode respectively are substantially parallel to each other, and the inductances generated in the input side connection conductor IC and the output side connection conductor OC are offset. is there. In this case, one end portion (end portion on the semiconductor multilayer structure PS side) of each input side connection conductor IC and each output side connection conductor OC is bent into an L shape, and is one side surface of the semiconductor multilayer structure PS. The heat dissipation fins F1 to F7 on both sides of the semiconductor elements E1 to E6 are connected by screws, for example. As a result, the snubber capacitors C1 to C6 and the semiconductor elements E1 to E6 are electrically connected through the copper radiating fins F1 to F7, respectively, so that the main circuit as shown in FIG. 1 is obtained.

  Further, the side other than the positive bus P or the negative bus N connected to the semiconductor multilayer structure PS on the side where the snubber capacitor C is not disposed in the semiconductor multilayer structure PS is parallel to the semiconductor multilayer structure PS. The negative bus N or the positive bus P is arranged close to each other, and input terminals PI and NI are arranged in the vertical direction at both ends of the positive bus P and the negative bus N, for example, as shown in FIG. Terminals PO and NO (not shown in FIG. 5 but hidden by snubber capacitors C2, C4 and C6 and upper capacitor mounting plate r2) are arranged in the vertical direction in the same manner as input terminals PI and NI. is there. As described above, the DC power source S is connected to the input terminals PI and NI, and the load L and the reflux circuit K are connected to the output terminals PO and NO.

  Then, a gate (or base) power supply panel GP including a gate driving circuit for turning off and turning on each semiconductor element E is disposed at a position described below. That is, as shown in FIGS. 2 and 4, on the side where the snubber capacitor C is not arranged, the positive bus P or the negative bus P arranged in parallel to the semiconductor multilayer structure PS and connected to the semiconductor multilayer structure PS is connected. A gate drive circuit is provided on the negative bus N side or the positive bus P side other than the side bus N. Specifically, the gate power supply panel GP is provided on the installation plate B as shown in FIG. 4 on the side opposite to the installation position of the rack R of the snubber capacitor C (on the opposite side across the semiconductor multilayer structure PS). This is a gate (or base) power supply panel GP on which components of the gate (or base) drive circuit of each semiconductor element E are mounted.

  4 and 5, I is an insulating plate, and WP is a cooling water pipe. In FIG. 5, the disk-like end plate at the end of the semiconductor stacked structure PS is omitted for the sake of clarity.

  According to the semiconductor switch device configured as described above, the whole can be made compact, the circuit inductance can be reduced, and the jump of the voltage of each semiconductor element at the time of current interruption can be suppressed. Specifically, it is close to and substantially parallel to the semiconductor multilayer structure PS installed on the installation plate B, and at least one snubber capacitor C is arranged above and below, and further the snubber capacitor C in the semiconductor multilayer structure PS. Of the negative side bus N or the positive side bus P other than the positive side bus P or the negative side bus N connected to the semiconductor multilayer structure PS. Since they are arranged close to each other, the whole is compact, that is, the storage space for the semiconductor multilayer structure PS, the snubber capacitor C, the positive bus P, or the negative bus N can be used effectively, and as a result, the entire can be made compact.

  As shown in FIG. 2, there are a case where half of the total number of snubber capacitors C are arranged at the upper position and the lower position, respectively, and the case where all the number of snubber capacitors C are not arranged up and down. This is a case compared to the case where the snubber capacitors C are arranged in a row so as to face the side surface of the multilayer structure PS. When the snubber capacitors C are arranged in a row, the arrangement length of the snubber capacitors is about twice the effective length of the semiconductor multilayer structure PS. This is because the device arrangement space cannot be effectively used.

  In the embodiment of the present invention, the semiconductor stacked structure PS is used because there is a merit that the axial length (element stacking direction) is short, and this merit is utilized.

  Further, the input side connection conductor IC and the output side connection conductor OC that connect the input side terminal and the output side terminal of each snubber capacitor C and the collector, anode, emitter, or cathode of each semiconductor element E of the semiconductor multilayer structure PS, respectively, Since the magnetic fluxes which are substantially parallel to each other and cancel out the magnetic fluxes generated in the input-side connection conductor IC and the output-side connection conductor OC are mutually cancelled, the total inductance of the self-inductance and the mutual inductance (one-round inductance) can be reduced. .

  Furthermore, in the above-described embodiment, each input-side connecting conductor IC that connects the input-side terminal and the output-side terminal of each snubber capacitor C and the collector, anode, emitter, or cathode of each semiconductor element E of the semiconductor multilayer structure PS, and By making each output side connection conductor OC into the same shape, variation in inductance in each semiconductor element E can be reduced, and as a result, imbalance of voltage jumping can be suppressed.

  FIG. 6 shows a main circuit of the second embodiment according to the semiconductor switch device of the present invention. For each of the snubber capacitors C1, C2, C3, C4, C5, C6 in the embodiment of FIG. The main circuit is the same as in FIG. 1 except that resistors RS1, RS2, RS3, RS4, RS5, and RS6 are connected in series, and the other collectors, anodes, emitters, and cathodes of the semiconductor elements E1 to E6. The input side connection conductor IC and the output side connection conductor OC to be connected are the same as those of the first embodiment in that the inductance generated in each is canceled out, and the other characteristic configurations described above are also described above. This is almost the same as the first embodiment.

  According to the second embodiment configured as described above, the following operational effects can be obtained. That is, for example, in the figure, there is a possibility that the semiconductor elements E1 to E6 may be damaged by turn-on surge currents from the snubber capacitors C1 to C6 when the semiconductor elements E1 to E6 are turned on. On the other hand, in the embodiment of FIG. 6, since the resistors RS1 to RS6 are connected in series with the snubber capacitors C1 to C6, the aforementioned turn-on surge current can be suppressed.

  FIG. 7 shows the main circuit of the third embodiment according to the semiconductor switch device of the present invention. The snubber capacitors C1, C2, C3, C4, C5 and C6 in the embodiment of FIG. , RS2, RS3, RS4, RS5, RS6 and diodes DS1, DS2, DS3, DS4, DS5, DS6 are added. Specifically, a parallel circuit of a resistor RS1 and a diode DS1 is connected in series to the snubber capacitor C1, the anode side of the diode DS1 is connected to the flat semiconductor element E1, and the cathode side of the diode DS1 is connected to the snubber capacitor C1. Components RS2, RS3, RS4, RS5, RS6, diodes DS2, DS3, DS4, DS5, DS6, which are connected to form a snubber circuit other than these, are similarly connected. Except for the points described above, the main circuit is the same as in FIG. 1, and the input side connection conductor IC and the output side connection conductor OC connected to the collectors, anodes, emitters or cathodes of the other semiconductor elements E1 to E6. Is the same as that of the first embodiment in that the inductance generated in each is canceled out, and the other characteristic configuration described above is also substantially the same as that of the first embodiment described above.

  According to the third embodiment configured as described above, the following operational effects can be obtained. That is, since the turn-off current flows through the diodes DS1 to DS6 when the semiconductor elements E1 to E6 are turned off, no voltage is generated at both ends of the resistors RS1 to RS6, and the overvoltage when the semiconductor elements E1 to E6 are turned off is suppressed. . Moreover, since the discharge current of the snubber capacitors C1 to C6 flows through the resistors RS1 to RS6 when the semiconductor elements E1 to E6 are turned on, the surge current is suppressed.

  The present invention is not limited to the embodiments described above, and can be implemented with various modifications. That is, in the above-described embodiment, an example in which an insulator, for example, an insulating plate is not provided between the input side connection conductor IC and the output side connection conductor OC has been described. However, as illustrated in FIG. By disposing the insulating plate IP between the outgoing connection conductors OC, the leakage of magnetic flux is reduced, and it is possible to significantly reduce the circuit inductance.

  In the above-described embodiment, the semiconductor laminated structure PS is an example in which the flat semiconductor element E and the refrigerant type, for example, the water-cooled type heat radiation fins F, are alternately combined. The conductive plate piece may be provided. For example, IEGT (Injection Enhanced Gate Transistor) is used as the semiconductor element E of the above-described embodiment. However, the semiconductor element E is not limited to this and may be another self-extinguishing semiconductor element.

The figure for demonstrating the main circuit of 1st Embodiment which concerns on the semiconductor switch apparatus of this invention. BRIEF DESCRIPTION OF THE DRAWINGS The schematic plan view for demonstrating 1st Embodiment which concerns on the semiconductor switch apparatus of this invention. The perspective view which shows only the principal part for demonstrating 1st Embodiment which concerns on the semiconductor switch apparatus of this invention. BRIEF DESCRIPTION OF THE DRAWINGS The schematic plan view for demonstrating 1st Embodiment which concerns on the semiconductor switch apparatus of this invention. The perspective view which shows only the principal part for demonstrating 1st Embodiment which concerns on the semiconductor switch apparatus of this invention. The figure for demonstrating the main circuit of 2nd Embodiment which concerns on the semiconductor switch apparatus of this invention. The figure for demonstrating the main circuit of 3rd Embodiment which concerns on the semiconductor switch apparatus of this invention.

Explanation of symbols

  PS ... Semiconductor laminated structure, E1, E2, E3, E4, E5, E6 ... Semiconductor element, C1, C2, C3, C4, C5, C6 ... Snubber capacitor, F1, F2, F3, F4, F5, F6, F7 ... Radiation fin, S ... Power source, P ... Positive bus, N ... Negative bus, L ... Load, B ... Installation plate, IC ... Incoming connection conductor, OC ... Outside connection conductor, r1 ... Lower capacitor installation plate, r2: upper capacitor mounting plate, r3: connecting plate, G: insulator, R: rack, IP: insulating plate, GP: gate power panel.

Claims (6)

At least two flat semiconductor elements are electrically connected in series, and a snubber capacitor electrically connected to both ends of each semiconductor element and a plurality of flat semiconductors with the snubber capacitor are connected in series. In the semiconductor switch device that connects the semiconductor laminated structure pressed in this way between one of the positive side bus or the negative side bus of the DC power source and the terminal of the load, and interrupts the current flowing between the DC power source and the load.
The semiconductor multilayer structure is disposed substantially parallel to an arbitrary position on an installation surface, and each of the snubber capacitors is in a direction perpendicular to the axial direction of the semiconductor multilayer structure, and at least one of the snubber capacitors is installed in the installation plane. The semiconductor multilayer structure is disposed in an upper position and a lower position in a direction perpendicular to the surface and parallel to the semiconductor multilayer structure on the side where the snubber capacitor is not disposed in the semiconductor multilayer structure. The negative side bus or the positive side bus other than the positive side bus or the negative side bus connected to the
The input side connection conductor and the output side connection conductor that connect the input side terminal and output side terminal of each snubber capacitor and the anode, collector, cathode, or emitter of each semiconductor element, respectively, are substantially parallel to each other, and A semiconductor switch device characterized in that the magnetic flux generated in each of the side connection conductor and the output side connection conductor is canceled.   2. The semiconductor switch device according to claim 1, wherein all of the connecting conductors connecting the semiconductor elements and the snubber capacitors have the same shape.   The semiconductor switch device according to claim 1, wherein an insulator is provided between the input side connection conductor and the output side connection conductor of each snubber capacitor.   The side of the negative bus other than the positive bus or the negative bus connected to the semiconductor multilayer structure on the side where the snubber capacitor is not disposed and parallel to the semiconductor multilayer structure, or 2. The semiconductor switch device according to claim 1, wherein a gate drive circuit for turning off and turning on each semiconductor element is provided on the positive bus side.   2. The semiconductor switch device according to claim 1, wherein a resistor is connected in series to each of the snubber capacitors.   A parallel circuit of a resistor and a diode is connected in series to each snubber capacitor, the anode side of each diode is connected to each flat semiconductor element, and the cathode side of each diode is connected to each snubber capacitor The semiconductor switch device according to claim 1, wherein:

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