JP4356434B2 - 3-level inverter circuit - Google Patents

Description

  The present invention relates to a three-level inverter circuit, and more particularly to the arrangement of packages constituting the circuit.

  PWM (Pulse Width Modulation) control 3-level inverter that cuts input DC voltage into output voltage and controls the number, interval, width, etc. of the pulse, and outputs AC with the desired 3-level frequency In recent years, IGBTs (Insulated Gate Bipolar Transistors) have been used as power device elements in terms of miniaturization and weight reduction, low loss and high efficiency, noise, harmonics and torque fluctuation prevention, and improved reliability. Is used.

On the other hand, in such a three-level inverter circuit, if the value of the wiring inductance between the packages is large, the turn-off surge voltage may increase. If the turn-off surge voltage cannot be suppressed within the safe operation area of the IGBT, the IGBT is destroyed.
As a method for suppressing the turn-off surge voltage, there is a method in which a snubber circuit that absorbs the energy of wiring inductance is separately connected in parallel to each IGBT using a capacitor. However, when the wiring inductance is large, the capacitor capacity of the snubber circuit that absorbs the energy also increases, causing problems such as an increase in the size of the device, an increase in device cost, a decrease in reliability due to an increase in the number of components, and an increase in device loss. Will be invited.

  As one method for solving such a problem, Patent Document 1 proposes the following method. That is, in the three-level power conversion device described in Patent Document 1, as shown in FIG. IGBT 2 -first coupling diode 5 -first IGBT 1 are arranged in this order, and the third IGBT 3 -second coupling diode 5- The fourth IGBT 4 is arranged in this order. A plurality of planar wiring boards that are electrically insulated by projecting all connection terminals of the first to fourth IGBTs 1 to 4 and the first and second coupling diodes 5 and 5 in one direction. Necessary electrical connection is made between the connection terminals of the first to fourth IGBTs 1 to 4 and the first and second coupling diodes 5 and 5 by the group (laminated connection plate) 30. By adopting such a configuration, the connection terminals of each package are arranged along a straight line to shorten the wiring between these connection terminals, and the distance between the forward and backward current paths is reduced. Thus, the wiring inductance existing in the current path is reduced. And the snubber circuit is unnecessary.

  Further, in the power module stack of the three-level inverter described in Patent Document 2, the same purpose as the apparatus described in Patent Document 1, that is, the purpose of reducing the wiring inductance, and in addition to this, the element is efficiently cooled. For this purpose, as shown in FIG. 1 of the same document, the first switching element 1, the first diode 5, and the second switching element 2, with the back surfaces facing both surfaces of the cooling fin base 10, The fourth switching element 4, the second diode 6, and the third switching element 3 are sequentially disposed in the order of connection, are disposed so as to surround the fin base 10 and have a U shape as a whole, and an insulating plate is provided. They are connected by a connection board (laminated connection board) formed between them.

Further, in the main circuit of the three-level power conversion device described in Patent Document 3, as shown in FIG. 1 of the same document, the emitter of the IGBT 21 of the upper arm unit 1 and the IGBT 22 are also used for the purpose of reducing the wiring inductance. The collector and the cathode of the clamp diode 41 are arranged on a straight line, these terminals are connected by the connection conductor 11, and the connection conductor 7 on the power source side of the IGBT 21 and the connection conductor 9 at the neutral point are arranged close to each other in parallel. Further, the connection conductor 10 and the connection conductor 9 of the AC side terminal are arranged close to each other in parallel, and the emitter of the IGBT 23 of the lower arm unit 2, the collector of the IGBT 24, and the cathode of the clamp diode 42 are arranged on a straight line, These terminals are connected by the connection conductor 12, and the connection conductor 8 on the power source side of the IGBT 24 and the connection conductor 9 at the neutral point are brought close to each other. And arranged in rows, also by parallel arranged close to the connecting conductor 10 on the AC side terminals and connection conductor 9, thereby reducing the wiring inductance of the current path.
Japanese Patent No. 3229931 (page 3-4, FIG. 1) Japanese Patent Laid-Open No. 10-201249 (page 5-6, FIG. 1) Japanese Patent Laid-Open No. 10-285950 (page 4, FIG. 1)

However, many coupling diodes used in high voltage circuits have a plate-like insulating barrier between the connection terminal cathode and anode. This insulation barrier also protrudes in the direction of the connection terminal. Therefore, when the switching element (IGBT) and the coupling diode are arranged on the same straight line as described above, the insulating barrier interferes with the laminated connection plate. Therefore, electrical connection between the respective packages cannot be performed with a simple flat plate-like laminated connection plate. That is, the laminated connecting plate may have a complicated shape, or a separate spacer may be required.
The present invention has been made to solve the above-described problems, and can suppress a turn-off surge voltage without requiring a snubber circuit and also make necessary electrical connections between components. It is an object of the present invention to provide a three-level inverter circuit that can simplify the structure of the connecting means and can realize a reduction in size and thickness of the device.

According to a first aspect of the present invention, a three-level inverter circuit includes a plurality of element packages each including a switching element and a plurality of diode packages each including a coupling diode arranged on a mounting surface, and connection terminals of the respective packages are provided. In the three-level inverter circuit that is connected via the laminated connection plate , a DC power source is arranged in parallel on one end side of the element package row, and the plurality of element packages are connected to the DC power source from the side opposite to the DC power source. Each of the first, second, third and fourth element packages, each of the first to fourth element packages including one switching element, and the plurality of diode packages. Are the first and second diode packages disposed at a predetermined distance in a direction orthogonal to the arrangement direction of the second and third element packages. The laminated connection plate is configured to connect a positive electrode terminal of the DC power source and a positive electrode side terminal of the first element package, and cover the first to fourth element packages. A second conductive connection plate connecting the anode terminal of the first diode package and the cathode terminal of the second diode package and the intermediate terminal of the DC power source and covering the first to fourth element packages and parts, and the third conductive connecting plate portion for connecting the other terminal to have a laminated structure through an insulating plate.

In the three-level inverter circuit according to a second aspect of the invention, between the power supply terminal of the DC power supply and said element package and the connection terminals of the diode package, the anode and cathode terminals of at least the diode package intermediate parts covered with the laminated connection plate so as to expose, electrically connected.

In the three-level inverter circuit according to a third aspect of the present invention, the third conductive connecting plate portion includes a negative terminal on the first element package, a positive terminal on the second element package, and a first terminal. A first divided connection plate for connecting a cathode terminal of the diode package, a negative electrode side terminal of the second element package, and a positive electrode side terminal of the third element package, and having an AC output terminal A connection plate, a third divided connection plate for connecting the negative electrode side terminal of the third element package, the positive electrode side terminal of the fourth element package, and the anode of the second diode package, and the negative electrode side of the fourth element package that consists of a fourth sub-connection plate for connecting the negative terminal of the terminal and the DC power source.

In the three-level inverter circuit according to the fourth aspect of the present invention, each of the plurality of element packages and the plurality of diode packages incorporates one element .

In the three-level inverter circuit according to a fifth aspect of the invention, the plurality of diode package and the plurality of device packages incorporates a respective two elements, without the respective elongated, the plurality of device packages are each The longitudinal direction is arranged perpendicular to the straight line, and the one diode package is arranged so that the three packages are U-shaped with respect to the two adjacent element packages.

  In the first invention, the plurality of element packages are arranged so that the input side connection terminals and the output side connection terminals thereof are along a straight line to form an element package row, and the plurality of diode packages are arranged in the arrangement direction of the element package rows. Therefore, a plurality of element packages can be easily connected by a laminated connection plate avoiding the diode package.

In the first invention, a DC power supply is arranged in parallel on one end side of the element package row, and the power supply terminal of the DC power supply and the connection terminals of the element package and the diode package are electrically connected by the laminated connection plate. Therefore, in the current path formed in the laminated connection plate between the connection terminal of the element package and the connection terminal of the DC power supply, the separation distance between the forward path and the return path can be reduced to some extent, and exists in the current path. Wiring inductance can be reduced.

Furthermore, in the first invention, the wiring between the connection terminals of the second and third element packages and the connection terminals of the first and second diode packages can be shortened to reduce the wiring inductance. Further, in the current path formed between the connection terminals of the first to fourth element packages and the connection terminal of the DC power supply, the separation distance between the forward path and the return path can be reduced to some extent and exists in the current path. Wiring inductance can be reduced.
In the second invention, at least the middle part of the anode terminal and the cathode terminal of the diode package is exposed. Therefore, even if the diode package has an insulation barrier, the laminated connection plate should have a flat plate shape. Can do.

In the third invention, the current path between the positive electrode terminal of the DC power source formed on the first conductive connection plate portion and the first element package, the anode terminal of the first diode package, and the second Since the current path between the cathode terminal of the diode package and the intermediate terminal of the DC power supply approaches a difference and is in the opposite direction, the magnetic fields generated by the currents cancel each other, and the wiring inductance is further reduced.

In the fourth invention, each of the element package and the diode package incorporates one element, so that the connection terminals of each package constituting one inverter circuit can be connected by a three-layer laminated connection plate.
In the fifth invention, each of the element package and the diode package incorporates two switching elements and is arranged so as to have a U-shape. Wiring can be shortened.

FIG. 1 is a configuration diagram showing element package arrangement and inter-package connection of the three-level inverter device according to the first embodiment of the present invention. In FIG. 1, a three-level inverter device 100 includes a first three-level inverter circuit 101 and a second three-level inverter circuit 102.
The first three-level inverter circuit 101 and the second three-level inverter circuit 102 are formed symmetrically with respect to the center line γ, and have exactly the same circuit configuration. Therefore, the description of the second three-level inverter circuit 102 is omitted, and only the first three-level inverter circuit 101 is described.

  The three-level inverter circuit 101 includes four element packages 1 to 4 (hereinafter also simply referred to as IGBTs), which are element packages IGBT (insulated Gate Bipolar Transistor) incorporating switching elements, and two diodes incorporating coupling diodes. Packages 5 and 6 (hereinafter also simply referred to as a combined package) and a DC power source 9 are provided. Furthermore, it has connection means (represented as wiring in FIG. 1) for electrically connecting these packages to each other at necessary places.

  The first to fourth IGBTs 1 to 4 are arranged along the first straight line α to form an element package row. The direct current power source 9 is also arranged substantially along the straight line α. The four IGBTs are arranged in the order of the fourth IGBT 4, the third IGBT 3, the second IGBT 2, and the first IGBT 1 from the DC power supply 9 side. The first to fourth IGBTs 1 to 4 may be arranged substantially on the straight line α, but the collector C and the emitter E which are connection terminals of the IGBTs 1 to 4 are accurately arranged on the straight line α. desirable.

  The first and second coupling diodes 5 and 6 are second straight lines that are a predetermined distance from the first straight line α on the side opposite to the center line γ and parallel to the first straight line α. Arranged along β. More specifically, the first coupling diode 5 is arranged at a position facing the second IGBT 2 on the second straight line β, and the second coupling diode 6 is connected to the third straight line β on the third straight line β. It arrange | positions in the position facing IGBT3. The DC power source 9 is configured by connecting capacitors 7 and 8 in series, and is provided with a positive terminal P, an intermediate terminal M, and a negative terminal N. The DC power supply 9 is actually connected with a power supply connection, but is not shown in the figure. The feature of the present invention is that the first and second coupling diodes 5 are arranged at positions shifted from the first to fourth IGBTs 1 to 4 arranged in a straight line. Go.

The collector C of the first IGBT 1 is connected to the positive terminal P of the DC power supply 9, and the emitter E is connected to the collector C of the second IGBT 2 and the cathode K of the first coupling diode 5. The anode A of the first coupling diode 5 is connected to the intermediate terminal M of the DC power source 9 and the cathode K of the second coupling diode 6. The emitter E of the second IGBT 2 is connected to the AC output terminal AC.
The collector C of the third IGBT 3 is connected to the AC output terminal AC, and the emitter E is connected to the collector C of the fourth IGBT 4 and the anode A of the second coupling diode 6. The cathode K of the second coupling diode 6 is connected to the intermediate terminal M of the DC power supply 9, and the emitter E of the fourth IGBT 4 is connected to the negative terminal N of the DC power supply 9.

FIG. 2 is a circuit diagram of the three-level inverter circuit 101 in FIG. 1, and is a diagram for explaining current paths in the six modes (mode 1 to mode 6) of the three-level inverter circuit 101 at the same time. In addition, L1-L5 in FIG. 2 has shown the wiring inductance which exists in a circuit.
FIG. 2A is a diagram for explaining a current path when the circuit 101 changes from mode 1 to mode 2. In mode 1 in which IGBT1 and IGBT2 are turned on and IGBT3 and IGBT4 are turned off, current flows through the path of capacitor 7, wiring inductance L1, IGBT1, IGBT2, and AC output terminal AC (current (1)).

  Next, when the state changes from mode 1 to mode 2, the IGBT 1 is turned off, and the current is commutated to the path of the intermediate terminal M → the wiring inductance L2 → the coupling diode 5 → the wiring inductance L3 → the IGBT 2 → the AC output terminal AC. (Current (2)). At this time, the current (1) flowing to the IGBT 1 via the wiring inductance L1 decreases, and conversely, the current flowing to the IGBT 2 via the wiring inductance L2, the coupling diode 5, and the wiring inductance L3 increases. Therefore, a voltage due to the reduction rate of current (1) −di / dt = −di / dt × L1 = V1 is induced in the wiring inductance L1 in the direction of the arrow shown in the drawing. Further, in the wiring inductances L2 and L3, voltage = di / dt × L2 = V2 and di / dt × L3 = V3 due to the increase rate di / dt of the current (2) are similarly induced in the directions of the arrows shown in the figure. . For this reason, at the time of this commutation, the voltage of the capacitor + V1 + V2 + V3 is applied to the IGBT 1 as a surge voltage.

  FIG. 2A is a diagram for explaining a current path when the circuit 101 changes from mode 2 to mode 3. When the mode 2 is changed to the mode 3, the current (2) is decreased because the IGBT 2 is turned off, and the current flowing through the flywheel diodes of the IGBT 3 and IGBT 4 through the wiring inductance L5 is increased. As a result, the voltage (−di / dt × L2 = V2, −di / dt × L3 = V3) due to the reduction rate of the current (2) −di / dt is induced in the wiring inductances L2 and L3 in the direction of the arrow shown in the figure. . In addition, voltage = di / dt × L5 = V5 due to the increase rate di / dt of the current (3) is induced in the wiring inductance L5 in the direction of the illustrated arrow. For this reason, at the time of this commutation, the voltage of the capacitor + V2 + V3 + V5 is applied to the IGBT 2 as a surge voltage.

  FIG. 2C illustrates a current path when the circuit 101 changes from mode 4 to mode 5. In mode 4 with the IGBT 3 and IGBT 4 turned on and the IGBT 1 and IGBT 2 turned off, the current flows through the path of the AC output terminal AC → IGBT 3 → IGBT 4 → the wiring inductance L 5 → the negative terminal N (current (4)). . Next, when the mode 4 changes to the mode 5, the IGBT 4 is turned off, and the current is commutated to the path of the AC output terminal AC → IGBT3 → the wiring inductance L4 → the coupling diode 2 → the wiring inductance L2 → the intermediate terminal M (current). (5)). At this time, the current (4) flowing through the wiring inductance L5 via the IGBT 4 decreases, and conversely, the current flowing through the coupling diode 2 via the wiring inductances L4 and L2 increases. Accordingly, a voltage = −di / dt × L5 due to the reduction rate of the current (4) −di / dt = −di / dt × L5 is induced in the wiring inductance L5 in the direction of the illustrated arrow. In addition, voltage = di / dt × L2 = V2 and di / dt × L4 = V4 are induced in the wiring inductances L2 and L4 in the directions indicated by arrows in the drawing, respectively, due to the increase rate di / dt of the current (5). For this reason, at the time of this commutation, the voltage of the capacitor 8 + V5 + V2 + V4 is applied to the IGBT 4 as a surge voltage.

  FIG. 2D is a diagram for explaining a current path when the circuit 101 changes from mode 5 to mode 6. When the mode 5 is changed to the mode 6, the current (5) decreases because the IGBT 3 is turned off, and the current (6) flowing through the flywheel diodes of the IGBT 1 and IGBT 2 through the wiring inductance L1 increases. Accordingly, the voltage (−di / dt × L2 = V2, −di / dt × L4 = V4) due to the reduction rate of the current (5) −di / dt is induced in the wiring inductances L2 and L4 in the direction of the arrow shown in the drawing. In addition, a voltage = di / dt × L1 = V1 due to an increase rate di / dt of the current (6) is induced in the wiring inductance L1 in the direction of the arrow in the drawing. For this reason, at the time of this commutation, the voltage of the capacitor + V2 + V4 + V1 is applied to the IGBT 3 as a surge voltage.

  When the wiring inductance becomes the largest in the above commutation operation, the mode 2 changes to the mode 3 shown in FIG. 2 (a) and the mode 5 shown in FIG. 2 (d). It is the time of change from mode to mode 6. That is, this is when a surge voltage is applied to the current path (a) of the one-dot chain line shown in FIG. 2 (a) and the current path (a) of the two-dot chain line shown in FIG. 2 (d). Therefore, in order to reduce the surge voltage (turn-off surge voltage) due to the above-described commutation operation, the wiring inductance in the current paths (a) and (b) may be reduced. In order to reduce the wiring inductance of the current path, the wiring length is shortened, or the current path is formed by a reciprocating path close to each other, and the magnetic fields generated by the currents flowing through the reciprocating path are canceled with each other. What should I do? This will be described in detail when explaining the laminated bus bar 40 which is an electrical connection means between the respective packages.

FIG. 3 is a diagram in which a current path (a) is added to the element package arrangement of the three-level inverter circuit 101 shown in FIG. FIG. 4 similarly shows a current path (b) indicated by a two-dot chain line in the element package arrangement of FIG.
FIG. 5 is a perspective view of a portion corresponding to the circuit 101 of the three-level inverter device 100 of the present embodiment. 6 is an exploded perspective view of FIG. 5 for explaining the structure of the laminated wiring board. In the present embodiment, each package is packaged with one element. Each package has a rectangular flat plate shape. Each package is provided with a connection terminal on a large-area surface opposite to the mounting surface (an upper surface in FIGS. 5 and 6). All the packages 1 to 6 are mounted on the mounting surface 30 a on the upper surface of the cooler 30. The arrangement of the respective packages 1 to 6 is as shown in the arrangement configuration diagram of FIG. 1, and the first to fourth IGBT packages 1 to 4 are arranged so as to be aligned on the first straight line α. ing.

Each of the first to fourth IGBT packages 1 to 4 has three connection terminals of the same polarity, such as three collectors C and three emitters E. Each connection terminal is formed so as to project in a direction standing perpendicularly to the mounting surface 30a which is a surface parallel to the first straight line α (that is, upward in FIG. 6).
One connection terminal is provided for each of the cathodes K and anodes A of the first and second coupling diodes 5 and 6. Insulation barriers 5 a and 6 a are provided between the cathodes K and the anodes A of the coupling diodes 5 and 6. The insulating barriers 5a and 6a have a flat plate shape extending in the vertical direction, and project so as to face the same direction as the connection terminal, that is, the direction standing perpendicular to the mounting surface 30a (that is, the upper side in FIG. 6). Is formed.

  In this way, the packages 1 to 6 are arranged so that all the connection terminals face the direction in which they are erected vertically to the mounting surface 30a. Therefore, as will be described later in detail, it can be easily connected to the flat laminated bus bar 40. The three same-polarity connection terminals of the first to fourth IGBT packages 1 to 4 are provided side by side in a direction orthogonal to the first straight line α. This is for improving the balance of the inductance between the connection terminals, and thereby the current balance between the connection terminals can also be improved.

  The cooler 30 on which these packages are mounted is an air-cooling type, and is made of a material having a good thermal conductivity and has a substantially rectangular flat plate shape. The cooler 30 absorbs heat generated by the first to fourth IGBTs 1 to 4 and the first and second coupling diodes 5 and 6. Further, the DC power source 9 including the capacitors 7 and 8 and the cooler 30 are installed together on the same plane which is a mounting surface of a device (not shown). The substantially flat cooler 30 and the DC power supply 9 are approximately equal in height from the mounting surface, so that the apparatus is made thinner.

  As an electrical connection means between the packages, a laminated bus bar 40 is provided as a laminated connecting plate in which a plurality of flat connecting plates are laminated. As shown in FIG. 6, the laminated bus bar 40 has a three-layer structure of a first layer to a third layer with the uppermost surface as the first layer. The first conductive connection plate portion 41 constituting the first layer and the second conductive connection plate portion 42 constituting the second layer are provided so as to cover the first to fourth IGBTs 1 to 4. . The 3rd conductive connection board part 43 which constitutes the 3rd layer is divided in the arrangement direction of the 1st-4th IGBT1-4, the 1st division connection board 44, the 2nd division connection board 45, the 3rd It is divided into divided connection plates 47. An insulating sheet (not shown) is sandwiched between the connection plates, and the connection plates are insulated from each other. In each connection plate, holes are drilled at predetermined positions in order to be electrically connected to the connection terminals of the respective packages 1 to 6.

The first conductive connection plate portion 41 connects the positive terminal P of the DC power source 9 and the collector C of the first IGBT 1. The second conductive connection plate portion 42 connects the anode terminal of the first combined package and the cathode terminal of the second diode package and the intermediate terminal M of the DC power supply 9.
Of the four split connection plates, the first split connection plate 44 provides electrical connection between the emitter E of the first IGBT 1, the collector C of the second IGBT 2, and the cathode K of the first coupling diode 5. Is going. The second divided connection plate 45 performs electrical connection between the emitter E of the second IGBT 2, the collector C of the third IGBT 3, and the AC output terminal AC.

  The third divided connection plate 46 makes electrical connection between the emitter E of the third IGBT 3, the collector C of the fourth IGBT 4, and the anode A of the second coupling diode 6. The fourth divided connection plate 47 performs electrical connection between the emitter E of the fourth IGBT 4 and the negative terminal N of the DC power supply 9. It is considered that the current flowing through each connection plate generally flows through the shortest path between the connection points.

  Further, the laminated bus bar 40 will be described. FIG. 7 is a front view of a connection board showing the structure of a laminated bus bar for connecting each package. FIG. 7 (a) is a conductive connection plate portion 41 constituting the first layer, and FIG. The conductive connection plate portion 42 constituting the two layers, FIG. 7C shows the first to fourth divided connection plates 44 to 47 constituting the third layer. An insulating sheet (not shown) is sandwiched between the connection plates, and the connection plates are insulated from each other. FIG. 8 is a diagram in which the conductive connection plate portion 41 constituting the first layer is added to the element package arrangement of the three-level inverter circuit 101 shown in FIG. FIG. 9 also shows the conductive connecting plate portion 42 constituting the second layer with a broken line. FIG. 10 similarly shows the first to fourth divided connection plates 44 to 47 constituting the third layer with broken lines.

  Here, the insulating barrier 5a erected between the cathode K and the anode A of the first coupling diode 5 in the protruding direction of the connection terminal (upward in FIG. 6) includes the first divided connection plate 44 and the second It passes through the gap formed between the divided connection plate 45 and extends in the protruding direction of the connection terminal through the side portion of the convex portion 42a of the conductive connection plate portion 42 on the first divided connection plate 44 side. . Further, the insulating barrier 6a erected between the cathode K and the anode A of the second coupling diode 6 in the protruding direction of the connection terminal (upward in FIG. 6) includes the third divided connection plate 46 and the fourth divided plate. It passes through the gap formed between the connecting plate 47 and the side of the convex portion 42a of the conductive connecting plate portion 42 on the third divided connecting plate 46 side, and then extends in the protruding direction of the connecting terminal. That is, the laminated bus bar 40 is manufactured so as not to interfere with the insulation barrier 5a and the insulation barrier 6a of the first coupling diode 5 and the second coupling diode 6.

Further, the first split connection plate 44 has the first height so that the portion connected to the cathode K of the first coupling diode 5 has the same height as the convex portion 42a of the conductive connection plate portion 42 of the second layer. A step portion 44a is formed on one side of the coupling diode 5 side. Further, the third split connection plate 46 is arranged on the second coupling diode 6 side so that the portion connected to the anode A of the second coupling diode 6 is at the same height as the convex portion 42 a of the second layer 42. A step 46a is formed on one side. Further, a side of the conductive connection plate portion 41 on the first IGBT 1 side is provided with a step so that the thickness of the conductive connection plate portion 42 and the conductive connection plate portion 43 can be absorbed and easily connected to the first IGBT 1. A portion 41a is formed.
In addition, a connection plate 48 bent in an L-shaped cross section is provided between the laminated bus bar 40 and the DC power supply 9, and is electrically connected by the connection plate 48.

  Next, the current flowing through each connection plate will be described with reference to FIGS. A current path to which a surge voltage is applied when changing from mode 5 to mode 6, that is, a current path (b) of a two-dot chain line shown in FIG. 4 will be described as an example. First, the current flowing from the positive terminal P of the DC power source 9 to the collector C of the first IGBT 1 is the DC power source of the first conductive connecting plate portion 41 as shown by a two-dot chain line b1 in FIG. From the 9th side to the first IGBT1 side, it flows in the longitudinal direction almost over the whole. Next, the current flowing from the cathode K of the second coupling diode 6 to the anode A of the first coupling diode 5 is the second conductive connecting plate as shown by a two-dot chain line b2 in FIG. It flows in the longitudinal direction of the portion 42 so as to cross the convex portion 42 a of the second conductive connecting plate portion 42. In addition, the current flowing from the cathode K of the second coupling diode 6 to the intermediate terminal M of the DC power supply 9 is projected on the second conductive connecting plate portion 42 as shown by a two-dot chain line b3 in FIG. It flows from the portion 42a toward the opposite end (the end of the DC power supply 9).

  Further, the current flowing from the emitter E of the first IGBT 1 to the collector C of the second IGBT 2 is the first IGBT 1 of the first split connection plate 44 as shown by a two-dot chain line b4 in FIG. The side end portion flows in the longitudinal direction from the first IGBT 1 toward the second IGBT 2. Further, the current flowing from the emitter E of the second IGBT 2 to the collector C of the third IGBT 3 is the second IGBT 2 of the second split connection plate 45 as shown by a two-dot chain line b5 in FIG. And the third IGBT 3. Finally, the current flowing from the emitter E of the third IGBT 3 to the anode A of the second coupling diode 6 is the central portion of the third divided connection plate 46 as shown by a two-dot chain line b6 in FIG. It flows in the direction perpendicular to the longitudinal direction.

In such a current path, the flow of the two-dot chain line b1 and the two-dot chain line b3 are close to each other and in opposite directions, so that the magnetic fields generated by the currents flowing therethrough cancel each other out. Inductance increases and wiring inductance decreases. The flow of b4, b5 and the flow of b1 also cancel each other. Produces the same effect.
In the description, the current path to which the surge voltage is applied when changing from mode 5 to mode 6, that is, the current path (b) of the two-dot chain line shown in FIG. The same applies to the current path to which the surge voltage is applied when changing from mode to mode 3, that is, the current path (a) indicated by the alternate long and short dash line shown in FIG.

  As described above, in the level inverter circuit 101 of the present embodiment, the first to fourth IGBTs 1 to 4 are aligned on the first straight line α, and the connection terminals are oriented in the direction orthogonal to the mounting surface 30a. In addition, the first and second coupling diodes 5 and 6 are disposed apart from the connection terminals of the IGBTs 1 to 4 in the direction orthogonal to the first straight line α, and are stacked bus bars. 40 is formed to cover at least the connection terminals of the plurality of IGBTs 1 to 4 and electrically connects the connection terminals of the plurality of IGBTs 1 to 4 to each other. Since the first and second coupling diodes 5 and 6 do not exist on the same straight line as the plurality of IGBTs 1 to 4, even if the first and second coupling diodes 5 and 6 are insulated barriers between the cathode and the anode, respectively. The IGBTs 1 to 4 can be connected to each other as required by, for example, a simple flat laminated bus bar 40. Further, since the plurality of IGBTs 1 to 4 are arranged so as to form a package row along the first straight line α, the distance between the forward path and the return path of each current path can be reduced to some extent, The wiring inductance existing in can be reduced. Thereby, a turn-off surge voltage can be suppressed without using a snubber circuit.

In addition, since the DC power supply 9 is disposed substantially along the first straight line α, the current path extending from the IGBTs 1 to 4 in the direction of the DC power supply 9 is parallel to the current path formed between the IGBTs 1 to 4 and They can be formed close to each other, and the wiring inductance can be further reduced.
Further, the first to fourth IGBTs 1 are formed by the laminated bus bar 40 in which the flat connection plates arranged so as to be substantially parallel to the plane in which the first to fourth IGBTs 1 to 4 are arranged are laminated. ˜4 are electrically connected, the structure of the laminated bus bar 40 is simplified, and the laminated bus bar 40 can be directly connected without using a spacer or the like, thereby eliminating the wiring inductance generated by the spacer. Can do. Further, the transmission line can be easily formed and the cost can be reduced, and the distance between the forward path and the return path of each of the current paths (a) and (b) can be reduced, so that the current paths (a) and (b ) Can be further reduced.

Furthermore, since the substantially planar cooler 30 and the DC power supply 9 on which the first to fourth IGBTs 1 to 4 and the first and second coupling diodes 5 and 6 are mounted are arranged on the same plane, the first The first to fourth IGBTs 1 to 4, the first and second coupling diodes 5 and 6, and the DC power supply 9 are arranged on substantially the same plane, so that the apparatus can be thinned.
Furthermore, the three-level inverter circuit 101 of the present embodiment uses IGBTs 1 to 4 as first to fourth switching elements. Therefore, it is possible to reduce the size and weight, reduce the loss and increase the efficiency, prevent noise, harmonics and torque fluctuations, and improve the reliability.

Further, the three-level inverter device 100 of the present embodiment includes first and second three-level inverter circuits 101 and 102. The DC power supply 9 of the two three-level inverter circuits 101 and 102, the first to the first The four IGBTs 1 to 4 and the first and second coupling diodes 5 and 6 are arranged symmetrically with respect to a straight line α parallel to the switching element rows of the first to fourth IGBTs 1 to 4. A two-parallel three-level inverter device with good sharing can be obtained.
In addition, although the laminated bus bar 40 which is the laminated connection board of the embodiment has a three-layer structure, the laminated connection board is not limited to three layers, and may have more layers.

Next, a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, a single-phase three-level inverter device is provided. Also, the arrangement of the IGBT, the coupling diode, and the DC power supply is different from that of the first embodiment.
In FIG. 11, for each phase of a single phase, symbols “a” and “b” are added to the respective elements corresponding to those of the first embodiment for easy understanding.
FIG. 12 is a configuration diagram showing element package arrangement and inter-package connection of the three-level inverter device 200 shown in FIG. In FIG. 12, the three-level inverter device 200 of this embodiment includes a first three-level inverter circuit 201 and a second three-level inverter circuit 202. The circuit 201 and the circuit 202 are connected to each other with a predetermined connection to constitute the circuit of FIG.

  The first three-level inverter circuit 201 includes IGBTs 1a to 4a as first to fourth IGBTs. The collector C1 of the first IGBT 1a is connected to the positive terminal P of the DC power supply 9, and the emitter E1 is connected to the cathode K of the first coupling diode 5a as the terminal C2E1 together with the collector C2 of the second IGBT 2a. The anode A of the first coupling diode 5a is connected to the intermediate terminal M of the DC power supply 9 together with the cathode K of the second coupling diode 6a. The emitter E2 of the second IGBT 2a is connected to the AC output terminal AC1.

  The collector C1 of the third IGBT 3a is connected to the AC output terminal AC1, and the emitter E1 is connected to the anode A of the second coupling diode 6a as the terminal C2E1 together with the collector C2 of the fourth IGBT 4a. The cathode K of the second coupling diode 6 a is connected to the intermediate terminal M of the DC power supply 9. The emitter E2 of the fourth IGBT 4a is connected to the negative terminal N of the DC power supply 9.

  The first three-level inverter circuit 202 includes IGBTs 1b to 4b as first to fourth IGBTs. The collector C1 of the first IGBT 1b is connected to the positive terminal P of the DC power supply 9, and the emitter E1 is connected to the cathode K of the first coupling diode 5b as a terminal C2E1 together with the collector C2 of the second IGBT 2b. The anode A of the first coupling diode 5b is connected to the intermediate terminal M of the DC power supply 9 together with the cathode K of the second coupling diode 6b. The emitter E2 of the second IGBT 2b is connected to the AC output terminal AC2.

  The collector C1 of the third IGBT 3b is connected to the AC output terminal AC2, and the emitter E1 is connected to the anode A of the second coupling diode 6b together with the collector C2 of the fourth IGBT 4b as a terminal C2E1. The cathode K of the second coupling diode 6 b is connected to the intermediate terminal M of the DC power supply 9. The emitter E2 of the fourth IGBT 4b is connected to the negative terminal N of the DC power supply 9.

  In the first three-level inverter circuit 201 of the present embodiment, the first and second IGBTs 1a and 2a are packaged so that two IGBTs become one, and the first package is a so-called 2-in-1 package. 11a. Similarly, the third and fourth IGBTs 3a and 4a are the second package 12a. Similarly, the first and second coupling diodes 5a and 6a are the third package 13a. Each package has an elongated rectangular flat plate shape. And the 1st package 11a and the 2nd package 12a are arrange | positioned in parallel, and the 3rd package 13a is arrange | positioned so that these two packages 11a and 12a may make a U shape. More specifically, the third package 13a is arranged at a right angle to both the first and second packages 11a and 12a arranged in parallel on the C2E1 side.

And in this embodiment, since it is such arrangement | positioning, the arrangement | positioning area of three 2 in 1 packages becomes small, and each element 1st-4th IGBT1a-4a and 1st, 2nd The coupling diodes 5a and 6a are more integrated. Therefore, the area efficiency can be further increased and the length of the current path can be shortened. As a result, the wiring inductance existing in the current path can be reduced.
The same applies to the second three-level inverter circuit 202.
In the three-level inverter device 200 of the present embodiment, when the wiring inductance becomes the largest in the commutation operation, when changing from mode 2 to mode 3 and from mode 5 to mode 6 as in the first embodiment. It is time to change to.

  A current path (c) to which a surge voltage is applied when changing from mode 2 to mode 3 is shown in FIG. Further, a current path (d) to which a surge voltage is applied when changing from mode 5 to mode 6 is shown by a thick two-dot chain line in FIG. In order to reduce the wiring inductance generated in these current paths (c) and (d), as in the first embodiment, the wiring length is shortened and the current paths are formed by reciprocating paths that are close to each other. A method of canceling out the magnetic fields generated by the currents flowing through the reciprocating path is effective.

  FIG. 15 is a perspective view of the three-level inverter device 200 of this embodiment. In the present embodiment, all of the first to third packages 11a to 13a of the first three-level inverter circuit 201 and the first to third packages 11b to 13b of the second three-level inverter circuit 202 are included. It is mounted on the mounting surface 30 a on the upper surface of the cooler 30. The arrangement of each element is as shown in the arrangement configuration diagram of FIG. 12, and the four packages 11a, 12a, 12b, and 13b as switch parts form a package row along the first straight line α. Are lined up.

  The cooler 30 absorbs heat generated by the packages 11a to 13a and the packages 11b to 13b. Capacitors 7 and 8 are installed together with the cooler 30 on the same plane as a mounting surface of a device (not shown). As described above, in the present embodiment, the first to third packages 11a to 13a of the first three-level inverter circuit 201 and the first to third packages 11b to 13b of the second three-level inverter circuit 202 are arranged. All packages are mounted on the cooler 30. The cooler 30 and the DC power source 9 are arranged on the same plane. In the DC power source 9, the heights of the capacitors 7 and 8 are offset by the height (thickness) of the cooler 30, and the connection terminals of the capacitors 7 and 8 and the connection terminals of the packages are on the same plane. Has been placed. In this way, the device is made thinner.

  A laminated bus bar 50 for providing necessary electrical connection between the packages is provided on the top of the package that is mounted. The laminated bus bar 50 is produced by laminating a plurality of flat connection plates in the same manner as the laminated bus bar 40 of the first embodiment. The stacked bus bar 50 electrically connects the packages 11a to 13a, the packages 11b to 13a, and the DC power supply 9.

  In the present embodiment, the first and second IGBTs 1a and 2a, the third and fourth IGBTs 3a and 4a, and the first and second coupling diodes 5a and 6a are each formed into a single elongated shape. Since these three packages are arranged so as to form a U shape, the length of the current path can be shortened, and the distance between the forward path and the return path of each current path can be reduced. Wiring inductance existing in the road is reduced.

  FIG. 16 is a front view showing a state in which the first and second layer connection plates are removed from the three-level inverter device 200 of the present embodiment. FIG. 17 is a front view of each connecting plate portion constituting the laminated bus bar for connecting the respective packages. FIG. 17 (a) is a laminated connecting plate portion constituting the first layer, and FIG. FIG. 17C is a front view showing the laminated connecting plate part constituting the third layer. FIG.

The split connection plate 53a of the third layer performs electrical connection between the AC output terminal AC1, the emitter E2 of the IGBT 2a, and the collector C1 of the IGBT 3a. The split connection plate 53b of the third layer performs electrical connection between the AC output terminal AC2, the emitter E2 of the IGBT 2b, and the collector C1 of the IGBT 3b.
The split connection plate 54a of the third layer makes an electrical connection between the collector of the IGBT 2a (emitter of the IGBT 1a) C2E1 and the cathode K of the coupling diode 5a. The split connection plate 54b of the third layer performs an electrical connection between the collector of the IGBT 2b (emitter of the IGBT 1b) C2E1 and the cathode K of the coupling diode 5b.

The split connection plate 55a of the third layer performs electrical connection between the anode A of the coupling diode 6a and the collector of the IGBT 4a (emitter of the IGBT 3a) C2E1. The split connection plate 55b of the third layer performs electrical connection between the anode A of the coupling diode 6b and the collector of the IGBT 4b (emitter of the IGBT 3b) C2E1.
The third-layer split connection plate 56 performs electrical connection between the cathode K of the coupling diode 6 a and the cathode K of the coupling diode 6 b and the intermediate terminal M of the DC power supply 9. The connection board 55 of the second layer performs electrical connection between the emitter E2 of the IGBT 4a, the emitter E2 of the IGBT 4b, and the negative terminal N of the DC power supply 9. The first-layer laminated connecting plate portion 51 performs electrical connection between the collector C1 of the IGBT 1a, the collector C1 of the IGBT 1b, and the positive terminal P of the DC power supply 9.

  In FIG. 17, the path of the current path (d) of the two-dot chain line shown in FIG. 14 is added. In the connection plate constituting the first layer shown in (a) in the figure and the connection plate constituting the third layer shown in (c), there is a portion where the flowing current paths partially overlap. In addition, among the overlapping portions, there are places where the directions are opposite and close to each other. In such a place, the magnetic fields cancel each other, and a certain reduction in wiring inductance can be expected.

Note that the same applies to the current path (c) indicated by the alternate long and short dash line shown in FIG.
Further, the three-level inverter device 200 of the present embodiment uses a switch component in which two switching elements are packaged. Therefore, a plurality of switching elements can be easily mounted with more area efficiency.
Needless to say, the number of switching elements to be packaged is not limited to two, and if more switching elements are packaged, the area efficiency is further improved.

  FIG. 18 is a circuit diagram showing another example of the three-level inverter device according to the second embodiment of the present invention. In the three-level inverter device 300, the emitters of the second IGBTs 2a and 2b and the collectors of the third IGBTs 3a and 3b are connected to one AC output terminal AC. The above-described three-level inverter device 200 has two outputs, AC1 and AC2, whereas the three-level inverter device 300 has one output. In the three-level inverter device 300 having such a configuration, the same effect as that of the above-described three-level inverter device 200 can be obtained.

  The three-level inverter circuit 201 having such a configuration includes a DC power source 9, a plurality of packages 11a to 13a, coupling diodes 5a and 6a, and a stacked bus bar 50 that electrically connects these electrical components. Yes. The DC power source 9 has a positive terminal P, an intermediate terminal M, and a negative terminal N, and the plurality of packages are connected in series between the positive terminal P and the AC output terminal AC1 in series. A first package 11a in which two IGBTs 1a and 2a are packaged, and third and fourth IGBTs 3a and 4a that are sequentially connected in series between the AC output terminal AC1 and the negative electrode terminal N. A first coupling diode 5a connected between the connection point of the first and second IGBTs 1a and 2a and the intermediate terminal M, and third and fourth IGBTs 3a. , 4a and a third package 13a packaged with a second coupling diode 6a connected between the intermediate point M and the intermediate terminal M, and the first, second and third packages 11a-13a. Is that The first and second packages 11a and 12a are arranged so as to be orthogonal to the first straight line α and in parallel with each other, and the third package 13a is provided at the ends of both the packages 11a and 12a. Are arranged so as to be parallel to the first straight line α, and the first, second and third packages 11a to 13a are arranged so as to form a U-shape.

Moreover, since the 1st, 2nd and 3rd packages 11a-13a are arrange | positioned so that a U-shape may be formed, an area ratio and an aggregation rate can be improved further.
In the three-level inverter device 200 of this embodiment, since the first and second three-level inverter circuits 201 and 202 are provided side by side, the current sharing to the circuits 201 and 202 is improved. Or it can be set as a 3 level inverter apparatus of a large current rating by making each element into a parallel connection structure. The same applies to the three-level inverter device 300.

  The three-level inverter devices of the first embodiment and the second embodiment each have two three-level inverter circuits, but a predetermined effect can be obtained with only one of the circuits. Needless to say. Further, although the IGBT is used as the switching element, a predetermined effect can be obtained even with another switching element such as a transistor, an intelligent power module, or an FET. The number of parallel elements is not limited to the two described in the second embodiment.

It is a block diagram which shows the element package arrangement | positioning and connection between packages of the 3 level inverter apparatus of 1st Embodiment. It is a circuit diagram of the 3 level inverter circuit of 1st Embodiment, and is a figure explaining each current path in each current mode of mode 1 to mode 6 of the same circuit. (A) is a current path when changing from mode 1 to mode 2, (A) is a current path when changing from mode 2 to mode 3, and (C) is a current path when changing from mode 4 to mode 5. Path (D) is a diagram for explaining a current path when changing from mode 5 to mode 6. FIG. 2 is a diagram in which a current path when changing from mode 2 to mode 3 is added to the element package arrangement of the three-level inverter circuit shown in FIG. FIG. 2 is a diagram in which a current path when changing from mode 5 to mode 6 is added to the element package arrangement of the three-level inverter circuit shown in FIG. 1 by a two-dot chain line. It is a perspective view of the 3 level inverter circuit of 1st Embodiment. It is a disassembled perspective view of FIG. 5 which shows the structure of the electrical connection between each package. It is a front view of each connection board which constitutes a lamination bus bar which performs connection between each package. (A) is a conductive connection plate portion constituting the first layer, (b) is a conductive connection plate portion constituting the second layer, and (c) is a conductive connection plate portion constituting the third layer. FIG. It is the figure which added the electroconductive connection board part which forms the 1st layer of a connection board to the element package arrangement | positioning of the 3 level inverter circuit shown in FIG. 1 with the broken line. It is the figure which added the electroconductive connection board part which forms the 2nd layer of a connection board to the element package arrangement | positioning of the 3-level inverter circuit shown in FIG. 1 with the broken line. FIG. 3 is a diagram in which each divided connection plate for forming a third layer of the connection plate is added to the element package arrangement of the three-level inverter circuit shown in FIG. 1 by a broken line. It is a circuit diagram of the 3 level inverter apparatus of 2nd Embodiment. It is a block diagram which shows the element package arrangement | positioning and connection between packages of the 3 level inverter apparatus of 2nd Embodiment. FIG. 13 is a diagram in which a current path when changing from mode 2 to mode 3 is added to the element package arrangement of the three-level inverter circuit shown in FIG. FIG. 13 is a diagram in which a current path when changing from mode 5 to mode 6 is added to the element package arrangement of the three-level inverter circuit shown in FIG. 12 by a two-dot chain line. It is a perspective view of the 3 level inverter apparatus of 2nd Embodiment. It is a front view which shows a mode that the 2nd layer and 3rd layer connection board of the 3 level inverter apparatus of 2nd Embodiment were removed. It is a front view of each connection board which constitutes a lamination bus bar which performs connection between each package. It is a circuit diagram which shows the other example of the 3 level inverter apparatus of 2nd Embodiment.

Explanation of symbols

  1-4, 1a-4a, 1b-4b 1st-4th IGBT (1st-4th switch element, element package), 5, 5a, 5b 1st coupling diode (diode package), 6, 6a , 6b Second coupled diode (diode package), 7, 8 capacitor, 9 DC power supply, 11a-13a, 11b-13b 1st to 3rd package, 30 cooler, 40, 50 stacked bus bar (connection means), 41-43 1st-3rd electroconductive connection board part, 44-47 1st-4th division | segmentation connection board, 100,200 3 level inverter apparatus, 101,102,201,202 3 level inverter circuit.

Claims (5)

A three-level inverter in which a plurality of element packages incorporating switching elements and a plurality of diode packages incorporating coupling diodes are arranged on the mounting surface, and the connection terminals of each package are connected via a stacked connection plate In the circuit
A DC power supply is juxtaposed on one end side of the element package row,
The plurality of element packages are composed of first, second, third, and fourth element packages arranged from the opposite side of the DC power source toward the DC power source, and the plurality of diode packages are The first and second diode packages are arranged at a predetermined distance apart in a direction orthogonal to the arrangement direction of the second and third element packages,
The laminated connection plate connects a positive electrode terminal of the DC power source and a positive electrode side terminal of the first element package, and covers the first to fourth element packages, and the first conductive connection plate part, A second conductive connecting plate connecting the anode terminal of the first diode package and the cathode terminal of the second diode package and the intermediate terminal of the DC power supply and covering the first to fourth element packages; 3-level inverter circuit and the third conductive connecting plate portion for connecting the other terminal is characterized in that have a laminated structure through an insulating plate. Between the connection terminals of the DC power supply terminal and the device package and the diode package, the covering of a laminated connection plate such that the intermediate portion of the anode and cathode terminals of at least the diode package is exposed, electrical The three-level inverter circuit according to claim 1, wherein the three-level inverter circuit is connected to. The third conductive connection plate portion includes a first divided connection plate that connects a negative terminal of the first element package, a positive terminal of the second element package, and a cathode terminal of the first diode package. A second divided connection plate for connecting the negative electrode side terminal of the second element package and the positive electrode side terminal of the third element package and having an AC output terminal; a negative electrode side terminal of the third element package; A third divided connection plate for connecting the positive electrode side terminal of the element package and the anode of the second diode package, and a fourth divided connection for connecting the negative electrode side terminal of the fourth element package and the negative electrode terminal of the DC power supply. The three-level inverter circuit according to claim 1 , wherein the three-level inverter circuit is configured by a plate. Wherein the plurality of device packages and the plurality of diodes packages, three-level inverter circuit according to any one of claims 1 to 3, characterized in that it incorporates a respective one element.   The plurality of element packages and the plurality of diode packages each include two elements and each have an elongated shape, and the plurality of element packages are arranged with their longitudinal directions orthogonal to the straight line, 2. The three-level inverter circuit according to claim 1, wherein the one diode package is arranged so that the three packages are U-shaped with respect to the element package.

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