JP7395935B2 - power converter - Google Patents

Description

The present invention relates to a power conversion device, and particularly to a power conversion device including a plurality of semiconductor modules.

2. Description of the Related Art Conventionally, a power conversion device including a plurality of semiconductor modules is known (for example, see Patent Document 1).

In the power conversion device disclosed in Patent Document 1, four switching elements (hereinafter referred to as switching elements Q1 to Q4) are connected in series between a positive terminal and a negative terminal. Further, two switching elements (hereinafter referred to as switching elements Q5 and Q6) are connected in series with each other between the connection point between switching element Q1 and switching element Q2 and the connection point between switching element Q3 and switching element Q4. It is connected. Further, switching elements Q1 and Q2 are housed in one module (hereinafter referred to as a first module). Further, switching elements Q2 and Q3 are housed in one module (hereinafter referred to as a second module). Further, switching elements Q5 and Q6 are housed in one module (hereinafter referred to as a third module).

Further, the connection point between the first module and the second module is connected to a midpoint terminal (middle potential). Further, a connection point between switching element Q5 and switching element Q6 housed in the third module is connected to an AC terminal. As a result, the power conversion device disclosed in Patent Document 1 outputs power at three levels of potential (upper potential, intermediate potential, and lower potential). Further, the first to third modules are mutually composed of the same modules. In other words, it is considered that the modules have the same breakdown voltage and the like.

International Publication No. 2017/141407

However, in a power conversion device that outputs power at three levels of potential as described in Patent Document 1, the magnitude of the surge voltage generated due to the switching of the switching elements included in each module is Varies between elements. Specifically, the inductance (length of a loop path (closed circuit) including the switching element), which is a cause of surge voltage, in the circuit after the switching element has switched differs between the plurality of switching elements. Here, in the above-mentioned Patent Document 1, the first to third modules are composed of modules having the same breakdown voltage. Therefore, if three modules are selected to withstand the maximum surge voltage applied to the switching element, the withstand voltage of one of the three modules will be higher than necessary (excessive performance). There is a problem.

This invention has been made to solve the above-mentioned problems, and one object of the invention is to provide a power conversion device that can suppress excessive performance.

In order to achieve the above object, a power conversion device according to one aspect of the present invention is a power conversion device that outputs power at three levels of potential: an upper potential, an intermediate potential, and a lower potential. an upper potential semiconductor module connected to an intermediate potential and housing therein a plurality of semiconductor elements including at least one upper potential switching element; and an upper potential semiconductor module connected to an intermediate potential and a lower potential and including at least one lower potential switching element. The intermediate semiconductor module includes a lower potential semiconductor module housing a plurality of semiconductor elements therein, and an intermediate semiconductor module connected to the upper potential semiconductor module and the lower potential semiconductor module and housing a plurality of intermediate switching elements therein. The breakdown voltage is configured to be larger than the breakdown voltage of the upper potential semiconductor module and the breakdown voltage of the lower potential semiconductor module, and each of the upper potential semiconductor module, the lower potential semiconductor module, and the intermediate semiconductor module has a positive side terminal and a negative side terminal. The output terminal of the intermediate semiconductor module and the output terminal of the lower semiconductor module are connected to each other when viewed from a direction perpendicular to the arrangement plane in which the upper potential semiconductor module, the lower potential semiconductor module, and the intermediate semiconductor module are arranged, including the terminal and the output terminal. , the lower potential semiconductor module and the intermediate semiconductor module are arranged next to each other, or the higher potential semiconductor module and the intermediate semiconductor module are arranged so that the positive side terminal of the intermediate semiconductor module and the output terminal of the upper semiconductor module are adjacent to each other. An intermediate semiconductor module is arranged .

In the power conversion device according to one aspect of the present invention, as described above, the withstand voltage of the intermediate semiconductor module is configured to be larger than the withstand voltage of the upper potential semiconductor module and the withstand voltage of the lower potential semiconductor module , and the upper potential Each of the semiconductor module, the lower potential semiconductor module, and the intermediate semiconductor module includes a positive terminal, a negative terminal, and an output terminal, and is perpendicular to the arrangement plane in which the upper potential semiconductor module, the lower potential semiconductor module, and the intermediate semiconductor module are arranged. The lower potential semiconductor module and the intermediate semiconductor module are arranged so that the output terminal of the intermediate semiconductor module and the output terminal of the lower semiconductor module are adjacent to each other when viewed from the direction, or the positive side terminal of the intermediate semiconductor module The upper potential semiconductor module and the intermediate semiconductor module are arranged so that the upper potential semiconductor module and the output terminal of the upper semiconductor module are adjacent to each other . Here, after the intermediate switching element is switched from on to off, the loop path (closed circuit) including the intermediate switching element includes an upper potential switching element (or lower potential switching element) in addition to the intermediate switching element. It includes a path connecting the intermediate switching element and the upper potential switching element (or lower potential switching element). That is, the number of elements included in one round path is relatively large, and the length of one round path is relatively long. For this reason, the inductance of one round path after switching the intermediate switching element becomes larger than the inductance of one round path including the upper potential switching element or the lower potential switching element. As a result, the surge voltage generated when switching the intermediate switching element becomes larger than the surge voltage generated when switching the upper potential switching element or the lower potential switching element from on to off. Therefore, by configuring as described above, unlike the case where the withstand voltages of the upper potential semiconductor module, intermediate semiconductor module, and lower potential semiconductor module are all made relatively large, excessive performance of the power conversion device can be prevented. Can be suppressed. Note that a detailed explanation of the route taken when the upper potential switching element, the intermediate switching element, and the lower potential switching element switch will be described later.
In the power conversion device according to the above-described one aspect, preferably , each of the upper potential semiconductor module, the lower potential semiconductor module, and the intermediate semiconductor module is arranged in the arrangement plane on which the upper potential semiconductor module, the lower potential semiconductor module, and the intermediate semiconductor module are arranged. The lower potential semiconductor module and the intermediate semiconductor module are arranged in a straight line so that the output terminal of the intermediate semiconductor module and the output terminal of the lower semiconductor module are adjacent to each other when viewed from the vertical direction, or The upper potential semiconductor module and the intermediate semiconductor module are arranged in a straight line so that the positive side terminal of the module and the output terminal of the upper semiconductor module are adjacent to each other.

In the power conversion device according to the first aspect, preferably, the withstand voltage of the intermediate semiconductor module is higher than the surge voltage when the intermediate switching element is switched from on to off. With this configuration, it is possible to prevent the intermediate switching element from being destroyed by surges generated due to switching of the intermediate switching element.

In this case, preferably, the withstand voltage of the intermediate semiconductor module is determined according to the inductance of a circuit related to the surge including the intermediate switching element when the intermediate switching element is switched from on to off. The voltage is selected to be higher than the withstand voltage of the lower potential semiconductor module. With this configuration, the withstand voltage of the intermediate semiconductor module is selected according to the inductance of the one-round path, so it is possible to suppress the selection of an intermediate semiconductor module whose withstand voltage is excessively large with respect to the inductance. . As a result, it is possible to suppress the power converter from increasing in size due to selection of an intermediate semiconductor module with an excessively high breakdown voltage (that is, a large intermediate semiconductor module).

In the power conversion device according to the above one aspect, preferably, the upper potential semiconductor module, the lower potential semiconductor module, and the intermediate semiconductor module each include a positive terminal, a negative terminal, and an output terminal, and the upper potential semiconductor module, Viewed from the direction perpendicular to the arrangement plane on which the lower potential semiconductor module and the intermediate semiconductor module are arranged, the positive terminal, negative terminal, and output terminal of the upper potential semiconductor module, the positive terminal, negative terminal, and The upper potential semiconductor module, the lower potential semiconductor module, and the intermediate semiconductor module are arranged so that the output terminal, the output terminal, the negative terminal, and the positive terminal of the lower potential semiconductor module are arranged in this order along a straight line. It is placed on the placement surface. With this configuration, the distance between the output terminal of the upper potential semiconductor module and the positive terminal of the intermediate semiconductor module becomes relatively small, so the length of the conductor that connects these terminals becomes long. Can be suppressed. Furthermore, since the distance between the negative terminal of the intermediate semiconductor module and the output terminal of the lower potential semiconductor module is relatively small, it is possible to suppress the length of the conductor connecting these terminals from increasing. . That is, it is possible to suppress an increase in inductance due to an increase in the length of the conductor.

In this case, preferably, a substantially flat positive flat conductor is connected to the positive terminal of the upper potential semiconductor module, a negative terminal of the upper potential semiconductor module, and a positive terminal of the lower potential semiconductor module. The positive flat plate conductor is arranged on the surface of the positive terminal of the upper potential semiconductor module, and the intermediate flat conductor is arranged on the arrangement surface of the positive flat plate conductor. is placed on the opposite surface. With this configuration, the positive flat conductor and the intermediate flat conductor are stacked so as to face each other, so that the magnetic flux generated due to the current flowing through the positive flat conductor and the magnetic flux generated due to the current flowing through the intermediate flat conductor are It is possible to cancel out the magnetic flux generated by the magnetic flux. As a result, an increase in inductance due to the magnetic flux of the flowing current can be suppressed.

In the power converter device including the positive flat conductor and the intermediate flat conductor, preferably the positive flat conductor is provided with a positive flat conductor hole, and the intermediate flat conductor is provided with a positive flat conductor hole. It is connected to the negative side terminal of the upper potential semiconductor module and the positive side terminal of the lower potential semiconductor module via the side flat plate conductor hole. With this configuration, even when the intermediate flat conductor is laminated on the positive flat conductor, the intermediate flat conductor and the negative of the upper potential semiconductor module can be easily connected to each other through the positive flat conductor hole of the positive flat conductor. The side terminal and the positive side terminal of the lower potential semiconductor module can be connected.

In the power converter device including the positive flat plate conductor and the intermediate flat conductor, preferably, the first connection flat conductor has a substantially flat plate shape and is connected to the output terminal of the upper potential semiconductor module and the positive terminal of the intermediate semiconductor module. a substantially flat second connecting flat conductor connected to the output terminal of the lower potential semiconductor module and the negative terminal of the intermediate semiconductor module; and a generally flat second connecting flat conductor connected to the negative terminal of the lower potential semiconductor module and a negative flat plate conductor, wherein the first connecting flat conductor, the second connecting flat plate conductor, and the negative flat plate conductor are arranged adjacent to each other on the surface of the intermediate flat conductor opposite to the arrangement surface. There is. With this configuration, the first connecting flat conductor, the second connecting flat conductor, the negative side flat conductor, and the intermediate flat conductor are stacked so as to face each other, so that the first connecting flat conductor, the second connecting flat conductor, and the second connecting flat conductor are stacked so as to face each other. The magnetic flux generated due to the current flowing through each of the flat plate conductor and the negative side flat conductor and the magnetic flux generated due to the current flowing through the intermediate flat plate conductor can be canceled out. As a result, an increase in inductance due to the magnetic flux of the flowing current can be suppressed.

In this case, preferably, the positive flat conductor is provided with a positive flat conductor hole, the intermediate flat conductor is provided with an intermediate flat conductor hole, and the first connection flat conductor is The second connecting flat conductor is connected to the output terminal of the upper potential semiconductor module and the positive terminal of the intermediate semiconductor module through the positive flat conductor hole and the intermediate flat conductor hole. The negative side flat conductor is connected to the output terminal of the lower potential semiconductor module and the negative terminal of the intermediate semiconductor module through the intermediate flat conductor hole and the positive flat conductor hole. It is connected to the negative side terminal of the lower potential semiconductor module via the lower potential semiconductor module. With this configuration, even when the first connecting flat conductor, the second connecting flat conductor, and the negative flat conductor are stacked on the positive flat conductor and the intermediate flat conductor, the positive flat conductor hole and the intermediate flat conductor Each conductor and each terminal can be easily connected through the holes.

In the power converter device including the first connecting flat conductor, the second connecting flat conductor, and the negative flat conductor, it is preferable that the first capacitor be connected to the positive flat conductor and the intermediate flat conductor; It further includes a second capacitor connected in series and connected to the negative flat plate conductor and the intermediate flat plate conductor, the positive flat plate conductor being connected to the positive terminal of the upper potential semiconductor module and substantially horizontal to the arrangement surface. It has an approximately L-shape including a first positive conductor portion and a second positive conductor portion connected to the first capacitor and approximately perpendicular to the arrangement surface, and the negative flat plate conductor is connected to the negative side of the lower potential semiconductor module. The intermediate flat plate has a substantially L-shape including a first negative conductor portion connected to the side terminal and substantially horizontal to the arrangement surface, and a second negative conductor portion connected to the second capacitor and substantially perpendicular to the arrangement surface. The conductor includes a first intermediate conductor portion that is connected to the negative terminal of the upper potential semiconductor module and a positive terminal of the lower potential semiconductor module and is substantially horizontal to the placement surface, and a first intermediate conductor portion that is connected to the first capacitor and the second capacitor and is parallel to the placement surface. It has a substantially L-shape including a substantially vertical second intermediate conductor portion. With this configuration, the positive flat conductor, the negative flat conductor, and the intermediate flat conductor are laminated, canceling out magnetic flux with each other (that is, reducing inductance), and stacking the positive flat conductor and the intermediate flat conductor. The conductor and the first capacitor can be connected, and the negative flat plate conductor and the intermediate flat plate conductor can be connected to the second capacitor.

In the power converter device including the first connecting flat conductor, the second connecting flat conductor, and the negative flat conductor, preferably, the first connecting flat conductor, the second connecting flat conductor, and the negative flat conductor are arranged on the arrangement surface. When viewed from a direction perpendicular to , the positive flat conductor and the intermediate flat conductor are arranged so as to overlap with each other. With this configuration, the first connecting flat conductor, the second connecting flat conductor, and the negative flat conductor are arranged so as to overlap the positive flat conductor and the intermediate flat conductor, so that it is possible to reliably The magnetic fluxes generated due to the current flowing through each conductor can cancel each other out.

According to the present invention, as described above, it is possible to suppress excessive performance of the power conversion device.

FIG. 1 is a circuit diagram of a power conversion device (power conversion section) according to the present embodiment. FIG. 2 is a top view of a semiconductor module according to this embodiment. FIG. 7 is a diagram showing a path through which current flows when switching element Q1 is on. FIG. 3 is a diagram showing a path through which current flows when switching element Q1 switches from on to off. FIG. 7 is a diagram showing a path through which current flows when switching element Q3 is on. FIG. 6 is a diagram showing a path through which current flows when switching element Q3 switches from on to off. FIG. 2 is a perspective view of a power conversion unit according to the present embodiment. FIG. 3 is a top view of the power conversion unit according to the present embodiment. FIG. 2 is a top view of the semiconductor module of the power conversion unit according to the present embodiment. FIG. 2 is an exploded perspective view of a power converter (conductor) according to the present embodiment. FIG. 2 is a perspective view of a positive flat plate conductor according to the present embodiment. FIG. 3 is a perspective view of the negative flat plate conductor according to the present embodiment. FIG. 3 is a perspective view of an intermediate flat conductor according to the present embodiment. FIG. 3 is a perspective view of a first connected flat conductor according to the present embodiment. It is a perspective view of the 2nd connection flat conductor by this embodiment.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments embodying the present invention will be described based on the drawings.

The configuration of a power conversion device 100 according to this embodiment will be described with reference to FIGS. 1 to 15.

As shown in FIG. 1, the power conversion device 100 is configured to output power at three levels of potential: an upper potential P, an intermediate potential M, and a lower potential N. Note that the power conversion device 100 is used, for example, as a PCS (Power Conditioning System). The power conversion device 100 outputs DC power generated by a solar cell as three-phase AC power. Power conversion device 100 includes a power conversion section 10. The power conversion unit 10 is provided for each phase (U phase, V phase, and W phase). The configuration of one power conversion section 10 will be described below.

As shown in FIG. 1, power conversion unit 10 includes a switching element Q1, a switching element Q2, a switching element Q3, and a switching element Q4 that are connected in series with each other. Switching elements Q1 to Q4 are connected between an upper potential P and a lower potential N. Further, a diode D is connected in antiparallel to each of the switching elements Q1 to Q4. Note that the switching elements Q1 to Q4 are, for example, IGBTs (Insulated Gate Bipolar Transistors) made of silicon (Si) semiconductors. Further, the diode D is made of a silicon (Si) semiconductor. Note that the switching element Q1 is an example of an "upper potential switching element" and a "semiconductor element" in the claims. Furthermore, switching elements Q2 and Q3 are examples of "intermediate switching elements" in the claims. Furthermore, the switching element Q4 is an example of a "lower potential switching element" and a "semiconductor element" in the claims.

Furthermore, the power conversion unit 10 includes a capacitor C1 and a capacitor C2 that are connected in series between the upper potential P and the lower potential N. Note that the connection point between the capacitor C1 and the capacitor C2 is at an intermediate potential M. Capacitor C1 and capacitor C2 are electrically connected in parallel to switching elements Q1 to Q4. Note that the capacitor C1 and the capacitor C2 are examples of a "first capacitor" and a "second capacitor" in the claims, respectively.

The power conversion unit 10 also includes a diode D1 that is electrically connected to a connection point N1 between the switching element Q1 and the switching element Q2, and a connection point N2 between the switching element Q3 and the switching element Q4, and is connected in series with each other. and a diode D2. Note that the diode D1 and the diode D2 function as clamp diodes. Further, the anode of the diode D1 is electrically connected to the intermediate potential M. Further, the cathode of the diode D1 is electrically connected to the connection point N1. An anode of diode D2 is electrically connected to connection point N2. Further, the cathode of the diode D2 is electrically connected to the intermediate potential M. Note that the diode D1 and the diode D2 are examples of a "semiconductor element" in the claims.

The power conversion section 10 is provided with a plurality of semiconductor modules 20 (semiconductor modules 20a to 20c). The semiconductor module 20a is connected to an upper potential P and an intermediate potential M (the connection point between the capacitor C1 and the capacitor C2). Moreover, the semiconductor module 20a houses at least one switching element (specifically, switching element Q1) and a diode D1 inside. Note that the diode D1 is configured by only the diode D functioning in a switching element configured from an IGBT and a diode D connected in antiparallel to the IGBT. That is, the semiconductor modules 20a and 20c are composed of modules having the same structure (a structure in which two switching elements are housed inside, referred to as 2in1). Note that the diode D1 may be housed in the semiconductor module 20a as a single diode. In this case, the semiconductor modules 20a and 20c are composed of modules having mutually different structures. Note that the semiconductor modules 20a, 20b, and 20c are examples of an "upper potential semiconductor module", "lower potential semiconductor module", and "intermediate semiconductor module" in the claims, respectively.

The semiconductor module 20b is connected to an intermediate potential M and a lower potential N. Further, the semiconductor module 20b houses at least one switching element (specifically, the switching element Q4) and a diode D2 therein. Note that the diode D2 is configured by only the diode D functioning in a switching element configured from an IGBT and a diode D connected in antiparallel to the IGBT. That is, the semiconductor modules 20b and 20c are composed of modules having the same structure (a structure in which two switching elements are housed inside). Note that the diode D2 may be housed in the semiconductor module 20b as a single diode. In this case, the semiconductor modules 20b and 20c are composed of modules having mutually different structures.

The semiconductor module 20c is connected to the semiconductor module 20a and the semiconductor module 20b. Further, the semiconductor module 20c houses therein a plurality of switching elements Q2 and a plurality of switching elements Q3.

As shown in FIG. 2, the semiconductor module 20 includes a positive terminal 21, a negative terminal 22, and an output terminal 23. On the surface of the semiconductor module 20, the positive terminal 21, the negative terminal 22, and the output terminal 23 are arranged in this order from the A1 direction to the A2 direction. Further, the semiconductor module 20 has a substantially rectangular parallelepiped shape. Further, the positive side terminal 21 and the negative side terminal 22 of the semiconductor module 20 function as a collector (C) terminal and an emitter (E) terminal, respectively. Further, the output terminal 23 of the semiconductor module 20 functions as an emitter terminal of one (Q2) of two switching elements (for example, Q2 and Q3) included in the semiconductor module 20 and a collector terminal of the other (Q3). .

Next, the operation of the power conversion device 100 when the switching element Q1 is switched from on to off and when the switching element Q3 is switched from on to off will be described.

As shown in FIG. 3, when the switching element Q1 (and the switching element Q2) is on, a current flows through the switching element Q1, the switching element Q2, and the capacitor C1 (hereinafter referred to as path A1). (see thick solid line) is formed. Next, as shown in FIG. 4, the switching element Q1 is switched from on to off, so that the current flowing through the above path A1 passes through the switching element Q2 and the diode D1 (hereinafter referred to as a freewheeling path). It flows along route A2 (see thick dotted line in FIG. 4). Furthermore, since the switching element Q1 is turned off, no current flows through the one-way path (hereinafter referred to as path A3, see the thick solid line in FIG. 4) via the switching element Q1, the capacitor C1, and the diode D1. The inductance (L) included in path A3 works to keep the current flowing. Therefore, a surge voltage Vce1 is generated in the switching element Q1 due to the inductance (L). The magnitude of the surge voltage Vce1 is approximately proportional to the inductance of the path A3.

As shown in FIG. 5, when switching element Q3 (and switching element Q2) is on, a current flows through a path (hereinafter referred to as path B1) in FIG. 5 via switching element Q3, diode D2, and capacitor C1. (see thick solid line) is formed. Next, as shown in FIG. 6, the switching element Q3 is switched from on to off, so that the current flowing through the above path B1 is transferred to a path (reflux path, hereinafter referred to as a freewheeling path) via the switching element Q2 and the switching element Q1. , route B2 (see thick dotted line in FIG. 6). Furthermore, since the switching element Q3 is turned off, a loop path (hereinafter referred to as path B3, indicated by the thick solid line in FIG. 6) via the switching element Q1, the switching element Q2, the switching element Q3, the diode D2, and the capacitor C1 (see), while no current flows, the inductance (L) included in path B3 acts to keep the current flowing. Therefore, a surge voltage Vce2 is generated in the switching element Q3 due to the inductance (L).

Here, the path length of one round path B3 formed by turning off switching element Q3 is longer than the path length of one round path A3 formed when switching element Q1 is turned off. Specifically, compared to the path A3, the path B3 connects the first connecting flat conductor 70 (see FIG. 1) that connects the switching element Q1 and the switching element Q2, and the switching element Q3 and the switching element Q4 (the diode D2). ) is additionally added as a second connecting flat conductor 80 (see FIG. 1). Further, the number of switching elements present in path B3 is three (Q1 to Q3), which is greater than the number (one) of switching elements (Q1) present in path A3. Therefore, the inductance of path B3 becomes larger than the inductance of path A3. For example, the inductance of path B3 is about 2.5 times larger than the inductance of path A3. As a result, the surge voltage Vce2 generated in the switching element Q3 when the switching element Q3 is turned off becomes larger than the surge voltage Vce1 generated in the switching element Q1 when the switching element Q1 is turned off.

Therefore, in this embodiment, the power conversion device 100 is configured such that the breakdown voltage of the semiconductor module 20c is higher than the breakdown voltage of the semiconductor module 20a and the breakdown voltage of the semiconductor module 20b. For example, the breakdown voltage of the semiconductor module 20c is about 1700V, and the breakdown voltage of the semiconductor module 20a and the semiconductor module 20b are about 1200V.

Note that the length (inductance) of one round path when the switching element Q4 is switched from on to off is the same as the length (inductance) of the path A3. Further, the length (inductance) of one round path when the switching element Q2 is switched from on to off is the same as the length (inductance) of the path B3.

Further, in this embodiment, the breakdown voltage of the semiconductor module 20c is higher than the surge voltage Vce2 (for example, about 1300 V) when the switching element Q2 or Q3 is switched from on to off. The breakdown voltage of the semiconductor module 20c is determined depending on the inductance of the circuit path B3 related to the surge, including the switching element Q2 or Q3 when the switching element Q2 or Q3 is switched from on to off. Also, the voltage is selected to be higher than the breakdown voltage of the semiconductor module 20b.

Next, losses in the switching elements Q1 to Q4 will be explained. By making the breakdown voltage of the semiconductor module 20c larger than the breakdown voltages of the semiconductor module 20a and the semiconductor module 20b, the conduction loss of the semiconductor module 20c increases. On the other hand, in a PCS or the like, since the power factor is operated near 1, the number of times the semiconductor module 20c is switched is small. Thereby, the switching loss of the semiconductor module 20c is small. On the other hand, the switching loss of the semiconductor module 20a and the semiconductor module 20b is large. As a result, even if the conduction loss of the semiconductor module 20c is large, the difference between the total loss of the semiconductor module 20c and the total loss of each of the semiconductor module 20a and the semiconductor module 20b is relatively small. That is, the influence on loss caused by increasing the withstand voltage of the semiconductor module 20c is relatively small.

Next, a specific structure of the power conversion device 100 will be explained.

As shown in FIGS. 7 and 8, the power conversion section 10 includes a cooling section 30. The cooling unit 30 includes a cooling unit main body 31 having a substantially flat plate shape, and radiation fins 32 extending downward (in the Z2 direction) from the cooling unit main body 31. Further, the plurality of semiconductor modules 20 are arranged on the upper surface 31a (Z1 direction side) of the cooling unit main body 31. Note that the surface 31a is an example of an "arrangement surface" in the claims.

In this embodiment, as shown in FIG. 9, the positive terminal 21, the negative terminal 22, the output terminal 23, and The positive terminal 21, negative terminal 22, and output terminal 23 of the semiconductor module 20c, and the output terminal 23, negative terminal 22, and positive terminal 21 of the semiconductor module 20b are arranged in this order along the straight line L1. Semiconductor module 20a, semiconductor module 20b, and semiconductor module 20c are arranged on surface 31a so as to be shown in FIG. Three semiconductor modules 20a, 20b, and 20c are provided in parallel for each phase. That is, nine parallel power conversion units 10 are provided. In all of the nine parallel semiconductor modules 20a to 20c of the power conversion section 10, the respective terminals (the positive terminal 21, the negative terminal 22, and the output terminal 23) are arranged in the above order. Note that the straight line L1 is along the X direction.

Further, in this embodiment, as shown in FIGS. 7, 8, and 10, the power conversion device 100 includes a substantially flat positive flat conductor 40. The positive flat conductor 40 is connected to the positive terminal 21 of the semiconductor module 20a. Further, the positive flat plate conductor 40 is connected to all of the positive terminals 21 of the nine parallel semiconductor modules 20a. The positive flat conductor 40 is arranged on the surface (directly above) of the positive terminal 21 of the semiconductor module 20a. Further, the positive flat plate conductor 40 is directly connected to the positive terminal 21 of the semiconductor module 20a with a screw or the like. Further, the positive flat conductor 40 is made of, for example, a copper bar. Moreover, the positive side flat conductor 40 is arranged so as to extend across the positive side terminals 21 of each of the plurality of (nine parallel) semiconductor modules 20a.

Further, in this embodiment, the power conversion device 100 includes a substantially flat intermediate plate conductor 50. The intermediate flat conductor 50 is connected to the negative terminal 22 of the semiconductor module 20a and the positive terminal 21 of the semiconductor module 20b. Further, the intermediate flat conductor 50 is connected to the negative side terminals 22 of the semiconductor modules 20a and the positive side terminals 21 of the semiconductor modules 20b in nine parallels. Further, the intermediate flat conductor 50 is made of, for example, a copper bar. The intermediate flat conductor 50 is arranged on the surface of the positive flat conductor 40 on the opposite side (Z1 direction side) from the surface 31a on which the semiconductor module 20a, the semiconductor module 20b, and the semiconductor module 20c are arranged. There is. Moreover, the intermediate flat conductor 50 is arranged so as to span the negative side terminals 22 of the semiconductor modules 20a and the positive side terminals 21 of the semiconductor modules 20b, which are plural (nine parallel).

Further, an insulating paper 60a is provided between the positive flat conductor 40 and the intermediate flat conductor 50. Thereby, the positive flat conductor 40 and the intermediate flat conductor 50 are insulated by the insulating paper 60a.

Further, in this embodiment, as shown in FIG. 10, the positive flat plate conductor 40 is provided with a hole 41. The intermediate flat conductor 50 connects the negative terminal 22 of the semiconductor module 20a and the positive terminal 21 of the semiconductor module 20b through the hole 41 of the positive flat conductor 40 (and the hole 61a of the insulating paper 60a). It is connected with screws etc. Specifically, a plurality of holes 41 are provided. Moreover, the hole 41 has a substantially rectangular shape. Note that the hole 41 is an example of a "positive side flat conductor hole" in the claims.

Further, as shown in FIG. 10, the power conversion device 100 includes a first connecting flat conductor 70 having a substantially flat plate shape. The first connecting flat conductor 70 is connected to the output terminal 23 of the semiconductor module 20a and the positive terminal 21 of the semiconductor module 20c. Further, the first connecting flat conductor 70 is made of, for example, a copper bar. Further, the first connection flat conductor 70 is arranged so as to extend across a plurality (three parallel) of the output terminal 23 of the semiconductor module 20a and the positive terminal 21 of the semiconductor module 20c. Therefore, three first connection flat conductors 70 are provided.

Further, as shown in FIG. 10, the power conversion device 100 includes a second connecting flat conductor 80 having a substantially flat plate shape. The second connecting flat conductor 80 is connected to the output terminal 23 of the semiconductor module 20b and the negative terminal 22 of the semiconductor module 20c. Further, the second connecting flat conductor 80 is made of, for example, a copper bar. Further, the second connecting flat conductor 80 is arranged so as to extend across a plurality (three parallel) of the output terminal 23 of the semiconductor module 20b and the negative terminal 22 of the semiconductor module 20c. Therefore, three second connecting flat conductors 80 are provided.

Further, as shown in FIG. 10, the power conversion device 100 includes a negative flat plate conductor 90 having a substantially flat plate shape. The negative flat plate conductor 90 is connected to the negative terminal 22 of the semiconductor module 20b. Further, the negative flat plate conductor 90 is made of, for example, a copper bar. Further, the negative flat plate conductor 90 is arranged to extend across the negative terminals 22 of a plurality of (nine parallel) semiconductor modules 20b.

In this embodiment, as shown in FIGS. 7, 8, and 10, the first connecting flat conductor 70, the second connecting flat conductor 80, and the negative flat conductor 90 are connected to the surface 31a of the intermediate flat conductor 50. are arranged adjacent to each other on the opposite surface (Z1 direction side). Specifically, the first connecting flat conductor 70, the second connecting flat conductor 80, and the negative flat conductor 90 are arranged in this order from the X1 direction toward the X2 direction. Furthermore, gaps are provided between the first connecting flat conductor 70 and the second connecting flat conductor 80 and between the second connecting flat conductor 80 and the negative flat conductor 90, respectively. Further, the first connecting flat conductor 70, the second connecting flat conductor 80, and the negative flat conductor 90 are arranged on the same plane so that their height positions are substantially the same.

Further, as shown in FIG. 10, an insulating paper 60b is provided between the first connecting flat conductor 70, the second connecting flat conductor 80, the negative side flat conductor 90, and the intermediate flat conductor 50. Thereby, the first connection flat conductor 70, the second connection flat conductor 80, the negative side flat conductor 90, and the intermediate flat conductor 50 are insulated by the insulating paper 60b. Further, the insulating paper 60b is provided with a hole 61b.

Further, in this embodiment, the positive flat conductor 40 is provided with a hole 41, and the intermediate flat conductor 50 is provided with a hole 51. Then, the first connection flat conductor 70 is connected through the hole 41 of the positive flat conductor 40 and the hole 51 of the intermediate flat conductor 50 (and the hole 61a of the insulating paper 60a and the hole 61b of the insulating paper 60b). , are connected to the output terminal 23 of the semiconductor module 20a and the positive side terminal 21 of the semiconductor module 20c by screws or the like. Further, the second connection flat conductor 80 is connected through the hole 41 of the positive flat conductor 40 and the hole 51 of the intermediate flat conductor 50 (and the hole 61a of the insulating paper 60a and the hole 61b of the insulating paper 60b). , are connected to the output terminal 23 of the semiconductor module 20b and the negative terminal 22 of the semiconductor module 20c by screws or the like. The negative flat conductor 90 is connected to the semiconductor module through the hole 41 of the positive flat conductor 40 and the hole 51 of the intermediate flat conductor 50 (and the hole 61a of the insulating paper 60a and the hole 61b of the insulating paper 60b). It is connected to the negative side terminal 22 of 20b with a screw or the like. Note that the hole 51 is an example of an "intermediate flat conductor hole" in the claims.

Further, as shown in FIG. 7, the capacitor C1 is connected to the positive flat conductor 40 and the intermediate flat conductor 50. Further, the capacitor C2 is connected in series to the capacitor C1, and is also connected to the negative flat conductor 90 and the intermediate flat conductor 50.

In this embodiment, as shown in FIG. 11, the positive flat conductor 40 includes a first positive conductor portion 42 that is substantially horizontal to the surface 31a, and a second positive conductor portion 43 that is substantially perpendicular to the surface 31a. It has a substantially L-shape including. The first positive conductor portion 42 is connected to the positive terminal 21 of the semiconductor module 20a. Further, the second positive conductor portion 43 is connected to the capacitor C1.

Further, in this embodiment, as shown in FIG. 12, the negative flat plate conductor 90 has a first negative conductor portion 92 that is approximately horizontal to the surface 31a, and a second negative conductor portion 93 that is approximately perpendicular to the surface 31a. It has an approximately L-shape that includes. The first negative conductor portion 92 is connected to the negative terminal 22 of the semiconductor module 20b. Further, the second negative conductor portion 93 is connected to the capacitor C2.

Further, in this embodiment, as shown in FIG. 13, the intermediate flat conductor 50 includes a first intermediate conductor portion 52 that is approximately horizontal to the surface 31a, and a second intermediate conductor portion 53 that is approximately perpendicular to the surface 31a. It has an L-shape. The first intermediate conductor portion 52 is connected to the negative terminal 22 of the semiconductor module 20a and the positive terminal 21 of the semiconductor module 20b. The second intermediate conductor portion 53 is connected to capacitor C1 and capacitor C2.

Specifically, as shown in FIG. 10, the second negative conductor portion 93 of the negative flat conductor 90, the second intermediate conductor portion 53 of the intermediate flat conductor 50, and the second positive side The conductor portions 43 are stacked from the X1 direction side toward the X2 direction side. A positive terminal (not shown) of the capacitor C1 is connected to a second positive conductor portion 43 of the positive flat plate conductor 40 by a screw or the like. Further, a negative terminal (not shown) of the capacitor C1 is connected to the second intermediate conductor portion 53 of the intermediate flat conductor 50 by a screw or the like. Further, a positive terminal (not shown) of the capacitor C2 is connected to the second intermediate conductor portion 53 of the intermediate flat conductor 50 by a screw or the like. Further, a negative terminal (not shown) of the capacitor C2 is connected to a second negative conductor portion 93 of the negative flat plate conductor 90 by a screw or the like.

Also, the hole 41 of the positive flat conductor 40 (see FIG. 11), the hole 91 of the negative flat conductor 90 (see FIG. 12), the hole 51 of the intermediate flat conductor 50 (see FIG. 13), and the first connection flat plate. The hole 71 of the conductor 70 (see FIG. 14) and the hole 81 of the second connecting flat conductor 80 (see FIG. 15) are each provided to ensure an insulation distance.

Moreover, in this embodiment, as shown in FIG. It is arranged so as to overlap the conductor 40 and the intermediate flat conductor 50. Specifically, substantially the entire surface of the first connecting flat conductor 70, substantially the entire surface of the second connecting flat conductor 80, and approximately the entire surface of the first negative conductor portion 92 of the negative flat conductor 90 are perpendicular to the surface 31a. When viewed from the direction, the first positive conductor portion 42 of the positive flat conductor 40 and the first intermediate conductor portion 52 of the intermediate flat conductor 50 overlap.

[Effects of this embodiment]
In this embodiment, the following effects can be obtained.

In this embodiment, as described above, the breakdown voltage of the semiconductor module 20c is configured to be higher than the breakdown voltages of the semiconductor module 20a and the semiconductor module 20b. Here, after switching the switching element Q3 (Q2) from on to off, the loop path (closed circuit) including the switching element Q3 (Q2) includes the switching element Q1 ( Q4) is arranged, and a path connecting switching element Q3 (Q2) and switching element Q1 (Q4) is included. That is, the number of elements included in one round path is relatively large, and the length of one round path is relatively long. Therefore, the inductance of the one-turn path after switching the switching element Q3 (Q2) becomes larger than the inductance of the one-turn path including the switching element Q1 or the switching element Q4. As a result, the surge voltage generated when switching the switching element Q3 (Q2) is larger than the surge voltage generated when switching the switching element Q1 or the switching element Q4 from on to off. Therefore, by configuring as described above, unlike the case where the breakdown voltages of all the semiconductor modules 20a to 20c are made relatively large, it is possible to suppress excessive performance of the power conversion device 100.

Furthermore, in this embodiment, as described above, the breakdown voltage of the semiconductor module 20c is higher than the surge voltage when the switching element Q3 (Q2) is switched from on to off. Thereby, it is possible to prevent the switching element Q3 (Q2) from being destroyed by a surge generated due to switching of the switching element Q3 (Q2).

Further, in this embodiment, as described above, the withstand voltage of the semiconductor module 20c is determined by the inductance of the circuit path related to the surge including the switching element Q3 (Q2) when the switching element Q3 (Q2) is switched from on to off. Accordingly, the breakdown voltage is selected to be higher than the breakdown voltage of the semiconductor module 20a and the breakdown voltage of the semiconductor module 20b. Thereby, the breakdown voltage of the switching element Q3 (Q2) is selected according to the inductance of the one-round path, so it is possible to prevent the semiconductor module 20c having an excessively large breakdown voltage with respect to the inductance from being selected. As a result, it is possible to suppress the power conversion device 100 from increasing in size due to the selection of the semiconductor module 20c having an excessively high breakdown voltage (that is, the large semiconductor module 20c).

Further, in this embodiment, as described above, the positive side terminal 21 and the negative side terminal 22 of the semiconductor module 20a are The output terminal 23, the positive side terminal 21, the negative side terminal 22 and the output terminal 23 of the semiconductor module 20c, and the output terminal 23, the negative side terminal 22 and the positive side terminal 21 of the semiconductor module 20b are arranged in this order on the straight line L1. Semiconductor module 20a, semiconductor module 20b, and semiconductor module 20c are arranged on surface 31a so as to be arranged along. As a result, the distance between the output terminal 23 of the semiconductor module 20a and the positive side terminal 21 of the semiconductor module 20c becomes relatively small, so that the length of the conductor connecting these terminals can be suppressed from increasing. I can do it. Furthermore, since the distance between the negative terminal 22 of the semiconductor module 20c and the output terminal 23 of the semiconductor module 20b becomes relatively small, it is possible to prevent the length of the conductor connecting these terminals from increasing. can. That is, it is possible to suppress an increase in inductance due to an increase in the length of the conductor.

Further, in the present embodiment, as described above, the positive flat conductor 40 is arranged on the surface of the positive terminal 21 of the semiconductor module 20a, and the intermediate flat conductor 50 is a semiconductor of the positive flat conductor 40. It is arranged on the surface opposite to the surface 31a on which the module 20a, semiconductor module 20b, and semiconductor module 20c are arranged. As a result, the positive flat conductor 40 and the intermediate flat conductor 50 are stacked so as to face each other, so that the magnetic flux generated due to the current flowing through the positive flat conductor 40 and the magnetic flux generated due to the current flowing through the intermediate flat conductor 50 are It is possible to cancel out the magnetic flux generated by the magnetic flux. As a result, an increase in inductance due to the magnetic flux of the flowing current can be suppressed.

Further, in this embodiment, as described above, the intermediate flat conductor 50 connects the negative terminal 22 of the semiconductor module 20a and the positive terminal 21 of the semiconductor module 20b through the hole 41 of the positive flat conductor 40. It is connected to the. As a result, even when the intermediate flat conductor 50 is stacked on the positive flat conductor 40, the intermediate flat conductor 50 and the negative terminal 22 of the semiconductor module 20a can be easily connected to each other through the hole 41 of the positive flat conductor 40. It can be connected to the positive terminal 21 of the semiconductor module 20b.

Furthermore, in this embodiment, as described above, the first connecting flat conductor 70, the second connecting flat conductor 80, and the negative flat conductor 90 are placed on the surface of the intermediate flat conductor 50 opposite to the surface 31a. are placed next to each other. As a result, the first connecting flat conductor 70, the second connecting flat conductor 80, the negative side flat conductor 90, and the intermediate flat conductor 50 are stacked so as to face each other. The magnetic flux generated due to the current flowing through each of the connecting flat conductor 80 and the negative side flat conductor 90 and the magnetic flux generated due to the current flowing through the intermediate flat conductor 50 can be canceled out. As a result, an increase in inductance due to the magnetic flux of the flowing current can be suppressed.

Furthermore, in this embodiment, as described above, the first connection flat conductor 70 connects to the output terminal 23 of the semiconductor module 20a through the hole 41 of the positive flat conductor 40 and the hole 51 of the intermediate flat conductor 50. , and the positive side terminal 21 of the semiconductor module 20c. Further, the second connection flat conductor 80 connects to the output terminal 23 of the semiconductor module 20b and the negative terminal 22 of the semiconductor module 20c through the hole 41 of the positive flat conductor 40 and the hole 51 of the intermediate flat conductor 50. It is connected to the. Further, the negative flat conductor 90 is connected to the negative terminal 22 of the semiconductor module 20b via the hole 41 of the positive flat conductor 40 and the hole 51 of the intermediate flat conductor 50. As a result, even when the first connecting flat conductor 70, the second connecting flat conductor 80, and the negative flat conductor 90 are stacked on the positive flat conductor 40 and the intermediate flat conductor 50, they can be connected through the holes 41 and 51. Therefore, each conductor and each terminal can be easily connected.

Further, in this embodiment, as described above, the positive flat conductor 40 is connected to the first positive conductor portion 42 that is connected to the positive terminal 21 of the semiconductor module 20a and is substantially horizontal to the surface 31a, and to the capacitor C1. It has a substantially L-shape including a second positive conductor portion 43 substantially perpendicular to the surface 31a. Further, the negative flat plate conductor 90 includes a first negative conductor portion 92 connected to the negative terminal 22 of the semiconductor module 20b and substantially horizontal to the surface 31a, and a second negative conductor portion 92 connected to the capacitor C2 and substantially perpendicular to the surface 31a. It has a substantially L-shape including a conductor portion 93. Further, the intermediate flat conductor 50 is connected to a first intermediate conductor portion 52 that is connected to the negative terminal 22 of the semiconductor module 20a and the positive terminal 21 of the semiconductor module 20b and is substantially horizontal to the surface 31a, and is connected to the capacitor C1 and the capacitor C2. It has a substantially L-shape including a second intermediate conductor portion 53 substantially perpendicular to the surface 31a. As a result, the positive flat conductor 40, the negative flat conductor 90, and the intermediate flat conductor 50 are laminated, and while canceling magnetic flux with each other (that is, reducing inductance), the positive flat conductor 40 and the intermediate flat conductor 50 are laminated. The conductor 50 and the capacitor C1 can be connected, and the negative side flat conductor 90 and the intermediate flat conductor 50 can be connected to the capacitor C2.

Further, in this embodiment, as described above, the first connecting flat conductor 70, the second connecting flat conductor 80, and the negative flat conductor 90 are connected to the positive flat conductor 40 when viewed from the direction perpendicular to the surface 31a. and is arranged so as to overlap the intermediate flat conductor 50. As a result, the first connection flat conductor 70, the second connection flat conductor 80, and the negative side flat conductor 90 are arranged so as to overlap the positive side flat conductor 40 and the intermediate flat conductor 50. , the magnetic flux generated due to the current flowing through each conductor can cancel each other out.

[Modified example]
Note that the embodiments disclosed this time should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is indicated by the claims rather than the description of the embodiments described above, and further includes all changes (modifications) within the meaning and range equivalent to the claims.

For example, in the above embodiment, an example was shown in which the semiconductor modules 20a, the semiconductor modules 20b, and the semiconductor modules 20c are each provided in nine parallels, but the present invention is not limited to this. For example, the above semiconductor modules may be arranged in several numbers other than nine in parallel.

Further, in the above embodiment, an example was shown in which the power conversion device is used as a PCS, but the present invention is not limited to this. For example, it is possible to apply the present invention to power conversion devices other than PCS.

Further, in the above embodiment, an example has been shown in which the switching element is an IGBT made of a silicon semiconductor, and the diode is made of a silicon semiconductor, but the present invention is not limited to this. For example, at least one of the switching element and the diode may be made of a wide bandgap semiconductor. Further, the switching element may be composed of a MOSFET.

Further, in the above embodiment, an example was shown in which the breakdown voltage of the switching elements Q2 and Q3 is about 1700V, and the breakdown voltage of the switching elements Q1 and Q4 is about 1200V, but the present invention is not limited to this. For example, as long as the breakdown voltages of switching elements Q2 and Q3 are higher than the breakdown voltages of switching elements Q1 and Q4, the breakdown voltages of the switching elements are not limited to the above breakdown voltages.

Further, in the above embodiment, the positive flat conductor, the intermediate flat conductor, and the first connecting flat conductor (second connecting flat conductor, negative flat conductor) are laminated in this order from the Z2 direction side to the Z1 direction side. Although the present invention is not limited to this example. For example, the stacking order of the conductors described above may be different.

20a Semiconductor module (upper potential semiconductor module)
20b semiconductor module (lower potential semiconductor module)
20c semiconductor module (intermediate semiconductor module)
31a Surface (placement surface)
40 Positive flat conductor 41 Hole (positive flat conductor hole)
42 First positive conductor portion 43 Second positive conductor portion 50 Intermediate flat conductor 51 Hole (intermediate flat conductor hole)
52 First intermediate conductor portion 53 Second intermediate conductor portion 70 First connecting flat conductor 80 Second connecting flat conductor 90 Negative flat conductor 92 First negative conductor portion 93 Second negative conductor portion 100 Power converter C1 Capacitor ( 1st capacitor)
C2 capacitor (second capacitor)
D1 diode (semiconductor element)
D2 diode (semiconductor element)
Q1 Switching element (upper potential switching element, semiconductor element)
Q2, Q3 switching element (intermediate switching element)
Q4 Switching element (lower potential switching element, semiconductor element)

Claims (11)

A power conversion device that outputs power at three levels of potential: an upper potential, an intermediate potential, and a lower potential,
an upper potential semiconductor module connected to the upper potential and the intermediate potential and housing therein a plurality of semiconductor elements including at least one upper potential switching element;
a lower potential semiconductor module that is connected to the intermediate potential and the lower potential and houses the plurality of semiconductor elements including at least one lower potential switching element;
an intermediate semiconductor module connected to the upper potential semiconductor module and the lower potential semiconductor module and housing a plurality of intermediate switching elements therein;
The breakdown voltage of the intermediate semiconductor module is configured to be higher than the breakdown voltage of the upper potential semiconductor module and the breakdown voltage of the lower potential semiconductor module ,
Each of the upper potential semiconductor module, the lower potential semiconductor module, and the intermediate semiconductor module includes a positive side terminal, a negative side terminal, and an output terminal, and the upper potential semiconductor module, the lower potential semiconductor module, and the intermediate semiconductor module The lower potential semiconductor module and the intermediate semiconductor module are arranged such that the output terminal of the intermediate semiconductor module and the output terminal of the lower semiconductor module are adjacent to each other when viewed from a vertical direction on the arrangement surface in which they are arranged. Alternatively, the upper potential semiconductor module and the intermediate semiconductor module are arranged such that a positive side terminal of the intermediate semiconductor module and an output terminal of the upper semiconductor module are adjacent to each other. Each of the upper potential semiconductor module, the lower potential semiconductor module, and the intermediate semiconductor module is viewed from a direction perpendicular to an arrangement plane on which the upper potential semiconductor module, the lower potential semiconductor module, and the intermediate semiconductor module are arranged, The lower potential semiconductor module and the intermediate semiconductor module are arranged in a straight line so that the output terminal of the intermediate semiconductor module and the output terminal of the lower semiconductor module are adjacent to each other, or The power conversion device according to claim 1, wherein the upper potential semiconductor module and the intermediate semiconductor module are arranged in a straight line so that a positive side terminal and an output terminal of the upper semiconductor module are adjacent to each other. The power conversion device according to claim 2 , wherein the withstand voltage of the intermediate semiconductor module is higher than a surge voltage when the intermediate switching element is switched from on to off. The breakdown voltage of the intermediate semiconductor module is determined by the breakdown voltage of the upper potential semiconductor module and the lower voltage depending on the inductance of a circuit related to a surge including the intermediate switching element when the intermediate switching element is switched from on to off. 4. The power conversion device according to claim 3 , wherein the potential is selected to be higher than the withstand voltage of the semiconductor module. The upper potential semiconductor module, the lower potential semiconductor module, and the intermediate semiconductor module are viewed from a direction perpendicular to the arrangement plane on which the upper potential semiconductor module, the lower potential semiconductor module, and the intermediate semiconductor module are arranged. , the positive terminal, the negative terminal and the output terminal of the upper potential semiconductor module, the positive terminal, the negative terminal and the output terminal of the intermediate semiconductor module, and the output of the lower potential semiconductor module. The upper potential semiconductor module, the lower potential semiconductor module, and the intermediate semiconductor module are arranged on the arrangement surface such that the terminal, the negative terminal, and the positive terminal are arranged in this order along a straight line. The power conversion device according to any one of claims 1 to 4 . a substantially flat positive flat plate conductor connected to the positive terminal of the upper potential semiconductor module;
further comprising a substantially flat intermediate plate conductor connected to the negative terminal of the upper potential semiconductor module and the positive terminal of the lower potential semiconductor module,
The positive flat plate conductor is arranged on the surface of the positive terminal of the upper potential semiconductor module,
The power conversion device according to claim 5 , wherein the intermediate flat conductor is arranged on a surface of the positive flat conductor opposite to the arrangement surface. The positive flat conductor is provided with a positive flat conductor hole,
The intermediate flat conductor is connected to the negative terminal of the upper potential semiconductor module and the positive terminal of the lower potential semiconductor module through the positive flat conductor hole of the positive flat conductor. The power conversion device according to claim 6 . a substantially flat first connecting flat conductor connected to the output terminal of the upper potential semiconductor module and the positive terminal of the intermediate semiconductor module;
a substantially flat second connection flat conductor connected to the output terminal of the lower potential semiconductor module and the negative terminal of the intermediate semiconductor module;
further comprising a substantially flat negative flat plate conductor connected to the negative terminal of the lower potential semiconductor module,
The first connecting flat conductor, the second connecting flat conductor, and the negative flat conductor are arranged adjacent to each other on a surface of the intermediate flat conductor opposite to the arrangement surface. 8. The power conversion device according to 6 or 7 . The positive flat conductor is provided with a positive flat conductor hole, and the intermediate flat conductor is provided with an intermediate flat conductor hole,
The first connecting flat conductor is connected to the output terminal of the upper potential semiconductor module and the positive terminal of the intermediate semiconductor module via the positive flat conductor hole and the intermediate flat conductor hole. ,
The second connecting flat conductor is connected to the output terminal of the lower potential semiconductor module and the negative terminal of the intermediate semiconductor module via the positive flat conductor hole and the intermediate flat conductor hole. ,
The power conversion device according to claim 8 , wherein the negative flat conductor is connected to the negative terminal of the lower potential semiconductor module via the positive flat conductor hole and the intermediate flat conductor hole. . a first capacitor connected to the positive flat conductor and the intermediate flat conductor; and a second capacitor connected in series to the first capacitor and to the negative flat conductor and the intermediate flat conductor. further comprising:
The positive flat plate conductor includes a first positive conductor portion connected to the positive terminal of the upper potential semiconductor module and substantially horizontal to the arrangement surface, and a first positive conductor portion connected to the first capacitor and substantially perpendicular to the arrangement surface. It has a substantially L-shape including two positive side conductor portions,
The negative flat plate conductor includes a first negative conductor portion connected to the negative terminal of the lower potential semiconductor module and substantially horizontal to the arrangement surface, and a first negative conductor portion connected to the second capacitor and substantially perpendicular to the arrangement surface. It has a substantially L-shape including two negative side conductor portions,
The intermediate flat conductor includes a first intermediate conductor portion that is connected to the negative terminal of the upper potential semiconductor module and the positive terminal of the lower potential semiconductor module and is substantially horizontal to the arrangement surface, the first capacitor, and The power conversion device according to claim 8 or 9 , having a substantially L-shape including a second intermediate conductor portion connected to the second capacitor and substantially perpendicular to the arrangement surface. The first connecting flat conductor, the second connecting flat conductor, and the negative flat plate conductor overlap the positive flat conductor and the intermediate flat conductor when viewed from a direction perpendicular to the arrangement surface. The power conversion device according to any one of claims 8 to 10 , wherein the power conversion device is arranged.

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