JP4836466B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device used as an IC chip (hereinafter also referred to as “ID chip”) capable of storing necessary information in a memory circuit or reading information by non-contact means such as wireless communication. In particular, the present invention relates to a semiconductor device used as an ID chip formed on an insulating substrate such as glass or plastic.

  Due to the development of computer technology and the improvement of image recognition technology, information recognition using a medium such as a barcode has become widespread and used for product data recognition and the like. In the future, it is expected that more information will be recognized. On the other hand, there is a drawback that the barcode reader needs to be in contact with the barcode and the amount of information recorded on the barcode cannot be increased so much in the case of reading information by barcode. An increase in storage capacity is desired.

  Due to such demands, ID chips using ICs have been developed in recent years. The ID chip stores necessary information in a memory circuit in the IC chip, and reads internal information using non-contact means, generally wireless means. The practical use of such an ID chip is expected to simplify product distribution, reduce costs, and ensure high security.

  An outline of an individual authentication system using an ID chip will be described with reference to FIG. FIG. 4 is a diagram showing an outline of a solid authentication system for the purpose of obtaining the individual information of the bag without contact. An ID chip 401 that stores specific solid information is attached to or embedded in a bag 404. An electromagnetic wave is transmitted to the ID chip 401 from an antenna unit 402 of an interrogator (also referred to as a lead dryer) 403. When receiving the electromagnetic wave, the ID chip 401 sends back individual information held by the ID chip to the antenna unit 402. The antenna unit 402 sends the returned individual information to the interrogator 403, and the interrogator 403 determines the individual information. In this way, the interrogator 403 can obtain information on the bag 404. Further, by using this system, it is possible to carry out logistics management, aggregation, removal of counterfeit products, and the like.

  An example of such ID chip technology is shown in FIG. The semiconductor device 200 used for the ID chip includes an antenna circuit 201, a rectifier circuit 202, a stabilized power supply circuit 203, an amplifier 208, a demodulation circuit 213, a logic circuit 209, a memory control circuit 212, a memory circuit 211, a logic circuit 207, an amplifier 206, and a modulation. The circuit 205 is configured. The antenna circuit 201 includes an antenna coil 301 and a tuning capacitor 302 (FIG. 3A). The rectifier circuit 202 includes diodes 303 and 304 and a smoothing capacitor 305 (FIG. 3B).

  The operation of such an ID chip will be described below. The AC signal received by the antenna circuit 201 is half-wave rectified by the diodes 303 and 304 and smoothed by the smoothing capacitor 305. Since the smoothed voltage includes a large number of ripples, it is stabilized by the stabilized power supply circuit 203, and the stabilized voltage is converted into the demodulating circuit 213, the amplifier 206, the logic circuit 207, the amplifier 208, and the logic circuit 209. , And supplied to the memory circuit 211 and the memory control circuit 212. On the other hand, a signal received by the antenna circuit 201 is input to the logic circuit 209 through the amplifier 208 as a clock signal. The signal input from the antenna is demodulated by the demodulation circuit 213 and input to the logic circuit 209 as data.

  In the logic circuit 209, the input data is decoded. Since the interrogator encodes the data with a modified mirror code, an NRZ-L code, or the like and transmits it, the logic circuit 209 decodes it. The decoded data is sent to the memory control circuit 212, and the stored data stored in the memory circuit 211 is read out accordingly. The memory circuit 211 needs to be a nonvolatile memory circuit that can be retained even when the power is turned off, and a mask ROM or the like is used. The stored content is, for example, 16-byte data (see FIG. 12A), and the family code is 4 bytes indicating the ID chip series, the application code is 4 bytes, and the user code is 4 bytes set by the user. It has become.

Signals to be transmitted and received include 125 kHz, 13.56 MHz, 915 MHz, 2.45 GHz, and the like, and ISO standards are set for each. Also, modulation / demodulation schemes for transmission and reception are standardized. An example of such an ID chip is, for example, Patent Document 1.
JP 2001-250393 A

The conventional ID chip semiconductor device described above has the following problems. When a mask ROM is used for the memory circuit, writing cannot be performed except during chip manufacture. Accordingly, there is a need for an ID chip capable of writing data other than during chip manufacture.
When an EEPROM is used for the memory circuit, the user can freely rewrite the contents, but it is possible for a person other than the original user to rewrite information that should not be rewritten for authentication, and forgery can also be performed. It is. Therefore, an ID chip that can be written only once is required to prevent such forgery.

  Accordingly, an object of the present invention is to provide a semiconductor device used as an ID chip that can be rewritten only once in a semiconductor device used for an ID chip. It is another object of the present invention to provide a semiconductor device used as an ID chip capable of writing data other than during chip manufacture.

  The present invention includes a modulation circuit, a demodulation circuit, a logic circuit, and a memory circuit on an insulating substrate, an antenna circuit is electrically connected to the modulation circuit and the demodulation circuit, and the logic circuit is connected to the demodulation circuit Are connected, the memory circuit stores an output signal of the logic circuit, and the memory circuit is a fuse memory circuit using a fuse element.

  In the semiconductor device, the fuse memory circuit includes a control circuit capable of writing only once.

  Further, the present invention includes a modulation circuit, a demodulation circuit, a logic circuit, and a memory circuit over an insulating substrate, and an antenna circuit is electrically connected to the modulation circuit and the demodulation circuit, and the demodulation circuit has a logic The circuit is connected, the memory circuit stores the output signal of the logic circuit, the memory circuit is a fuse memory circuit using a fuse element, and the logic circuit determines whether or not the memory circuit can be written by the data stored in the memory circuit. It is characterized by controlling.

  In the semiconductor device, the fuse element constituting the fuse memory circuit performs a memory operation by fusing a metal wiring.

  In the semiconductor device, the fuse element constituting the fuse memory circuit performs a storage operation by fusing the semiconductor thin film.

  In the semiconductor device, the fuse element constituting the fuse memory circuit performs a memory operation by short-circuiting an insulating film.

  In the semiconductor device, a power source for the memory operation of the fuse memory circuit is obtained by rectifying and boosting a signal output from the antenna circuit.

  In the semiconductor device, the power source when the fuse memory circuit performs the storage operation is obtained from an external high-voltage power source.

In the semiconductor device, at least one of the modulation circuit, the demodulation circuit, the logic circuit, and the memory circuit includes a thin film transistor (hereinafter also referred to as a “TFT (Thin Film Transistor)”). It is characterized by.

In the semiconductor device, the antenna circuit, the modulation circuit, the demodulation circuit, the logic circuit, and the memory circuit are each formed over the same insulating substrate, or the modulation circuit, the demodulation circuit, and the logic circuit The circuit and the memory circuit are each integrally formed on the same insulating substrate, and the antenna circuit is formed on another insulating substrate.

In the semiconductor device, the insulating substrate is one selected from glass, plastic, and a film-like insulator.

In the semiconductor device, the antenna circuit is formed above at least one of the pre-modulation circuit, the demodulation circuit, the logic circuit, and the memory circuit.

In the semiconductor device, a signal entering the antenna circuit is a radio signal.

  In the present invention, an ID chip is a semiconductor chip used for individual recognition, and is used for an IC tag, a wireless tag, an RFID, an IC card, a transponder, and the like.

  As described above, by using the present invention, information can be written only once into the memory circuit in the ID chip. In this way, data forgery of the ID chip can be prevented, and a semiconductor device used as an ID chip that ensures security can be configured. Further, it is possible to provide a semiconductor device used as an ID chip capable of writing data other than during chip manufacture.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in the drawings described below, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

  The semiconductor device 100 used for the ID chip includes an antenna circuit 101, a rectifier circuit 102, a stable power supply circuit 103, a boost power supply circuit 104, a modulation circuit 105, an amplifier 106, a logic circuit 107, an amplifier 108, a logic circuit 109, a level shift circuit 110, and a fuse. The memory circuit 111, the fuse memory control circuit 112, and the demodulation circuit 113 are configured (see FIG. 1). The antenna circuit 101 is the same as the conventional example shown in FIG. The rectifier circuit 102 is the same as the conventional example shown in FIG. In this embodiment mode, the antenna circuit 101 is formed over the semiconductor device 100, but the present invention is not limited to this, and the antenna circuit 101 may be connected to the outside of the semiconductor device 100.

  The operation of such an ID chip will be described below. The AC signal received by the antenna circuit 101 is rectified and smoothed by the rectifier circuit 102. Since the smoothed voltage includes a large number of ripples, the smoothed voltage is stabilized by the stable power supply circuit 103, and the stabilized voltage is converted into the boosted power supply circuit 104, the amplifier 106, the logic circuit 107, the amplifier 108, and the logic circuit 109. To supply.

  When writing to the fuse memory circuit 111, the boost power supply circuit 104 boosts the output voltage of the stable power supply circuit 103, and writing is performed to the fuse memory circuit 111 using the boosted voltage. The boosting power supply circuit 104 is a charge pump circuit or the like, but is not limited to a charge pump circuit. A clock signal for driving the boosting power supply circuit 104 may be generated using an AC signal input from the antenna circuit 101, or may be generated by providing an oscillation circuit in the semiconductor device 100.

  A signal input from the antenna circuit 101 is logically calculated by the logic circuit 109 and then input to the level shift circuit 110. The level shift circuit 110 operates with a voltage boosted by the boost power supply circuit 104 and amplifies the signal amplitude of the logic circuit 109. In addition, the logic circuit 109 designates the presence / absence of writing, an address, and the like to the fuse memory control circuit 112. The fuse memory circuit 111 writes data according to instructions from the fuse memory control circuit 112 and the level shift circuit 110.

  When the interrogator calls the data stored in the fuse memory circuit 111, the operation is as follows. The AC signal received by the antenna circuit 101 is rectified and smoothed by the rectifier circuit 102. Since the smoothed voltage includes a large number of ripples, the smoothed voltage is stabilized by the stable power supply circuit 103, and the stabilized voltage is converted into the boosted power supply circuit 104, the amplifier 106, the logic circuit 107, the amplifier 108, and the logic circuit 109. To supply. On the other hand, the AC signal received by the antenna circuit 101 is input to the logic circuit 109 through the amplifier 108, and a logic operation is performed. Then, the fuse memory control circuit 112 is controlled using the signal of the logic circuit 109 to call up the data stored in the fuse memory circuit 111. Next, the data stored in the fuse memory circuit 111 is processed by the logic circuit 107, and the modulation circuit 105 is operated by the output. The data is processed according to a method defined in standards such as ISO 14443, ISO 15693, ISO 18000, etc., but other standards may be used as long as consistency with the interrogator is ensured.

  When the modulation circuit 105 operates, the impedance of the antenna circuit 101 changes. This causes a change in the interrogator signal reflected by the antenna circuit 101. By reading this change, the interrogator can know the data stored in the fuse memory circuit 111 of the semiconductor device 100. Such a modulation method is called a load modulation method.

Hereinafter, the operation of the fuse memory circuit will be described with reference to FIG. The fuse memory circuit shown in FIG. 5 is a 6-bit memory circuit for simplification of description, but is not limited to 6 bits.
The fuse memory circuit includes a column decoder 501, a row decoder 502, a boost power supply circuit 503, an amplifier 504, N-type transistors 505 to 510, fuse elements 511 to 516, bit lines 517 to 519, word lines 520 and 521, column switches 522 to 524. , Switches 525 and 526, output wiring 527, memory load resistor 528, output terminal 529, power source 1 and power source 2 (FIG. 5). The power source 1 is for setting a high potential, and the power source 2 is for setting a low potential. However, when the transistors 505 to 510 are P-type transistors, the power source 1 sets a low potential and the power source 2 sets a high potential. In the following description, the transistors 505 to 510 are N-type.
Further, the memory cell 500 including the transistor 505 and the fuse element 511 will be described as a representative.

First, the case of performing initial reading will be described. Since the fuse elements 511 to 516 function as electric wirings in the initial state, the transistors 505 and 508 are connected to the bit line 517, the transistors 506 and 509 are connected to the bit line 518, and the transistors 507 and 510 are connected to the bit line 519. ing.
Here, for example, when reading data from the memory cell 500, the row decoder 502 is operated to activate the word line 520, whereby the transistors 505 to 507 are turned on. Next, the column decoder 501 is operated to turn on the column switch 522, whereby the bit line 517 and the output wiring 527 are connected. Further, the switch 526 is turned on to connect the output wiring 527, the memory load resistor 528, and the amplifier 504. At this time, the switch 525 is turned off.

  When the transistor 505 is turned on, current flows from the power source 1 to the memory load resistor 528, the switch 526, the output wiring 527, the column switch 522, the bit line 517, the fuse element 511, the transistor 505, and the power source 2. At this time, if a potential drop occurs in the memory load resistor 528 and the on-resistance of the transistor 505 is sufficiently smaller than the resistance value of the memory load resistor 528, the input potential of the amplifier 504 becomes low. Since the memory cells are all the same in the initial stage, the output is low regardless of which transistor is turned on.

Next, consider a case where the output of the memory cell 500 is set to high.
Here, for example, when reading data from the memory cell 500, the row decoder 502 is operated to activate the word line 520, whereby the transistors 505 to 507 are turned on. Next, the column decoder 501 is operated to turn on the switch 522, whereby the bit line 517 and the output wiring 527 are connected. Further, the switch 526 is turned on to connect the output wiring 527, the memory load resistor 528, and the amplifier 504. At this time, the switch 525 is turned off.
In order for the output of the memory cell 500 to be high even when the transistor 505 is turned on, the fuse element 511 needs to be cut and opened. At this time, the current flowing through the memory load resistor 528 does not exist except for a minute leak current, the input voltage of the amplifier 504 becomes the same as the potential of the power supply 1, and a high is output to the output terminal 529. At this time, the switch 525 is assumed to be off.

Next, a case where writing is performed so that high is output to the memory cell 500 is considered. First, the row decoder 502 is operated to activate the word line 520, whereby the transistors 505 to 507 are turned on. Next, the column decoder 501 is operated to turn on the switch 522, whereby the bit line 517 and the output wiring 527 are connected. At this time, the switch 525 is turned on and the switch 526 is turned off. When the switch 525 is turned on, the output wiring 527 is connected to the boost power supply circuit 503, and a high voltage is applied. Since the fuse element 511 is connected to the output wiring 527 via the column switch 522 and the transistor 505 is on, a high voltage is applied to both ends of the fuse element 511, and the fuse element 511 is blown by the flowing current. .
In this way, a non-volatile memory circuit can be realized by fusing the fuse element of the memory cell that performs high writing.

  Next, an embodiment in which writing is performed only once will be described. In this embodiment mode, as shown in FIG. 12B, a bit indicating the write state is added after the memory area (16 bytes in FIG. 12B) that is originally required by the memory circuit. Data indicating whether or not writing has been performed in this portion is stored.

  Next, the operation will be described with reference to FIG. FIG. 13 shows an internal block of the logic circuit 109. The logic circuit 109 includes a decode circuit 1301, a delay circuit 1302, a switch 1303, and a volatile memory circuit 1304. At the initial time, the write storage bit shown in FIG. 12B shows a state in which no write is performed. Here, it is assumed that a row is stored. (For the sake of explanation, low memory is used, but high memory may be used). When a signal is input from the antenna circuit 101 and the stabilized power supply is started, the fuse memory circuit 111 outputs this value to the volatile memory circuit 1304 in the logic circuit 109. The volatile memory circuit 1304 stores this value. The volatile memory circuit 1304 may have any circuit configuration as long as it can store DRAM, SRAM, registers, and the like.

  On the other hand, the signal input from the demodulation circuit 113 is decoded by the decoding circuit 1301, and then input to the switch 1303 through the delay circuit 1302. The switch 1303 is controlled by the volatile memory circuit 1304, and operates to turn on the switch 1303 if the data in the volatile memory circuit 1304 is low as described above. When the switch 1303 is on, the signal is output to the level shift circuit 110, and writing is performed in the fuse memory circuit 111 via the level shift circuit 110. When writing is completed, high is stored in the write storage bit shown in FIG. 12B (low is stored when the initial value is high). The delay circuit 1302 is for preventing data from passing through the switch 1303 and being output to the level shift circuit 110 before the stabilized power supply rises and the state of the switch 1303 is determined. May be used to prevent malfunction before the switch is determined.

  When high is stored in the write storage bit illustrated in FIG. 12B, the volatile memory circuit 1304 operates to turn off the switch 1303. In this way, since the first and subsequent data cannot pass through the switch 1303, writing to the memory circuit is limited to one time.

  Next, a one-time writing embodiment different from FIG. 13 will be described with reference to FIG. FIG. 14 shows an internal block of the logic circuit 109. The logic circuit 109 includes a decode circuit 1401, a delay circuit 1402, a switch 1403, and a fuse memory circuit 1404. The write storage bit shown in FIG. 12B is stored in the fuse memory circuit 1404, and in the initial state, the write is not performed. Here, it is assumed that a row is stored. (For the sake of explanation, low memory is used, but high memory may be used). When a signal is input from the antenna circuit and the stabilized power supply rises, the data is sent to the level shift circuit via the decode circuit 1401, the delay circuit 1402, and the switch 1403. After level shifting by the level shift circuit, data representing writing is sent to the fuse memory circuit 1404 and stored therein.

  On the other hand, the signal input from the demodulation circuit 113 is decoded by the decoding circuit 1401, and input to the switch 1403 through the delay circuit 1402. The switch 1403 is controlled by the fuse memory circuit 1404. When the data in the fuse memory circuit 1404 is low as described above, the switch 1403 operates to turn on the switch 1403. When the switch 1403 is on, a signal is output to the level shift circuit, and writing is performed to the fuse memory circuit 1404 via the level shift circuit. When writing is completed, high is stored in the write storage bit (fuse memory circuit 1404) shown in FIG. 12B (if the initial value is high, low is stored). The delay circuit 1402 is for preventing data from passing through the switch 1403 and being output to the level shift circuit before the stabilized power supply is turned on and the state of the switch 1403 is determined. It may be used to prevent malfunction before the switch is determined.

  When high is stored in the write storage bit shown in FIG. 12B, the fuse memory circuit 1404 operates to turn off the switch 1403. In this way, since the first and subsequent data cannot pass through the switch 1403, writing to the memory circuit is limited to one time.

  An example of the fuse element will be described with reference to FIG. The fuse element shown in FIG. 6A melts the metal wiring in the same manner as a general electric fuse. As the wiring material, a gate electrode material, a source electrode, or a drain electrode material constituting a thin film transistor (hereinafter referred to as TFT) can be used. The wiring width should be as narrow as possible so that fusing is possible with little heat generation, and is desirably 1 μm or less.

  Next, a case where an island region of a TFT is used as a fuse element will be described with reference to FIG. In the fuse element shown in FIG. 6B, since a large amount of current flows, it is desirable to add a large amount of N-type or P-type impurities and to keep the resistance value low. The wiring width should be as narrow as possible so that fusing is possible with little heat generation, and is desirably 1 μm or less.

  An embodiment of a fuse memory circuit having a fuse element different from the above is shown in FIG. The fuse element shown in FIG. 7 is a fuse element using a capacitor. The fuse element is a capacitor in an initial state, and is in a DC state in an open state. After writing, both ends are short-circuited. In this method, a high voltage is applied to both electrodes of a fuse element in which electrodes are provided on both sides of the insulating film, and the insulating film is destroyed and short-circuited. Such a fuse element is sometimes called an antifuse element. Here, an element that is initially open and then short-circuited is also called a fuse.

Hereinafter, the operation of the fuse memory circuit will be described with reference to FIG. The fuse memory circuit of FIG. 7 is a 6-bit memory circuit for simplicity of explanation, but is not limited to 6 bits. The fuse memory circuit includes a column decoder 701, a row decoder 702, a boost power supply circuit 703, an amplifier 704, N-type transistors 705 to 710, fuse elements 711 to 716, bit lines 717 to 719, word lines 720 and 721, and column switches 722 to 724. , Switches 725 and 726, output wiring 727, load resistor 728, output terminal 729, power source 1 and power source 2 (see FIG. 7). The power source 1 is a potential for setting a high potential, and the power source 2 is a potential for setting a low potential. However, when the transistors 705 to 710 are P-type transistors, the power source 1 sets a low potential and the power source 2 sets a high potential. In the following description, the transistors 705 to 710 are N-type.
Further, the memory cell 700 including the transistor 705 and the fuse element 711 will be described as a representative.

First, the case of performing initial reading will be described. Since the fuse elements 711 to 716 function as capacitive elements in the initial state, the transistors 705 and 708 and the bit line 717 are not connected in a direct current, and the transistors 706 and 709 and the bit line 718 are not connected in a direct current. The transistors 707 and 710 and the bit line 719 are not connected in a direct current manner.
Here, for example, when reading data from the memory cell 700, the row decoder 702 is operated to activate the word line 720, whereby the transistors 705 to 707 are turned on. Next, the column decoder 701 is operated to turn on the column switch 722, whereby the bit line 717 and the output wiring 727 are connected. Further, the switch 726 is turned on to connect the output wiring 727, the load resistor 728, and the amplifier 704. At this time, the switch 725 is turned off.

  Even when the transistor 705 is turned on, no current flows through the transistor 705 because the transistor 705 and the bit line 717 are not DC-connected. Therefore, no current flows through the load resistor 728, and the input potential of the amplifier 704 becomes high. Since the memory cells are all the same in the initial stage, the output becomes high regardless of which transistor is turned on.

Next, consider a case where the output of the memory cell 700 is set to low.
Here, for example, when reading data from the memory cell 700, the row decoder 702 is operated to activate the word line 720, whereby the transistors 705 to 707 are turned on. Next, the column decoder 701 is operated to turn on the column switch 722, whereby the bit line 717 and the output wiring 727 are connected. Further, the switch 726 is turned on to connect the output wiring 727, the load resistor 728, and the amplifier 704. At this time, the switch 725 is turned off.
In order for the output of the memory cell 700 to become low even when the transistor 705 is turned on, the fuse element 711 needs to be DC-conductive. If the fuse element 711 is DC-connected, current flows from the power source 1 to the power source 2 via the load resistor 728, switch 726, output wiring 727, column switch 722, bit line 717, fuse element 711, and transistor 705. . Due to the potential drop due to this current, the output of the memory cell 700 becomes low. Accordingly, the input voltage of the amplifier 704 becomes the same as the potential of the power supply 2, and low is output to the output terminal 729. At this time, the switch 725 is assumed to be off.

Next, consider a case where writing is performed such that a row is output to the memory cell 700. First, the row decoder 702 is operated to activate the word line 720, whereby the transistors 705 to 707 are turned on. Next, the column decoder 701 is operated to turn on the column switch 722, whereby the bit line 717 and the output wiring 727 are connected. At this time, the switch 725 is turned on and the switch 726 is turned off. When the switch 725 is turned on, the output wiring 727 is connected to the boost power supply circuit 703 and a high voltage is applied. Since the fuse element 711 is connected to the output wiring 727 via the column switch 722 and the transistor 705 is turned on, a high voltage is applied to both ends of the fuse element 711 and the fuse element 711 is short-circuited by the flowing current. .
In this manner, a nonvolatile memory circuit can be realized by short-circuiting the fuse element of the memory cell that performs row writing.

  Next, a fuse element that shorts the capacitance will be described with reference to a cross-sectional view of FIG. A thin insulating film 802 is sandwiched between the first conductive layer 801 and the second conductive layer 803. By applying a high voltage between the first conductive layer 801 and the second conductive layer 803, the insulating film 802 can be destroyed and the first conductive layer 801 and the second conductive layer 803 can be short-circuited. it can.

An example in which data is written to the fuse memory by using the external high-voltage power supply 903 instead of generating a high voltage by rectifying, stabilizing, and boosting the input signal from the antenna will be described with reference to FIG. The example shown in FIG. 9 is a method of fusing the resistance shown in FIG. 5, but a method of short-circuiting the capacitor shown in FIG. 7 may be used. Writing using such an external high-voltage power supply 903 is suitable for writing data during chip inspection. Generally, a high-voltage power supply is prepared for an LSI destroy apparatus, and writing can be performed using the power supply. After the electrical inspection of the chip is completed, the external high voltage power supply 903 can be connected to the pad 930 via an inspection probe to perform writing. The operation will be described below.
The fuse memory circuit includes a column decoder 901, a row decoder 902, an external high voltage power supply 903, an amplifier 904, N-type transistors 905 to 910, fuse elements 911 to 916, bit lines 917 to 919, word lines 920 and 921, and column switches 922 to 924. , Switches 925 and 926, output wiring 927, memory load resistor 928, output terminal 929, power source 1 and power source 2 (see FIG. 9). The power source 1 is for setting a high potential, and the power source 2 is for setting a low potential. However, when the transistors 905 to 910 are P-type transistors, the power supply 1 sets a low potential, and the power supply 2 sets a high potential. In the following description, the transistors 905 to 910 are N-type.
Further, the memory cell 900 including the transistor 905 and the fuse element 911 will be described as a representative.

First, the case of performing initial reading will be described. Since the fuse elements 911 to 916 function as electric wirings in the initial state, the transistors 905 and 908 are connected to the bit line 917, the transistors 906 and 909 are connected to the bit line 918, and the transistors 907 and 910 are connected to the bit line 919. ing.
Here, for example, when reading data from the memory cell 900, the row decoder 902 is operated to activate the word line 920, whereby the transistors 905 to 907 are turned on. Next, the column decoder 901 is operated to turn on the column switch 922, whereby the bit line 917 and the output wiring 927 are connected. Further, the switch 926 is turned on to connect the output wiring 927, the memory load resistor 928, and the amplifier 904. At this time, the switch 925 is turned off.

  When the transistor 905 is turned on, current flows from the power source 1 to the resistor 928, the switch 926, the output wiring 927, the column switch 922, the bit line 917, the fuse element 911, the transistor 905, and the power source 2. At this time, when a potential drop occurs in the resistor 928 and the on-resistance of the transistor 905 is sufficiently smaller than the resistance value of the resistor 928, the input potential of the amplifier 904 becomes low. Since the memory cells are all the same in the initial stage, the output is low regardless of which transistor is turned on.

Next, consider a case where the output of the memory cell 900 is set to high.
Here, for example, when reading data from the memory cell 900, the row decoder 902 is operated to activate the word line 920, whereby the transistors 905 to 907 are turned on. Next, the column decoder 901 is operated to turn on the column switch 922, whereby the bit line 917 and the output wiring 927 are connected. Further, the switch 926 is turned on, and the output wiring 927, the resistor 928, and the amplifier 904 are connected. At this time, the switch 925 is turned off.
In order for the output of the memory cell 900 to be high even when the transistor 905 is turned on, the fuse element 911 needs to be cut and opened. At this time, the current flowing through the resistor 928 does not exist except for a minute leak current, the input voltage of the amplifier 904 becomes the same as the potential of the power supply 1, and high is output to the output terminal 929. At this time, the switch 925 is assumed to be off.

Next, consider a case where writing is performed such that a high is output to the memory cell 900. First, the row decoder 902 is operated to activate the word line 920, whereby the transistors 905 to 907 are turned on. Next, the column decoder 901 is operated to turn on the column switch 922, whereby the bit line 917 and the output wiring 927 are connected. At this time, the switch 925 is turned on and the switch 926 is turned off. When the switch 925 is turned on, the output wiring 927 is connected to the external high voltage power source 903 via the pad 930, and a high voltage is applied. Since the fuse element 911 is connected to the output wiring 927 via the column switch 922 and the transistor 905 is on, a high voltage is applied to both ends of the fuse element 911, and the fuse element 911 is blown by the flowing current. .
In this way, a non-volatile memory circuit can be realized by fusing the fuse element of the memory cell that performs high writing.

  An example of a stabilized power supply circuit will be described with reference to FIG. The stabilized power supply circuit includes a reference voltage circuit and a buffer amplifier. The reference voltage circuit includes a resistor 2201 and diode-connected transistors 2202 and 2203, and generates a reference voltage corresponding to two VGS of the transistors. The buffer amplifier is composed of a differential circuit composed of transistors 2205 and 2206, a current mirror circuit composed of transistors 2207 and 2208, a current supply resistor 2204, a transistor 2209, and a common source amplifier composed of a resistor 2210.

  When the current flowing from the output terminal is large, the current flowing through the transistor 2209 decreases, and when the current flowing from the output terminal is small, the current flowing through the transistor 2209 increases, so that the current flowing through the resistor 2210 is substantially constant. Operate. Further, the potential of the output terminal is almost the same value as that of the reference voltage circuit. Although a stabilized power supply circuit including a reference voltage circuit and a buffer amplifier is shown here, the stabilized power supply circuit used in the present invention is not limited to the above, and may be another type of circuit.

  A method for simultaneously manufacturing the memory element described in Embodiment Mode and TFTs used for logic circuit portions such as a decoder, a selector, a writing circuit, and a reading circuit over an insulating substrate will be described with reference to FIGS. Note that, in this embodiment, an n-channel memory element having a floating gate, an n-channel TFT, and a p-channel TFT are shown as examples of the semiconductor element, but are included in the memory portion and the logic circuit portion in the present invention. The semiconductor element is not limited to this. Further, this manufacturing method is an example, and the manufacturing method over an insulating substrate is not limited.

  First, base films 3001 and 3002 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film are formed over a glass substrate 3000. For example, a silicon oxynitride film is formed as a base film 3001 with a thickness of 10 to 200 nm, and a silicon oxynitride silicon film is stacked as a base film 3002 with a thickness of 50 to 200 nm.

  The island-shaped semiconductor layers 3003 to 3005 are formed using a crystalline semiconductor film in which a semiconductor film having an amorphous structure is formed using a known laser crystallization method or thermal crystallization method. The island-like semiconductor layers 3003 to 3005 are formed to a thickness of 25 to 80 nm. There is no limitation on the material of the crystalline semiconductor film, but the crystalline semiconductor film is preferably formed of silicon or a silicon germanium (SiGe) alloy.

  Here, treatment for providing an overlap region for extracting charge on one side of the source region or the drain region of the semiconductor layer 3003 of the TFT used for the memory element may be performed.

  Next, a gate insulating film 3006 is formed to cover the island-shaped semiconductor layers 3003 to 3005. The gate insulating film 3006 is formed of an insulating film containing silicon with a thickness of 10 to 80 nm by using a plasma CVD method or a sputtering method. In particular, in an OTP type non-volatile memory, writing by hot electron injection and charge retention are important. Therefore, it is preferable that the gate insulating film has a thickness of 40 to 80 nm in which a tunnel current does not easily flow.

  Then, first conductive layers 3007 to 3009 are formed over the gate insulating film 3006 and removed by etching except for a region which later becomes a floating gate electrode and a region which becomes a gate electrode of a normal TFT.

  Next, a second gate insulating film 3010 is formed. The second gate insulating film 3010 is formed of an insulating film containing silicon with a thickness of 10 to 80 nm by using a plasma CVD method or a sputtering method. The second gate insulating film 3010 is removed by etching except for a region where the memory element exists.

  Subsequently, second conductive layers 3011 to 3013 are formed, and the first conductive layer 3007, the second gate insulating film 3010, the second conductive layer 3011 (memory element), or the first stacked layers are stacked. The conductive layer 3008, the first conductive layer 3009 stacked with the second conductive layer 3012, and the second conductive layer 3013 (ordinary TFT) are etched at once, so that a floating gate electrode, a control gate electrode, Then, a gate electrode of a normal TFT is formed.

  In this embodiment, the first conductive layers 3007 to 3009 are formed of TaN to a thickness of 50 to 100 nm, and the second conductive layers 3011 to 3013 are formed of W to a thickness of 100 to 300 nm. These materials are not particularly limited, and any of these materials may be formed of an element selected from Ta, W, Ti, Mo, Al, Cu, or the like, or an alloy material or a compound material containing the element as a main component.

  Subsequently, doping which imparts n-type to the TFT used for the memory element is performed to form first impurity regions 3014 and 3015. Next, doping for imparting p-type conductivity is performed on the p-channel TFT used in the logic circuit portion, so that second impurity regions 3016 and 3017 are formed. Subsequently, in order to form an LDD region of an n-channel TFT used in the logic circuit portion, doping for imparting n-type is performed, and third impurity regions 3018 and 3019 are formed. After that, sidewalls 3020 and 3021 are formed, and doping to impart n-type to the n-channel TFT used in the logic circuit portion is performed to form fourth impurity regions 3022 and 3023. These doping methods may be performed by an ion doping method or an ion implantation method. Through the above steps, impurity regions are formed in each island-like semiconductor layer.

  Next, a step of activating the impurity element added to each island-like semiconductor layer is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. Further, a heat treatment is performed at 300 to 450 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

Next, a first interlayer insulating film 3024 is formed using a silicon oxynitride film. The thickness of the first interlayer insulating film 3024 is 10 to 80 nm, which is about the same as that of the gate insulating film 3006. Subsequently, a second interlayer insulating film 3025 made of an organic insulating material such as acrylic is formed. Alternatively, an inorganic material can be used for the second interlayer insulating film 3025 instead of the organic insulating material. As the inorganic material, inorganic SiO ₂ , SiO ₂ (PCVD-SiO ₂ ) produced by a plasma CVD method, SOG (Spin on Glass; coated silicon oxide film), or the like is used. After forming the two interlayer insulating films, an etching process for forming a contact hole is performed.

  Then, electrodes 3026 and 3027 are formed in contact with the source and drain regions of the island-like semiconductor layer in the memory portion. Similarly, the electrodes 3028 to 3030 are formed in the logic circuit portion.

  As described above, a memory portion having an n-channel memory element having a floating gate and a logic circuit portion having an n-channel TFT having an LDD structure and a p-channel TFT having a single drain structure are formed on the same substrate. (See FIG. 15).

  In this embodiment, a manufacturing method from formation of a memory portion and a logic circuit portion to transfer to a flexible substrate will be described with reference to FIGS. Note that in this embodiment, an n-channel memory element having a floating gate, an n-channel TFT, and a p-channel TFT are shown as examples of the semiconductor element. However, in the present invention, the semiconductor element is included in the memory portion and the logic circuit portion. The semiconductor element to be used is not limited to this. Further, this manufacturing method is an example, and the manufacturing method over an insulating substrate is not limited.

  A peeling layer 4000 is formed over the insulating substrate 3000. As the separation layer 4000, a layer containing silicon as its main component such as amorphous silicon, polycrystalline silicon, single crystal silicon, or microcrystalline silicon (including semi-amorphous silicon) can be used. The peeling layer 4000 can be formed by a sputtering method, a plasma CVD method, or the like. In this embodiment, amorphous silicon having a thickness of about 500 nm is formed by a sputtering method and used as the peeling layer 4000. Subsequently, according to the work process shown in the second embodiment, a memory part and a logic circuit part as shown in FIG. 15 are formed.

  Next, a third interlayer insulating film 4001 is formed over the second interlayer insulating film 3025, and pads 4002 to 4005 are formed. For the pads 4002 to 4005, a conductive material having one or more metals such as Ag, Au, Cu, Pd, Cr, Mo, Ti, Ta, W, and Al, or a metal compound can be used.

  Then, a protective layer 4006 is formed over the third interlayer insulating film 4001 so as to cover the pads 4002 to 4005. The protective layer 4006 is formed using a material that can protect the pads 4002 to 4005 when the peeling layer 4000 is later removed by etching. For example, the protective layer 4006 can be formed by applying an epoxy resin, an acrylate resin, or a silicon resin soluble in water or alcohols over the entire surface (FIG. 16A).

  Next, a groove 4007 for separating the separation layer 4000 is formed (see FIG. 16B). The groove 4007 may be formed so long as the peeling layer 4000 is exposed. The groove 4007 can be formed by etching, dicing, scribing, or the like.

Next, the peeling layer 4000 is removed by etching (see FIG. 17A). In this embodiment, fluorine halide is used as an etching gas, and the gas is introduced from the groove 4007. In this embodiment, for example, ClF ₃ (chlorine trifluoride) is used, and the temperature is 350 ° C., the flow rate is 300 sccm, the atmospheric pressure is 8 × 10 ² Pa (6 Torr), and the time is 3 hours. Alternatively, a gas in which nitrogen is mixed with ClF ₃ gas may be used. By using halogenated fluorine such as ClF ₃ , the peeling layer 4000 is selectively etched, and the insulating substrate 3000 can be peeled off. The halogenated fluorine may be a gas or a liquid.

  Next, the peeled memory portion and logic circuit portion are attached to a support body 4009 with an adhesive 4008 (see FIG. 17B). As the adhesive 4008, a material capable of bonding the support body 4009 and the base film 3001 is used. As the adhesive 4008, various curable adhesives such as a reactive curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive can be used.

  As the support 4009, an organic material such as flexible paper or plastic can be used. Alternatively, a flexible inorganic material may be used as the support body 4009. The support 4009 preferably has a high thermal conductivity of about 2 to 30 W / mK in order to diffuse the heat generated in the integrated circuit.

  Note that the method of peeling the integrated circuit of the memory portion and the logic circuit portion from the insulating substrate 3000 is not limited to the method using etching of the silicon film as shown in this embodiment, and various other methods can be used. . For example, a metal oxide film can be provided between a substrate having high heat resistance and an integrated circuit, and the integrated circuit can be peeled by weakening the metal oxide film by crystallization. For example, the integrated layer can be peeled from the substrate by breaking the peeling layer by laser light irradiation. Further, for example, the integrated circuit can be peeled from the substrate by mechanically removing the substrate on which the integrated circuit is formed or removing the substrate by etching with a solution or gas.

  In addition, when the surface of the object has a curved surface, and the ID chip support bonded to the curved surface is bent so as to have a curved surface drawn by the movement of the generatrix such as a cone surface or a column surface, It is desirable to align the direction of the bus and the direction in which the TFT carrier moves. With the above configuration, even if the support is bent, it can be suppressed that the characteristics of the TFT are affected thereby. In addition, by setting the ratio of the area occupied by the island-shaped semiconductor film in the integrated circuit to 1 to 30%, it is possible to further suppress the influence of the TFT characteristics even if the support is bent. . This embodiment can be used in combination with the above embodiment mode and other embodiments.

  An example in the case of forming a flexible ID tag using a peeling process will be described with reference to FIG. The ID tag includes flexible protective layers 2301 and 2303 and an ID chip 2302 formed using a peeling process. In this embodiment, the antenna 2304 is formed not on the ID chip 2302 but on the protective layer 2303 and is electrically connected to the ID chip 2302. In FIG. 21A, the antenna is formed only over the protective layer 2303; however, an antenna may also be formed over the protective layer 2301. The antenna is preferably silver, copper, or a metal plated with them. The ID chip 2302 and the antenna are connected using an anisotropic conductive film and subjected to UV treatment, but the connection method is not limited to this.

  FIG. 21B shows a cross section of FIG. The ID chip 2302 has a thickness of 5 μm or less, and preferably has a thickness of 0.1 μm to 3 μm. Further, the thickness of the protective layers 2301 and 2303 is preferably (d / 2) ± 30 μm, where d is the thickness when the protective layers 2301 and 2303 are overlapped, and in particular, (d / 2) ± 10 μm is the best. The thickness of the protective layers 2301 and 2303 is desirably 10 μm to 200 μm. The area of the ID chip 2302 is 5 mm square or less, and desirably has an area of 0.3 mm square to 4 mm square.

The protective layers 2301 and 2303 are formed of an organic resin material and have a strong structure against bending. Since the ID chip 2302 itself using a peeling process is more resistant to bending than a single crystal semiconductor, the ID chip 2302 can be closely attached to the protective layers 2301 and 2303. The ID chip 2302 surrounded by the protective layers 2301 and 2303 may be arranged on the surface or inside of another individual object. It may also be embedded in paper.

In the case where the ID chip is curved, that is, an example in which TFTs are arranged perpendicular to the direction in which the ID chip draws an arc is described with reference to FIG. The TFT included in the ID chip in FIG. 19 is arranged so that the current flows, that is, the positions of the drain electrode, the gate electrode, and the source electrode are linear, and the influence of stress is reduced. By performing such an arrangement, variation in TFT characteristics can be suppressed. Further, the crystals constituting the TFT are aligned in the direction in which the current flows. By forming them with CWLC or the like, the S value is 0.35 V / dec or less (preferably 0.09 to 0.25 V / dec). The mobility can be 100 cm 2 / Vs or higher.
When a 19-stage ring oscillator is configured using such TFTs, the oscillation frequency is 1 MHz or higher, preferably 100 MHz or higher, at a power supply voltage of 3 to 5 V. At a power supply voltage of 3 to 5 V, the delay time per inverter stage is 26 ns, preferably 0.26 ns or less.

Further, in order not to destroy active elements such as TFTs due to stress, the ratio of the area of the active region (silicon island portion) of the active elements such as TFTs to the entire area is 5% to 50%. It is desirable.
In a region where there is no active element such as a TFT, a base insulating material, an interlayer insulating material, and a wiring material are mainly provided. The area other than the active region of the TFT is desirably 60% or more of the entire area.
The active region has a thickness of 20 to 200 nm, typically 40 to 170 nm, preferably 45 to 55 nm, and 145 to 155 nm.

  In this embodiment, an example in which an external antenna is attached to a circuit using the present invention will be described with reference to FIGS.

  FIG. 10A shows the circuit covered with a single antenna. An antenna 1001 is formed in a substrate 1000 shape, and a circuit 1002 using the present invention is connected. In the drawing, the periphery of the circuit 1002 is covered with the antenna 1001; however, a structure in which the entire surface is covered with the antenna and the circuit 1002 including the electrodes is attached thereon may be employed.

  FIG. 10B shows a thin antenna arranged around the circuit. An antenna 1004 is formed over a substrate 1003 and a circuit 1005 using the present invention is connected. The wiring of the antenna is an example and is not limited to this.

  FIG. 10C illustrates a high frequency antenna. An antenna 1007 is formed over a substrate 1006, and a circuit 1008 using the present invention is connected.

  FIG. 10D illustrates an antenna that is 180 degrees omnidirectional (same reception is possible from any direction). An antenna 1010 is formed over a substrate 1009 and a circuit 1011 using the present invention is connected.

  FIG. 10E shows an antenna elongated in a rod shape. An antenna 1013 is formed over a substrate 1012, and a circuit 1014 using the present invention is connected.

  The circuit using the present invention and connection to these antennas can be made by a known method. For example, the antenna and the circuit may be connected using wire bonding connection or bump connection, or one surface of the circuit formed as a chip may be attached to the antenna as an electrode. In this method, it can be attached using an ACF (anisotropy conductive film).

  The length required for the antenna differs depending on the frequency used for reception. In general, the length is preferably an integral number of a wavelength. For example, when the frequency is 2.45 GHz, it may be about 60 mm (1/2 wavelength) and about 30 mm (1/4 wavelength).

  Moreover, a board | substrate may be attached on the circuit of this invention, and also an antenna may be comprised on it. As an example, FIGS. 11A to 11C are a top view and a cross-sectional view of a substrate in which a substrate is mounted on a circuit and a spiral antenna is disposed.

  Note that the example shown in this embodiment is just an example, and does not limit the shape of the antenna. The present invention can be implemented with any shape of antenna. This example can be realized by using a configuration including any combination of the embodiment and the above Examples 1 to 7.

  In this embodiment, a specific method for manufacturing a thin film integrated circuit device including a TFT will be described with reference to FIGS. Here, for the sake of simplicity, a manufacturing method will be described by showing a cross-sectional structure of a CPU and a memory portion using n-type TFTs and p-type TFTs.

  First, the separation layer 61 is formed over the substrate 60 (FIG. 22A). Here, an a-Si film (amorphous silicon film) having a thickness of 50 nm (500 mm) was formed on a glass substrate (for example, a 1737 substrate manufactured by Corning) by a low pressure CVD method. As the substrate, in addition to a glass substrate, a quartz substrate, a substrate formed of an insulating material such as alumina, a silicon wafer substrate, a plastic substrate having heat resistance that can withstand a processing temperature in a later process, or the like can be used. .

  As the separation layer, a film containing silicon as a main component, such as polycrystalline silicon, single crystal silicon, and SAS (semi-amorphous silicon (also referred to as microcrystalline silicon or microcrystalline silicon)) in addition to amorphous silicon. Although it is desirable to use, it is not limited to these. The peeling layer may be formed by a plasma CVD method, a sputtering method, or the like in addition to the low pressure CVD method. Alternatively, a film doped with an impurity such as phosphorus may be used. Further, the thickness of the release layer is desirably 50 to 60 nm. Regarding SAS, it is good also as 30-50 nm.

Next, a protective film 55 (also referred to as a base film or a base insulating film) is formed over the separation layer 61 (FIG. 22A). Here, a three-layer structure of a SiON film with a thickness of 100 nm / a SiNO film with a thickness of 50 nm / a SiON film with a thickness of 100 nm is used. However, the material, the film thickness, and the number of stacked layers are not limited thereto. For example, instead of the lower SiON film, a heat-resistant resin such as siloxane having a film thickness of 0.5 to 3 μm may be formed by a spin coat method, a slit coater method, a droplet discharge method, or the like. Further, a silicon nitride film (SiN, Si ₃ N ₄ or the like) may be used. Each film thickness is preferably 0.05 to 3 μm, and can be freely selected from the range.

Here, the silicon oxide film can be formed by a method such as thermal CVD, plasma CVD, atmospheric pressure CVD, or bias ECRCVD using a mixed gas of SiH ₄ and O ₂ , TEOS (tetraethoxysilane) and O _2, or the like. it can. The silicon nitride film can be typically formed by plasma CVD using a mixed gas of SiH ₄ and NH ₃ . The SiON film or SiNO film can be typically formed by plasma CVD using a mixed gas of SiH ₄ and N ₂ O.

  In addition, when using the material which has silicon as main components, such as a-Si, as the peeling layer 61 and the island-like semiconductor film 57, SiOxNy is used as a protective film which touches them from the point of ensuring adhesiveness. Also good.

  Next, a thin film transistor (TFT) constituting a CPU and a memory of the thin film integrated circuit device is formed on the protective film 55. In addition to TFTs, thin film active elements such as organic TFTs and thin film diodes can also be formed.

  As a method for manufacturing a TFT, first, an island-shaped semiconductor film 57 is formed over the protective film 55 (FIG. 22B). The island-shaped semiconductor film 57 is formed using an amorphous semiconductor, a crystalline semiconductor, or a semi-amorphous semiconductor. In any case, a semiconductor film containing silicon, silicon germanium (SiGe), or the like as a main component can be used.

  Here, amorphous silicon having a thickness of 70 nm was formed, and the surface thereof was further treated with a solution containing nickel. Further, a crystalline silicon semiconductor film was obtained by a thermal crystallization process at 500 to 750 ° C., and crystallinity was improved by laser crystallization. Further, as a film formation method, a plasma CVD method, a sputtering method, an LPCVD method, or the like may be used. As the crystallization method, laser crystallization method, thermal crystallization method, thermal crystallization using other catalysts (Fe, Ru, Rh, Pd, Os, Ir, Pt, Cu, Au, etc.), or alternating them You may go multiple times.

In addition, a continuous wave laser may be used for the crystallization treatment of the semiconductor film having an amorphous structure, and a solid laser capable of continuous oscillation is used in order to obtain a crystal having a large particle size upon crystallization. It is preferable to apply the second to fourth harmonics of the fundamental wave (the crystallization in this case is referred to as CWLC). Typically, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) may be applied. In the case of using a continuous wave laser, laser light emitted from a continuous wave YVO ₄ laser having an output of 10 W is converted into a harmonic by a non-linear optical element. There is also a method in which a YVO ₄ crystal or GdVO ₄ crystal and a non-linear optical element are placed in a resonator to emit harmonics. Preferably, the laser beam is shaped into a rectangular or elliptical shape on the irradiation surface by an optical system, and the object to be processed is irradiated. In this case, a power density of about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation may be performed by moving the semiconductor film relative to the laser light at a speed of about 10 to 2000 cm / s.

  In the case of using a pulsed laser, a frequency band of several tens Hz to several hundreds Hz is usually used, but a pulsed laser having an oscillation frequency of 10 MHz or higher that is significantly higher than that may be used (in this case) Crystallization is referred to as MHzLC). It is said that the time from when the semiconductor film is irradiated with laser light by pulse oscillation until the semiconductor film is completely solidified is said to be several tens of nanoseconds to several hundreds of nanoseconds. The laser light of the next pulse can be irradiated after being melted by the laser light and solidifying. Therefore, unlike the case of using a conventional pulsed laser, the solid-liquid interface can be continuously moved in the semiconductor film, so that a semiconductor film having crystal grains continuously grown in the scanning direction is formed. Is done. Specifically, a set of crystal grains having a width of 10 to 30 μm in the scanning direction of the included crystal grains and a width of about 1 to 5 μm in a direction perpendicular to the scanning direction can be formed. By forming single crystal grains extending long along the scanning direction, it is possible to form a semiconductor film having almost no crystal grain boundaries in at least the channel direction of the TFT.

  Note that when siloxane which is a heat-resistant organic resin is used as a part of the protective film 55, heat can be prevented from leaking from the semiconductor film during the crystallization, and crystallization can be efficiently performed. It can be carried out.

A crystalline silicon semiconductor film is obtained by the above method. Note that the crystals are preferably aligned in the source, channel, and drain directions. The thickness of the crystal layer is preferably 20 to 200 nm (typically 40 to 170 nm, more preferably 50 to 150 nm). Thereafter, an amorphous silicon film for gettering the metal catalyst was formed on the semiconductor film via an oxide film, and gettering treatment was performed by heat treatment at 500 to 750 ° C. Furthermore, in order to control the threshold value as the TFT element, boron ions having a dose of the order of 10 ¹³ / cm ² were implanted into the crystalline silicon semiconductor film. Thereafter, the island-shaped semiconductor film 57 was formed by etching using the resist as a mask.

In forming a crystalline semiconductor film, a polycrystalline semiconductor film is directly formed by LPCVD (low pressure CVD) using disilane (Si ₂ H ₆ ) and germanium fluoride (GeF ₄ ) as source gases. Also, a crystalline semiconductor film can be obtained. The gas flow ratio is Si ₂ H ₆ / GeF ₄ = 20 / 0.9, the film forming temperature is 400 to 500 ° C., and He or Ar is used as the carrier gas, but the present invention is not limited to this.

Note that hydrogen or halogen of 1 × 10 ¹⁹ to 1 × 10 ²² cm ⁻³ , preferably 1 × 10 ^{19 to} 5 × 10 ²⁰ cm ⁻³ is preferably added to the channel region in the TFT. . Regarding the SAS, it is desirable to set it to 1 × 10 ¹⁹ to 2 × 10 ²¹ cm ⁻³ . In any case, it is desirable to contain more than the content of hydrogen or halogen contained in the single crystal used for the IC chip. Thereby, even if a local crack occurs in the TFT portion, it can be terminated (terminated) by hydrogen or halogen.

  Next, a gate insulating film 58 is formed over the island-shaped semiconductor film 57 (FIG. 22B). The gate insulating film 58 is preferably formed using a thin film formation method such as a plasma CVD method or a sputtering method, and a film containing silicon nitride, silicon oxide, silicon nitride oxide, or silicon oxynitride is formed as a single layer or a stacked layer. . In the case of stacking, for example, a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film is preferable from the substrate side.

  Next, the gate electrode 56 is formed (FIG. 22C). Here, after the Si and W (tungsten) layers are formed by sputtering, the gate electrode 56 is formed by etching using the resist 62 as a mask. Of course, the material, structure, and manufacturing method of the gate electrode 56 are not limited to this, and can be selected as appropriate. For example, a stacked structure of Si and NiSi (nickel silicide) doped with an n-type impurity or a stacked structure of TaN (tantalum nitride) and W (tungsten) may be used. Alternatively, a single layer may be formed using various conductive materials.

  In place of the resist mask, a mask such as SiOx may be used. In this case, a patterning process is added to a mask (referred to as a hard mask) made of SiOx, SiON, or the like. However, since the film thickness of the mask during etching is less than that of the resist, a gate electrode layer having a desired width may be formed. it can. Alternatively, the gate electrode 56 may be selectively formed by using a droplet discharge method without using the resist 62.

  As the conductive material, various materials can be selected depending on the function of the conductive film. In the case where the gate electrode and the antenna are formed at the same time, materials may be selected in consideration of their functions.

Note that although a mixed gas of CF ₄ , Cl ₂ , and O ₂ or Cl ₂ gas is used as an etching gas for forming the gate electrode by etching, it is not limited to this.

Next, the portions to become the p-type TFTs 70 and 72 are covered with a resist 63, and the gate electrode is used as a mask, and the impurity element 64 (typically P-type) imparting n-type is formed in the island-shaped semiconductor films of the n-type TFTs 69 and 71. (Phosphorus) or As (arsenic)) is doped at a low concentration (first doping step, FIG. 22D). The conditions of the first doping step are a dose of 1 × 10 ^{13 to} 6 × 10 ¹³ / cm ² and an acceleration voltage of 50 to 70 keV, but are not limited thereto. Through the first doping process, through doping is performed through the gate insulating film 58, and a pair of low-concentration impurity regions 65 is formed. The first doping step may be performed on the entire surface without covering the p-type TFT region with the resist.

Next, after removing the resist 63 by ashing or the like, a resist 66 covering the n-type TFT region is newly formed, and p-type is imparted to the island-like semiconductor films of the p-type TFTs 70 and 72 using the gate electrode as a mask. The impurity element 67 (typically B (boron)) to be doped is doped at a high concentration (second doping step, FIG. 22E). The conditions of the second doping step are a dose of 1 × 10 ^{16 to} 3 × 10 ¹⁶ / cm ² and an acceleration voltage of 20 to 40 keV, but are not limited thereto. Through this second doping step, through doping is performed through the gate insulating film 58, and a pair of p-type high concentration impurity regions 68 are formed.

Next, after removing the resist 66 by ashing or the like, an insulating film 75 was formed on the substrate surface (FIG. 23A). Here, a SiO ₂ film having a thickness of 100 nm was formed by a plasma CVD method. Thereafter, the insulating film 75 and the gate insulating film 58 were etched away by an etch-back method, and sidewalls (sidewalls) 76 were formed in a self-aligned manner (FIG. 23B). As the etching gas, a mixed gas of CHF ₃ and He was used. Note that the step of forming the sidewall is not limited to these.

  If an insulating film is also formed on the back surface of the substrate when the insulating film 75 is formed, the insulating film on the back surface is removed by etching using a resist covering the entire surface of the substrate as a mask (back surface processing).

The method for forming the sidewall 76 is not limited to the above. For example, the method shown in FIG. 24 can be used. FIG. 24A illustrates an example in which the insulating film 75 has a two-layer structure or more. The insulating film 75 has a two-layer structure of, for example, a 100 nm thick SiON (silicon oxynitride) film and a 200 nm thick LTO film (Low Temperature Oxide). Here, the SiON film was formed by the plasma CVD method, and the SiO ₂ film was formed by the low pressure CVD method as the LTO film. After that, by performing etch back, the sidewall 76 having an L shape and an arc shape is formed.

  FIG. 24B shows an example in which etching is performed so as to leave the gate insulating film 58 during etch back. In this case, the insulating film 75 may have a single layer structure or a laminated structure.

  The sidewall functions as a mask when a high concentration n-type impurity is doped later to form a low concentration impurity region or a non-doped offset region below the sidewall 76. In any of the formation methods, the etch-back conditions may be changed as appropriate depending on the width of the low-concentration impurity region or offset region to be formed.

Next, a resist 77 covering the p-type TFT region is newly formed, and an n-type impurity element 78 (typically P or As) is doped at a high concentration using the gate electrode 56 and the sidewall 76 as a mask. (Third doping step, FIG. 23C). The conditions of the third doping step are a dose amount: 1 × 10 ^{13 to} 5 × 10 ¹⁵ / cm ² and an acceleration voltage: 60 to 100 keV. By this third doping step, a pair of n-type high concentration impurity regions 79 are formed.

  Note that after removing the resist 77 by ashing or the like, the impurity region may be thermally activated. For example, after a 50 nm SiON film is formed, heat treatment may be performed in a nitrogen atmosphere at 550 ° C. for 4 hours. In addition, after the SiNx film containing hydrogen is formed to a thickness of 100 nm, defects in the crystalline semiconductor film can be improved by performing heat treatment at 410 ° C. for 1 hour in a nitrogen atmosphere. This terminates dangling bonds existing in, for example, crystalline silicon, and is called a hydrogenation process. Thereafter, a SiON film having a film thickness of 600 nm is formed as a cap insulating film for protecting the TFT. Note that the hydrogenation process may be performed after the formation of the SiON film. In this case, the SiNx film and the SiON film can be continuously formed. Thus, a three-layer insulating film of SiON, SiNx, and SiON is formed on the TFT, but the structure and material are not limited to these. In addition, these insulating films have a function of protecting the TFT, so that it is desirable to form them as much as possible.

  Next, an interlayer film 53 is formed over the TFT (FIG. 23D). As the interlayer film 53, a heat-resistant organic resin such as polyimide, acrylic, polyamide, or siloxane can be used. Depending on the material, spin coating, dipping, spray coating, droplet discharge methods (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. are adopted as the forming method. be able to. In addition, an inorganic material may be used. In that case, silicon oxide, silicon nitride, silicon oxynitride, PSG (phosphorus glass), BPSG (phosphorus boron glass), an alumina film, or the like can be used. Note that the interlayer film 53 may be formed by stacking these insulating films.

  Further, a protective film 54 may be formed on the interlayer film 53. As the protective film 54, a film containing carbon such as DLC (diamond-like carbon) or carbon nitride (CN), a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, or the like can be used. As a formation method, a plasma CVD method, an atmospheric pressure plasma, or the like can be used. Alternatively, a photosensitive or non-photosensitive organic material such as polyimide, acrylic, polyamide, resist, or benzocyclobutene, or a heat-resistant organic resin such as siloxane may be used.

  In order to prevent the film from peeling or cracking of these films due to the stress caused by the difference in thermal expansion coefficient between the interlayer film 53 or the protective film 54 and a conductive material or the like constituting the wiring to be formed later, A filler may be mixed in the film 53 or the protective film 54.

Next, after forming a resist, a contact hole is formed by etching, and a wiring 51 for connecting TFTs and a connection wiring 21 for connecting to an external antenna are formed (FIG. 23D). A gas used for etching when opening the contact hole is a mixed gas of CHF ₃ and He, but is not limited to this. Moreover, the wiring 51 and the connection wiring 21 may be formed simultaneously using the same material, or may be formed separately. Here, the wiring 51 connected to the TFT has a five-layer structure of Ti, TiN, Al—Si, Ti, and TiN, and is formed by sputtering and then patterned.

  In addition, by mixing Si in the Al layer, generation of hillocks in resist baking during wiring patterning can be prevented. Further, instead of Si, about 0.5% Cu may be mixed. Further, the hillock resistance is further improved by sandwiching the Al—Si layer with Ti or TiN. In the patterning, it is desirable to use the hard mask made of SiON or the like. Note that the wiring material and the formation method are not limited to these, and the material used for the gate electrode described above may be employed.

  In the present embodiment, the case where only the TFT region constituting the CPU 73, the memory 74, etc. and the terminal portion 80 connected to the antenna are integrally formed has been shown. Embodiments can be applied. In this case, an antenna is preferably formed on the interlayer film 53 or the protective film 54 and further covered with another protective film. As the conductive material of the antenna, Ag, Au, Al, Cu, Zn, Sn, Ni, Cr, Fe, Co, or Ti, or an alloy containing them can be used, but is not limited thereto. Further, the material may be different between the wiring and the antenna. Note that the wiring and the antenna are preferably formed so as to have a metal material having excellent malleability and ductility, and more preferably, the wiring and the antenna are made thick to withstand stress due to deformation.

  As a formation method, after forming a film on the entire surface by a sputtering method, patterning may be performed using a resist mask, or selective formation from a nozzle may be performed by a droplet discharge method. Note that the droplet discharge method here includes not only an inkjet method but also an offset printing method and a screen printing. The wiring and the antenna may be formed at the same time, or may be formed so that the other rides on after forming one first.

  Through the above steps, a thin film integrated circuit device composed of TFTs is completed. Although the top gate structure is used in this embodiment, a bottom gate structure (reverse stagger structure) may be used. Note that a base insulating film material, an interlayer insulating film material, and a wiring material are mainly provided in a region where a thin film active element portion (active element) such as a TFT does not exist, and this region is the entire thin film integrated circuit device. It is desirable to occupy 50% or more, preferably 70 to 95%. This makes it easy to bend the ID chip and facilitates handling of finished products such as ID labels. In this case, the island-shaped semiconductor region (island) of the active element including the TFT portion occupies 1 to 30%, preferably 5 to 15% of the entire thin film integrated circuit device.

Further, as shown in FIG. _23I , the distance (t _under ) from the semiconductor layer of the TFT to the lower protective layer and the upper interlayer film (the protective layer is formed from the semiconductor layer) in the thin film integrated circuit device. In some cases, it is desirable to adjust the thicknesses of the upper and lower protective layers or interlayer films so that the distance (t _over ) to the protective layer is equal or approximately equal. In this manner, by placing the semiconductor layer in the center of the thin film integrated circuit device, the stress on the semiconductor layer can be relaxed and the occurrence of cracks can be prevented.

  The semiconductor device of the present invention can be used for IC cards, IC tags, RFIDs, transponders, banknotes, securities, passports, electronic devices, bags, and clothes. In this embodiment, an example of an IC card, an ID tag, an ID chip, and the like will be described with reference to FIG.

  FIG. 18A shows an IC card, which can be used for credit card payment without using cash by using the fact that the memory of the built-in circuit can be rewritten in addition to personal identification, or electronic You can use it like money. A circuit unit 2001 using the present invention is incorporated in an IC card 2000.

  FIG. 18B shows an ID tag, which can be used for admission management in a specific place because it can be miniaturized in addition to personal identification. A circuit portion 2011 using the present invention is incorporated in the ID tag 2010.

  FIG. 18C shows an example in which an ID chip 2022 for managing a product when a product is handled at a retail store such as a supermarket is attached to the product. The present invention is applied to a circuit in the ID chip 2022. By using the ID chip in this way, not only inventory management becomes easy, but also damage such as shoplifting can be prevented. In the drawing, the protective film 2021 that also serves as an adhesive is used to prevent the ID chip 2022 from peeling off, but the ID chip 2022 may be directly attached using an adhesive. Moreover, it is preferable to produce using the flexible substrate mentioned in Example 2 on the structure attached to goods.

  FIG. 18D shows an example in which an ID chip for identification is incorporated at the time of product manufacture. In the drawing, an ID chip 2031 is incorporated in a display housing 2030 as an example. The present invention is applied to a circuit in the ID chip 2031. By adopting such a structure, it is possible to easily identify the manufacturer and manage the distribution of goods. Note that although the case of a display is taken as an example in the drawings, the present invention is not limited to this and can be applied to various electronic devices and articles.

  FIG. 18E shows an article transport tag. In the drawing, an ID chip 2041 is incorporated in a tag 2040. The present invention is applied to a circuit in the ID chip 2041. By adopting such a structure, it is possible to easily carry out transport destination selection, merchandise distribution management, and the like. In the drawings, the structure is such that a string-like object that binds the article is attached, but the present invention is not limited to this, and it is directly attached to the article using something like a sealing material. You may take a simple structure.

  FIG. 18F shows an example in which an ID chip 2052 is incorporated in the book 2050. The present invention is applied to a circuit in the ID chip 2052. By adopting such a structure, distribution management at a bookstore or lending processing at a library or the like can be easily performed. In the drawing, a protective film 2051 that also serves as an adhesive is used to prevent the ID chip 2052 from peeling off, but a structure in which the ID chip 2052 is directly attached using an adhesive or a cover of this book 2050 is used. You may take the structure embedded in.

  FIG. 18G illustrates an example in which an ID chip 2061 is incorporated into a banknote 2060. The present invention is applied to a circuit in the ID chip 2061. By adopting such a structure, it is possible to easily prevent the circulation of counterfeit bills. Note that it is more preferable to adopt a structure in which the ID2061 chip is embedded in the banknote 2060 in order to prevent the ID2061 chip from peeling off due to the nature of the banknote. The present invention is not limited to banknotes, and can be applied to papers such as securities and passports.

  FIG. 18H shows an shoe in which an ID chip 2072 is incorporated into a shoe 2070. The present invention is applied to a circuit in the RFID chip 2072. By adopting such a structure, it is possible to easily identify the manufacturer and manage the distribution of goods. In the drawing, a protective film 2071 that also serves as an adhesive is used to prevent the ID chip 2072 from peeling off. However, the ID chip 2072 is directly attached using an adhesive or embedded in a shoe 2070. The structure may be taken. The present invention is applicable not only to shoes but also to items worn on bags, clothes, and the like.

  A case will be described in which an ID chip is mounted on various articles for the purpose of ensuring security. Ensuring security can be understood from the aspect of preventing theft or forgery.

  As an example of theft prevention, a case where an ID chip is mounted on a bag will be described. As shown in FIG. 25, an ID chip 2502 is mounted on a bag 2501. For example, the ID chip 2502 can be mounted on a part of the bottom or side surface of the bag 2501. Since the ID chip 2502 is very thin and small, it can be mounted without deteriorating the design of the bag 2501. In addition, the ID chip 2502 has translucency, and it is difficult for a thief to determine whether the ID 2502 chip is mounted. Therefore, there is no possibility that the ID chip 2502 is removed by the theft.

  When such an ID chip mounting bag is stolen, information on the current position of the bag can be obtained using, for example, GPS (Global Positioning System). GPS is a system that captures a signal sent from a GPS satellite, obtains a time difference thereof, and performs positioning based on the time difference.

Further, in addition to the stolen article, it is possible to obtain information on the current position of forgotten or lost items using GPS.

  In addition to bags, ID chips can be mounted on vehicles such as automobiles and bicycles, watches and accessories.

  Next, as an example of forgery prevention, a case where an ID chip is mounted on a passport or a license will be described.

  FIG. 26A shows a passport 2601 on which an ID chip is mounted. In FIG. 26A, the ID chip 2602 is mounted on the cover of the passport 2601; however, the ID chip 2602 may be mounted on another page. The ID chip 2602 may be mounted on the surface because it has translucency. Further, the ID chip 2602 may be sandwiched between materials such as a cover and mounted inside the cover.

  FIG. 26B shows a license 2603 mounted with an ID chip. In FIG. 26B, the ID chip 2604 is mounted inside the license 2603. Further, since the ID chip 2604 has a light-transmitting property, the ID chip 2604 may be provided on the printing surface of the license 2603. For example. The ID chip 2604 can be mounted on the printing surface of the license 2603 and covered with a film. Further, the ID chip 2604 can be sandwiched between the materials of the license 2603 and mounted inside.

  Forgery can be prevented by mounting the ID chip on the article as described above. Further, forgery can be prevented by mounting an ID chip on the above-described bag. In addition, since a very thin and small ID chip is used, the design such as a passport and a license is not impaired. Furthermore, since the ID chip has translucency, it may be mounted on the surface.

  The ID chip can easily manage passports and licenses. Furthermore, since information can be stored in the ID chip without directly entering information in a passport or a license, privacy can be protected.

  A case where an IDF chip is mounted on a commodity such as food for safety management will be described with reference to FIG. A label 2702 on which an ID chip 2703 is mounted and a meat pack 2701 to which the label 2702 is attached are shown. The ID chip 2703 may be mounted on the surface of the label 2702 or may be mounted inside the label 2702. In the case of fresh food such as vegetables, an ID chip may be mounted on a wrap that covers the fresh food.

  The ID chip 2703 can record basic items related to the product such as the product production location, producer, processing date, expiration date, and application items such as cooking examples using the product. Such basic matters do not need to be rewritten, and are preferably recorded using a non-rewritable memory such as MROM. Such application items may be recorded using a rewritable and erasable memory such as EEROM.

  In addition, it is important to be able to know the state of animals and plants before processing in order to carry out food safety management. Therefore, it is preferable to embed an ID chip in animals and plants and acquire information on animals and plants by a reader device. Information on animals and plants includes breeding grounds, feed, breeders, presence of infectious diseases, and the like.

  Further, if the price of the product is recorded on the ID chip, the product can be settled more easily and in a shorter time than the method using the conventional barcode. That is, it is possible to settle a plurality of products on which the ID chip is mounted all at once. However, when reading a plurality of ID chips in this way, it is necessary to mount an anti-collision function in the reader device.

  Furthermore, depending on the communication distance of the ID chip, the product can be settled even if the distance between the register and the product is long. ID chips also help prevent shoplifting.

  Furthermore, the ID chip can be used in combination with other information media such as a barcode and a magnetic tape. For example, basic items that do not need to be rewritten are recorded on the ID chip, and information to be updated, such as discount prices and special price information, may be recorded on the barcode. This is because, unlike an ID chip, a bar code can easily correct information.

  By mounting the ID chip in this way, information that can be provided to the consumer can be increased, so that the consumer can purchase the product with peace of mind.

  A case will be described in which an ID chip is mounted on a product such as a beer bottle for distribution management. As shown in FIG. 28A, an ID chip 2802 is mounted on a beer bottle. For example, the ID chip 2802 can be mounted using the label 2801.

  In the ID chip, basic items such as the date of manufacture, the place of manufacture, and the materials used are recorded. Such basic matters do not need to be rewritten, and are preferably recorded using a non-rewritable memory such as MROM. In addition, individual items such as the delivery destination and delivery date and time of each beer bottle are recorded in the ID chip. For example, as shown in FIG. 28B, when each beer bottle 2803 flows by the belt conveyor 2806 and passes through the writer device 2805, each delivery destination and delivery date and time are recorded on the ID chip 2807 built in the label 2804. be able to. Such individual items may be recorded using a rewritable and erasable memory such as EEROM.

When product information purchased from a delivery destination is transmitted to the distribution management center through the network, based on this product information, the writer device or a personal computer that controls the writer device calculates the delivery destination and delivery date and time. A system that records on a chip should be constructed.

  Since delivery is performed for each case, an ID chip can be mounted for each case or for each of a plurality of cases, and individual items can be recorded.

  By installing an ID chip in such a beverage product in which a plurality of delivery destinations can be recorded, the time required for manual input can be reduced, and input errors caused by the time can be reduced. In addition, labor costs that are the most expensive in the field of logistics management can be reduced. Therefore, by mounting the ID chip, it is possible to carry out low-cost logistics management with few mistakes.

  Furthermore, application items such as foods suitable for beer and cooking methods using beer may be recorded at the delivery destination. As a result, it can serve as an advertisement for foods and the like, and the consumer's willingness to purchase can be enhanced. Such application items may be recorded using a rewritable and erasable memory such as EEROM. By mounting the ID chip in this way, information that can be provided to the consumer can be increased, so that the consumer can purchase the product with peace of mind.

  In order to perform manufacturing management, a manufactured product on which an ID chip is mounted and a manufacturing apparatus (manufacturing robot) controlled based on information on the ID chip will be described.

Currently, there are many scenes in which original products are produced. In such a case, production is performed on the production line based on the original information of the products. For example, in an automobile production line where the paint color of a door can be freely selected, an IDF chip is mounted on a part of the automobile, and the coating apparatus is controlled based on information from the ID chip. And you can produce an original car.
As a result of mounting the ID chip, it is not necessary to adjust the order of the cars to be put on the production line or the number having the same color in advance. For this reason, it is not necessary to set a program for controlling the painting apparatus to match the order and number of cars. That is, the manufacturing apparatus can operate individually based on the information of the ID chip mounted on the automobile.

  Thus, the ID chip can be used in various places. And the specific information regarding manufacture can be obtained from the information recorded on the ID chip, and the manufacturing apparatus can be controlled based on the information.

  Next, a mode in which an IC card using the ID chip of the present invention is used as electronic money will be described. FIG. 29 shows a state in which payment is performed using an IC card 2901. The IC card 2901 has the ID chip 2902 of the present invention. When the IC card 2901 is used, a register 2903 and a reader / writer 2904 are used. The ID chip 2902 holds information on the amount deposited in the IC card 2901, and the reader / writer 2904 can read the amount information without contact and send it to the register 2903. The register 2903 confirms that the amount deposited in the IC card 2901 is equal to or greater than the amount to be settled, and performs settlement. Then, information on the remaining amount after settlement is transmitted to the reader / writer 2904. The reader / writer 2904 can write the remaining amount information into the ID chip 2902 of the IC card 2901.

Note that a key 2905 for inputting a password or the like may be added to the reader / writer 2904 so that a third party can be prevented from making a settlement using the IC card 2901 without permission.
It should be noted that the examples shown in the present embodiment are only examples and are not limited to these applications.

  As described above, the application range of the present invention is extremely wide and can be applied as a solid recognition chip for any article. In addition, the present embodiment can be realized by using a configuration including any combination of the embodiment and Examples 1 to 10.

1 is a block diagram illustrating a configuration of a semiconductor device of the present invention. The block diagram which shows the structure of the conventional semiconductor device. The block diagram which shows the structure of the conventional semiconductor device. The figure which shows the outline | summary of RF tag system. The figure which shows the circuit structure of a fuse memory. The figure which shows the structure of a fuse element. The figure which shows the circuit structure of a fuse memory. The figure which shows the structure of a capacitive fuse element. The figure which shows the circuit structure of a fuse memory. The figure which shows the Example of the antenna of this invention. The figure which shows the Example of the antenna of this invention. The figure which shows the example of the data memorize | stored in a memory circuit. 1 is a block diagram of a logic circuit of the present invention. 1 is a block diagram of a logic circuit of the present invention. Process sectional drawing of this invention. Process sectional drawing of this invention. Process sectional drawing of this invention. The figure which shows the application example of this invention. The figure which shows arrangement | positioning of TFT in this invention. The figure which shows the example of the stable power supply circuit of this invention. The figure which combined the semiconductor device and protective layer of this invention. Process sectional drawing of this invention. Process sectional drawing of this invention. Process sectional drawing of this invention. The figure which shows the bag using this invention. The figure which shows the certificate using this invention. The figure explaining the foodstuff management using this invention. The figure explaining the physical distribution management using this invention. The figure explaining IC card settlement using the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Semiconductor device 101 Antenna circuit 102 Rectifier circuit 103 Stable power supply circuit 104 Boost power supply circuit 105 Modulation circuit 106 Amplifier 107 Logic circuit 108 Amplifier 109 Logic circuit 110 Level shift circuit 111 Fuse memory circuit 112 Fuse memory control circuit 113 Demodulation circuit

Claims (10)

An antenna circuit, a modulation circuit, a demodulation circuit, a logic circuit, and a memory circuit;
The antenna circuit is electrically connected to the modulation circuit and the demodulation circuit,
The demodulation circuit is electrically connected to the logic circuit;
The logic circuit is electrically connected to the memory circuit;
The memory circuit includes a fuse element, stores a signal output from the logic circuit ,
The logic circuit includes a switch and a volatile memory circuit,
When an initial value of a write storage bit of the memory circuit is input to the volatile memory circuit, the volatile memory circuit stores the initial value and outputs a signal for turning on the switch,
Data is written to the memory circuit through the switch by a signal input from the demodulation circuit, and writing to the memory circuit is completed and the write storage bit is rewritten to a value different from the initial value. When the rewritten value of the write storage bit is input to the volatile memory circuit, the volatile memory circuit stores the rewritten value and outputs a signal for turning off the switch. A featured semiconductor device. An antenna circuit, a modulation circuit, a demodulation circuit, a logic circuit, and a memory circuit;
The antenna circuit is electrically connected to the modulation circuit and the demodulation circuit,
The demodulation circuit is electrically connected to the logic circuit;
The logic circuit is electrically connected to the memory circuit;
The memory circuit includes a fuse element, stores a signal output from the logic circuit,
The logic circuit includes a switch and a fuse memory circuit,
When the write storage bit of the fuse memory circuit is an initial value, the fuse memory circuit outputs a signal for turning on the switch,
Data is written to the memory circuit through the switch by a signal input from the demodulation circuit, and writing to the memory circuit is completed and the write storage bit is rewritten to a value different from the initial value. Then, the fuse memory circuit outputs a signal for turning off the switch . In claim 1 or claim 2,
The logic circuit includes a decode circuit and a delay circuit,
A signal inputted from the demodulating circuit is decoded by the decoding circuit, passed through the delay circuit, and inputted to the switch. In any one of Claims 1 thru | or 3 ,
A semiconductor device wherein a memory operation is performed by fusing the fuse element. In any one of Claims 1 thru | or 3 ,
2. The semiconductor device according to claim 1, wherein the fuse element has a metal wiring, and a memory operation is performed by fusing the metal wiring. In any one of Claims 1 thru | or 3 ,
The fuse element has a semiconductor thin film, and a memory operation is performed by fusing the semiconductor thin film. In any one of Claims 1 thru | or 3 ,
The fuse element has a first conductive layer, a second conductive layer, and an insulating film between the first conductive layer and the second conductive layer,
A semiconductor device, wherein a memory operation is performed by short-circuiting the first conductive layer and the second conductive layer. In any one of Claims 1 thru | or 7 ,
At least one of the modulation circuit, the demodulation circuit, the memory circuit, and the logic circuit includes a thin film transistor. In any one of Claims 1 thru | or 8 ,
The semiconductor device, wherein the antenna circuit, the modulation circuit, the demodulation circuit, the logic circuit, and the memory circuit are provided over the same insulating substrate. In any one of Claims 1 thru | or 8 ,
The modulation circuit, the demodulation circuit, the logic circuit, and the memory circuit are integrally formed on a first insulating substrate,
The semiconductor device is characterized in that the antenna circuit is provided on a second insulating substrate.

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