JP2007201437A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption in a semiconductor device equipped with nonvolatile memory for storing specific information. <P>SOLUTION: This semiconductor device configures a nonvolatile memory circuit with a memory element which consists of an electric element 109 having a means for electrical conduction or insulation, a reset means 110 and a latch element 111. At wireless chip reset, the memory element stores different information in the latch element 111 depending on whether the electric element is an electrically conductive or insulated element. In this way, a low power consumption wireless chip can be produced with a nonvolatile memory mounted thereon inexpensively. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a semiconductor device for wireless communication. In particular, the present invention relates to a semiconductor device that supplies a power supply voltage generated from a wireless communication signal to a circuit formed using a semiconductor thin film transistor.

In recent years, small semiconductor devices (hereinafter referred to as wireless chips) in which an ultra-small IC chip and an antenna for wireless communication are combined are in the spotlight. The wireless chip can perform data writing and data reading by exchanging communication signals using a wireless communication device (hereinafter referred to as a reader / writer).

As an application field of the wireless chip, for example, merchandise management in the distribution industry can be cited. At present, merchandise management using bar codes and the like is the mainstream, but since bar codes are optically read, data cannot be read if there is a shield. On the other hand, since the wireless chip reads data wirelessly, it can be read even if there is a shield if radio waves can pass through. Accordingly, it is expected to improve the efficiency of product management and cost reduction. In addition, a wide range of applications such as a boarding ticket, an air passenger ticket, and automatic fee settlement are expected (see, for example, Patent Document 1).

JP 2005-209162 A

In the application field of the wireless chip as described above, a nonvolatile memory device that stores unique information in the wireless chip is necessary. The unique information is, for example, a unique number or a secret key for encrypted communication. Such a nonvolatile memory device can be roughly classified into a nonvolatile memory device using a writing method during manufacturing and a nonvolatile memory device using a writing method after manufacturing depending on a method for storing unique information.

As a nonvolatile memory device using a method of writing during manufacture, there is a nonvolatile memory device called a mask ROM. This uses a different photomask for each wireless chip in the nonvolatile memory device. On the other hand, as a nonvolatile memory device using a method of writing after manufacture, there is an electrically writable nonvolatile memory device called EPROM. In this method, the unique information is written into the EPROM by using a writing device. In this case, it is easy to store unique information different for each wireless chip in the nonvolatile storage device without changing the photomask.

In these nonvolatile memory devices, in order to extract stored information, an address signal, a read signal, or the like is input, an electric signal is extracted from the corresponding memory element, and a high potential signal or a low potential signal is detected using a sense amplifier or the like. The output information of the high potential signal (hereinafter referred to as “H” level or simply “H”, and the low potential signal as “L” level or simply “L”) is read. In such a nonvolatile storage device, a specific time is required after reading is requested until necessary information is read. Therefore, in order to mount such a nonvolatile memory device on a semiconductor device, a design in consideration of the delay is required. In addition, the sense amplifier consumes a large amount of current, leading to an increase in current consumption of the entire semiconductor device. Further, in such a nonvolatile memory device, since the number of read bits is determined, it is necessary to read other unnecessary information even when reading only one bit. This further increases the current consumption in the semiconductor device.

In view of such a problem, an object of the present invention is to reduce power consumption of a semiconductor device including a nonvolatile memory device that stores unique information. Another object of the present invention is to reduce the influence of a delay time until information is read from a nonvolatile memory device in the semiconductor device.

In the wireless chip of the present invention, a nonvolatile memory circuit is configured by a memory element including an electric element having means for electrically conducting or insulating, a reset element, and a latch element. In the memory element, information is stored in the latch element by the reset element and the electric element when the wireless chip is reset. This information becomes “H” or “L” depending on whether or not the electric element is electrically insulated. Electrical elements can be electrically insulated by mechanical cutting with laser drawing, electrical resistance that can be electrically insulated by applying overcurrent, diodes, phase change memory, There may be a memory transistor having a floating gate, a memory transistor having a MONOS structure, and the like.

With the above structure, a low-power consumption wireless chip mounted with a nonvolatile memory device can be provided at low cost. In addition, information stored in the nonvolatile memory device can be read without requiring a special circuit for reading such as a sense amplifier, and an increase in the circuit scale of the nonvolatile memory device can be suppressed. A wireless chip mounted with a nonvolatile memory device with a small area and low power consumption can be provided.

The structure of the present invention disclosed in this specification is a semiconductor device on which a nonvolatile memory device including a memory element including an electric element, a reset element, and a latch element is mounted, and the electric element is electrically Depending on whether it is conductive or insulated, it has means for storing different information in the latch element by the reset element.

In the above structure, the electrical element may be electrically insulated by being mechanically cut by laser drawing.

In the above structure, the electric element may be electrically insulated by applying an overcurrent and thermally destroying the element.

Further, in the above configuration, the electrical element is composed of a first diode and a second diode, and is electrically connected by applying an overcurrent to at least one of the diodes and thermally destroying it. This may be a feature.

In the above configuration, the electric element may be configured by a phase change memory in which an electric resistance value changes due to a phase change.

In the above structure, the electric element may be a nonvolatile memory transistor having a floating gate.

In the above structure, the electric element may be a memory transistor having a MONOS structure.

In the above structure, the semiconductor device may be formed using a thin film transistor using a semiconductor thin film formed over a substrate having an insulating surface as an active layer.

In the above structure, the substrate having an insulating surface may be any of a glass substrate, a quartz substrate, a plastic substrate, and an SOI substrate.

According to the present invention, a low-power consumption and high-performance wireless chip equipped with a nonvolatile memory device can be provided at low cost.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
A first embodiment of a wireless chip according to the present invention will be described with reference to FIG. FIG. 1 is a circuit diagram of a memory element of a nonvolatile memory device mounted on a wireless chip according to the present invention.

In FIG. 1, 101 is a power supply terminal, 102 is a ground terminal, 103 is a reset terminal, 104 is an output terminal, 105 is a P-type transistor, 107 is a first inverter, 108 is a second inverter, and 109 is an electric element. . The P-type transistor 105 constitutes the reset element 110. The source terminal of the P-type transistor 105 is connected to the power supply terminal 101, the drain terminal is connected to the output terminal 104, and the gate terminal is connected to the reset terminal 103. The first inverter 107 and the second inverter 108 constitute a latch element 111.

The electrical element is an electrical resistance that can be electrically insulated by mechanical cutting by laser drawing, an electrical resistance or diode that can be electrically insulated by application of overcurrent, a phase change memory, There may be a memory transistor having a floating gate, a memory transistor having a MONOS structure, and the like.

Next, the operation of the memory element will be described. First, consider the case where the electrical element 109 is electrically conductive. Here, it is assumed that the electric resistance of the electric element 109 is higher than the source-drain resistance of the P-type transistor 105. First, “L” is applied to the reset terminal 103 when the wireless chip is reset. Since the P-type transistor 105 is electrically conductive, “H” is output to the output terminal 104. At the same time, “H” is held in the latch element 111. After that, when “H” is applied to the reset terminal 103, the P-type transistor 105 is electrically insulated, and “L” is output to the output terminal 104 due to the electric resistance of the electric element 109. At the same time, the information held in the latch element 111 changes from “H” to “L”. When the wireless chip is operating, if “H” is kept at the reset terminal 103 as it is, “L” is always output from the output terminal 104.

On the other hand, consider a case where the electrical element 109 is electrically insulated. Here, “L” is applied to the reset terminal 103 when the wireless chip is reset. Since the P-type transistor 105 is electrically conductive, “H” is output to the output terminal 104. At the same time, “H” is held in the latch element 111. Thereafter, when “H” is applied to the reset terminal 103, the P-type transistor 105 is electrically insulated. Here, since the electric element 109 is electrically insulated, the information held in the latch element 111 remains “H”. Accordingly, “H” remains output to the output terminal 104. When the wireless chip is operating, if “H” is kept at the reset terminal 103 as it is, “H” is always output from the output terminal 104.

As described above, the output of the memory element can be set to “H” or “L” depending on whether the electric element in the memory element is electrically insulated or conductive. Further, only “L” is applied to the reset terminal 103 at the beginning of the circuit operation, and no access time is required for subsequent reading. And no special circuit such as a sense amplifier is required.

In this embodiment, the electric element 109 is connected between the ground terminal 102 and the output terminal 104, the source terminal of the P-type transistor 105 is the power supply terminal 101, the drain terminal is the output terminal 104, and the gate terminal is the reset terminal. 103, the electrical elements are connected between the power supply terminal 101 and the output terminal 104, the source terminal of the N-type transistor is connected to the ground terminal 102, the drain terminal is output to the output terminal 104, and the gate terminal is reset. It is good also as a structure connected to the terminal 103, respectively. In this case, if “H” is applied to the reset terminal 103 at the time of resetting, the output of the memory element is set to “L” or “H” depending on whether the electric element is electrically insulated or conductive. be able to.

With the above structure, a low-power consumption wireless chip mounted with a nonvolatile memory device can be provided at low cost. In addition, information stored in the nonvolatile memory device can be read without requiring a special circuit for reading such as a sense amplifier, and an increase in the circuit scale of the nonvolatile memory device can be suppressed. A wireless chip mounted with a nonvolatile memory device with a small area and low power consumption can be provided.

(Embodiment 2)
As a second embodiment of the wireless chip in the present invention, a wireless chip having a configuration different from that of the first embodiment will be described with reference to FIG. FIG. 2 is a circuit diagram of a memory element of the nonvolatile memory device mounted on the wireless chip in the present invention.

In FIG. 2, a power supply terminal 101, a ground terminal 102, a reset terminal 103, an output terminal 104, a P-type transistor 105, an N-type transistor 106, a first inverter 107, a second inverter 108, and an electric element 109 are shown. The P-type transistor 105 and the N-type transistor 106 constitute a reset element 210. The source terminal of the P-type transistor 105 is connected to the power supply terminal 101, the drain terminal is connected to the output terminal 104, and the gate terminal is connected to the reset terminal 103. The N-type transistor 106 has a source terminal connected to the ground terminal 102 and a gate terminal connected to the reset terminal 103. One of the two terminals of the electric element 109 is connected to the drain terminal and the output terminal 104 of the P-type transistor, and the other is connected to the drain terminal of the N-type transistor 106. The first inverter 107 and the second inverter 108 constitute a latch element 111.

The electric element 109 includes an electric resistance that can be electrically insulated by mechanical cutting by laser drawing, an electric resistance or diode that can be electrically insulated by application of overcurrent, and a phase change memory. There may be a memory transistor having a floating gate, a memory transistor having a MONOS structure, and the like.

Next, the operation of the memory element will be described. First, consider the case where the electrical element 109 is electrically conductive. In FIG. 2, “L” is applied to the reset terminal 103 when the wireless chip is reset. Since the P-type transistor 105 is electrically conductive and the N-type transistor 106 is electrically insulated, “H” is output to the output terminal 104. At the same time, “H” is held in the latch element 111. After that, when “H” is applied to the reset terminal 103, the P-type transistor 105 is electrically insulated and the N-type transistor 106 is electrically conducted, so that “L” is output to the output terminal 104. At the same time, the information held in the latch element 111 changes from “H” to “L”. When the wireless chip is operating, if “H” is kept at the reset terminal 103 as it is, “L” is always output from the output terminal 104.

On the other hand, consider a case where the electrical element 109 is electrically insulated. Here, “L” is applied to the reset terminal 103 when the wireless chip is reset. Since the P-type transistor 105 is electrically conductive and the N-type transistor 106 is electrically insulated, “H” is output to the output terminal 104. At the same time, “H” is held in the latch element 111. After that, when “H” is applied to the reset terminal 103, the P-type transistor 105 is electrically insulated and the N-type transistor 106 is electrically conducted. Here, since the electric element 109 is electrically insulated, the information held in the latch element 111 remains “H”. Accordingly, “H” remains output to the output terminal 104. When the wireless chip is operating, if “H” is kept at the reset terminal 103 as it is, “H” is always output from the output terminal 104.

As described above, the output of the memory element can be set to “H” or “L” depending on whether the electric element in the memory element is electrically insulated or conductive. Further, only “L” is applied to the reset terminal 103 at the beginning of the circuit operation, and at the time of subsequent reading, no access time is required for reading information, and no special circuit such as a sense amplifier is required.

In the present embodiment, the configuration in which the electric element 109 is connected between the N-type transistor 106 and the output terminal 104 is shown; however, the configuration in which the electric element is connected between the P-type transistor 105 and the output terminal 104 is shown. It is good. In this case, the output of the memory element can be “L” or “H” depending on whether the electric element is electrically insulated or conductive.

In the memory element constituting the nonvolatile memory device mounted on the wireless chip in this embodiment, the through current at the time of reset can be significantly reduced as compared with the first embodiment, so that further lower power consumption Is possible.

With the above structure, a low-power consumption wireless chip mounted with a nonvolatile memory device can be provided at low cost. In addition, information stored in the nonvolatile memory device can be read without requiring a special circuit for reading such as a sense amplifier, and an increase in the circuit scale of the nonvolatile memory device can be suppressed. A wireless chip mounted with a nonvolatile memory device with a small area and low power consumption can be provided.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

In this example, an example of an electric element included in the nonvolatile memory device mounted on the wireless chip of the present invention described in Embodiment Modes 1 and 2 is described with reference to FIGS.

FIG. 3A illustrates an example in which an electrical element is configured using the electrical resistance 301. The first terminal 302 and the second terminal 303 are electrically connected to the output terminal 104 and the ground terminal 102 in FIG. 1 described in Embodiment 1, respectively. In FIG. 2 described in Embodiment Mode 2, the output terminal 104 and the N-type transistor 106 are electrically connected to each other.

The electrical resistor 301 is provided with a region to be mechanically cut by laser drawing, and enables electrical insulation by cutting the region by laser drawing. Further, an overcurrent is applied between the first terminal 302 and the second terminal 303 to cause thermal breakdown, thereby enabling electrical insulation. As the electrical resistance 301, a metal thin film, a conductive semiconductor thin film, a conductive organic thin film, or the like can be used. Further, a phase change memory in which an electric resistance value changes due to a phase change may be used as the electric resistance 301. By using the phase change memory, information stored in the nonvolatile memory device mounted on the wireless chip in the present invention can be rewritten many times, so that the wireless chip can have high functionality.

In this embodiment, the example in which the electrical insulation is performed by cutting the electrical resistor 301 has been described. However, the electrical insulation performed in the present invention is not limited to this configuration. It is sufficient that the ground terminal 102 can be electrically insulated from the output terminal 104 and the reset element 110. Therefore, for example, the electrical element 109 and the ground terminal 102 may be electrically insulated, or the electrical element 109 and the reset terminal 103 and the output terminal 104 may be electrically insulated.

By configuring the electric element with an electric resistance, a wireless chip mounted with a nonvolatile memory device can be provided without increasing the layout area.

FIG. 3B illustrates an example in which an electrical element is formed using the first diode 311 and the second diode 312. The first terminal 313 and the second terminal 314 are electrically connected to the output terminal 104 and the ground terminal 102 in FIG. 1 described in Embodiment 1, respectively. In FIG. 2 described in Embodiment Mode 2, the output terminal 104 and the N-type transistor 106 are electrically connected to each other.

The first terminal 313 and the second terminal 314 are electrically insulated in the initial state. Here, when a high voltage is applied to the first terminal 313, the first diode 311 is thermally destroyed and becomes electrically conductive. At this time, when the first terminal 313 is set to a higher potential than the second terminal 314, the first terminal 313 and the second terminal 314 are electrically connected.

By forming the electrical element with a diode, the through current during operation can be significantly reduced, so that it is possible to provide a wireless chip with a lower current consumption mounted with a nonvolatile memory device.

FIG. 3C illustrates an example in which an electric element is formed using a floating gate memory transistor 321. Here, an example of an N-type memory transistor is considered as the floating gate type memory transistor 321, but a P-type memory transistor is also possible. In addition to the floating gate type memory transistor, a MONOS type memory transistor can be used as well.

The first terminal 322, the second terminal 323, and the third terminal 324 are electrically connected to the output terminal 104, the ground terminal 102, and the reset terminal 103 in FIG. 1 described in Embodiment 1, respectively. In FIG. 2 described in Embodiment Mode 2, the output terminal 104, the N-type transistor 106, and the reset terminal 103 are electrically connected to each other.

The floating gate type memory transistor 321 can change the threshold voltage according to the amount of charge accumulated in the floating gate. That is, it can be electrically insulated when the threshold voltage is high and electrically conductive when the threshold voltage is low.

For example, the floating gate type memory transistor 321 increases the threshold voltage by grounding the first terminal 322 and the second terminal 323 and applying a high voltage to the third terminal 324, that is, electric Can be electrically insulated. In addition, the first terminal 322 and the second terminal 323 are grounded, and a negative high voltage is applied to the third terminal 324, so that the threshold voltage is lowered, that is, electrically connected. Can do.

By configuring the electrical element with a floating gate type memory transistor, it can be rewritten many times and the through current during operation can be greatly reduced. It is possible to provide a chip.

With the above structure, a low-power consumption wireless chip mounted with a nonvolatile memory device can be provided at low cost. In addition, information stored in the nonvolatile memory device can be read without requiring a special circuit for reading such as a sense amplifier, and an increase in the circuit scale of the nonvolatile memory device can be suppressed. A wireless chip mounted with a nonvolatile memory device with a small area and low power consumption can be provided.

In this embodiment, as an example of a semiconductor device of the present invention, a wireless chip having a cryptographic processing function will be described with reference to FIGS. 16 is a block diagram of the wireless chip, and FIG. 17 is a layout diagram of the wireless chip.

First, a block configuration of a wireless chip is described with reference to FIG. In FIG. 16, the wireless chip 2601 includes a CPU 2602, a ROM 2603, a RAM 2604, a controller 2605, an arithmetic circuit 2606, an antenna 2607, a resonance circuit 2608, a power supply circuit 2609, a reset circuit 2610, and a clock generator. An analog portion 2615 including a circuit 2611, a demodulation circuit 2612, a modulation circuit 2613, and a power management circuit 2614 is included.
The controller 2605 includes a CPU interface (IF) 2616, a control register 2617, a code extraction circuit 2618, and an encoding circuit 2619. Note that in FIG. 16, for simplification of description, the communication signal is illustrated as being divided into a reception signal 2620 and a transmission signal 2621, but in actuality, both are superimposed, and the wireless chip 2601 and the reader / writer are overlapped. Are sent and received at the same time. Received signal 2620 is received by antenna 2607 and resonant circuit 2608, and then demodulated by demodulation circuit 2612. Further, the transmission signal 2621 is modulated by the modulation circuit 2613 and then transmitted from the antenna 2607.

In FIG. 16, when the wireless chip 2601 is placed in a magnetic field formed by a communication signal, an induced electromotive force is generated by the antenna 2607 and the resonance circuit 2608. The induced electromotive force is held by an electric capacity in the power supply circuit 2609, and the potential is stabilized by the electric capacity, and is supplied as a power supply voltage to each circuit of the wireless chip 2601. The reset circuit 2610 generates an initial reset signal for the entire wireless chip 2601.

For example, a signal that rises after a rise in the power supply voltage is generated as a reset signal. The clock generation circuit 2611 changes the frequency and duty ratio of the clock signal in accordance with the control signal generated by the power management circuit 2614. The demodulation circuit 2612 detects the fluctuation of the amplitude of the reception signal 2620 of the ASK method (amplitude modulation method) as the reception data 2622 of “0” / “1”. The demodulation circuit 2612 is a low-pass filter, for example.

Further, the modulation circuit 2613 transmits the transmission data by changing the amplitude of the ASK transmission signal 2621. For example, when the transmission data 2623 is “0”, the resonance point of the resonance circuit 2608 is changed, and the amplitude of the communication signal is changed. The power management circuit 2614 monitors the power supply voltage supplied from the power supply circuit 2609 to the arithmetic circuit 2606 or the current consumption in the arithmetic circuit 2606, and a control signal for changing the frequency and duty ratio of the clock signal in the clock generation circuit 2611. Is generated.

The operation of the wireless chip in this embodiment will be described. First, the wireless chip 2601 receives a reception signal 2620 including ciphertext data transmitted from the reader / writer. The received signal 2620 is demodulated by the demodulation circuit 2612, decomposed into a control command, ciphertext data, and the like by the code extraction circuit 2618 and stored in the control register 2617. Here, the control command is data specifying a response of the wireless chip 2601. For example, transmission of a unique ID number, operation stop, and decryption are designated. Here, it is assumed that a decryption control command is received.

Subsequently, in the arithmetic circuit 2606, the CPU 2602 decrypts (decrypts) the ciphertext using the secret key 2624 stored in advance in the ROM 2603 according to the decryption program stored in the ROM 2603.

The decrypted ciphertext (decrypted text) is stored in the control register 2617. At this time, the RAM 2604 is used as a data storage area. Note that the CPU 2602 accesses the ROM 2603, the RAM 2604, and the control register 2617 via the CPUIF 2616. The CPU IF 2616 has a function of generating an access signal for any of the ROM 2603, the RAM 2604, and the control register 2617 from an address requested by the CPU 2602.

Finally, in the encoding circuit 2619, transmission data 2623 is generated from the decoded text, the transmission data 2623 is modulated by the modulation circuit 2613, and the transmission signal 2621 is transmitted from the antenna 2607 to the reader / writer.

In this embodiment, as a calculation method, a method of processing by software, that is, a method of configuring a calculation circuit with a CPU and a large-scale memory and executing a program by the CPU has been described. It is also possible to select an appropriate calculation method and configure the calculation circuit based on the method. For example, as a calculation method, other methods such as a method of processing the operation in hardware and a method of using both hardware and software are conceivable. In the method of processing in hardware, an arithmetic circuit may be configured with a dedicated circuit. In the method using both hardware and software, a dedicated circuit, a CPU, and a memory constitute an arithmetic circuit, a part of the arithmetic processing is performed by the dedicated circuit, and the remaining arithmetic processing program is executed by the CPU. .

Next, the layout configuration of the wireless chip is described with reference to FIG. In FIG. 17, parts corresponding to those in FIG. 16 are denoted by the same reference numerals and description thereof is omitted.

In FIG. 17, an FPC pad 2707 is an electrode pad group used when an FPC (Flexible Print Circuit) is attached to the wireless chip 2601, and an antenna bump 2708 is an electrode pad for attaching an antenna (not shown). Note that when the antenna is attached, excessive pressure may be applied to the antenna bump 2708. Therefore, it is desirable not to dispose a component such as a transistor under the antenna bump 2708.

Note that in this embodiment, a configuration in which an antenna is externally described is described; however, a so-called on-chip antenna in which an antenna is directly formed over the wireless chip 2601 may be used. In this case, it is effective for miniaturization of the wireless chip.

The FPC pad 2707 is effective when used mainly for failure analysis. In the wireless chip, since the power supply voltage is obtained from the communication signal, for example, when a failure occurs in the antenna or the power supply circuit, the arithmetic circuit does not operate at all. For this reason, failure analysis becomes extremely difficult. However, the power supply voltage is supplied from the FPC to the wireless chip 2601 through the FPC pad 2707, and the arithmetic circuit is operated by inputting an arbitrary electric signal instead of the electric signal supplied from the antenna. Is possible. Therefore, failure analysis can be performed efficiently.

Furthermore, it is more effective to arrange the FPC pad 2707 so that measurement using a prober is possible. That is, in the FPC pad 2707, the electrode pad is arranged in accordance with the pitch of the prober needle, whereby measurement by the prober becomes possible. By using a prober, it is possible to reduce the number of steps for attaching the FPC during failure analysis. Further, since measurement can be performed even when a plurality of wireless chips are formed on a substrate, the number of steps for dividing each wireless chip can be reduced. In addition, it is possible to perform a non-defective inspection of the wireless chip immediately before the step of attaching the antenna during mass production. Accordingly, defective products can be selected at an early stage of the process, so that production costs can be reduced.

Note that the nonvolatile memory device including the electric elements described in Embodiment Mode 1, Embodiment Mode 2, and Example 1 can be incorporated in the ROM 2603 in this embodiment.

In this embodiment, the case where the semiconductor device of the present invention is formed using a thin film transistor (TFT) will be described with reference to FIGS.

FIG. 5A is a cross-sectional view of the TFT portion 1101 and the memory portion 1102 formed over the insulating substrate 1110. The TFT portion 1101 is preferably used for a transistor in an arithmetic circuit, for example. The memory unit 1102 is preferably used for a memory element of a nonvolatile memory, for example. As the insulating substrate 1110, a glass substrate, a quartz substrate, a substrate made of silicon, a metal substrate, a plastic substrate, or the like can be used.

In the case where a glass substrate is used, a thinned and polished surface opposite to the side on which the TFT or the like is formed can be used. Such a thin glass substrate can achieve a reduction in weight and thickness of the apparatus.

A base film 1111 is provided over the insulating substrate 1110. Thin film transistors 1120 and 1121 are provided in the TFT portion 1101 through a base film 1111, and thin film transistors 1122 are provided in the memory portion 1102 through a base film 1111. Each thin film transistor includes a semiconductor film 1112 processed into an island shape, a gate electrode 1114 provided via a gate insulating film, and an insulator (so-called sidewall) 1113 provided on a side surface of the gate electrode. The semiconductor film 1112 is formed to have a thickness of 0.2 μm or less, typically 40 nm to 170 nm, preferably 50 nm to 150 nm. Further, an insulating film (sidewall) 1113, an insulating film 1116 covering the semiconductor film 1112, and an electrode 1115 connected to the impurity region formed in the semiconductor film 1112 are included. Note that a contact hole is formed in the gate insulating film and the insulating film 1116, a conductive film is formed in the contact hole, and the conductive film is processed into a desired shape, so that the electrode 1115 connected to the impurity region is formed. be able to.

In the thin film transistor included in the wireless chip of the present invention, an insulating film such as a gate insulating film can be manufactured using high-density plasma treatment. The high-density plasma treatment means that the plasma density is 1 × 10 ¹¹ cm ⁻³ or more, preferably 1 × 10 ¹¹ cm ⁻³ to 9 × 10 ¹⁵ cm ⁻³ , such as a microwave (for example, a frequency of 2.45 GHz). This is plasma processing using high frequency. When plasma is generated under such conditions, the low electron temperature is changed from 0.2 eV to 2 eV. As described above, high-density plasma characterized by low electron temperature has low kinetic energy of active species, and thus can form a film with less plasma damage and fewer defects. In the film formation chamber capable of such plasma treatment, a substrate on which a semiconductor film processed into a desired shape is formed in the case where an object to be formed and a gate insulating film are formed. Then, a film forming process is performed with a distance between an electrode for plasma generation, a so-called antenna, and an object to be formed being 20 mm to 80 mm, preferably 20 mm to 60 mm. Such a high-density plasma treatment can realize a low-temperature process (substrate temperature of 400 ° C. or lower). Therefore, a plastic having low heat resistance can be formed on the substrate.

Such an insulating film can be formed in a nitrogen atmosphere or an oxygen atmosphere. The nitrogen atmosphere is typically a mixed atmosphere of nitrogen and a rare gas, or a mixed atmosphere of nitrogen, hydrogen, and a rare gas. As the rare gas, at least one of helium, neon, argon, krypton, and xenon can be used. The oxygen atmosphere is typically a mixed atmosphere of oxygen and a rare gas, a mixed atmosphere of oxygen, hydrogen, and a rare gas, or a mixed atmosphere of dinitrogen monoxide and a rare gas. As the rare gas, at least one of helium, neon, argon, krypton, and xenon can be used.

The insulating film formed in this way has little damage to other films and becomes dense. In addition, an insulating film formed by high-density plasma treatment can improve an interface state in contact with the insulating film. For example, when the gate insulating film is formed using high-density plasma treatment, the interface state with the semiconductor film can be improved. As a result, the electrical characteristics of the thin film transistor can be improved.

Although the case where high-density plasma treatment is used for manufacturing the insulating film has been described, the semiconductor film may be subjected to high-density plasma treatment. The semiconductor film surface can be modified by high-density plasma treatment. As a result, the interface state can be improved, and the electrical characteristics of the thin film transistor can be improved.

In order to improve flatness, insulating films 1117 and 1118 are preferably provided. At this time, the insulating film 1117 is preferably formed from an organic material, and the insulating film 1118 is preferably formed from an inorganic material. In the case where the insulating films 1117 and 1118 are provided, the electrode 1115 can be formed so as to be connected to the impurity regions through the contact holes in the insulating films 1117 and 1118.

Further, an insulating film 1125 is provided, and a lower electrode 1127 is formed so as to be connected to the electrode 1115. An insulating film 1128 is formed which covers an end portion of the lower electrode 1127 and has an opening so that the lower electrode 1127 is exposed. A memory material layer 1129 is formed in the opening, and an upper electrode 1130 is formed. In this manner, the memory element 1123 having the lower electrode 1127, the memory material layer 1129, and the upper electrode 1130 is formed.

The memory material layer 1129 is formed of an organic compound whose conductivity is changed by an electric effect or an optical effect, an inorganic insulator, or a layer formed by mixing an organic compound and an inorganic compound. The memory material layer 1129 may be a single layer or a stack of a plurality of layers. Alternatively, a mixed layer of an organic compound and an inorganic compound and a layer formed of an organic compound whose conductivity is changed by another electric action or optical action may be provided.

As the inorganic insulator that can form the memory material layer 1129, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like can be used.

As an organic insulator that can form the memory material layer 1129, an organic resin typified by polyimide, acrylic, polyamide, benzocyclobutene, epoxy, or the like can be used.

Further, as an organic compound that can form the memory material layer 1129 and whose conductivity is changed by an electric action or an optical action, an organic compound material having a high hole-transport property or an organic compound material having a high electron-transport property can be used. Can be used.

As an organic compound material having a high hole-transport property, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD), 4,4′-bis [ N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) or 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA) ), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) and 4,4′-bis (N- (4- (N, N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond) and phthalocyanines (abbreviation: H ₂ Pc), copper phthalo Phthalocyanine compounds such as cyanine (abbreviation: CuPc) and vanadyl phthalocyanine (abbreviation: VOPc) can be used. The substances described here are mainly substances having a hole mobility of 10 ⁻⁶ cm ² / Vs or higher. Note that other than the above substances, any substance that has a property of transporting more holes than electrons may be used.

  As an inorganic compound material that easily receives electrons, a metal oxide, metal nitride, or metal oxynitride of a transition metal in any of Groups 4 to 12 of the periodic table can be used. Specifically, titanium oxide (TiOx), zirconium oxide (ZrOx), vanadium oxide (VOx), molybdenum oxide (MoOx), tungsten oxide (WOx), tantalum oxide (TaOx), hafnium oxide (HfOx), niobium oxide (NbOx), cobalt oxide (CoOx), rhenium oxide (ReOx), ruthenium oxide (RuOx), zinc oxide (ZnO), nickel oxide (NiOx), copper oxide ( CuOx) or the like can be used. In addition, although metal oxides are given as specific examples here, it is of course possible to use nitrides or oxynitrides of these metals.

As an organic compound material having a high electron-transport property, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [ h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc., and a metal complex having a quinoline skeleton or a benzoquinoline skeleton Materials can be used. In addition, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) A material such as a metal complex having an oxazole-based or thiazole-based ligand such as ₂ ) can also be used. In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can be used. The substances mentioned here are mainly substances having an electron mobility of 10 ⁻⁶ cm ² / Vs or higher. Note that other than the above substances, any substance that has a property of transporting more electrons than holes may be used.

  As the inorganic compound material that easily gives electrons, alkali metal oxides, alkaline earth metal oxides, rare earth metal oxides, alkali metal nitrides, alkaline earth metal nitrides, and rare earth metal nitrides can be used. Specifically, lithium oxide (LiOx), strontium oxide (SrOx), barium oxide (BaOx), erbium oxide (ErOx), sodium oxide (NaOx), lithium nitride (LiNx), magnesium nitride (MgNx), calcium nitride (CaNx), yttrium nitride (YNx), lanthanum nitride (LaNx), or the like can be used.

  Furthermore, as an inorganic compound material, aluminum oxide (AlOx), gallium oxide (GaOx), silicon oxide (SiOx), germanium oxide (GeOx), indium tin oxide (hereinafter referred to as ITO), etc., Various metal oxides, metal nitrides or metal oxynitrides can be used.

  In the case where the memory material layer 1129 is formed of a compound selected from metal oxides or metal nitrides and a compound having a high hole-transport property, the steric hindrance is further increased (unlike a planar structure, three-dimensional A structure in which a compound (having a structure having a wide spread) is added may be used. As the compound having a large steric hindrance, 5,6,11,12-tetraphenyltetracene (abbreviation: rubrene) is preferable. However, besides this, hexaphenylbenzene, t-butylperylene, 9,10-di (phenyl) anthracene, coumarin 545T, and the like can also be used. In addition, dendrimers and the like are also effective.

Furthermore, 4-dicyanomethylene-2-methyl-6- [2- (1,1) is formed between a layer formed of an organic compound material having a high electron-transport property and an organic compound material layer having a high hole-transport property. 1,7,7-tetramethyljulolidyl-9-yl) ethenyl] -4H-pyran (abbreviation: DCJT), 4-dicyanomethylene-2-t-butyl-6- (1,1,7,7- Tetramethyljulolidyl-9-enyl) -4H-pyran, periflanthene, 2,5-dicyano-1,4-bis [2- (10-methoxy-1,1,7,7-tetramethyljulolidine-9 -Yl) ethenyl] benzene, N, N′-dimethylquinacridone (abbreviation: DMQd), coumarin 6, coumarin 545T, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), 9,9′-bianthryl, 9,10 -Luminescent substances such as diphenylanthracene (abbreviation: DPA), 9,10-bis (2-naphthyl) anthracene (abbreviation: DNA), 2,5,8,11-tetra-t-butylperylene (abbreviation: TBP) It may be provided.

For the memory material layer 1129, a material whose electrical resistance changes by an optical action can be used. For example, a conjugated polymer doped with a compound that generates an acid by absorbing light (a photoacid generator) can be used. As the conjugated polymer, polyacetylenes, polyphenylene vinylenes, polythiophenes, polyanilines, polyphenylene ethynylenes, and the like can be used. As the photoacid generator, arylsulfonium salts, aryliodonium salts, o-nitrobenzyl tosylate, arylsulfonic acid p-nitrobenzyl esters, sulfonylacetophenones, Fe-allene complex PF ₆ salts, and the like can be used. .

  Note that the memory material layer 1129 includes a phase change of a material that reversibly changes between a crystalline state and an amorphous state or a material that reversibly changes between a first crystalline state and a second crystalline state. Materials can also be used. It is also possible to use a material that changes only from an amorphous state to a crystalline state.

Materials that reversibly change between a crystalline state and an amorphous state include germanium (Ge), tellurium (Te), antimony (Sb), sulfur (S), tellurium oxide (TeOx), tin (Sn), A material having a plurality of materials selected from gold (Au), gallium (Ga), selenium (Se), indium (In), thallium (Tl), Co (cobalt), and silver (Ag), for example, Ge-Te _{-Sb-S, Te-TeO 2} -Ge-Sn, Te-Ge-Sn-Au, Ge-Te-Sn, Sn-Se-Te, Sb-Se-Te, Sb-Se, Ga-Se-Te, Ga-Se-Te-Ge, In-Se, In-Se-Tl-Co, Ge-Sb-Te, In-Se-Te, and Ag-In-Sb-Te-based materials can be given. The materials that reversibly change between the first crystal state and the second crystal state are silver (Ag), zinc (Zn), copper (Cu), aluminum (Al), nickel (Ni), A material having a plurality of materials selected from indium (In), antimony (Sb), selenium (Se), and tellurium (Te). For example, Ag—Zn, Cu—Al—Ni, In—Sb, In—Sb— Se and In-Sb-Te are mentioned. In this material, the phase change takes place between two different crystalline states. The material that changes only from the amorphous state to the crystalline state is selected from tellurium (Te), tellurium oxide (TeOx), palladium (Pd), antimony (Sb), selenium (Se), and bismuth (Bi). For example, Te—TeO ₂ , Te—TeO ₂ —Pd, and Sb ₂ Se ₃ / Bi ₂ Te ₃ can be given.

  The memory material layer 1129 can be formed by an evaporation method, an electron beam evaporation method, a sputtering method, a CVD method, or the like. Moreover, the mixed layer containing an organic compound and an inorganic compound can be formed by simultaneously forming the respective materials. The co-evaporation method using resistance heating evaporation, the co-evaporation method using electron beam evaporation, and resistance heating. It can be formed by a combination of the same or different methods such as co-evaporation by vapor deposition and electron beam vapor deposition, film formation by resistance heating vapor deposition and sputtering, and film formation by electron beam vapor deposition and sputtering.

Note that the memory material layer 1129 is formed to a thickness at which the conductivity of the memory element is changed by an electric action or an optical action.

The lower electrode 1127 or the upper electrode 1130 can be formed of a conductive material. For example, it can be formed of a film made of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), or silicon (Si), or an alloy film using these elements. In addition, light transmission of indium tin oxide (ITO), indium tin oxide containing silicon oxide, oxide conductive material formed using a target in which indium oxide is mixed with 2 to 20 wt% zinc oxide (ZnO), etc. Can be used.

In addition, an insulating film 1131 is preferably formed in order to improve planarity and prevent an impurity element from entering.

For the insulating film described in this embodiment, an inorganic material or an organic material can be used. As the inorganic material, silicon oxide or silicon nitride can be used. As the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or polysilazane can be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Polysilazane is formed using a polymer material having a bond of silicon (Si) and nitrogen (N) as a starting material.

FIG. 5B is a cross-sectional view of a memory in which a memory material layer is formed in the contact hole 1151 of the electrode 1115 unlike FIG. 5A. As in FIG. 5A, the memory element 1123 can be formed by using the electrode 1115 as the lower electrode and forming the memory material layer 1129 and the upper electrode 1130 over the electrode 1115. After that, an insulating film 1131 is formed. The other structure in FIG. 5B is the same as that in FIG.

When the memory element is formed in the contact hole 1151 in this manner, the memory element can be reduced in size. In addition, since a memory electrode is unnecessary, a manufacturing process can be reduced, and a wireless chip mounted with a memory can be provided at low cost.

As described above, a semiconductor device is composed of a thin film transistor using a semiconductor thin film formed on a substrate having an insulating surface such as a glass substrate, a quartz substrate, or a plastic substrate as an active layer, thereby achieving high performance and low power consumption. This semiconductor device can be provided at a lower weight and at a lower cost.

This embodiment can be implemented by being freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 1 and Embodiment Mode 2.

In this embodiment, a layout of a thin film transistor which forms part of a circuit in a semiconductor device of the present invention will be described with reference to FIGS.

A semiconductor layer corresponding to the semiconductor film 1112 described in Embodiment 3 is provided on the entire surface or part of a substrate having an insulating surface (a region having a larger area than that determined as a semiconductor region of a transistor) with a base film or the like interposed therebetween. Formed.
Then, a mask pattern is formed on the semiconductor layer by photolithography.
By etching the semiconductor layer using the mask pattern, an island-shaped semiconductor pattern 1201 having a specific shape including a source region, a drain region, and a channel formation region of the thin film transistor illustrated in FIG. 6 can be formed.

The shape of the patterned semiconductor layer is determined in consideration of the required circuit characteristics and appropriate layout based on the characteristics of the thin film transistor.

In the thin film transistor included in the circuit of the wireless chip of the present invention, the photomask for forming the semiconductor layer has a pattern.
This photomask pattern has corners and is rounded by removing a right triangle whose side is 10 μm or less.
The shape of the mask pattern can be transferred as a pattern shape of the semiconductor layer as shown in FIG.
In addition, when transferring to the semiconductor layer, the corner of the semiconductor pattern 1201 may be transferred so as to be more rounded than the corner of the photomask pattern. In other words, the corners of the semiconductor film pattern may be provided with roundness that is smoother than the photomask pattern. In FIG. 6, a gate electrode 1114, a gate wiring 1301, and an electrode 1115 that are formed later are indicated by dotted lines.

Next, a gate insulating film is formed over the semiconductor layer processed so that the corners are rounded.
Then, as shown in Embodiment 3, the gate electrode 1114 and the gate wiring 1301 are formed so as to partially overlap the semiconductor layer. The gate electrode or the gate wiring can be formed by a photolithography technique by forming a metal layer or a semiconductor layer.

The photomask for forming the gate electrode or the gate wiring has a pattern. This photomask pattern has corners, and one side of the right triangle formed at the corners is 10 μm or less, or 1/2 or less of the line width of the wiring, and 1/5 or more of the line width. The corner is deleted. The shape of the mask pattern can be transferred as a pattern shape of a gate electrode or a gate wiring as shown in FIG. Further, when transferring to the gate electrode or the gate wiring, the corner of the gate electrode or the gate wiring may be further rounded. That is, the corners of the gate electrode or the gate wiring may be provided with rounding with a smoother pattern shape than the photomask pattern.

The right-angled triangle with one side being 1/2 or less of the line width and 1/5 or more present at the corner of the gate electrode or gate wiring formed using such a photomask is removed, and the corner is rounded. Can be scared. Note that in FIG. 7, an electrode 1115 to be formed later is indicated by a dotted line.

Such a gate electrode or gate wiring is bent into a rectangle due to layout restrictions. Therefore, a rounded corner portion of the gate electrode or gate wiring is provided with a convex portion (outer side) and a concave portion (inner side). This rounded convex portion can suppress generation of fine powder due to abnormal discharge during dry etching by plasma. Also, in the rounded recess, even if there is fine powder that can be produced during washing, it can be washed away that it tends to collect at the corner. As a result, the yield can be improved.

Next, an insulating layer or the like corresponding to the insulating films 1116, 1117, and 1118 is formed over the gate electrode or the gate wiring as described in the third embodiment. Of course, in the present invention, the insulating film may be a single layer.

Over the insulating layer, an opening is formed in a predetermined position in the insulating film, and a wiring corresponding to the electrode 1115 is formed in the opening. This opening is provided in order to establish electrical connection between the semiconductor layer or gate wiring layer located in the lower layer and the wiring layer. The wiring is formed with a mask pattern by a photolithography technique and formed into a predetermined pattern by etching.

A certain element can be connected by wiring. This wiring does not connect a specific element with a straight line, but bends into a rectangle (hereinafter referred to as a bent portion) due to layout restrictions. In addition, the wiring width of the wiring may change in the opening and other regions. For example, in the opening, when the opening is equal to or larger than the wiring width, the wiring width is changed so as to widen at that portion. Further, since the wiring also serves as one electrode of the capacitor portion in the circuit layout, the wiring width may be increased.

In this case, in the bent portion of the photomask pattern, a right triangle having a side formed in the bent portion of 10 μm or less or 1/2 or less of the line width of the wiring and having a line width of 1/5 or more is deleted. . Then, as shown in FIG. 8, the wiring pattern is similarly rounded. One side existing at the corner of the wiring is ½ or less of the line width, and a right triangle of 1/5 or more can be deleted, and the bent portion can be rounded. In such rounded wiring, the convex part in the bent part suppresses the generation of fine powder due to abnormal discharge during dry etching by plasma, and in the concave part, even if it is fine powder made when cleaning, As a result of washing away the tendency to gather at the corner, the yield can be improved. When the corner of the wiring is rounded, it can be electrically conducted.

In the circuit having the layout shown in FIG. 8, the bend and the corner of the part where the wiring width changes are smoothed and rounded to suppress the generation of fine powder due to abnormal discharge during dry etching by plasma, Even if it is a fine powder which is made at the time of washing, it has the effect that the yield can be improved as a result of washing away that it tends to gather at the corner. That is, the problem of dust and fine powder in the manufacturing process can be solved. In addition, by adopting a configuration in which the corners of the wiring are rounded, electrical conduction can be achieved.
In particular, it is very advantageous to be able to wash away dust in wiring such as a drive circuit section provided with a large number of parallel wirings.

In the present embodiment, the three-layer layout of the semiconductor layer, the gate wiring, and the wiring has been described as having a rounded corner or bend, but the present invention is not limited to this. That is, in any one layer, it is only necessary to round the corners or the bent portions to solve problems such as dust and fine powder in the manufacturing process.

By configuring the semiconductor device using the layout as described above, a semiconductor device with high performance and low power consumption can be provided at a lower weight and at a lower cost.

Note that this embodiment can be implemented by being freely combined with Embodiment Mode 1, Embodiment Mode 2, and Embodiments 1 to 3.

In this embodiment, an example of forming a static RAM (SRAM) as one of the elements constituting the semiconductor device of the present invention will be described with reference to FIGS.

The semiconductor layers 1510 and 1511 illustrated in FIG. 9A are preferably formed using silicon or a crystalline semiconductor containing silicon as a component. For example, polycrystalline silicon or single crystal silicon obtained by crystallizing a silicon film by laser annealing or the like is applied. In addition, a metal oxide semiconductor, amorphous silicon, or an organic semiconductor that exhibits semiconductor characteristics can be used.

In any case, the semiconductor layer to be formed first is formed over the entire surface or part of the substrate having an insulating surface (a region having a larger area than that determined as a semiconductor region of the transistor). Then, a mask pattern is formed on the semiconductor layer by photolithography. By etching the semiconductor layer using the mask pattern, island-shaped semiconductor layers 1510 and 1511 having specific shapes including the source and drain regions and the channel formation region of the TFT are formed. The semiconductor layers 1510 and 1511 are determined in consideration of appropriate layout.

A photomask for forming the semiconductor layers 1510 and 1511 shown in FIG. 9A includes a mask pattern 1520 shown in FIG. The mask pattern 1520 differs depending on whether the resist used in the photolithography process is a positive type or a negative type. In the case of using a positive resist, the mask pattern 1520 shown in FIG. 9B is manufactured as a light shielding portion. The mask pattern 1520 has a shape obtained by deleting the top A of the polygon. Further, the bent portion B has a shape that is bent over a plurality of steps so that the corner portion does not become a right angle. In the photomask pattern, for example, the corners of the pattern (right triangles) are removed so that one side is 10 μm or less.

The shape of the mask pattern 1520 illustrated in FIG. 9B is reflected in the semiconductor layers 1510 and 1511 illustrated in FIG. In that case, a shape similar to the mask pattern 1520 may be transferred, or the corner of the mask pattern 1520 may be transferred to be more rounded. That is, a rounded portion having a smoother pattern shape than the mask pattern 1520 may be provided.

Over the semiconductor layers 1510 and 1511, an insulating layer containing at least part of silicon oxide or silicon nitride is formed. One purpose of forming this insulating layer is a gate insulating layer. Then, as illustrated in FIG. 10A, gate wirings 1612, 1613, and 1614 are formed so as to partially overlap the semiconductor layer. The gate wiring 1612 is formed corresponding to the semiconductor layer 1510. The gate wiring 1613 is formed corresponding to the semiconductor layers 1510 and 1511. The gate wiring 1614 is formed corresponding to the semiconductor layers 1510 and 1511. For the gate wiring, a metal layer or a highly conductive semiconductor layer is formed, and its shape is formed on the insulating layer by a photolithography technique.

A photomask for forming this gate wiring is provided with a mask pattern 1621 shown in FIG. This mask pattern 1621 is a corner, and one side of the (right triangle) is 10 μm or less, or less than 1/2 of the line width of the wiring, and the corner is deleted to a size of 1/5 or more of the line width. is doing. The shape of the mask pattern 1621 shown in FIG. 10B is reflected in the gate wirings 1612, 1613, and 1614 shown in FIG. In that case, a shape similar to the mask pattern 1621 may be transferred, or the corner of the mask pattern 1621 may be transferred so as to be further rounded. That is, a rounded portion having a smoother pattern shape than the mask pattern 1621 may be provided. That is, a right triangle whose one side is 1/2 or less of the line width and 1/5 or more is removed from the corners of the gate wirings 1612, 1613, and 1614, and the corners are rounded. The convex part suppresses the generation of fine powder due to abnormal discharge during dry etching with plasma, and the concave part improves the yield as a result of washing away even if fine powder is easily collected at the corner when cleaning. It has the effect that it can be made.

The interlayer insulating layer is a layer formed next to the gate wirings 1612, 1613, and 1614. The interlayer insulating layer is formed using an inorganic insulating material such as silicon oxide or an organic insulating material such as polyimide or acrylic resin. An insulating layer such as silicon nitride or silicon nitride oxide may be interposed between the interlayer insulating layer and the gate wirings 1612, 1613 and 1614. An insulating layer such as silicon nitride or silicon nitride oxide may be provided over the interlayer insulating layer. This insulating layer can prevent the semiconductor layer and the gate insulating layer from being contaminated by impurities that are not good for the TFT, such as exogenous metal ions and moisture.

An opening is formed at a predetermined position in the interlayer insulating layer. For example, it is provided corresponding to the gate wiring or semiconductor layer in the lower layer. A wiring layer formed of one or more layers of metal or metal compound is formed with a mask pattern by a photolithography technique and formed into a predetermined pattern by etching. Then, as illustrated in FIG. 11A, wirings 1715 to 1720 are formed so as to partially overlap the semiconductor layer. A wiring connects between specific elements. The wiring does not connect a specific element with a straight line, but includes a bent portion due to layout restrictions. In addition, the wiring width changes in the contact portion and other regions. In the contact portion, when the contact hole is equal to or larger than the wiring width, the wiring width is changed to widen at that portion.

A photomask for forming the wirings 1715 to 1720 includes a mask pattern 1722 shown in FIG. Even in this case, the wiring is a corner portion (right triangle) having a side of 10 μm or less, or 1/2 or less of the line width of the wiring and 1/5 or more of the line width. Remove the corners and make the corners have a rounded pattern. In such wiring, the convex part suppresses the generation of fine powder due to abnormal discharge when dry etching with plasma, and the concave part is easy to collect even in the case of cleaning even if it is fine powder. As a result of washing away, the yield can be improved. When the corner of the wiring takes a round, it can be electrically conducted. In addition, a large number of parallel wires are very convenient for washing away dust.

In FIG. 11A, n-channel transistors 1721 to 1724 and P-channel transistors 1725 and 1726 are formed. The n-channel transistor 1723 and the P-channel transistor 1725 and the n-channel transistor 1724 and the P-channel transistor 1726 constitute inverters 1727 and 1728. The circuit including these six transistors forms an SRAM. An insulating layer such as silicon nitride or silicon oxide may be formed over these transistors.

With such a structure, a semiconductor device with high performance and low power consumption can be provided at a lower weight and at a lower cost.

Note that this embodiment can be implemented by being freely combined with Embodiment Mode 1, Embodiment Mode 2, and Embodiments 1 to 4.

In this embodiment, a transistor included in a semiconductor device of the present invention will be described with reference to FIGS.

The transistor included in the semiconductor device of the present invention can be formed using a thin film transistor (TFT) in addition to a MOS transistor formed on a single crystal substrate. FIG. 12 is a diagram showing a cross-sectional structure of transistors constituting these circuits. FIG. 12 shows an n-channel transistor 1821, an n-channel transistor 1822, a capacitor 1824, a resistor 1825, and a p-channel transistor 1823. Each transistor includes a semiconductor layer 1805, a gate insulating layer 1808, and a gate electrode 1809. The gate electrode 1809 is formed with a stacked structure of a first conductive layer 1803 and a second conductive layer 1802. 13A to 13E are top views corresponding to the n-channel transistor 1821, the n-channel transistor 1822, the capacitor 1824, the resistor 1825, and the p-channel transistor 1823 shown in FIG. You can refer to them together.

In FIG. 12, an n-channel transistor 1821 is also called a lightly doped drain (LDD) on both sides of a gate electrode in the channel length direction (carrier flow direction), and has a source region and a drain region that form a contact with a wiring 1804. An impurity region 1807 doped at a lower concentration than the impurity concentration of the impurity region 1806 to be formed is formed in the semiconductor layer 1805. In the case of forming the n-channel transistor 1821, phosphorus or the like is added to the impurity regions 1806 and 1807 as an impurity imparting n-type conductivity. LDD is formed as a means for suppressing hot electron degradation and short channel effect.

As shown in FIG. 13A, in the gate electrode 1809 of the n-channel transistor 1821, the first conductive layer 1803 is formed so as to spread on both sides of the second conductive layer 1802. In this case, the first conductive layer 1803 is formed thinner than the second conductive layer. The thickness of the first conductive layer 1803 is formed so that ion species accelerated by an electric field of 10 to 100 kV can pass through. The impurity region 1807 is formed so as to overlap with the first conductive layer 1803 of the gate electrode 1809. That is, an LDD region overlapping with the gate electrode 1809 is formed. In this structure, an impurity region 1807 is formed in a self-aligned manner in the gate electrode 1809 by adding one conductivity type impurity through the first conductive layer 1803 using the second conductive layer 1802 as a mask. That is, the LDD overlapping with the gate electrode is formed in a self-aligning manner.

A transistor having LDD on both sides is applied to a transistor constituting a rectification TFT of a power supply circuit and a transmission gate (also referred to as an analog switch) used in a logic circuit in the embodiment. In these TFTs, since both positive and negative voltages are applied to the source region and the drain region, it is preferable to provide LDDs on both sides of the gate electrode.

Further, the first conductive layer 1803 may be processed so that both ends thereof are aligned when the second conductive layer 1802 is used to form the gate wiring. As a result, a fine gate wiring can be formed. Further, it is not necessary to form the LDD overlapping the gate electrode in a self-aligning manner.

In FIG. 12, an n-channel transistor 1822 has an impurity region 1807 doped in a lower concentration than the impurity concentration of the impurity region 1806 in the semiconductor layer 1805 on one side of the gate electrode. As shown in FIG. 13B, in the gate electrode 1809 of the n-channel transistor 1822, the first conductive layer 1803 is formed so as to spread on one side of the second conductive layer 1802. In this case as well, LDD can be formed in a self-aligned manner by adding an impurity of one conductivity type through the first conductive layer 1803 using the second conductive layer 1802 as a mask.

A transistor having an LDD on one side may be applied to a transistor to which only a positive voltage or only a negative voltage is applied between a source region and a drain region. Specifically, it may be applied to a transistor constituting a logic gate such as an inverter circuit, a NAND circuit, a NOR circuit, or a latch circuit, or a transistor constituting an analog circuit such as a sense amplifier, a constant voltage generation circuit, or a VCO.

In FIG. 12, the capacitor 1824 is formed with a gate insulating layer 1808 sandwiched between a first conductive layer 1803 and a semiconductor layer 1805. A semiconductor layer 1805 that forms the capacitor 1824 includes an impurity region 1810 and an impurity region 1811. The impurity region 1811 is formed in the semiconductor layer 1805 so as to overlap with the first conductive layer 1803. Further, the impurity region 1810 forms a contact with the wiring 1804. Since the impurity region 1811 can be doped with one conductivity type impurity through the first conductive layer 1803, the impurity concentrations in the impurity region 1810 and the impurity region 1811 can be the same or different. It is. In any case, since the semiconductor layer 1805 functions as an electrode in the capacitor 1824, it is preferable to reduce the resistance by adding an impurity of one conductivity type. In addition, as shown in FIG. 13C, the first conductive layer 1803 can function sufficiently as an electrode by using the second conductive layer 1802 as an auxiliary electrode. As described above, by using a composite electrode structure in which the first conductive layer 1803 and the second conductive layer 1802 are combined, the capacitor 1824 can be formed in a self-aligning manner.

The capacitor is used as a storage capacitor included in the power supply circuit in the embodiment or a resonance capacitor included in the resonance circuit. In particular, since both positive and negative voltages are applied between the two terminals of the capacitive element, the resonant capacitor needs to function as a capacitor regardless of whether the voltage between the two terminals is positive or negative.

In FIG. 13D, the resistance element 1825 is formed of the first conductive layer 1803. Since the first conductive layer 1803 is formed to a thickness of about 30 to 150 nm, a resistance element can be configured by appropriately setting the width and length thereof.

The resistance element is used as a resistance load included in the modulation / demodulation circuit in the embodiment. Also, it may be used as a load when current is controlled by a VCO or the like. The resistance element may be formed using a semiconductor layer containing an impurity element at a high concentration or a thin metal layer. In contrast to a semiconductor layer whose resistance value depends on the film thickness, film quality, impurity concentration, activation rate, and the like, a metal layer is preferable because the resistance value is determined by the film thickness and film quality, so that variation is small.

In FIG. 13E, a p-channel transistor 1823 includes an impurity region 1812 in a semiconductor layer 1805. The impurity region 1812 forms a source region and a drain region that form a contact with the wiring 1804. The structure of the gate electrode 1809 is a structure in which the first conductive layer 1803 and the second conductive layer 1802 overlap each other. The p-channel transistor 1823 is a single drain transistor without an LDD. In the case of forming the p-channel transistor 1823, boron or the like is added to the impurity region 1812 as an impurity imparting p-type conductivity. On the other hand, when phosphorus is added to the impurity region 1812, an n-channel transistor having a single drain structure can be obtained.

Plasma is excited by microwaves to one or both of the semiconductor layer 1805 and the gate insulating layer 1808, the electron temperature is 2 eV or less, the ion energy is 5 eV or less, and the electron density is about 10 ¹¹ to 10 ¹³ / cm ^3. Oxidation or nitridation may be performed by density plasma treatment. At this time, the substrate temperature is set to 300 to 450 ° C., and treatment is performed in an oxidizing atmosphere (O ₂ , N ₂ O, or the like) or a nitriding atmosphere (N ₂ , NH _3, or the like), so that the interface between the semiconductor layer 1805 and the gate insulating layer 1808 is obtained. The defect level of can be reduced. By performing this treatment on the gate insulating layer 1808, the insulating layer can be densified. That is, generation of charged defects can be suppressed and fluctuations in the threshold voltage of the transistor can be suppressed. In the case where the transistor is driven with a voltage of 3 V or lower, an insulating layer oxidized or nitrided by this plasma treatment can be used as the gate insulating layer 1808. When the driving voltage of the transistor is 3 V or more, the gate is formed by combining an insulating layer formed on the surface of the semiconductor layer 1805 by this plasma treatment and an insulating layer deposited by a CVD method (plasma CVD method or thermal CVD method). An insulating layer 1808 can be formed. Similarly, this insulating layer can also be used as a dielectric layer of the capacitor 1824. In this case, since the insulating layer formed by this plasma treatment is formed with a thickness of 1 to 10 nm and is a dense film, a capacitor having a large charge capacity can be formed.

As described with reference to FIGS. 12 and 13, elements having various structures can be formed by combining conductive layers having different film thicknesses. The region where only the first conductive layer is formed and the region where the first conductive layer and the second conductive layer are laminated are a photo provided with an auxiliary pattern having a light intensity reducing function consisting of a diffraction grating pattern or a semi-transmissive film. It can be formed using a mask or a reticle. That is, in the photolithography process, when the photoresist is exposed, the amount of light transmitted through the photomask is adjusted to vary the thickness of the resist mask to be developed. In this case, a resist having a complicated shape may be formed by providing a slit having a resolution limit or less in a photomask or a reticle. Alternatively, the mask pattern formed of the photoresist material may be deformed by baking at about 200 ° C. after development.

Further, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film, a region where only the first conductive layer is formed, the first conductive layer and the second conductive layer A region where the conductive layer is stacked can be formed continuously. As shown in FIG. 13A, a region where only the first conductive layer is formed can be selectively formed over the semiconductor layer. Such a region is effective on the semiconductor layer, but is not necessary in other regions (a wiring region continuous with the gate electrode). By using this photomask or reticle, it is not necessary to form a region of only the first conductive layer in the wiring portion, so that the wiring density can be substantially increased.

12 and 13, the first conductive layer is a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN) or molybdenum (Mo), or a refractory metal. An alloy or a compound mainly composed of is formed with a thickness of 30 to 50 nm. The second conductive layer is made of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or an alloy or compound containing a refractory metal as a main component. To a thickness of 300 to 600 nm. For example, different conductive materials are used for the first conductive layer and the second conductive layer, and a difference in etching rate is caused in an etching process performed later. As an example, TaN can be used for the first conductive layer, and a tungsten film can be used for the second conductive layer.

In this embodiment, a transistor, a capacitive element, and a resistive element having different electrode structures are formed by the same processing process using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function including a diffraction grating pattern or a semi-transmissive film. It shows that it can be made separately. Thus, elements having different forms can be formed and integrated without increasing the number of steps in accordance with circuit characteristics.

By forming a semiconductor device with the above transistors, a wireless chip with high performance and low power consumption can be provided at a lower weight and at a lower cost.

This embodiment can be implemented by being freely combined with Embodiment Mode 1, Embodiment Mode 2, and Embodiments 1 to 5.

In this embodiment, a system example using the semiconductor device of the present invention will be described with reference to FIGS. In this embodiment, a personal computer user authentication system with excellent security using a wireless chip as a semiconductor device according to the present invention will be described.

FIG. 14 is a schematic diagram of a user authentication system in the present embodiment, which shows a personal computer 2001 and a wireless chip 2002. An input device 2003 and a reader / writer 2004 are connected to the personal computer 2001.

The personal computer 2001 and the wireless chip 2002 have a common key 2005 for encryption. Specifically, the data of the common key 2005 is stored in the memories of the personal computer 2001 and the wireless chip 2002, respectively. The common key 2005 is 64-bit to 128-bit data, for example, and is used for encryption of plaintext (data before encryption) and decryption of the ciphertext. As the common key, a different common key is created for each registered user, and the personal computer 1501 has all the common keys. In other words, the personal computer 1501 has as many common keys as the number of users registered in a regular manner. On the other hand, the wireless chip 2002 is owned by a properly registered user and has only a common key unique to the user. The common key must be stored so that it is not known to others.

In this embodiment, a common key cryptosystem (ISO / IEC 9798-2 Information technology-Security techniques-Entity authentication-Part 2: An example of using a mechanical encryption metric) is used. Key encryption method (refer to ISO / IEC 9798-3 Information technology-Security techniques-Entity authentication-Part 3: Suitable for methods used in digital signature techniques, etc.) Can be used.

The personal computer 2001 has means for encrypting plaintext using the common key 2005. Specifically, it is assumed that software for executing an encryption algorithm is installed. The wireless chip 2002 also has means for decrypting the ciphertext using the common key 2005. Specifically, a decoding algorithm is executed in the arithmetic circuit shown in the above embodiment.

Hereinafter, a method of using the user authentication system in this embodiment will be described with reference to the flowchart of FIG.

First, a user who wishes to use inputs the user name and password in the personal computer 2001 using the input device 2003 (user name input 2101). The password is registered in advance by an authorized user. The personal computer 2001 encrypts a certain plaintext from the input user name using the corresponding common key (encrypted data creation 2102). Here, the plaintext may be data having a specific meaning or meaningless data. Next, the encrypted data is transmitted from the reader / writer 2004 (encrypted data transmission 2103). The wireless chip 2002 receives the encrypted data, decrypts the encrypted data using the common key 2005 (decryption process 2104), and transmits the decrypted data to the reader / writer (decrypted data transmission 2105). The personal computer 2001 compares the decrypted data with the first plaintext (authentication 2106), and if it matches, the personal computer 2001 recognizes that the user who wishes to use is a registered user and makes it available (normal use 2107). ).

In the user authentication system in the present embodiment as described above, the computer cannot be used unless the password is known and the wireless chip is not owned. Therefore, security is much higher than password-only authentication. Further, if the user carries the wireless chip, the user can use the personal computer without any change from the conventional authentication using only the password, and the new burden is small.

In this embodiment, personal computer user authentication has been described. However, the present invention can be easily applied to other systems that can be used only by authorized users. For example, it can be easily applied to ATM (Automated Teller Machine cash dispenser), CD (Cash Dispenser cash dispenser), and the like.

With the configuration as described above, a user authentication system with extremely high security using the semiconductor device of the present invention can be constructed at low cost.

Note that this embodiment can be implemented by being freely combined with Embodiment Mode 1, Embodiment Mode 2, and Embodiments 1 to 6.

In this embodiment, an antenna mounted on a semiconductor device according to the present invention will be described with reference to FIG. The antenna may have a size and shape that meet the purpose within the range defined by the Radio Law. Signals to be transmitted and received include 125 kHz, 13.56 MHz, 915 MHz, 2.45 GHz, and the like, and ISO standards are set for each. As a specific antenna, a dipole antenna, a patch antenna, a loop antenna, a Yagi antenna, or the like may be used. Hereinafter, the shape of the antenna connected to the wireless chip will be described.

FIG. 18A illustrates a wireless chip 1601 to which an external antenna 1602 is connected. In FIG. 18A, a wireless chip 1601 is provided in the center, and an antenna 1602 is connected to a connection terminal of the wireless chip 1601. In order to secure the length of the antenna, the antenna 1602 is bent into a rectangular shape.

FIG. 18B illustrates a mode in which the external antenna 1603 is provided on a connection terminal on one end side of the wireless chip 1601. In order to secure the length of the antenna, the antenna 1603 is bent and has a rectangular shape.

FIG. 18C illustrates a mode in which a bent external antenna 1604 is provided at both ends of the wireless chip 1601.

FIG. 18D illustrates a mode in which a linear external antenna 1605 is provided at both ends of the wireless chip 1601.

As described above, the shape of the antenna may be selected in accordance with the structure or polarization of the wireless chip or the application. Therefore, a folded dipole antenna may be used as long as it is a dipole antenna. As long as it is a loop antenna, it may be a circular loop antenna or a square loop antenna. If it is a patch antenna, a circular patch antenna or a square antenna may be used.

In the case of a patch antenna, an antenna using a dielectric material such as ceramic may be used. The antenna can be miniaturized by increasing the dielectric constant of the dielectric material used as the patch antenna substrate. In the case of the patch antenna, since the mechanical strength is high, it can be used repeatedly.

The dielectric material of the patch antenna can be formed of ceramic, organic resin, a mixture of ceramic and organic resin, or the like. Representative examples of ceramics include alumina, glass, forsterite and the like. Furthermore, a plurality of ceramics may be mixed and used. In order to obtain a high dielectric constant, the dielectric layer is preferably formed of a ferroelectric material. Representative examples of the ferroelectric material include barium titanate (BaTiO ₃ ), lead titanate (PbTiO ₃ ), strontium titanate (SrTiO ₃ ), lead zirconate (PbZrO ₃ ), lithium diobate (LiNbO ₃ ). And lead zirconate titanate (PZT). Further, a plurality of ferroelectric materials may be mixed and used.

Note that the structure described in any of the above embodiments and examples can be applied to the wireless chip 1601.

With the above structure, a high-performance semiconductor device can be provided.

Note that this embodiment can be implemented by being freely combined with Embodiment Mode 1, Embodiment Mode 2, and Embodiments 1 to 7.

In this embodiment, a structure different from the example described in Embodiment 8 will be described with reference to FIG. FIG. 4 is a circuit diagram and a layout of a semiconductor device including a wireless chip, a first antenna, a second antenna, a third antenna, and a capacitance in this embodiment.

FIG. 4A is a circuit diagram of the semiconductor device in this example. A semiconductor device illustrated in FIG. 4A includes a wireless chip 401, a first antenna (inner antenna) 402 mounted on the wireless chip 401, a second antenna 403, a third antenna 404, and an electric capacitor 405. An outer antenna 406 is configured by the second antenna 403, the third antenna 404, and the electric capacity 405.

When a communication signal from the reader / writer is received by the third antenna 404, an induced electromotive force due to electromagnetic induction is generated in the third antenna 404. Due to this induced electromotive force, an induced electromagnetic field is generated from the second antenna 403. By receiving the induced electromagnetic field by the first antenna 402, the first antenna 402 generates an induced electromotive force due to electromagnetic induction.

Here, by increasing the inductance of the third antenna 404, the induction electromagnetic field received by the first antenna 402 can be increased. That is, even if the inductance of the first antenna 402 is small, an induction electromagnetic field sufficient to operate the wireless chip 401 can be supplied. In the case where the first antenna 402 is an on-chip antenna, the wireless chip 401 has a small area, and thus the inductance cannot be increased so much. Therefore, when only the first antenna 402 is used, it is difficult to extend the communication distance of the wireless chip 401. However, with the configuration shown in this embodiment, the communication distance can be extended even with a wireless chip having an on-chip antenna.

FIG. 4B is a first example of the antenna layout of the semiconductor device in this embodiment. FIG. 4B illustrates an example in which the second antenna 403 is formed outside the third antenna 404. The first through hole 407 and the second through hole 408 are electrically connected, and an outer antenna is formed from the second antenna 403, the third antenna 404, and the electric capacity 405. . As the electric capacity 405, a chip capacitor, a film capacitor, or the like can be used. The layout as shown in FIG. 4B can form a narrow antenna, which is effective for providing a semiconductor device with a narrow shape.

FIG. 4C is a second example of the antenna layout of the semiconductor device in this example. FIG. 4C illustrates an example in which the second antenna 403 is formed inside the third antenna 404. The first through hole 409 and the second through hole 410 are electrically connected, and an outer antenna is formed from the second antenna 403, the third antenna 404, and the electric capacitance 405. . As the electric capacity 405, a chip capacitor, a film capacitor, or the like can be used. The layout as shown in FIG. 4C can form a narrow antenna, which is effective in providing a semiconductor device with a narrow shape.

With the above configuration, a high-performance semiconductor device with an extended communication distance can be provided.

Note that this embodiment can be implemented by being freely combined with Embodiment Mode 1, Embodiment Mode 2, and Embodiments 1 to 8.

In this embodiment, an example in which the semiconductor device of the present invention has a three-dimensional multilayer structure will be described with reference to FIG.

In FIG. 19, an integrated circuit 520a, an integrated circuit 520b, and an integrated circuit 520c manufactured over different substrates are separated from each substrate and bonded to each other with an insulating layer 510a and an insulating layer 510b. The nonvolatile memory device of the present invention described in the above embodiment modes and examples is used for the integrated circuit to be stacked. In this example, the nonvolatile memory device is used as the integrated circuit 520a. The semiconductor device having a multilayer structure in FIG. 19 includes insulating layers 501, 502, 503, 504, 505, 506, 507, 508, wiring layers 531 a, 531 b, 532 a, 532 b, and a memory element 530. The integrated circuit 520a including the transistor over the substrate 500 is attached to the integrated circuit 520b including the transistor over the insulating layer 504 by the insulating layer 510a. Similarly, the integrated circuit 520b is combined with the transistor over the insulating layer 506 through the insulating layer 510b. And a semiconductor device having a multi-layer structure.

The bonding process will be described. A liquid (fluid) insulating material is attached to the integrated circuit 520a by a spin coating method or a droplet discharge method, and the integrated circuit 520b which is peeled from the substrate by a peeling process is attached before the fluidity is lost. Match. After that, the insulating material is solidified by drying to form the insulating layer 510a. Therefore, the integrated circuit 520a and the integrated circuit 520b are fixed using the insulating layer 510a as an adhesive layer. Similarly, an insulating material having fluidity is attached to the integrated circuit 520b, and the integrated circuit 520c which is separated from the substrate by a separation process before the fluidity is not lost is attached. After drying, a stack of the integrated circuit 520a, the insulating layer 510a, the integrated circuit 520b, the insulating layer 510b, and the integrated circuit 520c is formed. For the insulating layer 510a and the insulating layer 510b, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or the like can be used. In this embodiment, a siloxane resin is used. When the insulating layer 510a and the insulating layer 510b are made of a fluid insulating material, it is preferable that the insulating layer 510a and the insulating layer 510b have relatively high viscosity and high adhesion to the integrated circuits. By using an insulating layer as an adhesive layer between integrated circuits as in this embodiment, it is not necessary to separately form an adhesive layer for bonding, and the process can be simplified.

Next, an opening is formed in the insulating layer included in the stacked structure, and the integrated circuit 520a, the integrated circuit 520b, and the integrated circuit 520c are electrically connected. The wiring layer 550a is formed in contact with the wiring layer 532a provided over the insulating layer 505 and the wiring layer 531a provided over the insulating layer 502, and the wiring layer 532b and insulating layer provided over the insulating layer 505 are formed. A wiring layer 550 b is formed in contact with the wiring layer 531 b provided over the layer 502. The wiring layer 550a is formed in the insulating layers 503, 504, 505, 506, and 507 and is formed in an opening that exposes the wiring layer 531a and the wiring layer 532a. Similarly, the wiring layer 550b is formed in the insulating layers 503, 504, 505, 506, and 507 and is formed in an opening that exposes the wiring layer 531b and the wiring layer 532b. The wiring layer 550a is electrically connected to the wiring layer 531a and the wiring layer 532a, and the wiring layer 550b is electrically connected to the wiring layer 531b and the wiring layer 532b.

Through the above steps, a multi-layered semiconductor device that has a stacked structure using integrated circuits that are bonded to each other through an insulating layer and that is electrically connected to the integrated circuits in each layer can be manufactured.

This embodiment can be implemented by being freely combined with Embodiment Mode 1, Embodiment Mode 2, and Embodiments 1 to 9.

In this embodiment, an example in which a mask ROM is formed as an example of the nonvolatile memory device of the present invention will be described.

The mask ROM is formed of a plurality of transistors and electronic elements, and the transistors and electronic elements constituting the mask ROM are formed by a photolithography method. At that time, for example, data can be written depending on whether or not a contact hole for wiring connected to one terminal of the electronic element (for example, the electric element 109 in FIG. 2) is opened. (On), when not opened, data (information) of 0 (off) can be written in the memory cell.

In the step of exposing the photoresist, before or after the step of exposing through the reticle (photomask) using an exposure apparatus such as a stepper, the photoresist on the region where the contact hole is opened is irradiated with an electron beam or a laser. . Thereafter, development, etching, and stripping of the photoresist are performed as usual. By doing so, it is possible to create a pattern for opening the contact hole and a pattern for not opening the contact hole only by selecting the irradiation region of the electron beam or laser without exchanging the reticle (photomask). That is, by selecting an electron beam or laser irradiation region, it is possible to manufacture a mask ROM in which different data is written for each semiconductor device when the semiconductor device is manufactured.

Using such a mask ROM, a unique identifier (UID: Unique Identifier) or the like for each semiconductor device can be formed when the semiconductor device is manufactured. Further, since the semiconductor device of this embodiment also has a memory that can be additionally written, data can be written after the semiconductor device is manufactured.

This embodiment can be implemented by being freely combined with Embodiment Mode 1, Embodiment Mode 2, and Embodiments 1 to 10.

FIG. 6 is a circuit diagram of a memory element of a semiconductor device according to the present invention. FIG. 6 is a circuit diagram of a memory element of a semiconductor device according to the present invention. FIG. 13 illustrates an example of a memory element of a semiconductor device in the present invention. 2A and 2B are a circuit diagram and a layout of an antenna mounted on a semiconductor device according to the present invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. FIG. 6 shows a layout of a semiconductor device according to the present invention. (Semiconductor layer) FIG. 6 shows a layout of a semiconductor device according to the present invention. (Gate wiring) FIG. 6 shows a layout of a semiconductor device according to the present invention. (wiring) FIG. 6 shows a layout of a semiconductor device according to the present invention. (Semiconductor layer) FIG. 6 shows a layout of a semiconductor device according to the present invention. (Gate wiring) FIG. 6 shows a layout of a semiconductor device according to the present invention. (wiring) FIG. 6 is a cross-sectional view of a semiconductor device according to the present invention. FIG. 10 shows an electric element included in a semiconductor device of the invention. 1 is a schematic diagram of a user authentication system using a semiconductor device according to the present invention. The flowchart of the user authentication system using the semiconductor device in this invention. FIG. 6 illustrates a configuration example of a semiconductor device in the present invention. FIG. 6 is a diagram showing a layout example of a semiconductor device in the present invention. FIG. 6 shows a layout of an antenna mounted on a semiconductor device according to the present invention. FIG. 6 illustrates a configuration example of a semiconductor device in the present invention.

Explanation of symbols

101 power supply terminal 102 ground terminal 103 reset terminal 104 output terminal 105 P-type transistor 106 N-type transistor 107 inverter 108 inverter 109 electric element 110 reset element 111 latch element 210 reset element 301 electric resistance 302 terminal 303 terminal 311 diode 312 diode 313 terminal 314 Terminal 321 Floating gate type memory transistor 322 Terminal 323 Terminal 324 Terminal 400 Low temperature process (substrate temperature 401 wireless chip 402 first antenna 403 second antenna 404 third antenna 405 capacitance 406 outer antenna 407 first through hole 408 Second through hole 409 First through hole 410 Second through hole 500 Substrate 501 Insulating layer 502 Insulating layer 503 Insulating layer 504 Layer 505 Insulating layer 506 Insulating layer 507 Insulating layer 508 Insulating layer 530 Memory element 907 Impurity region 1101 TFT unit 1102 Memory unit 1110 Insulating substrate 1111 Base film 1112 Semiconductor film 1113 Insulator 1114 Gate electrode 1115 Electrode 1116 Insulating film 1117 Insulating film 1118 Insulating Film 1120 Thin film transistor 1122 Thin film transistor 1123 Memory element 1125 Insulating film 1127 Lower electrode 1128 Insulating film 1129 Memory material layer 1130 Upper electrode 1131 Insulating film 1151 Contact hole 1201 Semiconductor pattern 1301 Gate wiring 1501 Personal computer 1502 Wireless chip 1510 Semiconductor layer 1520 Mask pattern 1601 Wireless Chip 1602 Antenna 1603 Antenna 1604 Antenna 1605 Antenna 1 612 gate wiring 1613 gate wiring 1614 gate wiring 1621 mask pattern 1715 wiring 1721 n-channel transistor 1722 mask pattern 1723 n-channel transistor 1724 n-channel transistor 1725 P-channel transistor 1726 P-channel transistor 1727 inverter 1802 conductive layer 1803 conductive layer 1804 Wiring 1805 Semiconductor layer 1806 Impurity region 1807 Impurity region 1808 Gate insulating layer 1809 Gate electrode 1810 Impurity region 1811 Impurity region 1812 Impurity region 1821 n-channel transistor 1822 n-channel transistor 1823 p-channel transistor 1824 Capacitor element 1825 Resistor element 2001 Personal Computer 2002 wireless chip 003 input unit 2004 reader / writer 2005 common key 2101 (user name input 2102 (encrypted data generation 2103 (encrypted data transmission 2104 (decoding process 2105 (decoded data transmission 2106 (authentication 2107 (normal use 2601 the wireless chip 2602 CPU
2603 ROM
2604 RAM
2605 Controller 2606 Arithmetic circuit 2607 Antenna 2608 Resonance circuit 2609 Power supply circuit 2610 Reset circuit 2611 Clock generation circuit 2612 Demodulation circuit 2613 Modulation circuit 2614 Power management circuit 2615 Analog unit 2616 CPUIF
2617 Control register 2618 Code extraction circuit 2619 Encoding circuit 2620 Received signal 2621 Transmitted signal 2622 Received data 2623 Transmitted data 2624 Private key 2707 FPC pad 2708 Antenna bump 501b Insulating layer 510a Insulating layer 510b Insulating layer 520a Integrated circuit 520b Integrated circuit 520c Integrated circuit 531a Wiring layer 531b Wiring layer 532a Wiring layer 532b Wiring layer 545T Coumarin 550a Wiring layer 550b Wiring layer

Claims (9)

A non-volatile memory device having a memory element including an electric element, a reset element, and a latch element is mounted,
The information is stored in the latch element by the reset element,
Information stored in the latch element is determined depending on whether the electric element is electrically conductive or insulated. In claim 1,
The semiconductor device is characterized in that the electrical element is electrically insulated by cutting by laser drawing. In claim 1,
The electrical device is electrically insulated by applying and destroying an overcurrent. In claim 1,
The electric element includes a first diode and a second diode, and is electrically connected by applying an overcurrent to at least one of the first diode and the second diode and destroying it. A semiconductor device characterized by the above. In claim 1,
The semiconductor device according to claim 1, wherein the electric element is a phase change memory whose electric resistance value is changed by a phase change. In claim 1,
The semiconductor device, wherein the electric element is a nonvolatile memory transistor having a floating gate. In claim 1,
The semiconductor device, wherein the electric element is a memory transistor having a MONOS structure. In any one of Claims 1 thru | or 7,
The semiconductor device, wherein the reset element or the latch element uses a thin film transistor having a semiconductor thin film formed on a substrate having an insulating surface as an active layer. In claim 8,
The substrate having an insulating surface is any one of a glass substrate, a quartz substrate, a plastic substrate, and an SOI substrate.

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