JP2005182551A - Thin film integrated circuit, semiconductor circuit, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize cost reduction and improved design and to provide an IC card and IC tag with excellent shock resistance. <P>SOLUTION: By forming on a glass substrate an integrated circuit to be built in the IC card or the IC tag, a large amount of devices can be produced at a time and the cost can be reduced. Moreover, a non-volatile memory which has common circuit structure and layout and can store random fixed data even if the same manufacturing process is used is built in and data are made to have an identification number unique to a chip. Thus, it is possible to avoid a raise in process cost accompanying manufacture of flash memories or a raise in mask cost by disposing photo masks at the time of forming a mask ROM. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

 The present invention relates to a semiconductor integrated circuit formed on a glass substrate or a flexible substrate, and a semiconductor device incorporating the semiconductor integrated circuit. The present invention also relates to a method for manufacturing the semiconductor integrated circuit.

 In recent years, the spread of IC cards as a medium replacing magnetic cards is accelerating. Although the IC card is more expensive than the magnetic card, it has the advantages of high security and a large amount of data, so that it has been adopted as a credit card or a resident card. There are two types of IC cards: contact type / non-contact type, and non-contact type is classified as proximity type / neighbor type / remote type. From the viewpoint of data transfer speed and usability, proximity type / neighbor type attracts attention. Yes.

 On the other hand, IC tags (or RFIDs) have become widespread for uses such as management of distribution items. In short, this is a substitute for a tag or bar code, and a non-contact type rewritable nonvolatile memory is mainly used. If it is adopted for disposable use, it is an area where a very large market is expected.

Also, a method has been proposed in which a fine IC chip is mounted on valuable securities to prevent unauthorized use and can be reused when it can be recovered to a regular management source (see Patent Document 1).
JP 2001-260580 A

 However, the cost of an IC card is higher than that of a magnetic card, and the IC tag is also expensive as a barcode replacement. As a result, it is limited to applications where added value is important, and is a factor that hinders its spread.

 In the integrated circuit, for example, a mask ROM is considered as a main option as a non-rewritable nonvolatile memory. However, since the data stored in the IC includes a chip-specific identification number and the like, the photomask used in the process of determining the data is disposable, resulting in an increase in cost.

 In addition, when the IC card has a function such as security, a CPU and a memory having a certain capacity are required, and the area of the IC chip built in the IC card becomes large. Since an IC chip is formed on a single crystal silicon substrate and is used thinly for a card, there is a problem that the impact resistance is low. Therefore, when the area of the IC chip is large, the reliability of the IC card is seriously affected.

 In addition, since the chip produced on the single crystal silicon substrate is thick, when it is mounted on a product or a product, particularly a paper such as a banknote, or a label attached to the product or the product itself, the surface is uneven. As a result, the design of products and products has been degraded.

 Therefore, an object of the present invention is to provide a semiconductor integrated circuit that realizes cost reduction and design improvement and is excellent in impact resistance, a semiconductor device having the semiconductor integrated circuit, and a method for manufacturing the semiconductor device.

In order to solve the above problems, the present invention is characterized in that an integrated circuit is formed on a glass substrate. An integrated circuit formed on a glass substrate is referred to as a semiconductor integrated circuit.
In the present invention, by forming a semiconductor integrated circuit over a large glass substrate, a large amount of semiconductor integrated circuits can be manufactured at a time, and cost can be reduced.

In the present invention, a semiconductor integrated circuit formed over a glass substrate may be transferred to a flexible substrate (hereinafter referred to as a flexible substrate). As a result, it is possible to realize a semiconductor integrated circuit having excellent impact resistance.
Which of the glass substrate and the flexible substrate is used may be selected in accordance with the required cost and impact resistance. When a glass substrate is used, a process related to transfer is not added, so the cost is lower. When a flexible substrate is used, high impact resistance can be realized.

 Further, in the present invention, a semiconductor integrated circuit formed on a glass substrate may be directly transferred to an object. As a result, the cost related to the flexible substrate can be reduced.

 Thereafter, the glass substrate may be further peeled off. In a semiconductor integrated circuit, a state where a glass substrate is peeled is referred to as a thin film integrated circuit. By peeling the glass substrate, the circuit can be made thinner, lighter, and smaller.

 In the present invention, the flexible substrate refers to a flexible substrate, and typically refers to a metal typified by stainless steel or a plastic substrate. Examples of the plastic include polynorbornene having a polar group, polyethylene terephthalate (PET), polyethersulfone (PES), polyethylene naphthalate (PEN), polycarbonate (PC), nylon, polyetheretherketone (PEEK), and polysulfone. (PSF), polyetherimide (PEI), polyarylate (PAR), polybutylene terephthalate (PBT), polyimide and the like.

In the present invention, a semiconductor device having an antenna in addition to a semiconductor integrated circuit or a thin film integrated circuit and reading data wirelessly or the like is referred to as an ID chip. The ID chip is mounted on a tag and has a function as a so-called electronic tag having a function of storing and reading data.
In addition to the function of storing and reading data, the ID chip has a function as a so-called IC card having a security function by incorporating a CPU.
Further, the ID chip may be used in a form such as an arbitrarily shaped seal, card, or label or in a form incorporated in a container.
As described above, the ID chip of the present invention can perform inventory, distribution item recognition and management, settlement processing, ID management, history management, location management, and the like.

In the ID chip, the antenna may be formed together with a semiconductor integrated circuit or a thin film integrated circuit, or may be connected to the antenna via an input / output terminal on the semiconductor integrated circuit or the thin film integrated circuit. Moreover, the contact type which does not incorporate an antenna may be sufficient, and the function of both a contact type and a non-contact type may be provided.

 In particular, the present invention uses the same manufacturing process and circuit configuration and layout in order to avoid an increase in process cost due to flash memory or the like, or an increase in mask cost due to the disposable use of a photomask when forming a mask ROM. However, the biggest feature is that a non-rewritable non-volatile memory in which random fixed data is stored every time it is manufactured is built in the ID chip.

 Specifically, such a memory is realized by utilizing variation in characteristics of TFTs to be manufactured. Note that variations in TFT characteristics include variations due to the grain pattern of the polycrystalline semiconductor film constituting the active layer of the TFT and various variations due to the process (film thickness, film quality, impurity concentration, etc.). In the present invention, a non-volatile memory having a common circuit configuration and layout and storing random fixed data every time it is manufactured using the same manufacturing process will be referred to as a random number ROM.

 Therefore, it is preferable to use a polycrystalline semiconductor film as an active layer of a TFT constituting a circuit portion for determining data in a random number ROM. Note that since the random number ROM is composed of normal TFTs, the random number ROM can be manufactured by the same manufacturing process as that for manufacturing other integrated circuits constituting the ID chip, and there is no increase in process cost associated with the manufacturing of the random number ROM. .

 By incorporating such a random number ROM in the ID chip, the data stored in the random number ROM can be used as data unique to the ID chip (such as an identification number). As a result, the process cost can be reduced as compared with the case of manufacturing a flash memory, and the mask cost can be suppressed as compared with the case where data unique to each chip is manufactured by a mask ROM. A cost ID chip can be realized.

 In addition, high security can be mentioned as another effect by using random number ROM. Since all random number ROMs are produced by the same circuit layout and manufacturing process, it is difficult to read the contents of data by a method other than electrical data reading. On the other hand, when a mask ROM is used, the identification number may be decoded by analyzing the circuit layout.

 The present invention realizes cost reduction by manufacturing a semiconductor integrated circuit on a large glass substrate instead of a conventional expensive silicon substrate. Further, by transferring a semiconductor integrated circuit manufactured on a glass substrate onto a flexible substrate depending on the use of the ID chip, an ID chip having excellent impact resistance can be provided.

 The present invention also stores chip-specific data (such as an identification number) in an ID chip using a random number ROM that utilizes variations in TFT characteristics, so that data specific to each chip can be stored using a mask ROM or flash memory. Compared with the case of storing, mask costs and process costs can be suppressed, and a low-cost ID chip can be provided.

 In addition, unlike the mask ROM, the data in the random number ROM is difficult to decrypt by a method other than electrical reading, so that high security is ensured.

Embodiments of the present invention will be described below with reference to the drawings.
It should be noted that the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of the embodiments and the examples.
Note that in the drawings for describing the embodiments, the same portions or portions having similar functions in one drawing are denoted by the same reference numerals, and repetitive description thereof is omitted.

 The first feature of the present invention is that a semiconductor integrated circuit constituting an ID chip is formed on a glass substrate or a flexible substrate, and secondly, a random number ROM is provided. The first feature can be implemented by a technique for forming a thin film transistor on a glass substrate and a technique for transferring a semiconductor integrated circuit formed on the glass substrate onto a flexible substrate. Details thereof will be described in a fourth embodiment. Below, the form in connection with a 2nd characteristic is demonstrated.

 As a simple configuration example of the ID chip of the present invention, a block diagram as shown in FIG. 1 can be given. FIG. 1 shows a contactless ID chip with a built-in antenna, which has a function of reading fixed data such as an identification number.

 Even if the function of the ID chip is limited to reading fixed data such as an identification number, it can be applied to various applications by supplementing the lacking function using network technology such as the Internet. It is possible.

 In FIG. 1, an ID chip 101 includes an antenna 102, an RF circuit 103, a power / clock signal / reset signal generation circuit 104, a data demodulation / modulation circuit 105, a control circuit 106, a mask ROM 107, and a random number ROM 108.

 All the integrated circuits shown in FIG. 1 are formed on a glass substrate or a flexible substrate. The antenna 102 may be formed on a substrate forming an integrated circuit, or may be outside the substrate forming the integrated circuit and connected to the integrated circuit via an input / output terminal.

 The RF circuit 103 is a circuit that receives an analog signal from the antenna 102 and outputs the analog signal received from the data modulation circuit from the antenna 102. The power source / clock signal / reset signal generation circuit 104 is a circuit that generates a constant power source, a reset signal, and a clock signal based on the received signal, and the data demodulation / modulation circuit 105 extracts data from the received signal and controls This circuit converts the digital signal received from 106 into an analog signal to be output to the antenna 102.

 On the other hand, the control circuit 106 controls the mask ROM 107 and the random number ROM 108, and reads data according to the demodulated received signal. Specifically, the address signal and enable signal of the mask ROM 107 and the random number ROM 108 are generated, the data is read, and the read data is sent to the data modulation circuit.

 The random number ROM 108 has a common circuit configuration and layout, and is a memory circuit that stores random fixed data every time it is manufactured even if the same manufacturing process is used. ) Can be used as a ROM. Hereinafter, the form of the random number ROM will be described with reference to FIGS.

 FIG. 2A shows a typical configuration example of a random number ROM. In FIG. 2, the random number ROM includes a decoder 201, a memory cell array 202, and a read circuit 203. The decoder 201 receives the address signal and selects the word line of the corresponding address. The memory cell array 202 includes memory cells 204 arranged in a matrix. Memory cells in the same row are connected to the same word line, and memory cells in the same column are connected to the same bit line. A memory cell is selected through a word line, and data is read out through a bit line. The reading circuit 203 inputs a bit line, amplifies the bit line potential, and reads data.

 FIG. 2B shows an example of a memory cell constituting a random number memory. The memory cell is composed of one TFT 205. One of the source electrode and the drain electrode of the TFT is connected to the bit line, and the remaining one and the gate electrode are connected to the word line. In the memory cell, when a voltage Vword higher than the threshold voltage Vth of the TFT 205 is applied to the word line, the bit line is charged with a potential of (Vword−Vth). Since the threshold voltage of the TFT has variations due to grain patterns and process variations, if the variation is δVth, an analog potential according to the distribution shown in FIG. 2C is charged to the bit line. become. As a result, this memory cell outputs a random potential based on variations in the threshold voltage of the TFT.

 FIG. 3 shows a configuration example of the read circuit, and shows a read circuit corresponding to one column of memory cells. The read circuit 301 includes a reference memory cell 302, a differential amplifier circuit 303, and a latch circuit 304. When the word line is selected, the memory cell 305 charges the bit line with the potential Vbit. On the other hand, a reference potential Vref is output from the reference memory cell 302, and these two potentials are compared and amplified by the differential amplifier circuit 303 and stored in the latch circuit 304.

 Note that the reference potential Vref is preferably close to the average value of the bit line potential charged by the memory cell. By doing so, also in each memory cell column, the memory cell data is assigned to 0 or 1 with a probability of almost ½, and a uniform random number is generated. For example, this can be realized by increasing the channel width of the TFT constituting the reference memory cell.

 As described above, a 1-bit random number is determined and latched based on the difference between the threshold voltage of the TFT constituting the reference memory cell 302 and the threshold voltage of the TFT constituting the selected memory cell 305. Stored in the circuit 304. More precisely, the random number is determined including variations in TFTs constituting the differential amplifier circuit 303, but in any case, the random numbers are determined by variations in TFT characteristics. In this way, it is possible to configure a random number ROM that stores random fixed data using the same manufacturing process.

 Note that the random number ROM described above can be manufactured by using a normal TFT manufacturing technique, and can be manufactured by the same process as that for manufacturing other integrated circuits. Therefore, there is no increase in the process cost associated with the production of the random number ROM, and the process cost can be kept low compared with the case of producing a flash memory.

Since the value stored in the random number memory circuit is random, the probability that the same ID is stored in different ID chips is not zero. However, even if a capacity of, for example, about 128 bits is considered, there are 2 ¹²⁸ random numbers that can exist, and the probability of matching the random numbers is substantially 0, so this is not a problem.

 By using the random number ROM as described above and using that data as data (identification number etc.) unique to the ID chip, it is possible to avoid disposable photomasks and increase process costs when manufacturing mask ROMs. It is possible to manufacture a low-cost ID chip without accompanying.

 Examples of the present invention are shown below.

 In this embodiment, a configuration example of a random number ROM different from the examples shown in FIGS. 2 and 3 will be described with reference to FIG. 2 and 3, the random number ROM that performs data determination by comparing each memory cell with the reference memory cell is shown. However, in this embodiment, data determination is performed by comparing potentials between adjacent memory cells. The structural example of random number ROM to perform is shown.

 FIG. 5 shows only a portion related to reading of a 1-bit random number in the memory cell array 506 and the reading circuit 501. When the memory cells 504 and 505 in the memory cell array 503 are selected, a potential reflecting the threshold voltage of the TFT constituting each memory cell is charged to the corresponding bit line. The differential amplifier circuit 502 amplifies the potential difference between both bit lines and stores data in the latch circuit 503.

 Compared with the random number ROM shown in FIG. 2, the configuration of the random number ROM according to the present embodiment is less susceptible to process variations that depend on the location because the memory cells to be compared are adjacent to each other. There is. As a result, it is possible to obtain high-quality random numbers with little distribution unevenness such as characteristic variations based on grain patterns. On the other hand, the type shown in FIG. 2 is a circuit configuration that is advantageous in terms of area, although random random numbers may be generated depending on the process.

 If the ID chip has only a function of reading fixed data such as an authentication number, a small amount of data is sufficient. For example, 128 bits is sufficient as an identification number unique to the ID chip. In such a case, it is possible to adopt a configuration in which the initial value of the shift register is given instead of arranging the memory cells constituting the random number ROM in a matrix.

 Such an example will be described with reference to FIG. 4A is a block diagram, FIG. 4B is a circuit diagram obtained by extracting a part thereof, and FIG. 4C is a timing chart. In FIG. 4A, a shift register 401 receives a clock signal and a load signal, and a random number ROM 402 receives a load signal and an address signal. The circuit shown in the figure loads random number data from the random number ROM to the shift register 401 by the load signal, and then serially outputs the random number data from the shift register 401 according to the clock signal.

 FIG. 4B shows an example of a circuit configuration related to 1 bit of the random number in the block diagram shown in FIG. In the figure, a shift register 401 using a clocked inverter and memory cells 406 and 407 connected to both ends of a flip-flop 403 constituting the shift register 401 via selection TFTs 404 and 405 are shown.

 FIG. 4C shows a timing chart. First, with the clock signal stopped, the initial value is loaded from the random number ROM 402 into the shift register 401. When the load signal is asserted, the power supply potential of the shift register 401 is grounded and the information stored in the register is erased, and a random potential is read from the memory cells 406 and 407 to the bit lines B1 and B2. The signal is applied to both ends P1 and P2 of the flip-flop 403 via the selection TFT. Thereafter, when the load signal is deasserted, the selection transistor is turned off and the register and the memory cell are disconnected. At the same time, the flip-flop 403 stores data having the analog potential charged by the memory cells 406 and 407 as an initial value, and loading of the random number into the shift register 401 is completed. Thereafter, by operating the clock signal, data unique to the chip is serially output.

 As described above, it is possible to realize a simple circuit having a function of storing and reading data unique to the ID chip.

 The present invention can also be used as a high-performance ID chip having a logic unit including a CPU or the like. FIG. 6 shows an example of such a configuration. In the figure, an ID chip 601 includes an antenna 602, an RF circuit 603, a power / clock signal / reset signal generation circuit 604, a data demodulation / modulation circuit 605, and a logic unit 606. The logic unit 606 further includes a control circuit 607, a CPU 608, a program ROM 609, a work RAM 610, and a random number ROM 611.

 The integrated circuit shown in FIG. 6 is all formed on a glass substrate or a flexible substrate. The antenna 602 may be formed on a substrate forming an integrated circuit, or may be outside the substrate forming the integrated circuit and connected to the integrated circuit through an input / output terminal.

 The ID chip shown in FIG. 6 is not limited to the function of simply reading the identification number assigned to the ID chip, and the CPU 608 can have various functions by executing a program stored in the program ROM 609 and performing processing. .

 Typically, it is a security function, and it is possible to perform processing such as password verification, memory divided into segments, and access authority controlled for each segment. It is also possible to perform encryption / decryption processing. For the encryption / decryption processing, dedicated hardware may be provided to improve the processing speed.

 Note that in the case where such a complicated integrated circuit is realized using a single crystal silicon substrate, the circuit area becomes large and impact resistance performance becomes a problem. In this respect, in the present invention, an ID chip having a high impact resistance can be realized even if the circuit area is somewhat increased by forming it on a flexible substrate.

 Note that this embodiment can be implemented in combination with other embodiments.

 In this embodiment, a process of forming a semiconductor element on a glass substrate and then transferring it to a plastic substrate will be described. A known method may be used for forming the semiconductor element on the glass substrate, and only a simple description will be given. In this embodiment, two TFTs are shown as an example of a semiconductor element, but the same applies when a diode, a resistance element, a capacitor element, or the like is formed.

  First, as illustrated in FIG. 7A, a metal film 701 is formed over the first substrate 700 by a sputtering method. Here, tungsten is used for the metal film 701, and the film thickness is 10 nm to 200 nm, preferably 50 nm to 75 nm. After the metal film 501 is formed, the oxide film 702 is formed without being exposed to the air. Here, a silicon oxide film is formed as the oxide film 702 so as to have a thickness of 150 nm to 300 nm.

  When the oxide film 702 is formed, pre-sputtering is performed in which plasma is generated by blocking the target and the substrate with a shutter as a pre-sputtering step. By pre-sputtering, a very thin metal oxide film 703 with a thickness of several nanometers is formed between the metal film 701 and the oxide film 702. In this embodiment, the metal oxide film 703 is made of tungsten oxide.

  Next, a base film 704 is formed using a PCVD method. Here, as the base film 704, a silicon oxynitride film is formed to a thickness of about 100 nm. After the base film 704 is formed, a semiconductor film 705 is formed. The semiconductor film 705 may be an amorphous semiconductor or a polycrystalline semiconductor. Thereafter, a high-quality polycrystalline semiconductor film is formed by laser crystallization or thermal crystallization. In the present invention, variation in TFT characteristics due to the grain pattern of the polycrystalline semiconductor film is important for the data stored in the random number ROM. In particular, in a TFT constituting a memory cell of a random number ROM, when the crystal grain size is about the same as the channel length, the characteristic variation becomes large, which is preferable.

In this embodiment, top gate TFTs 706 and 707 are formed using a polycrystalline semiconductor film (FIG. 7B).
A base film is formed on a substrate having an insulating surface as necessary, and a semiconductor film is formed. Thereafter, the semiconductor film is crystallized using laser light.

As the laser light, a continuous wave laser (CW laser) or a pulsed laser (pulse laser) can be used. Lasers include Ar laser, Kr laser, excimer laser, YAG laser, Y ₂ O ₃ laser, YVO ₄ laser, YLF laser, YalO ₃ laser, glass laser, ruby laser, alexandride laser, Ti: sapphire laser, copper vapor One or a plurality of lasers or gold vapor lasers can be used. The beam shape of the laser is preferably linear, and the length of the long axis may be 200 to 350 μm. Further, the laser may have an incident angle θ (0 <θ <90 degrees) with respect to the semiconductor film.

  Note that continuous wave fundamental laser light and continuous wave harmonic laser light may be emitted, or continuous wave fundamental laser light and pulsed harmonic laser light are emitted. You may do it.

The laser may be oscillated with a frequency of 10 MHz or more. A semiconductor film with high crystallinity can be obtained by a high-frequency oscillation laser as in the case of a continuous wave laser.

Further, crystallization may be performed using a heating furnace instead of laser light. In this case, crystallization can be performed at a low temperature by adding a metal element that promotes crystallization, such as Ni.

When a quartz substrate is used, a crystalline semiconductor film can be formed directly. Depending on the source gas, a crystalline semiconductor film can be formed directly on the glass substrate. In this case, a crystalline semiconductor film is directly formed on the surface to be formed using heat or plasma using a fluorine-based gas such as GeF ₄ or F ₂ and a silane-based gas such as SiH ₄ or Si ₂ H _6. Form.

 Thereafter, an island-shaped semiconductor film is formed by patterning, a gate insulating film 708 is formed, a gate electrode layer is formed and gate electrodes 709 and 710 are formed by patterning, and a source region, a drain region, an LDD region, etc. are formed by adding impurities. Then, the first interlayer insulating film 711 is formed, the contact holes are formed, and the wirings 712 to 715 are sequentially formed. Further, a second interlayer insulating film 716 is formed, contact holes are formed, and pads 717 are formed as necessary. The pad 717 is used as an antenna connection terminal of a non-contact ID chip or an input / output terminal of a contact ID chip.

  Next, a protective layer 718 is formed over the second interlayer insulating film 716 and the pad 717. The protective layer 718 can protect the surfaces of the second interlayer insulating film 716 and the pad 717 when the second substrate is attached or peeled later, and is removed after the second substrate is peeled off. A material that can be used is used. For example, the protective layer 718 can be formed by applying an epoxy resin, an acrylate resin, or a silicone resin soluble in water or alcohols over the entire surface and baking the resin (FIG. 7C).

  Next, the metal oxide film 703 is crystallized. By crystallization, the metal oxide film 703 is easily broken at the grain boundary, and later peeling is facilitated. In this example, crystallization was performed by heat treatment at 400 ° C. to 550 ° C. for about 0.5 to 5 hours.

  Next, treatment for partially reducing the adhesion between the metal oxide film 703 and the oxide film 702 or the adhesion between the metal oxide film 703 and the metal film 701 to form a part that triggers the start of peeling. I do. Specifically, the metal oxide film 703 is partially irradiated with a laser beam along the periphery of the region to be peeled off, or pressure is locally applied from the outside along the periphery of the region to be peeled off. In other words, the metal oxide film 703 may be damaged in the layer or in the vicinity of the interface.

  Next, the second substrate 720 is attached to the protective layer 718 using the double-sided tape 719, and the third substrate 722 is attached to the first substrate 700 using the double-sided tape 721. The third substrate 722 prevents the first substrate 700 from being damaged in a subsequent peeling step. As the second substrate 720 and the third substrate 722, it is preferable to use a substrate having higher rigidity than the first substrate 700, such as a quartz substrate or a semiconductor substrate.

  Next, the metal film 701 and the oxide film 702 are physically peeled off. The peeling starts from a region where the adhesion of the metal oxide film 703 to the metal film 701 or the oxide film 702 is partially lowered in the previous step. Then, the semiconductor element (here, TFTs 706 and 707) is separated from the second substrate 720 side, and the first substrate 700 and the metal film 701 are separated from each other while being adhered to the third substrate 722 side. The state after peeling is shown in FIG.

  Next, the flexible substrate 723 and the oxide layer 702 are bonded with an adhesive 724 (FIG. 8A). As the flexible substrate 723, a known material such as a metal typified by stainless steel or a plastic substrate can be used. In addition, as the adhesive 724, various curable adhesives such as a reaction curable adhesive, a thermosetting adhesive, a photocurable adhesive such as an ultraviolet curable adhesive, and an anaerobic adhesive can be used.

  Next, as shown in FIG. 8B, the double-sided tape 719 and the second substrate 720 are peeled from the protective layer 718 sequentially or simultaneously. Then, as shown in FIG. 8C, the protective layer 718 is removed. Here, since a water-soluble resin is used for the protective layer 718, it is dissolved in water and removed.

 As described above, by forming a semiconductor element on a glass substrate and further transferring it to a flexible substrate as necessary, a semiconductor integrated circuit incorporated in the ID chip of the present invention can be manufactured.

 This embodiment can also be applied to the modes shown in other embodiments.

  An application example of the present invention will be described with reference to FIG. The semiconductor integrated circuit constituting the ID chip of the present invention may be manufactured on a glass substrate and bonded directly to a flexible substrate or an object using a transfer technique from the glass substrate. In this case, the ID chip has a thin film integrated circuit peeled from the glass substrate. Hereinafter, description will be made using a thin film integrated circuit.

A semiconductor integrated circuit or a thin film integrated circuit operates using a signal received from an antenna, but the antenna may be formed together with the semiconductor integrated circuit or separately.

  FIG. 9A illustrates a state where the thin film integrated circuit 901 and the antenna 902 are formed together and directly bonded to the object 903. In the case of the mode shown in FIG. 9A, since the connection between the antenna and the thin film integrated circuit is already completed, there is an advantage that the bonding accuracy is not so much required and the bonding can be completed only once.

  Note that FIG. 9A illustrates a mode in which the thin film integrated circuit 901 and the antenna 902 are directly attached to the object 903; however, the thin film integrated circuit 901 and the antenna 902 over a flexible substrate are attached to the object 903. You may make it match. In this case, the attachment of the IC tag to the object becomes easier and the versatility of the IC tag can be improved.

  FIG. 9B illustrates a state in which the thin film integrated circuit 911 and the antenna 912 are formed separately and bonded to the object 913 together. Note that in FIG. 9B, the antenna 912 is formed on the flexible substrate 914 and further bonded to the object 913. The antenna 912 may be separately formed and transferred onto the flexible substrate 914, or directly by a printing method typified by a screen printing method or an offset printing method, a droplet discharge method, a vapor deposition method, a photolithography method, or the like. It may be used and formed on the flexible substrate 914.

  The droplet discharge method means a method of forming a predetermined pattern by discharging droplets containing a predetermined composition from the pores, and includes an ink jet method and the like in its category.

  Note that the thin film integrated circuit 911 and the antenna 912 may be stacked to be stacked as illustrated in FIG. 9B or may be bonded to each other. The order in which the thin film integrated circuit 911 and the antenna 912 are stacked is not limited to the mode illustrated in FIG.

  In FIG. 9B, the separately formed antenna 912 and the thin film integrated circuit 911 may be attached to the same support and further attached to the object 913 in that state. In this case, the attachment of the IC tag to the object becomes easier and the versatility of the IC tag can be improved.

  FIG. 9C illustrates an example in which the antenna 122 is formed over the object 123 in advance. The antenna 922 may be separately formed and attached to the object 923, or may be formed on the object 923 using a direct printing method, a droplet discharge method, a vapor deposition method, a photolithography method, or the like. You can keep it. Then, the thin film integrated circuit 921 is attached directly to the object 923 on which the antenna 922 is formed, or in a state where the thin film integrated circuit 921 is formed on the flexible substrate. Note that the thin film integrated circuit 921 may be attached to be aligned with the antenna 922 or may be attached to the antenna 922 so as to be stacked.

 Note that this embodiment can be implemented in combination with any of the other embodiments.

 In this embodiment, a method for manufacturing a thin film integrated circuit incorporated in an ID chip of the present invention, particularly a step of peeling a semiconductor integrated circuit from a substrate will be described. Since other structures such as a thin film transistor are the same as those in the above embodiment, the same reference numerals are given and description thereof is omitted.

As shown in FIG. 12A, a peeling layer 720 is formed over a substrate 700, and a plurality of ID chips having a thin film integrated circuit are formed over the peeling layer with a base film 704 interposed therebetween.

 As the substrate, a glass substrate, a quartz substrate, a substrate formed of an insulating material such as alumina, a silicon wafer substrate, a plastic substrate having heat resistance that can withstand a processing temperature in a subsequent process, or the like can be used. In this case, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y) (x, y = 1, 2,...) For example, a base insulating film for preventing diffusion of impurities from the substrate side may be formed. In addition, a substrate in which an insulating film such as silicon oxide or silicon nitride is formed on the surface of a metal such as stainless steel or a semiconductor substrate can also be used.

 The peeling layer (peel off layer) is a layer provided between the substrate and the thin film integrated circuit, and the substrate and the thin film integrated circuit can be separated later by removing the peeling layer. As the separation layer, a layer mainly containing silicon (Si, silicon) such as amorphous silicon, polycrystalline silicon, single crystal silicon, or SAS (semi-amorphous silicon (also referred to as microcrystalline silicon)) is used. it can.

Since halogenated fluorine such as ClF ₃ (chlorine trifluoride) has a characteristic of selectively etching silicon, by using a layer mainly composed of silicon (Si, silicon) as a peeling layer, ClF ₃ The release layer can be easily removed with a gas or liquid containing.

The base film is provided between the peeling layer and the thin film integrated circuit, and has a role of protecting the thin film integrated circuit from etching with fluorine halide such as ClF ₃ . Here, fluorine halide such as ClF ₃ has a characteristic of selectively etching silicon, but silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy or SiNxOy) are hardly etched. Accordingly, the peeling layer is etched with time, but the base film made of silicon oxide, silicon nitride, or silicon oxynitride is hardly etched, so that damage to the thin film integrated circuit can be prevented.

Note that the combination of the release layer and the base film is limited to the above materials, provided that a material that is etched by halogenated fluorine such as ClF ₃ is used as the release layer and a material that is not etched is used as the base film. It is not a thing and can be selected suitably.

  As shown in FIG. 12B, a groove 721 is formed at the boundary between a plurality of ID chips.

  The groove forming the boundary of the thin film integrated circuit can be formed by dicing, scribing, etching using a mask, or the like. In the case of dicing, a blade dicing method using a dicing apparatus (dicer) is generally used. The blade is a grindstone in which diamond abrasive grains are embedded, and has a width of about 30 to 50 μm, and the thin film integrated circuit is separated by rotating the blade at a high speed. In the case of scribing, there are a diamond scribing method and a laser scribing method. In the case of etching, a mask pattern can be formed by exposure and development processes, and element isolation can be performed by dry etching, wet etching, or the like. In dry etching, an atmospheric pressure plasma method may be used.

  As shown in FIG. 12C, a gas or liquid 722 containing fluorine halide is introduced into the groove, and the peeling layer is removed.

Further, as the halogenated fluorine, a gas in which nitrogen is mixed with the above ClF ₃ or the like may be used. Further, ClF ₃ may be a liquid (boiling point: 11.75 ° C.) depending on the temperature of the reaction space, and wet etching can be employed at that time. Note that ClF ₃ can be produced through a process of Cl ₂ (g) + 3F ₂ (g) → 2ClF ₃ (g) by reacting chlorine with fluorine at 200 ° C. or higher. An etchant that etches the release layer and does not etch the underlying film is not limited to ClF ₃ and is not limited to fluorine halide.

  After that, as shown in FIG. 12D, the peeling layer is etched with time, so that the substrate 800 can be finally peeled. On the other hand, silicon oxide, silicon nitride, silicon oxynitride, or the like, a base film made of a heat resistant resin, and an interlayer insulating film are hardly etched, so that damage to the thin film integrated circuit can be prevented. Note that the peeled substrate 700 can be reused, which leads to cost reduction. In the case of reuse, it is desirable to control so that no scratches are generated on the substrate in the dicing, scribing or the like. However, even when scratches are generated, an organic resin or an inorganic film may be formed by a coating method or a droplet discharge method (inkjet method or the like), and planarization may be performed.

  Note that a protective layer 718 is preferably formed over the thin film integrated circuit in order to protect the thin film integrated circuit from being etched by fluorine halide or the like. In particular, when etching is performed by heating a halogenated fluorine gas as in the low pressure CVD method, it is desirable to use a heat resistant organic resin or a heat resistant inorganic film. As a typical heat-resistant organic resin, a skeleton structure is formed by a bond of silicon and oxygen, and a material containing at least hydrogen as a substituent, or at least a fluorine, an alkyl group, or an aromatic hydrocarbon as a substituent There is a material having one kind, which is also referred to as a so-called siloxane resin.

  In this embodiment, a jig (jig) may be formed above the plurality of thin film integrated circuits with an adhesive, and a gas or liquid containing fluorine halide may be introduced into the groove.

  The jig refers to a support substrate for temporarily fixing the thin film integrated circuit so that the thin film integrated circuit is not separated apart after the peeling layer is removed. The jig is formed for each thin film integrated circuit constituting a single chip or thin film integrated circuit, or for each element formed by integrating a plurality of thin film integrated circuits in the horizontal direction or the height direction. The shape of the jig is preferably a comb-like structure provided with protrusions in order to facilitate the introduction of a gas or liquid containing halogenated fluorine later, but a flat jig may be used. Moreover, as a jig, a glass substrate, a quartz substrate, a stainless steel (SUS) substrate, etc., mainly composed of silicon oxide that is not affected by halogenated fluorine can be used. It is not limited to.

  In addition, an adhesive for temporary bonding is provided between the jig and the thin film integrated circuit. As the adhesive, a material whose adhesive strength (adhesive strength) is reduced or lost by UV light irradiation can be used. Alternatively, a re-peelable and re-adhesive adhesive used for 3M Post-it (registered trademark) products, Moore Note Sticks (registered trademark) products, or the like may be used. Of course, the material is not limited to these as long as the material allows the jig to be easily removed.

  In this embodiment, an insulating film having heat resistance may be formed on the thin film integrated circuit, and a groove may be formed at the boundary between the plurality of thin film integrated circuits.

  As the insulating film having heat resistance, a skeleton structure is formed by a bond of silicon and oxygen, and a material containing at least hydrogen as a substituent, or at least one of fluorine, an alkyl group, or an aromatic hydrocarbon as a substituent. A material having heat resistance, that is, a heat-resistant organic resin such as a siloxane resin, or a heat-resistant inorganic material can be used.

 The peeling method as in this embodiment applies stress to a substrate on which a plurality of thin film integrated circuits are formed, and is compared with a physical method in which the substrate is physically peeled off from a substrate on which a plurality of thin film integrated circuits are formed. When the thin film integrated circuit is separated, a chemical method using a halogenated fluorine is employed, which is preferable because element separation can be reliably performed.

  As described above, as described above, a substrate such as a metal such as stainless steel or a semiconductor substrate on which an insulating film such as silicon oxide or silicon nitride is formed can be used. For example, as shown in FIG. 15A, an Si film 900 is covered and an oxide film, that is, a silicon oxide film 901 is formed by thermal oxidation or the like, and this can be used as a substrate. Thereafter, similarly, as shown in FIG. 15B, a gas or liquid 822 containing fluorine halide is introduced into the groove, and the release layer is removed. Then, as shown in FIG. 15C, the substrate 800 can be finally peeled off.

 Note that this embodiment can be implemented in combination with any of the other embodiments.

In this embodiment, a completed drawing of the ID chip of the present invention will be described. In this embodiment, an ID chip on which a semiconductor integrated circuit is mounted will be described. However, a thin film integrated circuit from which a substrate is peeled may be mounted.

As shown in FIG. 13A, a region (semiconductor integrated circuit region) 850 including a semiconductor integrated circuit or the like over the substrate 800 is formed. The above embodiment can be referred to for a method for manufacturing a semiconductor integrated circuit or the like.
An antenna 851 is formed over the semiconductor integrated circuit region with an insulating film 852 interposed therebetween. The antenna can be formed by, for example, a droplet discharge method. As the insulating film 852, for example, the protective film 813 described in the above embodiment can be used.
The antenna needs to be connected to the semiconductor integrated circuit. Therefore, for example, a contact hole is formed in the insulating film, and a connection terminal portion provided in the antenna is connected to a pad included in the semiconductor integrated circuit. At this time, you may connect via a conductive resin.

After that, as illustrated in FIG. 13B, an insulating film 853 functioning as a protective film is formed so as to cover the semiconductor integrated circuit and the antenna. The insulating film 853 can be formed using an organic material or an inorganic material. As a result, the semiconductor integrated circuit can be protected from the outside, and the ID chip can be completed in a form that is easy to carry. Further, by covering with an insulating film 853, the function of the semiconductor integrated circuit can be assisted.

FIG. 14A is a cross-sectional view taken along a line AB in FIG.
A semiconductor integrated circuit 850 provided over the substrate 800, an insulating film 852 provided over the semiconductor integrated circuit, an antenna 851 provided over the insulating film, and an insulating film 854 functioning as a protective film provided so as to cover the antenna Are formed in order, and an insulating film 853 is provided so as to cover them.
The contact hole is formed in the insulating film as described above, and the antenna and the semiconductor integrated circuit can be connected by connecting the connection terminal portion provided in the antenna and the pad included in the semiconductor integrated circuit (not shown). ).

By forming the antenna on the semiconductor integrated circuit, the ID chip can be miniaturized.

Further, the ID chip can be completed with a structure other than those shown in FIGS. 13 and 14A.

For example, as illustrated in FIG. 14B, an antenna 851 may be provided on the insulating film 853 side. The antenna is covered with an insulating film 855 functioning as a protective film, and a contact hole is provided in a region connected to the semiconductor integrated circuit.
On the semiconductor integrated circuit side, a contact hole is provided in a region connected to the antenna in the insulating film 852 provided over the pad 812. Then, the pad 812 included in the semiconductor integrated circuit and the antenna 851 can be connected through the conductive resin 856.

Thus, by forming an antenna on the insulating film 853 side and forming it separately from the semiconductor integrated circuit, the yield is improved.

  As shown in FIG. 14C, an antenna 851a provided over the semiconductor integrated circuit and an antenna 851b provided on the insulating film 853 side may be formed together. In this case, a contact hole is provided in a region connected to the antenna 851b in the insulating film 854 covering the antenna 851a, and a contact hole is provided in a region connected to the antenna 851a in the insulating film 855 covering the antenna 851b. Then, the antenna 851a and the antenna 851b can be connected through the conductive resin 856.

  With such a structure in which the antenna is formed in many regions, a highly sensitive ID chip can be formed.

As described above, the ID chip can have various configurations.

  In this embodiment, an example in which the ID chip of the present invention is used as an IC tag will be described.

  The ID chip of the present invention can be used in various fields. For example, it is possible to attach the ID chip of the present invention to a product label and manage the distribution of the product using the ID chip.

  As shown in FIG. 10A, an IC tag 1002 is formed on a support having a sticky back surface such as a seal 1001. Then, the IC tag 1002 is attached to a product label 1003. Next, as illustrated in FIG. 10B, the label 1003 to which the IC tag 1002 is attached is attached to the product 1004.

  The identification information regarding the product 1004 can be read wirelessly as shown in FIG. 11C from the IC tag 1002 attached to the label 1003. For example, it is possible to manage the database by reading a unique identification number from a random number ROM built in the IC tag and collating it on the network. The database includes a record of the distribution process of the product 1004 and a record of the process in the production stage, so that the wholesaler, retailer, and consumer can grasp the place of production, producer, date of manufacture, processing method, and the like. It becomes possible. In this way, it is possible to easily manage merchandise in the distribution process.

  In this embodiment, only an example of the use of the ID chip of the present invention is shown. The application of the ID chip of the present invention is not limited to the form shown in FIG. 10, and can take various forms.

 Note that this embodiment can be implemented in combination with those shown in Embodiments 1 to 7.

  In this embodiment, a usage form of the ID chip of the present invention will be described.

  FIGS. 11A, 11B, and 11C show examples of a product pack 1121 on which a check 1101, a passport 1111, and a display label 1123 each having an ID chip 1102 of the present invention are attached.

  Forgery of banknotes, checks, family register copies, resident cards, traveler's checks, passports, and the like can be prevented by using data in a random number ROM that cannot rewrite data contained in the ID chip of the present invention as an identification number. Further, for example, using the ID chip of the present invention for food products whose merchandise value is greatly influenced by the production area, producer, etc. is useful for preventing impersonation of the production area, producer, etc. at a low cost.

  Further, since the ID chip of the present invention is inexpensive, it is suitable for an application that is finally discarded by a consumer. In particular, in the case of a product (for example, FIG. 11C) in which the difference in price between several yen and several tens of yen greatly affects sales, the inexpensive ID chip of the present invention is very useful. If the price of the product is written as data on the ID chip 1122, the product can be settled even if the distance between the register and the product is longer than the method using a conventional barcode, and shoplifting is prevented. Also useful.

  Moreover, since the ID chip of the present invention has flexibility and excellent impact resistance, the shape can be changed to some extent in accordance with the shape of the object to which the ID chip is attached. Therefore, the ID chip of the present invention can be used for various applications that cannot be used by using an integrated circuit formed over a single crystal silicon substrate.

  Note that this embodiment can be implemented in combination with those shown in Embodiments 1 to 7.

The block diagram of ID chip of the present invention. The figure explaining random number ROM in this invention. The figure explaining random number ROM in this invention. The figure explaining random number ROM and a shift register in this invention. The figure explaining random number ROM in this invention. The block diagram of ID chip of the present invention. The manufacturing process figure of ID chip | tip of this invention. The manufacturing process figure of ID chip | tip of this invention. The figure showing the form of the ID chip of this invention. An application example of the ID chip of the present invention. An application example of the ID chip of the present invention. The manufacturing process figure of ID chip of this invention which has a peeling process. The figure explaining the completed figure of an ID chip. Sectional drawing explaining the completion figure of ID chip. The manufacturing process figure of ID chip of this invention which has a peeling process.

Claims (8)

A non-rewritable nonvolatile memory having a thin film transistor,
The nonvolatile memory stores unique data based on characteristic variations of the thin film transistor,
A thin film integrated circuit characterized in that data of the nonvolatile memory can be read out in a contactless manner by connecting an antenna. It has a non-rewritable non-volatile memory composed of thin film transistors and an antenna,
The nonvolatile memory stores unique data based on characteristic variations of the thin film transistor,
A thin film integrated circuit, wherein the data of the nonvolatile memory can be read without contact. 3. The thin film integrated circuit according to claim 1, wherein the active layer of the thin film transistor is made of a polycrystalline semiconductor film. 4. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit according to claim 1 is formed on a glass substrate or a flexible substrate. A semiconductor device incorporating the thin film integrated circuit according to claim 1. A semiconductor device incorporating the semiconductor integrated circuit according to claim 4. It has a non-rewritable nonvolatile memory composed of thin film transistors,
The nonvolatile memory stores unique data based on characteristic variations of the thin film transistor,
A semiconductor device, wherein the data in the nonvolatile memory can be read without contact. A card or tag on which the semiconductor device according to any one of claims 5 to 7 is mounted.

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