JP2003151294A - Programmed value determining circuit, semiconductor integrated circuit device including the same, and method for determining programmed value - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a programmed value determining circuit in which both of area of programmable elements and a leak current are reduced. SOLUTION: During a first period after power is turned on, both a PMOS transistor Qp1 and a NMOS transistor Qn1 are turned off, and a storage node is disconnected from a power source line VDD and a ground line VSS. During a second period after the first period, at least the NMOS transistor Qn1 is turned on, the storage node is connected to the ground line VSS through a program element 10, and a state of the storage node is detected by a detecting section 11. During a third period after the second period, the PMOS transistor Qp1 and the NMOS transistor Qn1 are turned off, and a state of the storage node is held by a latch section 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device including a program element, and more particularly to a technique for reducing the leak current and the area of the program element.
In addition, the present invention is a technique for making the area of a fuse element and the like compatible with the elimination of a leak current flowing through the residual resistance thereof in a memory block in which a plurality of program elements must be mounted for redundancy relief. Regarding

[0002]

2. Description of the Related Art Conventionally, a fuse element is generally used as a program element used in a memory block or the like, and the fuse element is programmed by irradiating it with a laser to blow (blown) it. The method of setting presence / absence is common. However, in order to accurately blow the fuse element with the laser, it is necessary to adjust the power of the irradiation laser.

FIGS. 12A, 12B and 12C are circuit diagrams showing a configuration example of a conventional program value determination circuit using a fuse element as a program element used in a memory block or the like. FIG. 12A shows a fuse element 10.
The state without the program before blowing 0, FIG. 12B
12C shows a programmed state after blowing the fuse element 100 with high laser power, and FIG. 12C shows a programmed state after blowing the fuse element 100 with low laser power.

In FIG. 12A, when a logic "H" level voltage is applied to the input node N1, the first stage PMOS transistor Qp1 is turned off, the first stage NMOS transistor Qn1 is turned on, and the fuse element 100 is in the connected state. , The intermediate node (storage node) N2 is the ground line VS
It becomes the logic "L" level which is the potential of S, and the PMO
The S transistor Qp3 is turned on, the NMOS transistor Qn2 in the subsequent stage is turned off, and the voltage of the logic "H" level which is the potential of the power supply line VDD is output to the output node N3. As a result, the PMOS transistor Qp2 is turned off. This state is the state without the program.

On the other hand, in FIGS. 12B and 12C,
When the fuse element 100 is blown, the input node N
When a logical "H" level voltage is applied to 1, the first stage P
Although the MOS transistor Qp1 is turned off and the first-stage NMOS transistor Qn1 is turned on, the fuse element 100 is in a cut state, so that the intermediate node N2 is at the potential of the power supply line VDD when the PMOS transistor Qp2 is turned on. It becomes "H" level, the PMOS transistor Qp3 in the subsequent stage is turned off, and the NMOS transistor Q in the subsequent stage
n2 is turned on, and the ground line VSS is applied to the output node N3.
The voltage of the logic "L" level which is the potential of is output. This state is the state with the program.

[0006]

As shown in FIG. 12B, in order to completely blow the fuse element 100 (residual resistance value of the fuse element 100 is set to, for example, 1 M ohm or more), the power of the laser to be irradiated is increased. However, there is a possibility that the fuse element in the adjacent region may be blown. Therefore, when a plurality of fuse elements are provided, there is a problem that the area is increased due to an increase in the interval between the fuse elements and the inability to lay out transistors in adjacent regions.

On the other hand, if the power of the laser to be irradiated is lowered, the irradiation point is also narrowed and the influence on the adjacent region can be reduced. However, as shown in FIG. 12C, the residual resistance value of the fuse element 100 becomes low (for example, 10 kΩ or less), and the power line VDD is connected to the ground line VSS via the PMOS transistor Qp2 and the NMOS transistor Qn1 in the ON state. Leakage current Ilea
There is a problem that k flows.

FIG. 13 is a diagram showing the relationship between the fuse pitch Hpitch and the relative laser power Lpower, the residual resistance value Rfuse after blowing the fuse element 100, and the leak current Ileak flowing therethrough.

As shown in FIG. 13, the fuse pitch Hp
Relative laser power Lpower
When is smaller, the fuse element 100 is completely blown or not blown, and becomes unstable, and the residual resistance value Rfuse has a large variation. In particular, when the residual resistance value Rfuse becomes small, the leak current Ilea
Since there is a problem that k becomes large, the fuse pitch Hpitch, that is, the area and the leakage current Il are conventionally used.
It required a trade-off with eak.

In the future, as the process becomes finer and many functions are integrated, the importance of constructing a circuit for realizing the defect relief function by an FPGA (Field Programmable Gate Array) or the like will increase, and LSI will be implemented. It is considered that the need for the on-board programming elements will increase rapidly. At this time, the problem is the area of the program element.

As a method of constructing the program element,
In addition to the method of blowing the fuse element with the laser as described above, the high voltage is applied to melt the polysilicon wiring, or the high voltage stress is applied to increase the threshold voltage like the flash memory. There is a way. But,
In all of these, in order to stably generate a change in resistance value and a change in threshold voltage, it is necessary to place a distance from an adjacent device or increase the area of itself.

When the area is prioritized to increase the integration,
It is expected that the resistance value of the polysilicon wiring and the threshold voltage of the flash memory will not be sufficiently changed to cause a leak current problem.

The present invention has been made in view of the above problems, and an object thereof is to eliminate the trade-off relationship between the area of the program element and the leak current, and reduce both the area of the program element and the leak current. A program value determination circuit, a semiconductor integrated circuit device having the program value determination circuit, and a program value determination method are provided.

[0014]

In order to achieve the above-mentioned object, a program value judging circuit according to the present invention includes a program element accompanied by a change in resistance value with and without a program, and first and second control signals. Of the first and second power supply terminals, the first and second power supply terminals connected in series with the program element between the first power supply terminal and the second power supply terminal. At least a first switch element is inserted between the first connection circuit and a second power supply terminal, and a first circuit in which at least a second switch element connected in series with the program element is inserted, and an intermediate connection A detection unit including a second circuit that converts the potential of the node to a logic level and outputs the logic level to an output node, and a latch that latches the potential of the intermediate connection node and uses the intermediate connection node as a storage node for a program value A second switching element is turned on during a second period after the first period after the power is turned on, and the storage node is connected to the second power supply terminal via the program element. The state of the storage node is detected by the detection unit, the first and second switch elements are both turned off in the third period after the second period, and the state of the storage node is held by the latch unit. Is characterized by.

In the program value determination circuit according to the present invention, both terminals of the program element are disconnected from at least one of the first and second power supply terminals during the first and third periods, respectively, and the second terminal During the period of, it is characterized in that it is connected between the first and second power supply terminals directly or via the first and second switch elements.

In the program value judgment circuit according to the present invention, the first switch element is composed of a first transistor which is drive-controlled by the first control signal, and the second switch element is composed of the second control signal. The memory node is connected to the first power supply terminal via the first transistor and is connected to one terminal of the program element via the second transistor. The other terminal of the program element is connected to the second power supply terminal, and the first transistor is turned off in the first period, turned on in the second period, and turned on in the third period by the first control signal. Is turned off during the period, and the second transistor is turned off during the first period, turned on during the second period, and turned off during the third period by the second control signal. Features and That.

With the above configuration, the period (second period) for detecting the program state of the program element is limited to a certain period when the power is turned on, and only during that period, the storage node for the program value operates the program element. Is connected to one of the power supply terminals via the other, but otherwise (first and third periods)
Is controlled, and control is performed to completely disconnect the program element from the leak path between the power supply terminals. This eliminates the trade-off relationship between the area of the program element and the leak current, and both the area of the program element and the leak current can be reduced.

Alternatively, in the program value determination circuit according to the present invention, the first switch element is composed of a first transistor which is drive-controlled by a first control signal, and a second transistor
Of the switch element is composed of a second transistor which is driven and controlled by the second control signal, and the storage node is connected to the first power supply terminal via the first transistor,
Is connected to one terminal of the program element through the transistor of, the other terminal of the program element is connected to the second power supply terminal, and the first transistor is connected to the first and second terminals by the first control signal. The second transistor is turned on during the third period and is turned off during the third period, and the second transistor is turned off during the first period, turned on during the second period, and turned on during the third period by the second control signal. Is turned off during the period.

According to this structure, the storage node is temporarily set to the logic "H" level from the power supply line VDD via the first transistor before the second period starts, regardless of whether the storage node is programmed or not. By being precharged, it is possible to more stably determine whether or not there is a program in the second period.

In the program value judgment circuit according to the present invention, the latch means includes a third circuit connected between the intermediate connection node and the output node, and the third circuit and the second circuit cooperate with each other. Then, the intermediate connection node is used as a storage node for the program value.

In this case, the third circuit includes the third and fourth circuits.
Is connected to the first and second power supply terminals via a signal line for transmitting the control signal, and power is supplied. Further, the first and second control signals are delayed more than the third and fourth control signals, and the first control signal and the second control signal, and the third control signal and the fourth control signal are It is preferable to have a logical inversion relationship.

According to the above configuration, the current load of the latch means is disconnected from the storage node of the detection section with a margin of time td before entering the second period, and the latch section operates in the second period. A stable program value determination operation can be realized by latching the state of the storage node before the state of the storage node has a margin of time td before the state ends, before it ends. Further, since the four control signals have a delay and a logical inversion relationship, they can be easily generated.

In the program value determination circuit according to the present invention, the current flowing in the third period is defined by the leak current of the latch means or the off currents of the first and second switch elements.

In order to achieve the above-mentioned object, the first semiconductor integrated circuit device according to the present invention has the program value judgment circuit according to the present invention, and the permissible value of the leakage current flowing through each program element is In the set semiconductor integrated circuit device, the program value determination circuit is configured such that when the current flowing when the voltage near the power supply voltage is applied to the program element exceeds the allowable value of the leakage current, there is no program, It is characterized in that it is determined that the program is present when the current is less than or equal to the allowable value, and one of the binary logic levels is output to the functional circuit as the determination result.

In this case, the first semiconductor integrated circuit device is
A semiconductor memory device having a plurality of regular memory blocks and one redundant memory block, the functional circuit comprising:
A redundancy repair circuit for replacing a defective normal memory block with a normal normal memory block adjacent thereto or the redundant memory block.

According to the above configuration, when a fuse element that is blown by laser irradiation to be in a cut state and has a program is used as the program element, shift redundancy using a program value determination circuit that solves the problem of leak current is used. A relief circuit can be realized, and the power consumption of the semiconductor memory during standby can be reduced.

In order to achieve the above-mentioned object, a second semiconductor integrated circuit device according to the present invention has a program value determination circuit according to the present invention, and an allowable value of a current flowing through each program element is set. In the semiconductor integrated circuit device described above, the program value determination circuit is configured such that when the current flowing when the voltage near the power supply voltage is applied to the program element is equal to or less than the allowable value of the current, the program is not When it exceeds the allowable value, it is determined that the program exists, and one of the binary logic levels is output to the functional circuit as the determination result.

In this case, the second semiconductor integrated circuit device is
A semiconductor memory device having a plurality of regular memory blocks and one redundant memory block, the functional circuit comprising:
A redundancy repair circuit for replacing a defective normal memory block with a normal normal memory block adjacent thereto or the redundant memory block.

According to the above configuration, when a program element that is short-circuited due to gate breakdown and has a program is used as the program element, the relationship of the leak current when the fuse element is used as the program element is reversed.

To achieve the above object, a third semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device in which one chip is divided into a plurality of circuit blocks having different power supply systems. And a second program value determination circuit having a configuration similar to that of the first program value determination circuit. A second circuit block which is provided and has a smaller number of power-off times than the first circuit block, and the first program value determination circuit is limited to a certain period from power-on to power-off. , And each of the first to third periods at least once.

According to this configuration, the program value determination circuit that solves the problem of the leak current is applied to the LSI in which the power saving function is prioritized and the power supply is turned off and the power supply is turned on repeatedly for a part of the mounted circuit. Thus, the power consumption can be significantly reduced.

In order to achieve the above object, a fourth semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device in which one chip is divided into a plurality of circuit blocks having different power supply systems, and the power is cut off. And a second circuit block in which the power is turned on repeatedly, and a second circuit block in which the power is cut off less than the first circuit block. The second circuit block is the first circuit block. A corresponding first program value determination circuit according to the present invention;
And a second program value determination circuit corresponding to the second circuit block.

According to this structure, since the first and second program value determination circuits are arranged in the second circuit block in which the number of times of power interruption is smaller than that in the first circuit block, the power is turned on. As compared with the third semiconductor integrated circuit device in which a current is supplied to each program element, there is no fear that the memory capacity of the program element will deteriorate, the reliability of the program can be improved, and power saving can be further promoted. You can

In order to achieve the above-mentioned object, a fifth semiconductor integrated circuit device according to the present invention has a plurality of chips including at least a first chip and a second chip, and the second chip is a second chip. A multi-chip type semiconductor integrated circuit device which is laminated on the surface of one chip with its surface facing down and is electrically connected thereto, wherein the first chip has a first circuit block, and a second circuit block is provided. The chip has a second circuit block,
The first circuit block has a first program value determination circuit according to the present invention corresponding to the first circuit block and a configuration similar to the first program value determination circuit, and corresponds to the second circuit block. And a second program value determination circuit for performing the same.

According to this structure, in the semiconductor integrated circuit device having the chip-on-chip (COC) structure,
In addition to the advantages of the program value determination circuit according to the present invention, even after the second chip is pasted on the surface of the first chip with the surface facing down, for example, in the memory block included in the second circuit block. On the other hand, when performing redundancy repair, there is an advantage that the program element of the second program value determination circuit can be easily programmed by laser irradiation or the like.

In the third to fifth semiconductor integrated circuit devices, the plurality of program value judgment circuits including the first and second program value judgment circuits can make the timings of the first and second control signals different. preferable.

According to this structure, it is possible to prevent the malfunction of the logic level determination of the storage node due to the current flowing through the plurality of program elements at the same time and the voltage drop in the second period.

In order to achieve the above object, a sixth semiconductor integrated circuit device according to the present invention is a multi-chip type semiconductor integrated device in which a chip module having a plurality of chips arranged in a plane is mounted on a substrate. In a circuit device, a plurality of chips have a plurality of corresponding circuit blocks, and among the plurality of circuit blocks, the circuit block arranged closest to the power supply circuit formed on the substrate is the circuit block. And a program value determination circuit according to the present invention corresponding to the above, and a program value determination circuit having the same configuration as the program value determination circuit and corresponding to another circuit block.

According to this structure, in the semiconductor integrated circuit device in which the multi-chip module (MCM) is mounted on the substrate, in addition to the advantages of the program value determination circuit according to the present invention, a plurality of programs can be stored in one chip. By consolidating the value determination circuits, it is possible to easily program the program elements of the program value determination circuit, and a chip in which a plurality of program value determination circuits are integrated
By making the chip closest to the power supply circuit that generates a high voltage or a large current, it is not necessary to add an extra area or a process for increasing the withstand voltage when determining the program value, as compared with the case where it is distributed. There is an advantage that high voltage and large current can be easily supplied.

In the sixth semiconductor integrated circuit device, a program value judgment circuit corresponding to a circuit block arranged at a position closest to the power supply circuit formed on the substrate and a program value judgment circuit corresponding to another circuit block. It is preferable that the timings of the first and second control signals are made different between the plurality of program value determination circuits including and.

According to this structure, it is possible to prevent the malfunction of the logic level determination of the storage node due to the current flowing through the plurality of program elements simultaneously and the voltage drop in the second period.

In order to achieve the above object, the program value determination method according to the present invention operates according to a program element accompanied by a change in resistance value with and without a program, and first and second control signals. Includes first and second switch elements connected in series with the program element between the first power supply terminal and the second power supply terminal, and at least the first switch element is provided between the first power supply terminal and the intermediate connection node. A first circuit in which at least a second switch element inserted in series with the program element is inserted between the intermediate connection node and the second power supply terminal and a potential of the intermediate connection node is set to a logic level. Program value determination using a second circuit for converting into the output node and outputting to the output node, and latch means for latching the potential of the intermediate connection node and using the intermediate connection node as a storage node for the program value A second period after the first period after the power is turned on, at least the second switch element is turned on, and the storage node is connected to the second power terminal via the program element, In the step of detecting the state of the storage node by the first and second circuits and in the third period after the second period, both the first and second switch elements are turned off, and the latch means operates the storage node. Holding a state.

According to this method, the period (second period) in which the program state of the program element is detected is limited to a certain period when the power is turned on, and only during that period, the storage node for the program value is set to the program element. Is connected to one of the power supply terminals via, but otherwise (first and third periods)
Is controlled, and control is performed to completely disconnect the program element from the leak path between the power supply terminals. This eliminates the trade-off relationship between the area of the program element and the leak current, and both the area of the program element and the leak current can be reduced.

[0044]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

Here, before describing the embodiment,
First, the concept of the present invention will be described. INDUSTRIAL APPLICABILITY The present invention is applied to a system LSI which is required for future portable device applications and the like, which does not involve a leak current during standby and needs to incorporate many program elements. Therefore, the present invention has the features listed below.

(1) The period during which the program state of the program element is detected is limited to a certain period when the power is turned on,
Only during that period, the storage node for the program value is connected to at least one power supply terminal through the program element, but is otherwise disconnected, and control is performed to completely disconnect the program element from the leak path between the power supply terminals. .

Further, by providing means for latching the state of the program value storage node, the program value is held by the latch means even when the program value storage node is completely disconnected from the power supply terminal. To do so.

(2) LS in which the power saving function is prioritized and the power supply is cut off and turned on repeatedly for a part of the mounted circuit.
In the case of I, the control of the above (1) is repeated only for the program value determination circuit mounted in the circuit block that repeatedly shuts down the power and turns on the power. Of course, the program value determination circuit in the circuit block in which the power is not shut off may repeat the control of (1) in synchronization with the operation of the program value determination circuit in the circuit block in which the power is shut off. Alternatively, only the program value determination circuit can be connected to a power supply line that is not shut off.

Next, based on the above concept of the present invention,
A specific embodiment will be described.

(First Embodiment) FIGS. 1A and 1B.
[FIG. 3] is a configuration example of a program value determination circuit according to the first embodiment of the present invention, and is a circuit diagram showing a state without a program and a state with a program, respectively.

1A and 1B, the program value determination circuit includes a program element 10 (for example, a fuse element blown by a laser, a fuse element blown by applying a high voltage), a first control line 13 and a first control line 13. According to the first control signal RSTp and the second control signal RSTn respectively applied to the two control lines 14, the program element 1
Based on a change in the resistance value of 0, a detection unit 11 that detects the presence or absence of a program and a latch unit 12 that latches the level of the storage node 15 are included.

In the detection section 11, the gate has the first control line 13
, A source connected to the power supply line VDD, a drain connected to the storage node 15 and a PMOS transistor Qp1 (first switch element), a gate connected to the second control line 14, and a source connected to the program element. N connected to one end of 10 and its drain connected to the storage node 15
A MOS transistor Qn1 (second switch element),
The gate is connected to the storage node 15, and the source is the power line V
A PMOS transistor Qp2 connected to DD and a drain connected to the output node 16; and an NMOS transistor Qn2 connected to the storage node 15 at the gate, connected to the ground line VSS at the source, and connected to the output node 16 at the drain. including.

That is, the detection unit 11 includes the PMOS transistor Qp1 and the NMOS transistor Q which are connected in series.
It is configured by a two-stage inverter including an inverter made up of n1 (first circuit) and an inverter made up of a PMOS transistor Qp2 and an NMOS transistor Qn2 (second circuit) connected in series.

The other end of the program element 10 is connected to the ground line VSS.

In this embodiment, the program element 1
Although 0 is connected between the NMOS transistor Qn1 and the ground line VSS, the present invention can be similarly applied to the case where the program element is inserted in another place between the two power supply terminals in the first circuit. One of ordinary skill in the art would readily understand.

In the latch section 12, the gate is the output node 16
, A source connected to the power supply line VDD, a drain connected to the storage node 15, a gate connected to the output node 16, a source connected to the ground line VSS, and a drain connected to the storage node 15.
And an NMOS transistor Qn3 connected to.

That is, in the latch section 12, the PMOS transistor Qp3 and the NMOS transistor Qn3 are connected in series, and an inverter (third circuit) for feeding back from the output node 16 to the storage node 15 and the PMOS transistor Qp2 connected in series are provided. And an inverter (second circuit) including an NMOS transistor Qn2.

Next, the operation of the program value judging circuit having such a structure will be described with reference to FIG.

FIG. 2 is a timing chart for determining the presence / absence of a program with the above configuration. As shown in FIG. 2, first, in the period T1, the first control signal RSTp
Is a logic "H" level, the second control signal RSTn is a logic "L" level, and both the PMOS transistor Qp1 and the NMOS transistor Qn1 are off.
Therefore, the storage node 15 becomes the logic "L" level regardless of the presence or absence of the program, and the output signal ROUTn to the output node 16 becomes the logic "H" level.

Next, at the beginning of the period T2 (determination period),
The first control signal RSTp is changed from the logic "H" level to "L".
When the level of the second control signal RSTn is changed from the logic "L" level to the "H" level, both the PMOS transistor Qp1 and the NMOS transistor Qn1 are turned on. At this time, when the fuse element, which is the program element 10, is in the connected state, that is, the state without programming (FIG. 1A), the storage node 15 remains at the logic “L” level, and therefore the output signal ROUTn also has the logic “H”. It remains at the level.

On the other hand, the fuse element which is the program element 10 is in the cut state, that is, the state with the program (FIG. 1).
B), the PMOS transistors Qp1 and N
When both the MOS transistors Qn1 are turned on, the storage node 15 transits from the logic "L" level to the "H" level, and the output signal ROUTn transits from the logic "H" level to the "L" level.

In the subsequent period T3, the first control signal R
STp is set to "H" level and the second control signal RSTn is set to logic "L" level to turn off both the PMOS transistor Qp1 and the NMOS transistor Qn1. At this time, since the level of the storage node 15 is held by the latch unit 12, the output signal ROUTn maintains the logic “H” level when there is no program, and the output signal ROUTn outputs the logic “L” when there is a program. Maintain the level.

Therefore, in the period T2, the output signal RO
If UTn is a logic "H" level, it can be determined that there is no program, and if the output signal ROUTn is a logic "L" level, it can be determined that there is a program.

As described above, the pulse signal is generated as the first control signal RSTp and the second control signal only during the determination period T2 of the presence / absence of the program, and the PMOS transistor Qp1 and the NMOS transistor Qn1 are both turned on, and other than that. In the periods T1 and T3, on the contrary, both the PMOS transistor Qp1 and the NMOS transistor Qn1 are turned off.

As a result, the PMOS transistors Qp1 and NM can be used in the standby state where the leakage current is a problem.
Since both the OS transistors Qn1 are off, no leak current flows even if the program element 10 after blowing has a residual resistance value of several k ohms.

Further, conventionally, as shown in FIGS. 12A, 12B and 12C, when the PMOS transistor Qp2 is used for latching, the NMOS transistor Qp is used.
n1 must be on, and as shown in FIG. 12C, when the storage node N2 is at the logic "H" level, the leak current Ileak flows as long as the program element 100 has a residual resistance value. . Therefore, in order to suppress the leak current Ileak, the current capacity of the PMOS transistor Qp2 that latches the logic "H" level of the storage node N2 must be reduced, and as a result, there is a residual resistance value even a little. The storage node N2 is pulled to the ground line VSS side to be at the logic "L" level, and there is a high possibility that the program will fail.

However, according to the present embodiment, since the problem of the leak current is solved, the PMOS transistor Qp
The current capacity of 1 can be increased, and as a result, even if there is a small residual resistance value, the conventional program will not fail.

(Second Embodiment) The second embodiment of the present invention has the same circuit configuration as that of the first embodiment, but the PMOS transistors are respectively formed by the first control signal RSTp and the second control signal RSTn. The control methods of Qp1 and NMOS transistor Qn1 are different.

FIG. 3 is a timing chart for determining whether or not there is a program in the second embodiment of the present invention. As shown in FIG. 3, in the present embodiment, the first control signal RSTp and the second control signal RSTp are set in the period T1 after the power is turned on.
Control signals RSTn of both are set to logic "L" level, and P
It differs from the first embodiment shown in FIG. 2 in that the MOS transistor Qp1 is turned on and the NMOS transistor Qn1 is turned off.

Due to this difference, the storage node 15 is temporarily precharged to the logic "H" level from the power supply line VDD via the PMOS transistor Qp1 before the determination period T2, regardless of the presence or absence of the program. As a result, only the PMOS transistor Qp3, which is a feedback transistor forming the latch unit 12, is turned on, the precharge current by the PMOS transistor Qp1 of the storage node 15 before the determination period T2 and the current load condition of the feedback transistor Qp3 become constant, and The presence / absence of the program at T2 can be determined more stably.

(Third Embodiment) FIGS. 4A and 4B.
[FIG. 6] is a circuit diagram showing a configuration example of a program value determination circuit according to a third embodiment of the present invention, showing a state without a program and a state with a program, respectively. The present embodiment differs from the first and second embodiments in the configuration of the latch section.

In FIGS. 4A and 4B, the latch unit 4
2, the gate is connected to the output node 16, the source is connected to the third control line 43, and the drain is the storage node 15
Connected to the output node 16, and the source thereof is the fourth control line 44.
N connected to the storage node 15 with the drain connected to
It includes a MOS transistor Qn3.

That is, in the latch section 12, the PMOS transistor Q which constitutes the feedback inverter.
Power supply to p3 and the NMOS transistor Qn3 is performed by the third control signal ARSTp via the third control line 43 and the fourth control signal ARSTn via the fourth control line 44, respectively.

With such a configuration, it is possible to eliminate the influence of the feedback transistors Qp3 and Qn3 as a current load when determining whether or not there is a program without increasing the number of transistors.

FIG. 5A and FIG. 5B are other configuration examples of the program value determination circuit according to the third embodiment of the present invention, and are circuit diagrams showing states without a program and with a program, respectively. The present embodiment is the first and second
The difference from the above embodiment is the configuration of the latch section.

In FIGS. 5A and 5B, the latch unit 5
2 has a PMOS transistor Qp whose gate is connected to the output node 16 and whose drain is connected to the storage node 15.
3, an NMOS transistor Qn having a gate connected to the output node 16 and a drain connected to the storage node 15.
3, the gate is connected to the third control line 53, the source is connected to the power supply line VDD, the drain is connected to the source of the PMOS transistor Qp3, and the gate is connected to the fourth control line 54. And an NMOS transistor Qn4 whose source is connected to the ground line VSS and whose drain is connected to the source of the NMOS transistor Qn3.

That is, in the latch section 52, the PMOS transistors Qp4 and NM are respectively supplied by the third control signal ARSTp and the fourth control signal ARSTn.
By controlling on / off of the OS transistor Qn4, the feedback transistors Qp3 and Qn3 operate as a tri-state inverter.

According to this structure, the number of transistors increases, but the third control signal ARSTp and the fourth control signal ARSTp are increased.
The control signal ARSTn of the third control signal ARSTn does not need to be supplied with power and only drives the gates of the PMOS transistor Qp4 and the NMOS transistor Qn4, respectively. Therefore, compared with the configuration of FIGS. 4A and 4B, the third control signal ARSTn of FIG.
The driving load due to RSTp and the fourth control signal ARSTn can be reduced.

FIGS. 6A and 6B, and FIGS. 5A and 5B.
9 is a timing chart for determining whether or not there is a program, which is common to the configurations shown in FIG. In FIG. 6, the first
The timing relationship between the control signal RSTp, the second control signal RSTn, and the output signal ROUTn is the same as that in FIG. 2, but the third control signal ARSTp and the fourth control signal ARSTn are respectively controlled by the first control signal The timing is earlier than the signal RSTp and the second control signal RSTn by the time td. These four control signals are
Since the inversion and delay times are in the relationship of td, they can be easily generated.

Due to the above timing relationship, the latch unit 4
Feedback transistor Qp forming 2, 52
3, the current load of Qn3 is disconnected from the storage node 15 of the detection unit 11 with a margin of time td before entering the determination period T2, and the feedback transistor Qp
3, and Qn3 latches the storage node 15 before the determination period T2 ends with a margin of time td before the state of the storage node 15 disappears, whereby a stable program value determination operation can be realized.

In the above embodiments, the second circuit in the detection section is illustrated and explained as a part of the latch section, but the latch section is configured without using the second circuit. It will be readily apparent to those skilled in the art that various modifications are possible within the scope of the present invention.

(Fourth Embodiment) In the fourth embodiment of the present invention, the case where the program value determination circuit shown in FIGS. 1A and 1B is applied to a redundancy repair circuit of a semiconductor memory will be described with reference to FIGS. This will be described with reference to FIG. The program value determination circuit shown in FIGS. 4A and 4B or FIGS. 5A and 5B may be applied to the redundancy repair circuit.

In FIG. 7, the memory cell array of the semiconductor memory is divided into a plurality of normal memory blocks and one redundant memory block, and a normal memory block having a defective address is replaced with an adjacent normal memory block or redundant memory block. It is a circuit block diagram which shows one structural example of a shift signal generation circuit.

In FIG. 7, the shift signal generating circuit is composed of a plurality of program value judging circuits 71 to 75, a plurality of AND circuits 76 to 80, and a plurality of logic inverting circuits 81 to 85. The output signals ROUTn of the program value determination circuits 71 to 75 are input to one input terminals of the AND circuits 76 to 80, respectively, and the output signals of the AND circuits corresponding to the adjacent memory blocks are input to the other input terminals. The shift signals shift1 to shift5 are output from the AND circuits 76 to 80, respectively. Further, the shift signals shift1 to sh from the AND circuits 76 to 80
ift5 is inverted by the logic inversion circuits 81 to 85,
Inverted shift signals xshift1 to xshift5 are generated.

With this configuration, the program elements in the program value determination circuits 71, 72, 73, and 75 are in the connected state, that is, the state without programming, for the normal memory block having no defective address and the program value Output signals RO from the decision circuits 71, 72, 73, 75
Since all UTn are at the logic "H" level, the shift signals shift1, shift2, shift3 are at the logic "H" level.

However, for an abnormal normal memory block having a defective address, the program element in the program value determination circuit 74 is in a disconnected state, that is, there is a program state, and the output signal ROUTn from the program value determination circuit 74 is present. Becomes a logic "L" level, and the shift signal shift4 becomes a logic "L" level. Further, since the shift signal shift4 of logic "L" level is input to the adjacent AND circuit 80, the shift signal shift5 also becomes logic "L" level.

As described above, the shift signal continues to be at the logic "H" level before the program value judging circuit 74 corresponding to the memory block having the defective address, but for the program value judging circuit 74 and thereafter, All logical "L"
Switch to level.

The shift signal shift and the inverted shift signal xshift are stored in the memory block M shown in FIG.
1, M2, ... (in FIG. 8, shift1, x
(only shift1, shift2, and xshift2 are shown), and sense amplifier output selection circuits 86 and 87 provided for each I / O unit, if the shift signal shift is at a logical "H" level, the sense amplifier output of its own memory block And the shift signal shift is at the logic “L” level, the shift can be performed so as to select the sense amplifier output of the memory block on the right side having no defective address.

This technique is called a shift redundancy technique, and does not sacrifice access time due to address judgment.
Redundancy repair is possible and is a widely known technique, but it can also be applied to such a technique.

As described above, according to the present embodiment, it is possible to provide a shift redundancy repair circuit to which a program value determination circuit that solves the problem of leak current, which has not been heretofore applied, is applied.
The program value determination circuit of the present invention can be used in such a redundancy repair circuit, but its application is not limited.

(Fifth Embodiment) Next, as a fifth embodiment of the present invention, the program value judging circuit according to the first to third embodiments is arranged in a circuit block in order to give priority to a power saving function. On the other hand, a case where the device is mounted in a semiconductor integrated circuit device (hereinafter, abbreviated as LSI) which partially repeats power-off and power-on will be described.

FIG. 9A is a plan view schematically showing a configuration example of the semiconductor integrated circuit device according to the fifth embodiment of the present invention. In FIG. 9A, the LSI 90 is composed of a first circuit block 91 in which power interruption and power activation are repeated and a second circuit block 92 in which power interruption is not performed.

In this case, the first program value judgment circuit 911 provided in the first circuit block 91 in which the power supply is turned off and the power supply is turned on is repeated, and the first program value judgment circuit 911 has the first control signal RSTp and the second control signal RSTn (third control signal RSTn). In the case where the program value determination circuit of the above embodiment is mounted, the third control signal ARSTp and the fourth control signal ARSTn)
By determining whether or not there is a program in the program element only for a certain period when the power is turned on, the determination of the program value is repeated.

On the other hand, the second program value judging circuit 9 provided in the second circuit block 92 in which the power is not shut off.
Reference numeral 21 determines the program value only once at a predetermined timing when the power is turned on.

The second program value judging circuit 9 provided in the second circuit block 92 in which the power is not cut off.
21 may repeat the determination of the program value in synchronization with the operation of the first program value determination circuit 911 provided in the first circuit block 91 in which the power is shut off and the power is repeatedly turned on.

FIG. 9B is a plan view schematically showing another configuration example of the semiconductor integrated circuit device according to the fifth embodiment of the present invention.

In the configuration shown in FIG. 9A, the corresponding first program value determination circuit 911 is provided in the first circuit block 91 in which the power supply is shut off and the power supply is repeatedly turned on.
In the configuration shown in (1), the second circuit block 92 in which the power is not cut off is provided with the first program value determination circuit 911 corresponding to the first circuit block 91. Other configurations are the same as those in FIG. 9A.

In the configuration of FIG. 9B, since the first program value determination circuit 911 and the second program value determination circuit 921 are both arranged in the second circuit block 92 in which the power is not cut off, the power is turned on. This is effective in applications in which power interruption is frequently repeated, or applications in which a program value cannot be determined unless a large current is applied or a high voltage is applied.

That is, it is possible to improve the reliability of the program without fear of increasing the number of times the current is passed for determining the program value and degrading the storage capacity of the program element. Moreover, since it is sufficient to flow a large current or apply a high voltage only once to determine the program value,
Power saving can be further promoted.

In the present embodiment, the second circuit block 92 has been described as having no power cut off.
The second circuit block 92 may be configured such that the number of times of power interruption is smaller than that of the first circuit block 91.

(Sixth Embodiment) Next, as a sixth embodiment of the present invention, the program value determination circuit according to the first to third embodiments is a semiconductor having a chip-on-chip (COC) structure. The case of being mounted on an integrated circuit device will be described.

FIG. 10A is a schematic perspective view showing a structural example of a semiconductor integrated circuit device having a COC structure according to the sixth embodiment of the present invention. In FIG. 10A, the second chip 102 is attached to and electrically connected to the surface of the first chip 101 with the surface facing down. First
The first memory block 1011 included in the first circuit block is configured in the chip 101, and the second memory block 1021 included in the second circuit block is configured in the second chip 102. There is.

FIG. 10B is a plan view schematically showing the internal structure of the first memory block 1011 shown in FIG. 10A. In FIG. 10B, the first memory block 1011
Is a memory array 1012 and a memory peripheral circuit 101.
3 and a program value determination circuit 1014. The program value determination circuit 1014 includes a first program value determination circuit 1014-1 for performing redundant relief on the first memory block 1011 and a first program value determination circuit 1014-1 for performing redundant relief on the second memory block 1021. 2 program value determination circuit 1014-2.

With this configuration, even after the second chip 102 is pasted on the surface of the first chip 101 with the surface thereof facing down, the second memory block 102 is also attached.
When performing redundant repair for 1, the program element of the second program value determination circuit 1014-2 can be easily programmed by laser irradiation or the like.

(Seventh Embodiment) Next, as a seventh embodiment of the present invention, the program value determination circuits according to the first to third embodiments are arranged in a multi-chip module (MC).
The case of the semiconductor integrated circuit device mounted in M) will be described.

FIG. 11A is a schematic perspective view showing a configuration example of a semiconductor integrated circuit device having an MCM according to the seventh embodiment of the present invention. In FIG. 11A, MCM110
The first chip 111, the second chip 112, and the third chip 113 are arranged on a plane with high density and are mounted on the substrate. The first chip 111, the second chip 112, and the third chip 113 are respectively configured with a first memory block 1111, a second memory block 1121, and a third memory block 1131. A power supply circuit 114 that generates a large current or a high voltage is mounted on the board.

FIG. 11B is a plan view schematically showing the internal structure of the first memory block 1111 shown in FIG. 11A. In FIG. 11B, the first memory block 1111
Is a memory array 1112 and a memory peripheral circuit 111.
3 and a program value determination circuit 1114. The program value determination circuit 1114 includes a first program value determination circuit 1114-1 for performing redundant relief on the first memory block 1111 and a first program value determination circuit 1114-1 for performing redundant relief on the second memory block 1121. The second program value determination circuit 1114-2 and the third program value determination circuit 1114-3 for performing the redundancy repair for the third memory block 1131.

As described above, in addition to the first program value determination circuit 1114-1, the first memory block 1111 arranged closest to the power supply circuit 114 has the second memory block 1111.
The program value determination circuit 1114-2 and the third program value determination circuit 1114-3 are configured.

With such a configuration, by integrating a plurality of program value judgment circuits in one chip,
A program element of the program value determination circuit can be easily programmed by laser irradiation or the like, and a chip in which a plurality of program value determination circuits are integrated is most suitable for the power supply circuit 114 that generates a high voltage or a large current. By using chips that are close to each other, it is possible to easily supply high voltage and large current at the time of program value determination, without requiring an extra area or additional process for increasing the withstand voltage, as compared with the case of distributed arrangement. it can.

In each of the above embodiments, the fuse element which is blown by the laser irradiation to be in the open state to have the program is described as the program element, but the present invention is not limited to this. Without
For example, it is possible to use an element which is in a short state due to gate breakdown and has a program. In this case, the first
When applied to the above embodiment, the storage node is held at the logic “H” level when there is no program, and held at the logic “L” level when there is a program,
The relationship of the leak current when the fuse element is used is reversed.

In each of the above-described embodiments, the current flowing in the power saving mode (third period) is defined by the leak current of the latch unit which cannot disconnect the power supply, or the first control signal RSTp. And the second control signal RSTn
PMOS transistor Qp1 with resistance change according to
(First switch element) and NMOS transistor Qn1
It is defined by the off current of the (second switch element).

In addition, in the fifth to sixth embodiments described above, when a plurality of program value determination circuits are provided,
It is preferable to make the timings of the first control signal RSTp and the second control signal RSTn supplied to each different. Accordingly, in the second period (judgment period), it is possible to prevent erroneous operation of the logic level determination of the storage node due to a current flowing through the plurality of program elements simultaneously and a voltage drop.

[0113]

As described above, according to the present invention,
PROBLEM TO BE SOLVED: To realize a program value determination circuit in which both the area of a program element and a leak current are reduced by eliminating the trade-off relationship between the area of a program element and a leakage current, a semiconductor integrated circuit device having such a program value determination circuit, and a program value determination method. It becomes possible to do. This allows
It is possible to provide the most suitable technology for application to a system LSI that is required for future portable equipment applications and the like, which does not involve a leak current during standby and needs to incorporate many program elements.

[Brief description of drawings]

FIG. 1A is a circuit diagram showing a configuration example of a program value determination circuit according to a first embodiment of the present invention, showing a state without a program.

FIG. 1B is a circuit diagram showing a configuration example of a program value determination circuit according to the first embodiment of the present invention, showing a state with a program;

FIG. 2 is a timing chart for determining whether or not a program exists with the configuration of FIG.

FIG. 3 is a timing chart for determining whether or not there is a program in the second embodiment of the present invention by using a program value determination circuit having the same configuration as in FIG.

FIG. 4A is a circuit diagram showing a configuration example of a program value determination circuit according to a third embodiment of the present invention, showing a state without programming.

FIG. 4B is a circuit diagram showing a configuration example of a program value determination circuit according to a third embodiment of the present invention, showing a state with a program.

FIG. 5A is another configuration example of the program value determination circuit according to the third embodiment of the present invention, which is a circuit diagram showing a state without programming.

FIG. 5B is another example of the configuration of the program value determination circuit according to the third embodiment of the present invention, and is a circuit diagram showing a state with a program.

FIG. 6 is a timing chart for determining the presence or absence of a program by the configuration of FIGS. 4A and 4B or 5A and 5B.

FIG. 7 is a circuit block diagram showing a configuration example of a shift signal generation circuit to which a program value determination circuit according to a fourth embodiment of the present invention is applied.

8 is a circuit diagram showing a configuration example of a redundancy repair circuit of a semiconductor memory to which a shift signal shift and an inverted shift signal xshift from the shift signal generation circuit of FIG. 7 are supplied.

FIG. 9A is a plan view schematically showing a configuration example of a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

FIG. 9B is a plan view schematically showing another configuration example of the semiconductor integrated circuit device according to the fifth embodiment of the present invention.

FIG. 10A is a COC according to a sixth embodiment of the present invention.
Schematic perspective view showing one structural example of a semiconductor integrated circuit device having a structure

FIG. 10B is a first memory block 1 shown in FIG. 10A.
011 is a plan view schematically showing the internal structure of 011.

FIG. 11A is an MCM according to a seventh embodiment of the present invention.
Schematic perspective view showing one configuration example of a semiconductor integrated circuit device in which the

FIG. 11B is a first memory block 1 shown in FIG. 11A.
The top view which shows the internal structure of 111 typically

12A is a circuit diagram showing a configuration example of a conventional program value determination circuit, showing a state without programming before blowing the fuse element 100. FIG.

FIG. 12B is a circuit diagram showing a configuration example of a conventional program value determination circuit, showing a state with programming after blowing the fuse element 100 with high laser power.

FIG. 12C is a circuit diagram showing a configuration example of a conventional program value determination circuit, showing a state with a program after blowing the fuse element 100 with low laser power.

FIG. 13 is a diagram showing the relationship between the fuse pitch Hpitch and the relative laser power Lpower, the residual resistance value Rfuse and the leak current Ileak after the fuse element 100 is blown in the configurations of FIGS. 12A, 12B, and 12C.

[Explanation of symbols]

10 program elements 11 Detector 12, 42 Latch part 13 First control line 14 Second control line 15 Storage node 16 output nodes 43, 53 Third control line 44, 54 Fourth control line 71, 72, 73, 74, 75 Program value determination circuit 76, 77, 78, 79, 80 AND circuit 81, 82, 83, 84, 85 Logic inversion circuit 86,87 Sense amplifier output selection circuit 90 LSI 91 First Circuit Block 911 First program value determination circuit 92 Second circuit block 921 Second program value determination circuit 101 First Chip 1011 First memory block 1012 memory array 1013 Memory peripheral circuit 1014 Program value judgment circuit 1014-1 First program value determination circuit 1014-2 Second program value determination circuit 110 Multi Chip Module (MCM) 111 First Chip 1111 First memory block 1112 memory array 1113 Memory peripheral circuit 1114 Program value judgment circuit 1114-1 First program value determination circuit 1114-2 Second program value determination circuit 1114-3 Third program value determination circuit 112 Second chip 1121 second memory block 113 Third Chip 1131 Third memory block 114 power supply circuit

Claims (22)

[Claims] 1. A program element with a change in resistance value with and without a program, which operates in response to first and second control signals, and which is provided between a first power supply terminal and a second power supply terminal. A first and a second switch element connected in series to the program element, wherein at least the first switch element is inserted between the first power supply terminal and the intermediate connection node, and the intermediate connection node and the first connection element; A first circuit in which at least the second switch element is connected in series to the program element between the second power supply terminal and the second circuit, and the potential of the intermediate connection node is converted to a logic level and output to the output node. A first circuit after the power is turned on, and a detection unit including a second circuit for latching the potential of the intermediate connection node and using the intermediate connection node as a storage node for a program value. In the second period after, at least the second switch element is turned on, the storage node is connected to the second power supply terminal through the program element, and the state of the storage node is detected. Detected in a third period after the second period, the first and second periods.
And the switch elements are both turned off, and the state of the storage node is held by the latch unit. 2. Both terminals of the program element are disconnected from at least one of the first and second power supply terminals during the first and third periods, respectively, and are disconnected during the second period. The program value determination circuit according to claim 1, wherein the program value determination circuit is connected between the first and second power supply terminals directly or through the first and second switch elements. 3. The first switch element comprises a first transistor which is drive-controlled by the first control signal, and the second switch element is drive-controlled by the second control signal. A second transistor, the storage node is connected to the first power supply terminal via the first transistor, and is connected to one terminal of the program element via the second transistor; The other terminal of the program element is connected to the second power supply terminal, and the first transistor is turned off during the first period and turned on during the second period by the first control signal. The second transistor is turned off during the third period, the second transistor is turned off during the first period, and turned on during the second period by the second control signal. First Programmed value determining circuit of claim 1, wherein the time period, characterized in that turned off. 4. The first switch element comprises a first transistor which is drive-controlled by the first control signal, and the second switch element is drive-controlled by the second control signal. A second transistor, the storage node is connected to the first power supply terminal via the first transistor, and is connected to one terminal of the program element via the second transistor; The other terminal of the program element is connected to the second power supply terminal, and the first transistor is turned on by the first control signal during the first and second periods, and the third transistor is turned on.
Is turned off during the period of time, the second transistor is turned off during the first period, turned on during the second period, and turned off during the third period by the second control signal. The program value determination circuit according to claim 1, wherein the program value determination circuit is in a state. 5. The latch means includes a third circuit connected between the intermediate connection node and the output node, and the third circuit and the second circuit cooperate with each other. The program value determination circuit according to claim 1, wherein the intermediate connection node is a storage node for the program value. 6. The third circuit is connected to the first and second power supply terminals via a signal line for transmitting third and fourth control signals, and is supplied with power. The program value determination circuit according to claim 5. 7. The first and second control signals are delayed with respect to the third and fourth control signals, and the first and second control signals and the third and fourth control signals. 7. The program value determination circuit according to claim 6, wherein each has a logical inversion relationship. 8. The program value determination circuit according to claim 1, wherein the current flowing in the third period is defined by a leak current of the latch means. 9. The program value determination circuit according to claim 1, wherein the current flowing in the third period is defined by the off currents of the first and second switch elements. 10. A semiconductor integrated circuit device having the program value determination circuit according to claim 1, wherein an allowable value of a leak current flowing through each program element is set, wherein the program value determination circuit comprises: No current when the current flowing when a voltage near the power supply voltage is applied to the program element exceeds the allowable value of the leak current,
A semiconductor integrated circuit device, characterized in that when there is less than the allowable value of the leak current, it is determined that a program is present, and as a result of the determination, one of binary logic levels is output to a functional circuit. 11. The semiconductor integrated circuit device is a semiconductor memory device having a plurality of normal memory blocks and one redundant memory block, wherein the functional circuit adjoins the normal memory block having a defect. 11. The semiconductor integrated circuit device according to claim 10, wherein the semiconductor integrated circuit device is a redundant relief circuit for replacing a normal memory block or the redundant memory block. 12. A semiconductor integrated circuit device having the program value determination circuit according to claim 1, wherein an allowable value of a current flowing through each program element is set, wherein the program value determination circuit is the When the current flowing when a voltage near the power supply voltage is applied to the program element is below the allowable value of the current, it is determined that there is no programming, and when it exceeds the allowable value of the current, it is determined that there is a program, and the determination result A semiconductor integrated circuit device characterized by outputting any one of binary logic levels to a functional circuit. 13. The semiconductor integrated circuit device is a semiconductor memory device having a plurality of normal memory blocks and one redundant memory block, wherein the functional circuit adjoins the normal memory block having a defect. 13. The semiconductor integrated circuit device according to claim 12, wherein the semiconductor integrated circuit device is a redundancy repair circuit for replacing a normal memory block or the redundant memory block. 14. A semiconductor integrated circuit device in which one chip is divided into a plurality of circuit blocks having different power supply systems, wherein a first program value determination circuit which is the program value determination circuit according to claim 1 is provided. A first circuit block that is repeatedly turned off and turned on, and a second program value determination circuit having the same configuration as the first program value determination circuit are provided. Second, the number of times power is cut off is small
And the first program value determination circuit has each of the first to third periods at least once during a fixed period from power-on to power-off. Semiconductor integrated circuit device. 15. The timing of the first and second control signals is made different between at least one first program value determination circuit and at least one second program value determination circuit. 15. The semiconductor integrated circuit device according to claim 14. 16. A semiconductor integrated circuit device in which one chip is divided into a plurality of circuit blocks having different power supply systems, wherein a first circuit block in which power supply interruption and power supply application are repeated, and the first circuit block. A second circuit block in which the power is shut off less frequently than the second circuit block, wherein the second circuit block is the program value determination circuit according to claim 1.
A first program value determination circuit corresponding to the circuit block of, and a configuration similar to the first program value determination circuit,
A semiconductor integrated circuit device comprising: a second program value determination circuit corresponding to the second circuit block. 17. The timing of the first and second control signals is made different among a plurality of program value determination circuits including the first and second program value determination circuits. The semiconductor integrated circuit device described. 18. A plurality of chips including at least a first chip and a second chip, wherein the second chip is
A multi-chip type semiconductor integrated circuit device, which is laminated on the surface of the first chip with the surface thereof facing down and electrically connected, wherein the first chip has a first circuit block, The second chip has a second circuit block, and the first circuit block is the program value determination circuit according to claim 1.
A first program value determination circuit corresponding to the circuit block of, and a configuration similar to the first program value determination circuit,
A semiconductor integrated circuit device comprising: a second program value determination circuit corresponding to the second circuit block. 19. The timing of the first and second control signals is made different among a plurality of program value judgment circuits including the first and second program value judgment circuits. The semiconductor integrated circuit device described. 20. A multi-chip type semiconductor integrated circuit device in which a chip module comprising a plurality of chips arranged in a plane is mounted on a substrate, wherein the plurality of chips have a plurality of corresponding circuit blocks. The circuit block arranged closest to the power supply circuit configured on the substrate among the plurality of circuit blocks is the program value determination circuit according to claim 1, and the program corresponding to the circuit block. A value determining circuit, and a configuration similar to that of the first program value determining circuit,
A semiconductor integrated circuit device including a program value determination circuit corresponding to another circuit block. 21. A plurality of circuits including a program value determination circuit corresponding to the circuit block arranged at a position closest to the power supply circuit formed on a substrate and a program value determination circuit corresponding to the other circuit block. 21. The semiconductor integrated circuit device according to claim 20, wherein the timings of the first and second control signals are made different between the program value determination circuits. 22. A program element having a change in resistance value with and without a program, which operates in response to first and second control signals, and is provided between a first power supply terminal and a second power supply terminal. First and second serially connected program elements
The switching element, and at least the first switch element is inserted between the first power supply terminal and the intermediate connection node, and the program element is provided between the intermediate connection node and the second power supply terminal. A first circuit in which at least the second switch element connected in series is inserted, a second circuit which converts the potential of the intermediate connection node into a logic level and outputs the logical level to an output node, and a second circuit of the intermediate connection node A program value determination method using a latch means for latching a potential and using the intermediate connection node as a storage node for a program value, wherein the method is at least the second period after the first period after power-on. The second switch element is turned on, and the storage node is connected to the second node via the program element.
The step of detecting the state of the storage node by the first and second circuits by connecting the first and second power supply terminals to the first and second circuits.
And turning off both switch elements, and holding the state of the storage node by the latch means.