KR101115454B1 - Semiconductor integrated circuit - Google Patents

Abstract

In a fuse circuit using a fuse-end control signal for preventing a fail fail, a semiconductor integrated circuit that prevents an error in recognition of a fuse state even when a timing change of a power-up signal due to a change in process, voltage, temperature, or the like occurs. Is provided. According to an aspect of the present invention, a fuse-end control signal generation unit for generating a control signal for both ends of the fuse in response to the power-up signal and the first signal activated after the activation time of the power-up signal; And a fuse whose potential at both ends thereof is controlled by the fuse-end control signal, wherein a fuse state sensing node is initialized by the power-up signal, and a fuse signal is changed according to a potential change of the sensing node corresponding to a state of the fuse. Provided is a semiconductor integrated circuit having a fuse circuit unit for outputting the same.

Description

[0001] SEMICONDUCTOR INTEGRATED CIRCUIT [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuit design technology, and more particularly, to a fuse circuit of a semiconductor integrated circuit.

The semiconductor integrated circuit includes circuits of the same pattern, and redundancy circuits are arranged together so that some circuits may be released in good condition depending on process variables.

In particular, in the case of a semiconductor memory device, a large number of memory cells are integrated in one chip. If any one of these memory cells is defective, the memory chip is treated as defective and cannot be used.

As a result of high integration, a larger number of memory cells are integrated into a limited size chip. If a defect occurs in one cell, if the entire memory chip is treated as defective, the number of memory chips to be treated as defective will increase. This makes it impossible to produce economical semiconductor memory devices.

In order to solve this problem, a conventional semiconductor memory device includes a fuse circuit and a redundant cell array. The fuse circuit includes a plurality of fuses, and replaces the defective cells with redundancy cells depending on whether the fuses blow in the repair process. The redundancy cell array and the fuse circuit are formed in the semiconductor manufacturing process. In the repair process, a memory cell determined as defective is replaced with a redundancy cell, and the repair process is mainly performed by selectively disconnecting a fuse in a fuse circuit using a laser beam.

On the other hand, after the fuse blows (Blowing) may cause a failure that the fuse blown again by the electrical / chemical migration (Migration) action is connected again. This failure is often referred to as Hast Fail. Hast failures are frequently generated by replacing conventional aluminum with copper as a metal wiring material, and mainly occur when testing reliability at high temperature, voltage, and 100% moisture.

Hast failing is commonly indicated by the use of copper in the semiconductor fabrication process for the operation of semiconductor integrated circuits operating at high speeds, but may also occur when aluminum or other materials are used. Hast fail occurs after fuse blowing in the repair process, making it difficult to find and repair. Hast failures are a factor in lowering the productivity of semiconductor integrated circuits and degrading the performance and reliability of semiconductor integrated circuits.

The present invention is intended to prevent the occurrence of an error in the recognition of the fuse state in the fuse circuit using the control signal across the fuse to prevent the hash fail, even if the timing of the power-up signal due to the change in the process, voltage, temperature, etc. do.

According to an aspect of the present invention, a fuse-end control signal generation unit for generating a control signal for both ends of the fuse in response to the power-up signal and the first signal activated after the activation time of the power-up signal; And a fuse whose potential at both ends thereof is controlled by the fuse-end control signal, wherein a fuse state sensing node is initialized by the power-up signal, and a fuse signal is changed according to a potential change of the sensing node corresponding to a state of the fuse. Provided is a semiconductor integrated circuit having a fuse circuit unit for outputting the same.

According to another aspect of the invention, the logic combination unit for logic combination of the power-up signal and the reset signal; A pulse generator for outputting a control signal for both ends of the fuse having a predetermined pulse width in response to the transition of the output signal of the logic combination unit; And a fuse whose potential at both ends thereof is controlled by the fuse-end control signal, wherein a fuse state sensing node is initialized by the power-up signal, and a fuse signal is changed according to a potential change of the sensing node corresponding to a state of the fuse. Provided is a semiconductor integrated circuit having a fuse circuit unit for outputting the same.

According to another aspect of the present invention, an RS latch unit for outputting a control signal across the fuse using a power-up signal as a reset input and a pulse signal generated by receiving a command signal applied from the outside as a set input; And a fuse whose potential at both ends thereof is controlled by the fuse-end control signal, wherein a fuse state sensing node is initialized by the power-up signal, and a fuse signal is changed according to a potential change of the sensing node corresponding to a state of the fuse. Provided is a semiconductor integrated circuit having a fuse circuit unit for outputting the same.

In the fuse circuit using the fuse-end control signal for preventing the fail fail, if the fuse-end control signal is generated by additionally applying a signal that is activated after the power-up is completed, the power due to changes in process, voltage, temperature, etc. Even when the up signal changes in timing, an error in the recognition of the fuse state can be prevented.

1 to 3 are circuit diagrams illustrating a fuse circuit of a semiconductor integrated circuit for explaining the present invention.
FIG. 4 is a timing diagram illustrating a waveform of the conventional fuse-end control signal FC and the fuse-end control signal FC_NEW applied to the present invention.
5 is a circuit diagram illustrating a first embodiment of the fuse-end control signal FC_NEW generation circuit of the present invention.
6 is a circuit diagram illustrating a second implementation of the fuse-end control signal FC_NEW generation circuit of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may more easily implement the present invention.

1 to 3 are circuit diagrams illustrating a fuse circuit of a semiconductor integrated circuit for explaining the present invention.

Referring to FIG. 1, a fuse circuit of a semiconductor integrated circuit includes a fuse F1 connected between a power supply voltage terminal VDD and a sensing node A and a power-up signal PWRUP as a gate input. The NMOS transistor T1 having a source / drain connected between the VSS and the sensing node A and the state of the sensing node A voltage are latched and output as a fuse signal FOUT. Inverter latches I1 and I2.

The NMOS transistor T1 is turned on by receiving the power-up signal PWRUP provided by the power-up circuit. The power-up signal PWRUP is a signal indicating that the power supply voltage VDD is applied to the semiconductor integrated circuit and thus rises to a predetermined level internally. The power-up signal PWRUP typically maintains a logic level low state when the power supply voltage VDD is applied, and maintains a logic level high state when the power supply voltage VDD rises above a predetermined level.

In order to replace the defective area with a redundancy circuit preliminarily arranged in the repair process, if the fuse needs to be blown, the laser is irradiated to blow the fuse F1. If the fuse F1 is blown during the repair process, the sensing node A is turned low when the power-up signal PWRUP is input and the NMOS transistor T1 is turned on.

If the fuse F1 is not blown during the repair process, even if the power-up circuit PWRUP is input and the NMOS transistor T1 is turned on, the sensing node A is at a logic level due to the driving force by the power supply voltage VDD. It goes high.

The inverter latches I1 and I2 output a fuse signal FOUT having a logic level low when the voltage level of the sensing node A is higher than the logic threshold of the inverter I2, and the voltage level of the sensing node A is increased. If it is lower than the logic threshold of the inverter I2, the fuse signal FOUT in a logic level high state is output.

2 illustrates a fuse circuit of an improved form compared to the fuse circuit of FIG. 1.

Referring to FIG. 2, in the illustrated fuse circuit, a source is connected to the fuse F1, a power supply voltage terminal VDD, a drain is connected to one end of the fuse F1, and the control signal FC at both ends of the fuse is connected to a gate input. A PMOS transistor T2, a source connected to the other end of the fuse F2, a drain connected to the sensing node A, and a power-up of the PMOS transistor T3 having the fuse-end control signal FC as a gate input; MOS transistor T4 connected to the source / drain between the ground voltage terminal VSS and the sensing node A and the state of the voltage of the sensing node A. Inverter latches I3 and I4 for latching and outputting the same as the fuse signal FOUT.

The fuse-end control signal FC is a signal produced by processing the power-up signal PWRUP, and is a pulse signal activated at a logic level low with a predetermined width at the time of activation of the power-up signal PWRUP.

The electrical / chemical migration phenomenon that causes a fail failure is caused by the application of the VDD-VSS bias across the blown fuse. The fuse circuit of FIG. 2 temporarily transmits the control signal FC of the fuse to the fuse state detection section. It activates to sense the state of the fuse (F2) and latch it, and in the subsequent section to turn off the PMOS transistors (T2, T3) to block the formation of the VDD-VSS bias across the fuse (F2).

Basically, when the power-up signal PWRUP is activated to logic level high at power-up, the sensing node A is initialized to logic level low.

If the fuse F2 is not blown during the repair process, the fuse-end control signal FC is activated to a logic level low, and the PMOS transistors T2 and T3 are turned on. Accordingly, the power supply voltage terminal VDD and the sensing node are turned on. A path is formed between (A) so that the sensing node A is at a logic level high state.

On the other hand, when the fuse F2 is blown during the repair process, the power supply voltage VDD is blown by the blown fuse F2 even when the PMOS transistors T2 and T3 are turned on because the control signal FC across the fuse is activated at a logic level low. Since the transmission of is blocked, the sensing node A remains at the logic level low. Since both ends of the fuse F2 are turned off at the logic level high and the PMOS transistors T2 and T3 are turned off, the both ends of the fuse F2 are floated, so that the VDD-VSS bias is applied to both ends of the fuse F2. Prevent formation. Therefore, generation of a hash fail can be prevented.

3 is a fuse circuit of another semiconductor integrated circuit. Compared to the circuit of FIG. 2, the same configuration as that of the inverter I5 receiving the control signal FC across the fuse is added instead of removing the PMOS transistor T2 connected to one end of the fuse F3. Have

This fuse circuit also prevents the occurrence of the VSS at the both ends of the fuse F3 or at least the VDD-VSS bias after the period in which the state of the fuse F3 is sensed, thereby fundamentally blocking the occurrence of a fail fail. .

Since the configuration and operation of the NMOS transistor T6 and the inverter latches I6 and I7 are the same as those of the circuit of FIG. 2, description thereof will be omitted.

The fuse-end control signal FC disclosed in FIGS. 2 and 3 is simply a pulse signal obtained by processing a power-up signal pwurup. The state of the fuse F3 is detected during the period in which the control signal FC across the fuse is activated.

However, the activation timing of the power-up signal pwurup changes according to environmental changes such as process, voltage, and temperature. Therefore, the activation timing of the fuse-end control signal FC generated by processing the power-up signal PWRUP also changes. The change in activation timing of the control signal FC across the fuse means that the level of the power supply voltage VDD transmitted to the sensing node A may be changed in the fuse state detection period, which discharges the sensing node A. This means that the level of the fuse signal FOUT may vary according to the relationship between the driving force of the driving NMOS transistor and the power supply voltage VDD transmitted to the sensing node A. FIG. That is, the cutting state of the fuse F3 may be mistransmitted to cause a malfunction of the semiconductor integrated circuit.

In the present invention, as shown in Figures 2 and 3 to improve the manner of generating the control signal FC of the both ends of the fuse to control the bias of both ends of the fuse to prevent.

FIG. 4 is a timing diagram illustrating a waveform of the conventional fuse-end control signal FC and the fuse-end control signal FC_NEW applied to the present invention.

In the case of the conventional fuse-end control signal FC is generated by receiving the power-up signal (PWRUP) that is activated in the period in which the power supply voltage (VDD) is rising, while being activated in the rising period of the power supply voltage (VDD), It can be seen that the fuse-end control signal FC_NEW applied to the invention is activated to a logic level low for a predetermined period when the power-up is completed and the power supply voltage VDD is completely stabilized.

Therefore, when the fuse-end control signal FC_NEW of the present invention is applied to the fuse circuit as shown in FIGS. 2 and 3, the fuse state can be detected while the power supply voltage VDD is stabilized. It is possible to fundamentally prevent a fuse state detection error caused by such a variable.

5 is a circuit diagram illustrating a first embodiment of the fuse-end control signal FC_NEW generation circuit of the present invention.

The fuse-end control signal FC_NEW generation circuit shown in FIG. 5 uses the NAND gate ND1 for inputting the reset signal RES and the power-up signal PWRUP, and the output signal of the NAND gate ND1 as an input. A control signal for both ends of the fuse by inputting the inverter I8, the inverted delays I9, I10, and I11 that input the output signal of the inverter I8, and the output signal of the inverter I8 and the output signal of the inverted delay. And a NAND gate ND2 for outputting FC_NEW.

Here, the inversion delays (I9, I10, I11) and the NAND gate (ND2) are typical rising edge triggered pulse generators, and the inversion delays (I9, I10, I11) represent the control signals FC_NEW across the fuse. The pulse width will be determined.

On the other hand, the reset signal RES is an external reset signal applied from the outside after the power-up is completed, on the premise that it is activated to a logic level high.

During power-up, the power-up signal PWRUP is activated at a logic level high. After that, the reset signal RES is activated at a logic level high while the power-up is completed to maintain a stable level.

Accordingly, the output signal of the inverter I8 transitions to the logic level high in response to the time when the reset signal RES is activated to the logic level high, and the inversion delays I9, I10, and I11 and the NAND gate ND2 The fuse-end control signal FC_NEW is generated to be activated at a logic level low for a predetermined period from the transition point.

6 is a circuit diagram illustrating a second implementation of the fuse-end control signal FC_NEW generation circuit of the present invention.

The fuse-end control signal FC_NEW generation circuit shown in FIG. 6 inputs a NOR gate NOR1 for inputting an active signal ACT and a mode register set signal MRS, and an output signal of the NOR gate NOR1. An inverter I12 to be set and an RS latch for setting the power-up signal PWRUP as a reset (R) input and an output signal of the inverter I12 as a set (S) are provided.

Here, the RS latch may be implemented as a cross-coupled NOR latch composed of two NOR gates NOR2 and NOR3.

The active signal ACT and the mode register set signal MRS are both high active pulse signals generated by using a command signal applied from the outside after the power-up sequence ends.

First, when the power-up signal VWR rises to a predetermined level during power-up and the power-up signal PWRUP is activated at a logic level high, the active signal ACT and the mode register set signal MRS are both at a logic level low. The fuse-end control signal FC_NEW is initialized to a logic level high.

On the other hand, when the power-up sequence ends and any one of the active signal ACT and the mode register set signal MRS is pulsed non-level high, the output signal of the inverter I12 becomes logic level high. As a result, the fuse-end control signal FC_NEW is activated to a logic level low. Afterwards, when the active signal ACT or the mode register set signal MRS are deactivated to the logic level low again, the fuse-end control signal FC_NEW is deactivated to the logic level high again.

When the fuse-end control signal FC_NEW generated in accordance with the first and second embodiments as described above is applied to the fuse circuit as shown in FIGS. 2 and 3, the fuse state may be set in a state where the power supply voltage VDD is stabilized. By detecting, it is possible to fundamentally prevent fuse state detection errors caused by variables such as process, voltage, and temperature.

Although the technical spirit of the present invention has been described in detail according to the above-described embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

For example, the reset signal RES used together with the power-up signal PWRUP in the above-described fuse-end control signal generation circuit (FIG. 5) is a signal applied from the outside. Thus, a scheme for applying the reset signal from the outside is not secured. In the case of a semiconductor integrated circuit, an internally generated reset signal may be used to activate an internal latch after the power supply voltage VDD is completely stabilized.

In addition, the above-described fuse both ends control signal generation circuit (FIG. 6) has been described using an example in which both the active signal ACT and the mode register set signal MRS are used as signals that are activated after the power-up sequence is completed. The present invention can be applied to the use of other signals in addition to these signals, or in the case of using only one signal (the inverter may be used instead of the Norgate).

On the other hand, the logic used in the embodiment (FIG. 5, 6) of the fuse-end control signal generation circuit may be replaced with other logic or omitted depending on the type of signal used and the activation level.

I1 to I13: Inverter
ND1: NAND gate
NOR1 to NOR3: NORGATE
F1, F2, F3: Fuse

Claims (13)

A fuse-end control signal generator configured to generate a fuse-end control signal in response to a power-up signal and a first signal activated after an activation time of the power-up signal; And
And a fuse whose potentials at both ends thereof are controlled by the fuse-end control signal, and a fuse state sensing node is initialized by the power-up signal, and a fuse signal is changed according to a potential change of the sensing node corresponding to the fuse state. It has a fuse circuit for outputting,
The fuse circuit unit,
The fuse;
A first MOS transistor connected between a power supply voltage terminal and one side of the fuse and configured as a gate input of the control signal across the fuse;
A second MOS transistor connected between the other side of the fuse and the fuse state sensing node and using the control signal across the fuse as a gate input;
A third MOS transistor connected between a ground voltage terminal and the fuse state sensing node and configured to use the power-up signal as a gate input; And
And an output unit configured to output the fuse signal corresponding to a change in potential of the sensing node.
delete A fuse-end control signal generator configured to generate a fuse-end control signal in response to a power-up signal and a first signal activated after an activation time of the power-up signal; And
And a fuse whose potentials at both ends thereof are controlled by the fuse-end control signal, and a fuse state sensing node is initialized by the power-up signal, and a fuse signal is changed according to a potential change of the sensing node corresponding to the fuse state. It has a fuse circuit for outputting,
The fuse circuit unit,
The fuse having one side connected to a power supply voltage terminal;
An inverter for driving one side of the fuse by inverting the control signal across the fuse;
A PMOS transistor connected between the other side of the fuse and the fuse state sensing node and having a control signal across the fuse as a gate input; And
An NMOS transistor connected between a ground voltage terminal and the fuse state sensing node and configured to use the power-up signal as a gate input; And
And an output unit configured to output the fuse signal corresponding to a change in potential of the fuse state detection node.
The method according to claim 1 or 3,
And the output unit comprises an inverter latch for latching a logic value corresponding to the potential of the fuse state sensing node and outputting the same as the fuse signal.
A logic combination unit for logically combining the power-up signal and the reset signal;
A pulse generator for outputting a control signal for both ends of the fuse having a predetermined pulse width in response to the transition of the output signal of the logic combination unit; And
And a fuse whose potentials at both ends thereof are controlled by the fuse-end control signal, and a fuse state sensing node is initialized by the power-up signal, and a fuse signal is changed according to a potential change of the sensing node corresponding to the fuse state. It has a fuse circuit for outputting,
The fuse circuit unit,
The fuse;
A first MOS transistor connected between a power supply voltage terminal and one side of the fuse and configured as a gate input of the control signal across the fuse;
A second MOS transistor connected between the other side of the fuse and the fuse state sensing node and using the control signal across the fuse as a gate input;
A third MOS transistor connected between a ground voltage terminal and the fuse state sensing node and configured to use the power-up signal as a gate input; And
And an output unit configured to output the fuse signal corresponding to a change in potential of the sensing node. delete A logic combination unit for logically combining the power-up signal and the reset signal;
A pulse generator for outputting a control signal for both ends of the fuse having a predetermined pulse width in response to the transition of the output signal of the logic combination unit; And
And a fuse whose potentials at both ends thereof are controlled by the fuse-end control signal, and a fuse state sensing node is initialized by the power-up signal, and a fuse signal is changed according to a potential change of the sensing node corresponding to the fuse state. It has a fuse circuit for outputting,
The fuse circuit unit,
The fuse having one side connected to a power supply voltage terminal;
An inverter for driving one side of the fuse by inverting the control signal across the fuse;
A PMOS transistor connected between the other side of the fuse and the fuse state sensing node and having a control signal across the fuse as a gate input; And
An NMOS transistor connected between a ground voltage terminal and the fuse state sensing node and configured to use the power-up signal as a gate input; And
And an output unit configured to output the fuse signal corresponding to a change in potential of the fuse state detection node.
The method according to claim 5 or 7,
And the output unit comprises an inverter latch for latching a logic value corresponding to the potential of the fuse state sensing node and outputting the same as the fuse signal.
delete An RS latch unit for setting the power-up signal as a reset input and outputting a control signal between fuses by setting a pulse signal generated by receiving a command signal applied from the outside as a set input; And
And a fuse whose potentials at both ends thereof are controlled by the fuse-end control signal, and a fuse state sensing node is initialized by the power-up signal, and a fuse signal is changed according to a potential change of the sensing node corresponding to the fuse state. It has a fuse circuit for outputting,
The pulse signal is an active signal generated by receiving an active command or a mode register set command generated by receiving a command or a combination signal of the active signal and the mode register set signal.
The method of claim 10,
The fuse circuit unit,
The fuse;
A first PMOS transistor connected between a power supply voltage terminal and one side of the fuse and configured as a gate input of the control signal across the fuse;
A second PMOS transistor connected between the other side of the fuse and the fuse state sensing node and using the control signal across the fuse as a gate input;
An NMOS transistor connected between a ground voltage terminal and the fuse state sensing node and configured to use the power-up signal as a gate input; And
And an output unit configured to output the fuse signal corresponding to a change in potential of the sensing node.
The method of claim 10,
The fuse circuit unit,
The fuse having one side connected to a power supply voltage terminal;
An inverter for driving one side of the fuse by inverting the control signal across the fuse;
A PMOS transistor connected between the other side of the fuse and the fuse state sensing node and having a control signal across the fuse as a gate input; And
An NMOS transistor connected between a ground voltage terminal and the fuse state sensing node and configured to use the power-up signal as a gate input; And
And an output unit configured to output the fuse signal corresponding to a change in potential of the fuse state detection node.
The method according to claim 11 or 12, wherein
And the output unit comprises an inverter latch for latching a logic value corresponding to the potential of the fuse state sensing node and outputting the same as the fuse signal.

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