KR20110076681A

KR20110076681A - Semiconductor memory device

Info

Publication number: KR20110076681A
Application number: KR1020090133437A
Authority: KR
Inventors: 나형준
Original assignee: 주식회사 하이닉스반도체
Priority date: 2009-12-29
Filing date: 2009-12-29
Publication date: 2011-07-06

Abstract

The present invention provides a semiconductor device having a fuse circuit that can reduce power consumption. The present invention is a fuse connected to one side of the sensing node; A first switch providing a driving voltage to the other side of the fuse in response to a first level of a control signal; A second switch providing a ground voltage to the sensing node in response to a second level of the control signal; And a fuse signal output unit configured to output a fuse signal corresponding to the voltage of the sensing node, wherein the control signal is activated only in a predetermined section for checking whether the fuse is cut.

Semiconductor, Fuse, Repair, Program

Description

Semiconductor device {SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a semiconductor device, and more particularly, to a fuse circuit of a semiconductor memory device.

In a typical memory device, a large number of memory cells are integrated in one chip. If any one of these memory cells is defective, the memory chip is treated as defective and cannot be used. In the trend of integrating a larger number of memory cells in a finite size chip due to high integration, if the entire memory chip is treated as defective when one cell fails, the number of memory chips to be treated as defective increases. This makes it impossible to produce economical semiconductor memory devices.

In order to solve this problem, a conventional semiconductor memory device is provided with a spare cell other than the fuse circuit. The fuse circuit includes a plurality of fuses and replaces a defective cell with a spare cell depending on whether the fuse blows in the repair process. Spare cells and fuse circuits are formed in extra space during the semiconductor manufacturing process. In the repair process, a repair operation is performed to replace a memory cell determined as defective with a spare cell.

Fuses include physical fuses and electrical fuses. In the method using a physical fuse, the repair process is performed by irradiating a laser beam to the fuse and selectively blowing the fuse in a wafer state where the semiconductor process is completed. The disadvantage of physical fuses is that the repair process can be performed only in the wafer state, before the semiconductor memory device is manufactured into a package.

Meanwhile, the semiconductor device may include a plurality of test related circuits for defect analysis and characteristic improvement. In the test mode, when the improvement of the circuit characteristics or the malfunction of the semiconductor memory device is confirmed, the fuse circuit is used to reflect the changes of the circuit which has been performed in the test mode even during the actual operation. That is, when a specific fuse of the fuse circuit is cut, the corresponding specific test mode is basically reflected when the actual memory device operates.

The present invention provides a semiconductor device having a fuse circuit that can reduce power consumption.

The present invention is a fuse connected to one side of the sensing node; A first switch providing a driving voltage to the other side of the fuse in response to a first level of a control signal; A second switch providing a ground voltage to the sensing node in response to a second level of the control signal; And a fuse signal output unit configured to output a fuse signal corresponding to the voltage of the sensing node, wherein the control signal is activated only in a predetermined section for checking whether the fuse is cut.

The control signal may be a reset signal for a reset operation of the semiconductor device.

The first and second switches may be MOS transistors, respectively.

The control signal may be activated in a power-up mode of the semiconductor device.

The fuse signal output unit may include: first and second inverters connected to buffer the voltage level of the sensing node; And a third MOS transistor receiving the output of the first inverter as a gate and connected in parallel with the second MOS transistor.

According to the present invention, the power consumed in the fuse circuit can be greatly reduced. Therefore, the power consumption of the semiconductor device including the fuse circuit can be reduced.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuse circuit widely used in a semiconductor device, and to a technology capable of reducing power consumption to several thousandths during a power-up process while maintaining the function of an existing circuit.

1 is a circuit diagram showing a fuse circuit of a semiconductor device for explaining the present invention.

Referring to FIG. 1, the fuse circuit includes a PMOS transistor MP1, an NMOS transistor MN1 and MN2, an inverter IN1 and IN2, and a fuse F. Referring to FIG. The PMOS transistor MP1 receives a ground voltage VSS through its gate, one side of the PMOS transistor MP1 is connected to the fuse F, and the other side of the PMOS transistor MP1 receives a power supply voltage VDD. One side of the fuse F is connected to the sensing node a, and the other side is connected to one side of the PMOS transistor MP1.

The NMOS transistor MN1 receives a reset signal R through a gate, one side of the NMOS transistor MN1 is connected to the sensing node a, and the other side of the NMOS transistor MN1 receives a ground voltage. The inverters IN1 and IN2 output a fuse signal OUT buffering the voltage level of the sensing node a. One side of the NMOS transistor MN2 is applied to the sensing node a, and the other side receives the ground voltage VSS, and receives the output signal of the inverter IN1 through the gate.

FIG. 2 is a waveform diagram illustrating an operation of the semiconductor device of FIG. 1. More specifically, FIG. 2A is a waveform diagram of the fuse signal OUT when the fuse F is not cut, and FIG. 2B is a fuse signal when the fuse F is cut. A waveform diagram for (OUT). 2C is a waveform diagram showing the amount of current consumed during the power-up process when the fuse F is not cut.

An operation of a fuse circuit of a semiconductor device will be described with reference to FIGS. 1 and 2.

The circuit shown in Figure 1 is a circuit for detecting whether the fuse is cut. The fuse circuit of FIG. 1 outputs a low level fuse signal OUT when the fuse F is cut, and outputs a high level fuse signal OUT when the fuse F is not cut.

The PMOS transistor MP1 receives the ground voltage VSS as a gate and maintains a turn-on state to provide a power supply voltage VSS to one end of the fuse F. FIG. The reset signal R is input in the form of a pulse that temporarily maintains a high level in a power-up mode in which a power supply voltage is supplied to the semiconductor device. Therefore, the sensing node (a) goes low level in the power-up mode and maintains a low level when the fuse F is blown, and switches from a low level to a high level when the fuse F is not blown. do. The power-up mode refers to a section in which a power supply voltage is supplied to the semiconductor device during an initial operation, and at this time, the power supply voltage VDD rises to a predetermined level from the ground voltage. The fuse signal OUT is output at a low level when the sensing node a maintains a low level, and is output at a high level when the sensing node a maintains a high level.

The fuse circuit shown in FIG. 1 has a problem that a large through current of several tens of uA occurs in the power-up mode. The reason why such a through current is generated is that the ground voltage VSS is always turned on by inputting the gate of the PMOS transistor MP1, so that the PMOS transistor MP1 is input while the reset signal R is input at a high level. This is because the NMOS transistor NM1 is turned on at the same time. In other words, after the reset signal R rises and becomes greater than or equal to the threshold voltage Vth of the NMOS transistor NM1, a large amount of through current is formed from the reset signal R to just before the ground voltage VSS level.

The semiconductor device must have a large number of fuse circuits shown in FIG. 1 to replace defective parts therein with spare circuits. Thus, if a through circuit consumes tens of uA in one fuse circuit, the semiconductor device consumes several mA to several tens of mA in power-up mode. FIG. 2C shows that the semiconductor device consumes a lot of current in the power-up mode.

In order to solve this problem, the present invention provides a semiconductor device having a fuse circuit capable of reducing power consumed in a power-up mode.

3 is a circuit diagram illustrating a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 3, the fuse circuit includes a PMOS transistor MP11, an NMOS transistor MN11 and MN12, an inverter IN11 and IN12, and a fuse F. As shown in FIG. The PMOS transistor MP11 receives a reset signal R through its gate, one side of the PMOS transistor MP11 is connected to the fuse F, and the other side of the PMOS transistor MP11 receives a power supply voltage VDD. One side of the fuse F is connected to the sensing node a, and the other side is connected to one side of the PMOS transistor MP11.

The NMOS transistor MN11 receives a reset signal R through a gate, one side of the NMOS transistor MN11 is connected to the sensing node a, and the other side of the NMOS transistor MN11 receives a ground voltage. The inverters IN11 and IN12 output the fuse signal OUT buffering the voltage level of the sensing node a. One side of the NMOS transistor MN12 is applied to the sensing node a, and the other side receives the ground voltage VSS, and receives the output signal of the inverter IN11 through the gate.

4 is a waveform diagram illustrating an operation of the semiconductor device of FIG. 3. More specifically, FIG. 3A is a waveform diagram of the fuse signal OUT when the fuse F is not cut, and FIG. 3B is a fuse signal when the fuse F is cut. A waveform diagram for (OUT). FIG. 3C is a waveform diagram showing the amount of current consumed during the power-up process when the fuse F is not cut.

An operation of the fuse circuit of the semiconductor device will be described with reference to FIGS. 3 and 4.

The circuit shown in FIG. 3 is also a circuit for detecting fuse cutting. The fuse circuit of FIG. 3 outputs a low level fuse signal OUT when the fuse F is cut, and outputs a high level fuse signal OUT when the fuse F is not cut.

The PMOS transistor MP1 receives the reset signal R as a gate and maintains a turn-on state for a period in which the reset signal R is at a low level, thereby providing a power supply voltage VSS to one end of the fuse F. FIG. . The reset signal R is input in the form of a pulse that temporarily maintains a high level in a power-up mode in which a power supply voltage is supplied to the semiconductor device. Therefore, the sensing node (a) goes to the low level in the power-up mode and maintains the low level if the fuse (F) is blown, and switches from the low level to the high level if the fuse (F) is not blown. do. The power-up mode refers to a section in which a power supply voltage is supplied to the semiconductor device during an initial operation, and at this time, the power supply voltage VDD rises to a predetermined level from the ground voltage. The fuse signal OUT is output at a low level when the sensing node a maintains a low level, and is output at a high level when the sensing node a maintains a high level.

Therefore, the fuse circuit according to the present embodiment does not always maintain the turn-on state because the PMOS transistor MP1 providing the power supply voltage VDD to the fuse F receives the reset signal R as the gate. It is turned on only when the reset signal R is at a low level. The reset signal R is maintained at a low level only while checking whether the fuse cutting detection circuit is cut in the power-up mode.

Therefore, the through current passing through the PMOS transistor MP11 and the N-mode transistor NM11 can be reduced as compared with the fuse circuit of FIG. 1. As described above, a semiconductor device generally includes a plurality of fuse circuits, and among the plurality of fuse circuits provided in the semiconductor device, there may be a large number of fuse circuits that maintain a state in which an actual fuse is not cut. Since the semiconductor device according to the present embodiment can reduce the current consumed in the fuse circuit in the power-up mode, the current consumed in operation of the semiconductor device can be greatly reduced. The amount of current saving in the power up process according to the present invention can range from several mA to tens of mA. Figure 4 (c) shows that the current consumed during the power-up process according to the present invention is reduced.

Although the present invention has been described in detail with reference to exemplary embodiments above, those skilled in the art to which the present invention pertains can make various modifications to the above-described embodiments without departing from the scope of the present invention. Will understand. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined by the scope of the appended claims, as well as the appended claims.

FIG. 2 is a waveform diagram illustrating the operation of the semiconductor device of FIG. 1. FIG.

4 is a waveform diagram illustrating an operation of the semiconductor device of FIG. 3.

Explanation of symbols on the main parts of the drawings

F: fuse MP11: PMOS transistor

MN11, MN12: NMOS transistor IN11, IN12: inverter

Claims

A fuse connected to one side of the sensing node;

A first switch providing a driving voltage to the other side of the fuse in response to a first level of a control signal;

A second switch providing a ground voltage to the sensing node in response to a second level of the control signal; And

And a fuse signal output unit configured to output a fuse signal corresponding to the voltage of the sensing node, wherein the control signal is activated only in a predetermined section for checking whether the fuse is cut.

The method of claim 1,

And the control signal is a reset signal for a reset operation of the semiconductor device.

The method of claim 1,

And the first and second switches are MOS transistors, respectively.

The method of claim 1,

And the control signal is activated in a power-up mode of the semiconductor device.

The method of claim 3, wherein

The fuse signal output unit

Connected first and second inverters for buffering the voltage level of the sensing node; And

And a third MOS transistor configured to receive an output of the first inverter through a gate and be connected in parallel with the second MOS transistor.