JP4830993B2 - Degradation detection method for semiconductor device - Google Patents

Degradation detection method for semiconductor device Download PDF

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JP4830993B2
JP4830993B2 JP2007181868A JP2007181868A JP4830993B2 JP 4830993 B2 JP4830993 B2 JP 4830993B2 JP 2007181868 A JP2007181868 A JP 2007181868A JP 2007181868 A JP2007181868 A JP 2007181868A JP 4830993 B2 JP4830993 B2 JP 4830993B2
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拡 田久保
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Fuji Electric Co Ltd
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Description

この発明は、パワー半導体素子を用いた電力変換装置、例えばインバータや無停電電源装置(UPS)などにおいて、パワーモジュールの劣化、その中でも半導体チップや絶縁基板の接合に使用される半田の劣化を検出する方法に関する。   The present invention detects power module degradation in power conversion devices using power semiconductor elements, such as inverters and uninterruptible power supplies (UPS), and in particular, degradation of solder used for joining semiconductor chips and insulating substrates. On how to do.

インバータやUPSなどでは、一般にブリッジ接続されたバイポーラトランジスタやMOS−FET,IGBT(絶縁ゲート型バイポーラトランジスタ)などのパワー半導体素子をスイッチングすることにより電力変換を行なっている。
このような変換装置の例として、単相ブリッジインバータの構成例を図5に示す。これは、上下直列に接続されたパワー半導体素子(IGBT)3a,3bおよびダイオード(FWD:還流ダイオード)4a,4bを交互にスイッチングすることで、負荷であるモータ5に電力を供給するものである。なお、1は直流電源、2はモジュール容器、2a〜2cは端子を示す。
In an inverter, a UPS, or the like, power conversion is generally performed by switching a power semiconductor element such as a bridge-connected bipolar transistor, MOS-FET, or IGBT (insulated gate bipolar transistor).
As an example of such a converter, a configuration example of a single-phase bridge inverter is shown in FIG. This supplies power to the motor 5 that is a load by alternately switching power semiconductor elements (IGBT) 3a and 3b and diodes (FWD: freewheeling diodes) 4a and 4b connected in series in the vertical direction. . Reference numeral 1 denotes a DC power source, 2 denotes a module container, and 2a to 2c denote terminals.

このような回路に適用されるパワー半導体素子は、接続や冷却を簡便にするために複数の素子(チップ)を1つのパッケージ(モジュール)に収納して使用されるのが一般的であり、半導体を内蔵したパッケージを通常パワーモジュールと呼ぶ。
ブリッジ回路を構成するために、直列接続された2つのIGBTを収納したモジュールの外観例を図6に、また、そのモジュール断面図を図7にそれぞれ示す。
A power semiconductor element applied to such a circuit is generally used by storing a plurality of elements (chips) in one package (module) in order to simplify connection and cooling. A package with a built-in is usually called a power module.
FIG. 6 shows an example of the appearance of a module containing two IGBTs connected in series to form a bridge circuit, and FIG. 7 shows a sectional view of the module.

図6に示すモジュール容器2には、直流電源1からの入力端子2a,2b、負荷への接続端子2cおよびオン,オフ信号を入力するためのゲート端子2dが設けられている。
に示すように、表面に回路パターン12a〜12cが形成されたセラミック製絶縁基板12の回路パターン面(上面側)に、半導体チップ3a,3bが半田などのろう材により固着されており、各回路パターン12a〜12cと各チップとはアルミニウムワイヤ9a,9bによってボンディング接続され、図5のような回路が構成される。
The module container 2 shown in FIG. 6 is provided with input terminals 2a and 2b from the DC power supply 1, a connection terminal 2c to the load, and a gate terminal 2d for inputting an on / off signal.
As shown in FIG. 7 , the semiconductor chips 3a and 3b are fixed to the circuit pattern surface (upper surface side) of the ceramic insulating substrate 12 having the circuit patterns 12a to 12c formed on the surface thereof by a brazing material such as solder. The circuit patterns 12a to 12c and the chips are bonded to each other by aluminum wires 9a and 9b to form a circuit as shown in FIG.

また、セラミック製絶縁基板12の裏面にもベタパターン12dが設けられており、銅合金のような放熱板11に半田などによりろう付けされる。半導体チップ3a,3bや配線パターン12a〜12cなどの電気回路側と放熱板11は、セラミック基板12で絶縁されているので、感電を防止する目的で放熱板11を接地しても良く、使い勝手の良い構成にされる。   A solid pattern 12d is also provided on the back surface of the ceramic insulating substrate 12, and is brazed to the heat radiating plate 11 such as a copper alloy with solder or the like. Since the electric circuit side such as the semiconductor chips 3a and 3b and the wiring patterns 12a to 12c and the heat sink 11 are insulated by the ceramic substrate 12, the heat sink 11 may be grounded for the purpose of preventing electric shock. Good configuration.

ところで、上記のように構成されるパワーモジュールには、装置の断続的な運転による急激な温度変化により、接合に使用されている半田材が変質,劣化し、クラック(ひび割れ)が発生し、半導体チップの熱伝達が阻害され、半導体チップの温度が上昇し、ついには素子破壊してしまうという問題がある。半導体チップは上述のように、主に半田材により電極へロウ付けされるが、半導体チップ(シリコン材)と電極(鋼材)とは線膨張係数が異なる(鋼材:17×10-6/℃、シリコン:8×10-6/℃で、約3倍の差がある)ため、その間にはさまれた半田材にはせん断応力が発生する。 By the way, in the power module configured as described above, due to a rapid temperature change due to intermittent operation of the device, the solder material used for bonding is deteriorated and deteriorated, and a crack (crack) is generated. There is a problem that the heat transfer of the chip is hindered, the temperature of the semiconductor chip rises, and the element is finally destroyed. As described above, the semiconductor chip is brazed to the electrode mainly by a solder material, but the semiconductor chip (silicon material) and the electrode (steel material) have different linear expansion coefficients (steel material: 17 × 10 −6 / ° C., (Silicon: 8 × 10 −6 / ° C., which is a difference of about 3 times), a shear stress is generated in the solder material sandwiched between them.

したがって、長期にわたる断続通電を行なわせると、その温度変化による繰り返しのせん断応力により、接合部に亀裂(クラック)が進行する。或る程度亀裂が進行すると、亀裂部分では熱伝導率が低下する(いわゆる熱抵抗が増大する)ため、半導体チップの放熱性が阻害され、チップが過熱し、ついには半導体チップの破壊が引き起こされる。この半導体チップの発熱の繰り返しによるパワーモジュールの劣化および寿命をパワーサイクル耐量(またはパワーサイクル寿命)と呼び、パワーモジュールの信頼性を判断するための、非常に重要な項目の1つになっている。   Therefore, when intermittent energization is performed for a long time, a crack (crack) progresses in the joint due to repeated shear stress due to the temperature change. When the crack progresses to some extent, the thermal conductivity decreases at the cracked portion (so-called thermal resistance increases), so the heat dissipation of the semiconductor chip is hindered, the chip overheats, and eventually the semiconductor chip is destroyed. . This deterioration and life of the power module due to repeated heat generation of the semiconductor chip is called power cycle tolerance (or power cycle life), and is one of the very important items for judging the reliability of the power module. .

図8はパワーモジュールのパワーサイクル寿命特性曲線の例で、接合部の温度変化量(ΔTj)が大きくなると、各部の変形(膨張)量も大きくなり、上述のせん断応力も増大するため、パワーサイクル回数が低下することを示している。
図9は亀裂の進行状態を説明するもので、チップ裏面と回路パターン間を接合している半田材13に、亀裂13aが発生していることを示している。図9(a)では、比較的温度が高くなるチップ中央部の劣化、図9(b)では、チップ端部から広がるクラックの発生を示している。
FIG. 8 is an example of a power cycle life characteristic curve of the power module. When the temperature change amount (ΔTj) of the joint portion increases, the deformation (expansion) amount of each portion also increases and the above-described shear stress increases. It shows that the number of times decreases.
FIG. 9 illustrates the progress of cracks, and shows that cracks 13a have occurred in the solder material 13 that joins the back surface of the chip and the circuit pattern. FIG. 9A shows the deterioration of the center portion of the chip where the temperature is relatively high, and FIG. 9B shows the occurrence of cracks spreading from the end portion of the chip.

図10は、半導体チップ表面から金属ベース11までの熱抵抗(Rth)の推移を示している。パワーサイクルの回数とともに熱抵抗値が漸増し、寿命末期においては初期値に対し40%から60%程度まで熱抵抗値が急増し、破壊に至ることが判明した。
このようなパワー半導体素子の劣化を検出し、素子が破壊する直前に交換を促すことにより、設備機器のトラブルを防止する予防保全機能の実現が要望されており、特性劣化の推定,検出技術が例えば特許文献1,2に開示されている。
FIG. 10 shows the transition of the thermal resistance (Rth) from the semiconductor chip surface to the metal base 11. It was found that the thermal resistance value gradually increased with the number of power cycles, and at the end of the life, the thermal resistance value rapidly increased from 40% to about 60% with respect to the initial value, leading to destruction.
There is a demand for the realization of preventive maintenance functions to prevent troubles in equipment by detecting such deterioration of power semiconductor elements and prompting replacement immediately before the element breaks down. For example, it is disclosed in Patent Documents 1 and 2.

特許文献1には、半導体チップの半田劣化を検出する方法として、半導体チップ表面およびケース部に熱電対などの温度センサを設け、その温度差を計測することにより熱抵抗を算出し、劣化を判定する技術が示されている。
しかし、チップ表面へのセンサ取り付けが必要であるため、組立工程が複雑になったり、センサからの微弱な信号を制御回路へ配線する必要があるため、配線に重畳されるノイズに対する注意が必要になる。また、長期にわたる使用過程において、万一センサが外れてしまった場合には温度検出が不可能となるため、寿命検出も不能になってしまうと言う問題がある。
In Patent Document 1, as a method of detecting solder deterioration of a semiconductor chip, a temperature sensor such as a thermocouple is provided on the surface of the semiconductor chip and the case portion, and the thermal resistance is calculated by measuring the temperature difference to determine the deterioration. Technology to do is shown.
However, it is necessary to attach the sensor to the chip surface, so the assembly process becomes complicated, and a weak signal from the sensor must be wired to the control circuit, so it is necessary to pay attention to the noise superimposed on the wiring. Become. In addition, in the course of long-term use, there is a problem that if the sensor is removed, temperature detection becomes impossible and life detection becomes impossible.

一方、特許文献2には、図8のような予め求めてある半導体素子のパワーサイクル寿命特性曲線(温度変化幅に対するパワーサイクルの依存特性)と、実際の運転における温度,回数を比較し、特性曲線と照らし合わせて寿命推定を行なう技術が開示されている。しかし、ここでは単純な回数のみのカウントであり、実際の半田劣化状態を観測していないため、推定誤差が大きくなってしまう。通常、変換装置の負荷状態は一定ではなく、温度変化幅も運転状況によって様々に異なるため、単一の温度条件でのサイクル寿命数から実物のパワーサイクル寿命を推定することは極めて難しい。
また、予め半導体素子のパワーサイクル寿命特性曲線を求めておく必要があり、評価に時間が掛かる。さらに、メモリなどに寿命曲線および温度変化値、装置の運転履歴を記憶させておく必要があり、装置構成が複雑になる。
On the other hand, Patent Document 2 compares a power cycle life characteristic curve (a power cycle dependency characteristic with respect to a temperature change width) of a semiconductor element obtained in advance as shown in FIG. A technique for performing life estimation in comparison with a curve is disclosed. However, here, the count is a simple number, and since an actual solder deterioration state is not observed, an estimation error becomes large. Usually, the load state of the conversion device is not constant, and the temperature change width varies depending on the operating conditions. Therefore, it is extremely difficult to estimate the actual power cycle life from the number of cycle lifes under a single temperature condition.
In addition, it is necessary to obtain a power cycle life characteristic curve of the semiconductor element in advance, which takes time for evaluation. Furthermore, it is necessary to store a life curve, a temperature change value, and an operation history of the apparatus in a memory or the like, which complicates the apparatus configuration.

特開2003−172760号公報JP 2003-172760 A 特開2005−354812号公報JP 2005-354812 A

従って、この発明の解決しようとする課題は、パワーモジュールの半田接合部の劣化を効率よく正確に検出できるようにすることにある。   Therefore, the problem to be solved by the present invention is to enable efficient and accurate detection of deterioration of the solder joint portion of the power module.

上記課題を解決すため、請求項1の発明では、直流電源間に直列接続された半導体モジュールを有する半導体装置において、
前記直列接続された半導体素子に同時にオンパルスを与え、そのオンパルス期間での短絡電流値を検出することにより、半導体素子の劣化を検知可能にしたことを特徴とする。
In order to solve the above problem, in the invention of claim 1, in a semiconductor device having a semiconductor module connected in series between DC power supplies,
The semiconductor elements connected in series are simultaneously given an on-pulse, and a short-circuit current value in the on-pulse period is detected, thereby making it possible to detect deterioration of the semiconductor element.

上記請求項の発明においては、前記検出された短絡電流値を予め設定した基準レベルと比較し、その短絡電流値が基準レベルと異なったとき、半導体素子の劣化を検出することができ(請求項の発明)、この請求項の発明においては、前記基準レベルは、初期の短絡電流値に相当するレベルであることができる(請求項の発明)。

In the first aspect of the invention, the detected short-circuit current value is compared with a preset reference level, and when the short-circuit current value is different from the reference level, deterioration of the semiconductor element can be detected (invoice) invention of claim 2), in the invention of claim 2, wherein the reference level may be a level corresponding to the initial short-circuit current value (the invention of claim 3).

この発明では、直流電源間にブリッジ接続された半導体モジュールの、直列に接続された対の素子を同時にオンさせて短絡電流を流し、これにより半導体チップを発熱させ、流れる短絡電流を計測する。負荷状態によらず一定の短絡電流を流せるので、正確に熱抵抗の劣化を検出でき、パワーモジュールの破壊前に寿命を把握することが可能となる。   In the present invention, a pair of elements connected in series in a semiconductor module bridge-connected between DC power supplies are simultaneously turned on to cause a short-circuit current to flow, thereby causing the semiconductor chip to generate heat and measuring the flowing short-circuit current. Since a constant short-circuit current can flow regardless of the load state, it is possible to accurately detect the deterioration of the thermal resistance and to grasp the life before the power module is destroyed.

図1はこの発明の実施の形態を示す回路図で、IGBT3a,3bが直列に接続されたブリッジ回路の1相分を示す。IGBT3a,3bには駆動回路8a,8bが接続されており、制御回路10から発生される駆動信号15a,15bを増幅してIGBTを駆動するものである。そして、このように駆動されるIGBT3aに流れる電流を、電流検出器16により検出する。
電流検出器16により検出された電流信号は比較器6により基準電圧値7と比較され、短絡電流値が基準レベル以下または以上になったとき(基準レベルと異なるとき)は比較器6の出力14が反転する。この出力を寿命到達信号として検出することにより、パワーモジュールが破壊する前に寿命到達の検出が可能となる。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and shows one phase of a bridge circuit in which IGBTs 3a and 3b are connected in series. Drive circuits 8a and 8b are connected to the IGBTs 3a and 3b. The drive signals 15a and 15b generated from the control circuit 10 are amplified to drive the IGBT. Then, the current detector 16 detects the current flowing through the IGBT 3a driven in this way.
The current signal detected by the current detector 16 is compared with the reference voltage value 7 by the comparator 6, and when the short-circuit current value is below or above the reference level (when different from the reference level), the output 14 of the comparator 6 is output. Is reversed. By detecting this output as the end of life signal, it is possible to detect the end of life before the power module breaks down.

また、負荷の状態によらず、安定してIGBTを発熱させるため、この発明では上下アームのIGBT3a,3bに対し、短絡により破壊しない程度の、ごく短時間同時にオンさせるパルス(寿命計測用パルス)を入力し、大電流の短絡電流を流すことにより、その短絡電流値の温度依存性を利用することで、熱抵抗を計測できるようにしている。   In addition, in order to stably generate heat in the IGBT regardless of the load state, in the present invention, the IGBTs 3a and 3b of the upper and lower arms are simultaneously turned on for a very short time so as not to be broken by a short circuit (life measurement pulse). Is input, and a large short-circuit current is allowed to flow, so that the thermal resistance can be measured by utilizing the temperature dependence of the short-circuit current value.

図2に、IGBTの出力特性曲線(コレクタ・エミッタ間電圧−コレクタ電流)を示す。短絡時に流れる短絡電流値は、この出力特性曲線上に黒丸印で示す動作点で決定される。すなわち、IGBTに流れる短絡電流値はコレクタ・エミッタ間電圧、つまり直流電源1の電圧値、接合部温度Tj、およびゲート電圧値により決定される。一般的には、短絡電流値は正の温度係数を持っており、接合部温度が高いほど短絡電流は低くなる傾向があることが分かる。   FIG. 2 shows an output characteristic curve (collector-emitter voltage-collector current) of the IGBT. The value of the short-circuit current that flows at the time of a short circuit is determined by the operating point indicated by a black circle on the output characteristic curve. That is, the short-circuit current value flowing through the IGBT is determined by the collector-emitter voltage, that is, the voltage value of the DC power supply 1, the junction temperature Tj, and the gate voltage value. Generally, the short-circuit current value has a positive temperature coefficient, and it can be seen that the short-circuit current tends to decrease as the junction temperature increases.

図3に、寿命計測用パルスのタイミングチャートを示す。
ここでは、IGBT3aおよび3bに対し、それぞれ図3(a)に示すような、短時間の同時オンパルス信号を入力している。これに伴い、IGBTのコレクタ・エミッタ端子間には直流電源電圧が直接印加されるため、図2に示したようにIGBTには大電流のパルス状短絡電流が流れる(図3(c)参照)。このパルス電流のピークは一般的に、IGBT定格の5〜10倍程度の電流となる。
FIG. 3 shows a timing chart of the life measurement pulse.
Here, short-time simultaneous on-pulse signals as shown in FIG. 3A are input to the IGBTs 3a and 3b, respectively. Accordingly, a direct current power supply voltage is directly applied between the collector and emitter terminals of the IGBT, so that a large pulsed short-circuit current flows through the IGBT as shown in FIG. 2 (see FIG. 3C). . The peak of this pulse current is generally about 5 to 10 times the IGBT rating.

短絡電流が流れると、IGBTでは大きな損失が発生し、図3(b)に示すように、接合部温度Tjは急激に上昇する。一方、短絡電流(IGBTのコレクタ電流値)は、短絡期間中のTjの上昇に伴い漸減するが、熱抵抗が劣化、すなわち半田接合部が劣化している場合には、上述のように放熱がクラックにより阻害されるため、正常な状態と比較すると接合部温度Tjの上昇も高くなり(図3(b)の点線参照)、結果として短絡電流値は図3(c)に点線で示すように、正常時に比較して低くなる。   When a short-circuit current flows, a large loss occurs in the IGBT, and the junction temperature Tj rapidly increases as shown in FIG. On the other hand, the short-circuit current (the collector current value of the IGBT) gradually decreases as Tj increases during the short-circuit period. However, when the thermal resistance is deteriorated, that is, when the solder joint is deteriorated, heat dissipation is performed as described above. Since it is hindered by cracks, the increase in the junction temperature Tj is also higher than in the normal state (see the dotted line in FIG. 3B). As a result, the short-circuit current value is as shown by the dotted line in FIG. , Lower than normal.

上記短絡電流値を、比較器6において基準レベル7(正常時の短絡電流値)と比較し、基準レベル以下の場合は温度上昇が高い、すなわち半田接合部が劣化しているものと判断する。
一方、IGBTの温度係数が負の場合には、温度が高くなると短絡電流値は上昇するため、基準レベル以上の短絡電流が流れた場合には、熱抵抗が劣化したものと判断するようにする。
The short-circuit current value is compared with a reference level 7 (normal short-circuit current value) in the comparator 6, and if it is below the reference level, it is determined that the temperature rise is high, that is, the solder joint is deteriorated.
On the other hand, when the temperature coefficient of the IGBT is negative, the short-circuit current value increases as the temperature increases. Therefore, when a short-circuit current exceeding the reference level flows, it is determined that the thermal resistance has deteriorated. .

図4に、この発明の別の実施の形態を示す。これは、コレクタ電流を検出する手段として、IGBT3aに設けられた電流検出用エミッタ端子を利用するものである。この電流検出用エミッタ端子に、コレクタ電流の数100ないし数1000分の1の電流を流すと、電流検出抵抗17にはコレクタ電流に比例する電流信号が発生する。この電流信号の大小比較をすることにより、図1と同様にして半田接合部の劣化を検出することができる。
なお、IGBTの短絡耐量(時間)は、一般的には10マイクロ秒程度であり、この時間以下の寿命計測パルスを入力すれば良い。
FIG. 4 shows another embodiment of the present invention. This utilizes a current detection emitter terminal provided in the IGBT 3a as means for detecting the collector current. When a current of several hundreds to several thousandths of the collector current is supplied to the current detection emitter terminal, a current signal proportional to the collector current is generated in the current detection resistor 17. By comparing the magnitudes of the current signals, it is possible to detect the deterioration of the solder joint as in FIG.
In addition, the short circuit withstand capability (time) of the IGBT is generally about 10 microseconds, and a life measurement pulse less than this time may be input.

寿命計測パルスは必要に応じ、運転開始時や一定の累積期間毎に入力させれば良い。さらに、上下アームパルス15a,15bは、短絡電流が流れる期間が確保されれば、上下同じタイミングやパルス時間幅である必要も無い。
また、寿命計測パルス発生中には、IGBTのゲート電圧を低減させることにより、短絡電流を抑制して計測時間を延長することも可能である。
The life measurement pulse may be input at the start of operation or every certain accumulation period as necessary. Further, the upper and lower arm pulses 15a and 15b do not need to have the same timing and pulse time width as long as a period during which a short-circuit current flows is ensured.
In addition, during the lifetime measurement pulse generation, it is possible to suppress the short-circuit current and extend the measurement time by reducing the gate voltage of the IGBT.

以上では、直流電源間に2つのIGBTを接続した2レベルインバータの例を説明したが、多数のIGBTを直列に接続した3レベル以上のインバータについても、全てのIGBTを同時にオンさせることで、同様の効果が得られることは勿論である。   In the above, an example of a two-level inverter in which two IGBTs are connected between DC power supplies has been described, but the same applies to all three or more inverters in which a large number of IGBTs are connected in series by simultaneously turning on all the IGBTs. Of course, this effect can be obtained.

この発明の実施の形態を示す構成図Configuration diagram showing an embodiment of the present invention IGBTの出力特性曲線図IGBT output characteristics curve 図1の動作説明図FIG. 1 is an explanatory diagram of the operation. この発明の別の実施の形態を示す構成図The block diagram which shows another embodiment of this invention 一般的なインバータ回路を示す回路図Circuit diagram showing a general inverter circuit パワーモジュールの外観図External view of power module 図6の断面図Sectional view of FIG. パワーサイクル寿命を示す特性曲線図Characteristic curve diagram showing power cycle life 半田接合部の亀裂の説明図Illustration of cracks in solder joints パワーサイクルにおける熱抵抗(Rth)の推移説明図Transition diagram of thermal resistance (Rth) in power cycle

符号の説明Explanation of symbols

1…直流電源、2…モジュール容器、2a〜2d…端子、3a,3b…IGBT、4a,4b…ダイオード、5…負荷(モータ)、6…比較器、7…基準値、8a,8b…駆動回路、9a,9b…ワイヤ配線、10…制御回路、11…放熱板、12…絶縁基板、12a〜12c…配線パターン、13…半田材、13a…亀裂、15a,15b…駆動信号(上下アームパルス)、16…電流検出器、17…電流検出抵抗。   DESCRIPTION OF SYMBOLS 1 ... DC power supply, 2 ... Module container, 2a-2d ... Terminal, 3a, 3b ... IGBT, 4a, 4b ... Diode, 5 ... Load (motor), 6 ... Comparator, 7 ... Reference value, 8a, 8b ... Drive Circuits 9a, 9b ... wire wiring, 10 ... control circuit, 11 ... heat sink, 12 ... insulating substrate, 12a-12c ... wiring pattern, 13 ... solder material, 13a ... crack, 15a, 15b ... drive signal (upper and lower arm pulses) ), 16 ... current detector, 17 ... current detection resistor.

Claims (3)

直流電源間に直列接続された半導体モジュールを有する半導体装置において、
前記直列接続された半導体素子に同時にオンパルスを与え、そのオンパルス期間での短絡電流値を検出することにより、半導体素子の劣化を検知可能にしたことを特徴とする半導体装置の劣化検出方法。
In a semiconductor device having a semiconductor module connected in series between DC power supplies,
A degradation detection method for a semiconductor device, wherein degradation of a semiconductor element can be detected by simultaneously applying an on-pulse to the semiconductor elements connected in series and detecting a short-circuit current value during the on-pulse period .
前記検出された短絡電流値を予め設定した基準レベルと比較し、その短絡電流値が基準レベルと異なったとき、半導体素子の劣化を検出することを特徴とする請求項に記載の半導体装置の劣化検出方法。 2. The semiconductor device according to claim 1 , wherein the detected short-circuit current value is compared with a preset reference level, and deterioration of the semiconductor element is detected when the short-circuit current value is different from the reference level. Degradation detection method. 前記基準レベルは、初期の短絡電流値に相当するレベルであることを特徴とする請求項に記載の半導体装置の劣化検出方法。 3. The semiconductor device deterioration detection method according to claim 2 , wherein the reference level is a level corresponding to an initial short-circuit current value.
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