JP4581930B2 - Anomaly detection device for power semiconductor elements - Google Patents

Anomaly detection device for power semiconductor elements Download PDF

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JP4581930B2
JP4581930B2 JP2005261470A JP2005261470A JP4581930B2 JP 4581930 B2 JP4581930 B2 JP 4581930B2 JP 2005261470 A JP2005261470 A JP 2005261470A JP 2005261470 A JP2005261470 A JP 2005261470A JP 4581930 B2 JP4581930 B2 JP 4581930B2
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semiconductor element
power semiconductor
abnormality
means
detecting
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JP2007071796A (en
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聡毅 滝沢
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富士電機システムズ株式会社
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Description

  The present invention relates to an abnormality detection device for protecting a power semiconductor element used in a power conversion device or the like from destruction due to a high temperature or the like.

FIG. 3 shows a main circuit configuration of an inverter that performs DC-AC conversion as an example of a power converter.
In FIG. 3, 1 is a DC power source, 2 is a load such as an electric motor, and 3 is an inverter unit for converting a DC voltage into an AC voltage having a predetermined magnitude and frequency. Although not shown, the DC power supply 1 is generally configured by rectifying and smoothing an AC power supply voltage using a diode rectifier and a large-capacity electrolytic capacitor.

In the inverter unit 3, 4 is an IGBT as a power semiconductor element, and 5 is a free-wheeling diode connected in reverse parallel to the IGBT 4, and a total of six of them are connected to three-phase upper and lower arms.
Reference numeral 6 denotes a drive / protection circuit for the IGBT 4, and a module in which the IGBT 4 and the drive / protection circuit 6 are integrated is generally called an IPM (intelligent power module). Reference numeral 20 denotes a control circuit that exchanges signals with the drive / protection circuit 6 to control on / off of each IGBT 4.
Here, the drive / protection circuit 6 not only drives the IGBT 4 but also performs a protective operation for protecting the IGBT 4 from overcurrent and overheating.

  FIG. 4 is an internal configuration diagram of the drive / protection circuit 6 having overcurrent protection and overheat protection functions. Reference numeral 7 denotes a sense emitter terminal as a current detection terminal for detecting an overcurrent of the IGBT 4 (the IGBT 4 in this case is also referred to as an IGBT with a sense function), and the sense emitter terminal 7 is formed in the IGBT chip 4C. Has been.

In the drive / protection circuit 6 shown in FIG. 4, 8 is a gate drive circuit for receiving the control signal from the control circuit 20 to turn on / off the IGBT 4. Reference numeral 9 denotes a temperature detection diode built in the IGBT chip 4C, and a current flows from the current source 10 in the drive / protection circuit 6, and the current-temperature characteristics (temperature is high) of the diode 9 as shown in FIG. Then, the comparator 12 determines whether or not the temperature of the IGBT chip 4C is equal to or higher than the temperature corresponding to the reference voltage 11 using the characteristic that the voltage V f with respect to the same current value I 0 is lowered.
When the temperature detected by the diode 9 exceeds the set value, an alarm signal is output to the control circuit 20 in FIG. 3 through the OR circuit 13 and a signal is also output to the gate drive circuit 8 side. The IGBT 4 is forcibly cut off.

Reference numeral 14 denotes a current detection resistor connected in series with the sense emitter terminal 7. When the voltage across the resistor 14 exceeds the reference voltage 15, it is determined that an overcurrent flows through the IGBT 4, and the comparator 16 and the OR Alarm output and forced shut-off of the IGBT 4 are executed via the circuit 13.
In general, when an alarm signal is output, the control circuit 20 also forcibly stops the apparatus.

Next, FIG. 6 is a schematic cross-sectional view of the IPM in which the IGBT 4 and the drive / protection circuit 6 described above are integrated, and mainly shows a mounting structure of the IGBT chip 4C and the freewheeling diode chip 5C.
In FIG. 6, 171 is a copper base, 172 is an insulating material, 173 and 174 are copper foil patterns (the insulating material 172 and the copper foil patterns 173 and 174 are collectively referred to as an insulating substrate), and the IGBT chip 4C and the freewheeling diode chip 5C. Are soldered onto the copper foil patterns 173 and 174, respectively. Reference numerals 175 and 176 denote solder layers. Reference numeral 177 denotes a case.
Here, illustration and description of the mounting structure of the drive / protection circuit 6 are omitted.

Now, generally, when IPM is used over a long period of time, the solder layers 175 and 176 cause thermal fatigue due to the difference in thermal expansion coefficient between the solder layers 175 and 176 and the copper foil patterns 173 and 174. As a result, as shown in FIG. Thus, when the crack 178 begins to enter, for example, the thermal resistance between the IGBT chip 4C and the insulating substrate increases rapidly, and the temperature increase rate of the IGBT chip 4C also increases rapidly. For this reason, the temperature detection operation by the diode 9, the comparator 12, the OR circuit 13 and the like in FIG. 4 described above is not in time, and there is a possibility that the IGBT chip 4C is finally destroyed. Further, when a crack 178 enters the solder layers 175 and 176, the IPM has already reached the end of its life, and the power conversion device needs to be replaced at an early stage.

As a conventional technique, a constant collector current is passed through a semiconductor element in advance, and the collector-emitter voltage and temperature are measured and stored as initial values. Patent Document 1 describes a method for determining deterioration of a power semiconductor element in which a difference between a measured value and the initial value is compared with a reference value to determine deterioration of an element including a bonding wire and a solder layer. .
In addition, the temperature of the electrodes provided on the front and back sides of the power semiconductor element is measured by two thermocouples, respectively, and the measured temperature value and the measured on-residual voltage of the semiconductor element are compared with the initial values, and Japanese Patent Application Laid-Open No. 2004-133867 discloses an abnormality detection device for a semiconductor device that detects the occurrence of cracks due to deterioration.

JP 2002-5989 A ([0021] to [0034], FIG. 1, FIG. 4 etc.) JP 2003-172760 A ([0071] to [0084], FIGS. 1 to 3 etc.)

In the prior art described in Patent Document 1, the collector current flow process in the initial state and the steady state for the purpose of detecting deterioration, the collector-emitter voltage and temperature measurement process, the storage process, etc. are indispensable. Since these steps need to be performed separately from the normal operation of the power converter, the deterioration detection operation is complicated. In addition, it is necessary to store the above-described measurement values, which causes deterioration detection operation, complicated circuit configuration, and increased cost.
Also in the prior art described in Patent Document 2, temperature or voltage detection in the initial state and storage of measured values are required as in Patent Document 1, and two thermocouples and voltage measurement circuits are required. Therefore, it has the same problem as Patent Document 1.
Furthermore, Patent Documents 1 and 2 do not particularly disclose a configuration for clearly discriminating overheating and deterioration due to occurrence of cracks from overheating due to overcurrent, for example.

  Therefore, the problem to be solved by the present invention is to detect abnormalities such as cracking due to thermal fatigue as overheating due to overcurrent, etc., in parallel with the on / off operation of the semiconductor element in the normal operation of the power converter, In addition, an object of the present invention is to provide a power semiconductor element abnormality detection device that can be realized with a relatively simple circuit configuration.

In order to solve the above-mentioned problem, the invention described in claim 1 is a power semiconductor element abnormality detection device including a current detection terminal and an electrode of an element chip joined to a conductor, wherein the current detection In an abnormality detection device for a power semiconductor element that detects a current flowing in a terminal and performs a protective operation on the semiconductor element,
First means for detecting an element temperature when the semiconductor element is turned off and on according to a control signal for turning on and off the semiconductor element and obtaining a temperature difference thereof;
A second means for detecting that the ON time of the semiconductor element is a set value or less;
A third means for detecting that a current flowing through the semiconductor element is a set value or less;
Comparison means for detecting that the temperature difference obtained by the first means exceeds a set value;
And a second means, a third means, and a means for detecting thermal fatigue of the conductor based on a logical product of all the detection outputs from the comparison means.

  According to a second aspect of the present invention, in the first aspect, the conductor is a solder layer for bonding the electrode to the surface of the copper foil pattern, and the means for detecting thermal fatigue of the solder layer is a thermal layer. It detects cracks due to fatigue.

  According to a third aspect of the present invention, at the time of thermal fatigue detection according to the first or second aspect, the power conversion device having the semiconductor element as a constituent element is controlled according to an abnormality control algorithm.

  According to a fourth aspect of the present invention, in the third aspect, the abnormality control algorithm includes a control operation that immediately shuts off the semiconductor element and stops the operation of the power converter.

The invention described in claim 5 is, in claim 4,
The abnormal-time control algorithm includes a control operation for stopping the operation of the power conversion apparatus after a predetermined time has elapsed or after execution of a preset operation pattern.

The invention described in claim 6 is any one of claims 3 to 5,
The abnormal time control algorithm includes a control operation for outputting an alarm signal to the outside.

According to the present invention, a temperature difference between before and after turning on / off is detected using a control signal for turning on / off a semiconductor element, and when this temperature difference exceeds a set value, the element is turned on for a long time or overcurrent. A state other than the time is detected as occurrence of abnormality due to thermal fatigue.
This eliminates the need to measure and store the initial values of voltage and temperature for the purpose of detecting deterioration of the elements as in Patent Documents 1 and 2 described above. Can be executed. Therefore, it is possible to expect a simplified circuit configuration including the storage means for initial values and the like, and the burden on the control means for executing the abnormality detection operation can be reduced.
Further, since it is possible to detect the occurrence of abnormality due to thermal fatigue as another abnormality factor such as overcurrent, it is possible to respond appropriately and promptly thereafter.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a configuration diagram of a drive / protection circuit 6A according to the embodiment, and a main part thereof constitutes an abnormality detection device of the present invention. In FIG. 1, the same components as those in FIG. 4 are denoted by the same reference numerals.
The drive / protection circuit 6A, like the drive / protection circuit 6 in FIG. 3, drives the IGBT 4 constituting the inverter unit 3 and the like according to a control signal from the control circuit 20, and cracks the solder layer due to thermal fatigue. It has a function to protect against such as.

  In FIG. 1, a control signal a (on time t is given) from the control circuit 20 given to the gate drive circuit 8 is a second one-shot circuit via a first one-shot circuit 31 and a NOT circuit 33. 34, respectively. The output signals of these one-shot circuits 31 and 34 are applied as triggers to the first and second sample and hold circuits 32 and 35, respectively. With the above configuration, the first sample and hold circuit 32 causes the rise of the control signal a. The input signal b is sampled and held at the timing, and the second sample hold circuit 35 is configured to sample and hold the input signal b at the falling timing of the control signal a.

An input signal b of the sample and hold circuits 32 and 35 is a current signal of the diode 9, that is, a temperature detection signal of the IGBT 4, and an output signal c of the first sample and hold circuit 32 corresponds to a temperature detection value immediately before the IGBT 4 is turned on. The output signal d of the second sample and hold circuit 35 corresponds to the temperature detection value immediately before the IGBT 4 is turned off.
These signals c and d are input to the differentiator 36 to calculate a deviation. The deviation is a signal e corresponding to a temperature difference (temperature rise value) before and after the IGBT 4 is energized.
Here, when the ON time t of the control signal a is short, it is difficult to accurately detect the temperature rise value before and after the IGBT 4 is energized. Therefore, the signal (temperature difference) e is significant for the ON time t. It is necessary to set a certain long period so as to have a correct value.

If a crack or the like is not generated in a solder layer (for example, solder layer 175 in FIG. 6) in which the IGBT chip 4C is bonded onto the copper foil pattern and the sound is healthy, the temperature difference before and after the IGBT 4 is turned on / off is the solder layer itself. The normal thermal resistance value, the on-time t of the IGBT 4, the characteristics of the IGBT 4 itself, and the current that actually flows through the IGBT 4 can be calculated. The temperature difference when the solder layer is healthy is set as the reference voltage 56 of the comparator 57.
As a result, the comparator 57 compares the temperature difference e with the reference voltage 56, and outputs a “High” level thermal fatigue detection signal f to the AND circuit 42 when the temperature difference e exceeds the reference voltage 56. That is, when the crack is generated in the solder layer and the thermal resistance value is increased, the temperature difference e is increased. Therefore, the occurrence of a crack due to thermal fatigue is detected by comparison with the reference voltage 56 by the comparator 57, and the signal f Is output.

On the other hand, the integrator 37 to which the control signal a is input is for measuring the on time t of the IGBT 4. When the on time t exceeds the set value by the reference voltage 39, the comparator 38 and the third A “Low” level signal g is output to the AND circuit 42 via the one-shot circuit 40.
As for this signal g, the thermal fatigue detection signal f is erroneously output when the IGBT 4 is turned on for a long time despite the soundness of the solder layer and the temperature difference e exceeds the reference voltage 56. It is for preventing.

Further, the overcurrent detection signal of the IGBT 4 output from the comparator 59 is input to the fourth one-shot circuit 41, and the “Low” level output signal h is input to the AND circuit 42 together with the signals f and g. ing.
That is, even when an overcurrent flows through the IGBT 4, the temperature difference e may exceed the reference voltage. Therefore, the output signal h of the one-shot circuit 41 is the thermal fatigue detection signal f when the temperature rises due to such an overcurrent. It has a function to prevent erroneous output.

  An output signal i of the AND circuit 42 to which the above-described signals f, g, and h are input is sent to the control circuit 20 as an abnormality detection signal due to thermal fatigue. When all of the signals f, g, and h are at the “High” level, the on-time t of the IGBT 4 is not more than the set value, and the current flowing through the IGBT 4 is not more than the overcurrent level. This means that the temperature difference e before and after the IGBT 4 is turned on and off exceeds the set value (reference voltage 56) when the solder layer is healthy. A detection signal i is output.

As described above, according to the present embodiment, it is possible to discriminate and detect only the overheating state caused by thermal fatigue by excluding the overheating phenomenon due to the long-term on or overcurrent of the IGBT 4. For this reason, appropriate countermeasures such as replacement of the IGBT chip 4C and the IPM can be quickly executed.
In addition, the abnormality detection operation can be performed by using the control signal a for operating the power converter, and the abnormality detection is performed by effectively using the control signal a. Minimized signal, operation and process.
Further, since measurement and storage of initial values is not required as in the prior art, there is an advantage that a circuit used for these is unnecessary, the circuit configuration can be simplified, and the burden on the control means is small. .

Next, FIG. 2 shows a control algorithm in the control circuit 20.
When there is no abnormality detection signal i described above with respect to the operation command j of the power conversion device having the inverter unit 3 (when the signal i is at the “Low” level), the normal control algorithm 53 is executed via the AND gate 51. The algorithm 53 is validated and the algorithm 53 is executed via the OR gate 55.
On the other hand, when the abnormality detection signal i is generated (when the signal i is at the “High” level), the abnormality control algorithm 54 is validated via the AND gate 52 and this algorithm 54 is executed via the OR gate 55. .

Here, the normal time control algorithm 53 is an algorithm necessary for a control operation for turning on / off each IGBT in order to output a voltage of a predetermined magnitude and frequency from the power converter, and the abnormal time control algorithm is an It means an algorithm that immediately stops the operation of the power conversion device or outputs an alarm signal by the all gate off operation.
However, in some cases, even if a crack or the like is generated in the solder layer, if the temperature of the IGBT chip is equal to or lower than the absolute maximum rated temperature, there is little risk of immediate destruction. The operation of the power conversion device may be stopped later.

  In the embodiment of the present invention, detection of cracks due to thermal fatigue and detection of overcurrent are performed by the drive / protection circuit 6A in the IPM, but may be performed in the control circuit 20 of the power converter. Of course.

It is a block diagram of the drive and protection circuit which shows embodiment of this invention. It is explanatory drawing of the control algorithm in a control circuit. It is a main circuit block diagram of an inverter. FIG. 4 is an internal configuration diagram of a drive / protection circuit in FIG. 3. It is a current-temperature characteristic view of a temperature detection diode. It is a schematic sectional drawing of IPM. It is a schematic sectional drawing of IPM when a crack generate | occur | produces in a solder layer.

Explanation of symbols

4: IGBT
4C: IGBT chip 6A: Drive / protection circuit 7: Sense emitter terminal 8: Gate drive circuit 9: Diode 10: Current source 14: Resistor 37: Differentiator 31, 34, 40, 41: One-shot circuit 32, 35: Sample Hold circuit 33: NOT circuit 38, 57, 59: Comparator 39, 56, 58: Reference voltage 42: AND circuit 51, 52: AND gate 53: Control algorithm at normal time 54: Control algorithm at abnormal time 55: OR gate

Claims (6)

  1. A power semiconductor element abnormality detection device including a current detection terminal and an electrode of an element chip bonded to a conductor, and detecting a current flowing through the current detection terminal to protect the semiconductor element In the power semiconductor element abnormality detection device to perform,
    First means for detecting an element temperature when the semiconductor element is turned off and on according to a control signal for turning on and off the semiconductor element and obtaining a temperature difference thereof;
    A second means for detecting that the ON time of the semiconductor element is a set value or less;
    A third means for detecting that a current flowing through the semiconductor element is a set value or less;
    Comparison means for detecting that the temperature difference obtained by the first means exceeds a set value;
    Means for detecting thermal fatigue of the conductor by a logical product of all detection outputs by the second means, the third means, and the comparison means;
    An apparatus for detecting an abnormality of a power semiconductor element, comprising:
  2. In the power semiconductor element abnormality detection device according to claim 1,
    The conductor is a solder layer for joining the electrode to the surface of a copper foil pattern,
    The means for detecting thermal fatigue of the solder layer detects cracks due to thermal fatigue, and an abnormality detecting device for a power semiconductor element.
  3.   An abnormality detection device for a power semiconductor element, wherein a power conversion device including the semiconductor element as a component is controlled according to an abnormality control algorithm when thermal fatigue is detected according to claim 1 or 2.
  4. In the power semiconductor element abnormality detection device according to claim 3,
    The abnormality control device for a power semiconductor element, wherein the abnormality control algorithm includes a control operation for immediately shutting off the semiconductor element and stopping the operation of the power converter.
  5. In the power semiconductor element abnormality detection device according to claim 4,
    The abnormality detection device for a power semiconductor element, wherein the abnormality control algorithm includes a control operation for stopping the operation of the power converter after a predetermined time has elapsed or after execution of a preset operation pattern.
  6. In the abnormality detection apparatus for a power semiconductor element according to any one of claims 3 to 5,
    The abnormality detection apparatus for a power semiconductor element, wherein the abnormality control algorithm includes a control operation for outputting an alarm signal to the outside.
JP2005261470A 2005-09-09 2005-09-09 Anomaly detection device for power semiconductor elements Active JP4581930B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106597245A (en) * 2016-11-04 2017-04-26 山东科技大学 IGBT fault monitoring device and method

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4725552B2 (en) * 2007-05-09 2011-07-13 トヨタ自動車株式会社 Semiconductor device leakage current inspection apparatus and inspection method
DE102008045410B4 (en) 2007-09-05 2019-07-11 Denso Corporation Semiconductor device with IGBT with built-in diode and semiconductor device with DMOS with built-in diode
JP4924578B2 (en) * 2007-09-05 2012-04-25 株式会社デンソー Semiconductor device
JP5061860B2 (en) * 2007-11-19 2012-10-31 横河電機株式会社 Mounting circuit and semiconductor test equipment
JP2011024382A (en) * 2009-07-17 2011-02-03 Fuji Electric Systems Co Ltd Gate drive circuit
JP5974548B2 (en) 2012-03-05 2016-08-23 富士電機株式会社 Semiconductor device
CN103105572B (en) * 2013-01-25 2016-04-13 北京金风科创风电设备有限公司 For the device of test I GBT module
JP2014207566A (en) * 2013-04-12 2014-10-30 パナソニック デバイスSunx株式会社 Photoelectric sensor
JP6015718B2 (en) * 2014-07-14 2016-10-26 トヨタ自動車株式会社 Information output device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06281693A (en) * 1992-08-28 1994-10-07 Fuji Electric Co Ltd Measuring method for thermal resistance of semiconductor device
JPH11262270A (en) * 1998-03-13 1999-09-24 Toshiba Corp Intelligent power module and power converting device using the same
JP2003134795A (en) * 2001-10-22 2003-05-09 Hitachi Ltd Fault sensing system
JP2003172760A (en) * 2001-12-05 2003-06-20 Omron Corp Abnormality detection device for semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06281693A (en) * 1992-08-28 1994-10-07 Fuji Electric Co Ltd Measuring method for thermal resistance of semiconductor device
JPH11262270A (en) * 1998-03-13 1999-09-24 Toshiba Corp Intelligent power module and power converting device using the same
JP2003134795A (en) * 2001-10-22 2003-05-09 Hitachi Ltd Fault sensing system
JP2003172760A (en) * 2001-12-05 2003-06-20 Omron Corp Abnormality detection device for semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106597245A (en) * 2016-11-04 2017-04-26 山东科技大学 IGBT fault monitoring device and method
CN106597245B (en) * 2016-11-04 2019-01-18 山东科技大学 A kind of monitoring device and method of IGBT failure

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