JP5245306B2 - Degradation protection method for semiconductor device - Google Patents

Description

  The present invention relates to a protection method for detecting deterioration of a power module and preventing its destruction in a power conversion device using a power semiconductor element, such as an inverter or an uninterruptible power supply (UPS).

Inverters, UPSs, and the like generally perform power conversion by switching power semiconductor elements such as bridge-connected bipolar transistors, MOS-FETs, and IGBTs (insulated gate bipolar transistors).
As an example of such a converter, a configuration example of a single-phase bridge inverter is shown in FIG. This supplies power to the motor 5 that is a load by alternately switching power semiconductor elements (IGBT) 3a and 3b and diodes (FWD: freewheeling diodes) 4a and 4b connected in series in the vertical direction. . Reference numeral 1 denotes a DC power source, 2 denotes a module container, and 2a to 2c denote terminals.

A power semiconductor element applied to such a circuit generally stores a plurality of elements (chips) in one package (module) for easy connection and cooling. Is usually called a power module.
FIG. 4 shows an example of the appearance of a module containing two IGBTs connected in series to form a bridge circuit, and FIG. 5 shows a sectional view of the module.

The module container 2 shown in FIG. 4 is provided with input terminals 2a and 2b from the DC power source 1, a connection terminal 2c to the load, and a gate terminal 2d for inputting an on / off signal.
As shown in FIG. 5, the semiconductor chips 3a and 3b are fixed to the circuit pattern surface (upper surface side) of the ceramic insulating substrate 12 having the circuit patterns 12a to 12c formed on the surface thereof by a brazing material such as solder. The circuit patterns 12a to 12c and the chips are bonded to each other by aluminum wires 9a and 9b, thereby forming a circuit as shown in FIG.

  A solid pattern 12d is also provided on the back surface of the ceramic insulating substrate 12, and is brazed to the heat radiating plate 11 such as a copper alloy with solder or the like. Since the electric circuit side such as the semiconductor chips 3a and 3b and the wiring patterns 12a to 12c and the heat sink 11 are insulated by the ceramic substrate 12, the heat sink 11 may be grounded for the purpose of preventing electric shock. Good configuration.

  By the way, in the power module configured as described above, due to a rapid temperature change due to intermittent operation of the device, not only the internal terminal connection portion is disconnected due to thermal fatigue, but also the semiconductor chip is caused by a spark generated at the time of disconnection. There is a problem of destroying. Connection from the semiconductor chip surface (emitter terminal surface) to electrodes, external connection terminals, etc. by bonding wires such as aluminum as described above, that is, by rubbing the wires and connection surfaces with ultrasonic waves and plastically deforming with frictional heat Is done.

The connection is a connection point between aluminum (wiring material) and silicon (semiconductor chip). The linear expansion coefficient of each material is aluminum: 23 × 10 ⁻⁶ / ° C., silicon: 8 × 10 ⁻⁶ / ° C., There is a difference of about 3 times. Therefore, when intermittent energization is performed over a long period of time, due to the difference in expansion coefficient due to the temperature change, stress is repeatedly generated in the joint portion, and a crack (crack) progresses in the joint portion. If this crack progresses to some extent, the voltage drop at the crack portion increases, and the amount of heat generation increases, so that the crack progresses at an accelerated rate and eventually causes disconnection.

This deterioration and life of the power module due to repeated heat generation is called power cycle tolerance (or power cycle life), and is one of the very important items for judging the reliability of the power module.
FIG. 6 is an example of a power cycle life characteristic curve of the power module, and shows that the number of power cycles decreases as the temperature change amount (ΔTj) of the junction increases.

FIG. 7 illustrates the progress of cracks, and shows that cracks 9c (shown by jagged lines) occur at the connection points between the surfaces of the chips 3a and 3b and the bonded wires 9a and 9b.
FIG. 8 shows an example of resistance value measurement at the connection point. In the initial state, the resistance value of the wire connection portion is about 2 mΩ, but the resistance value increases with the number of power cycles, and it has been found that the resistance value rapidly increases to about 5 mΩ at the end of the life, leading to destruction.
There is a demand for the realization of preventive maintenance functions that prevent troubles in equipment by promptly detecting such characteristic deterioration of power semiconductor elements and prompting replacement immediately before the element breaks down. Estimating and detecting characteristic deterioration For example, Patent Documents 1 and 2 disclose such techniques.

Patent Document 1 discloses a technique for detecting a separation of a semiconductor chip wiring by providing a dummy wiring whose wiring strength is weaker than that of the main wiring and detecting that the main wiring is near the end of its life from the separation. Yes.
However, not only does the wiring process at the time of module manufacture become complicated, but in the case of wire peeling at the actual life, the electrodes on the chip surface are often damaged by sparks, and the peeling of the dummy wiring immediately reaches the product life. There is a problem to say.

  On the other hand, Patent Document 2 compares the power cycle life characteristic curve (depending on the power cycle with respect to the temperature change width) of a semiconductor element obtained in advance as shown in FIG. A technique for performing life estimation in comparison with a curve is disclosed. However, since this is a simple count only and the actual peeling state is not observed, the estimation error becomes large. Usually, the additional state of the conversion device is not constant, and the temperature change width varies depending on the operating conditions. Therefore, it is extremely difficult to estimate the actual power cycle life from the number of cycle lifes under a single temperature condition.

In addition, it is necessary to obtain a power cycle life characteristic curve of the semiconductor element in advance, which takes time for evaluation. Furthermore, it is necessary to store a life curve, a temperature change value, and an operation history of the apparatus in a memory or the like, and the apparatus configuration becomes complicated.
Also, since the resistance value of the junction is about several mΩ, the voltage drop at the current value that the power module normally passes is very small at about 0.2 to 0.5 V, so it is very difficult to detect with high accuracy. . Furthermore, since the current value confidence of the power module varies depending on the operating state and is not always constant, it is very difficult to detect the resistance value of the joint in accordance with the current value.

JP 2005-286209 A JP-A-08-05768

  Therefore, the problem to be solved by the present invention is to enable efficient and accurate detection of deterioration of the internal wiring of the power module.

In order to solve the above-mentioned problem, in the invention of claim 1, a voltage drop in a wire wiring connected to the surface of the semiconductor module by connecting a semiconductor module having a plurality of semiconductor elements connected in series between DC power sources In which deterioration of a semiconductor element is detected by detecting an on-pulse, simultaneously applying an on-pulse to a plurality of semiconductor elements connected in series between the DC power supplies, and detecting a voltage drop in the wire wiring during the on-pulse period. And

In the invention described in claim 1, as compared to the previous SL reference level set a voltage drop in advance of the wire wiring, when the voltage drop of the wire wiring is equal to or greater than the reference level, it is possible to detect the deterioration of the semiconductor element (Invention of Claim 2 ).

  In the present invention, a pair of elements connected in series in a semiconductor module bridge-connected between DC power supplies are simultaneously turned on to cause a short-circuit current to flow, and a voltage drop in the wire wiring at that time is measured. As a result, a constant current can flow regardless of the load state, so that a voltage drop at the wire junction can be accurately detected, and the lifetime of the semiconductor module can be grasped before destruction.

  FIG. 1 is a circuit diagram showing an embodiment of the present invention, and shows one phase of a bridge circuit in which IGBTs 3a and 3b are connected in series. Drive circuits 8a and 8b are connected to the IGBTs 3a and 3b. The drive signals 15a and 15b generated from the control circuit 10 are amplified to drive the IGBT. Reference numerals 9a and 9b denote the same wire wiring as in FIG. 5, and comparators 6a and 6b are provided to detect voltage drop levels in the wire wirings 9a and 9b, and the comparison with the reference values 7a and 7b is performed.

  When the voltage drop in the wire wirings 9a and 9b exceeds the reference value, that is, when the crack of the wire joint progresses, the outputs 14a and 14b of the comparators 6a and 6b are inverted. By detecting it, it is possible to detect the end of life before the power module is destroyed. Further, in order to accurately detect such a small voltage drop as described above, in the present invention, the pulses that cause the IGBTs 3a and 3b of the upper and lower arms to be simultaneously turned on for a very short time so as not to be broken by a short circuit (life measurement pulse). Is input, and a large short-circuit current is allowed to flow, so that a minute resistance value can be measured regardless of the state of the load.

FIG. 2 shows a timing chart of a life measurement pulse.
Short-time simultaneous on-pulse signals as shown in FIGS. 2A and 2B are input to the IGBTs 3a and 3b, respectively. As a result, a large pulsed short-circuit current as shown in FIG. 2C flows through the IGBTs 3a and 3b. In general, the peak of the pulse current is about 5 to 10 times the IGBT rating.

For example, in a 100 A rated IGBT, the short circuit current reaches 500 to 1000 A, so the voltage drop (Vwire) at the junction resistance is 500 A short circuit current and 2 mΩ junction resistance (initial). Then, it becomes as follows.
Vwire = 500A × 2mΩ = 1V
On the other hand, if the junction resistance at the time of life was 5 mΩ,
Vwire = 500A × 5mΩ = 2.5V
Therefore, by setting the life level voltage values 7a and 7b near the middle between the initial time and the life time as shown in FIG.

  Since the detected voltage is about several volts, it is less susceptible to external noise and the like than when detecting a voltage drop of 1 V or less when measured at the rated current. Moreover, since the short-circuit current characteristics are determined by the characteristics of the element (IGBT) chip, it is possible to accurately detect the voltage drop regardless of the magnitude of the load current. Since the short-circuit tolerance (time) of the IGBT chip is generally about 10 microseconds, a life measurement pulse shorter than this time may be used.

  Further, the life measurement pulse may be input at the start of operation or every certain accumulation period as necessary. Furthermore, the upper and lower arm pulses 15a and 15b as drive signals do not need to have the same timing and pulse time width as long as the short-circuit current flows. In addition, during the lifetime measurement pulse generation, it is possible to suppress the short-circuit current and extend the measurement time by reducing the gate voltage of the IGBT.

  In the above, an example of a two-level inverter in which two IGBTs are connected between DC power supplies has been described, but the same applies to all three or more inverters in which a large number of IGBTs are connected in series by simultaneously turning on all the IGBTs. Of course, this effect can be obtained. Also, the wire voltage of all IGBTs among a plurality of modules in the inverter may be detected, and if the operation responsibilities are the same, the life of each module is considered to be almost the same. The voltage may be detected.

Configuration diagram showing an embodiment of the present invention FIG. 1 is an explanatory diagram of the operation. Circuit diagram showing a general inverter circuit External view of power module Sectional view of FIG. Characteristic curve diagram showing power cycle life characteristics Explanatory drawing of cracks in wire bonding Explanatory diagram of resistance transition at bonding connection in power cycle

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... DC power supply, 2 ... Module container, 2a-2d ... Terminal, 3a, 3b ... IGBT, 4a, 4b ... Diode, 5 ... Load (motor), 6a, 6b ... Comparator, 9a, 9b ... Wire wiring, 10 ... Control circuit, 11 ... Heat sink, 12 ... Insulating substrate, 12a to 12c ... Wiring pattern, 15a, 15b ... Drive signal (upper and lower arm pulses).

Claims (2)

A semiconductor module including a plurality of semiconductor elements connected in series is connected between DC power supplies, and the deterioration of the semiconductor element is detected by detecting a voltage drop in the wire wiring connected to the surface of the semiconductor module. A method for protecting a deterioration of a semiconductor device , comprising: simultaneously applying an ON pulse to a plurality of semiconductor elements connected in series between the DC power supplies, and detecting a voltage drop in the wire wiring during the ON pulse period .   2. The semiconductor device according to claim 1, wherein the voltage drop of the wire wiring is compared with a preset reference level, and deterioration of the semiconductor element is detected when the voltage drop of the wire wiring is equal to or higher than the reference level. Deterioration protection method.

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