JP2017184298A - Electric power conversion system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electric power conversion system capable of improving the service life of power semiconductor modules connected in parallel.SOLUTION: The electric power conversion system includes: a plurality of power semiconductor modules 20 (PM1, PM2) connected in parallel; a controller 304 for controlling the plurality of power semiconductor modules. The controller suppresses a load current of the power semiconductor module with the largest increment of thermal resistance among the plurality of power semiconductor modules.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a power conversion device in which a plurality of power semiconductor modules are connected in parallel.

  The power conversion device reduces the loss generated from the power semiconductor device by realizing a higher-speed switching operation by technological innovation of the power semiconductor device used in the power semiconductor module which is a main component. Thereby, especially a cooler can be reduced in size, As a result, size reduction of a power converter device is realized.

  Inverters, converters, and choppers that are power converters include UPS (Uninterruptible Power-supply System), PCS (Power Conditioning System), AC drive, and other industrial power converters, and hybrid vehicles (HEV: It is widely used as an in-vehicle power conversion device such as a hybrid electric vehicle (EV) and an electric vehicle (EV), and further as a power conversion device for home appliances. In addition to downsizing, these power conversion devices are required to have long-life products that have low running costs due to power conversion efficiency and low maintenance costs such as component replacement.

  In addition to the power semiconductor module and the cooler, the power conversion device includes a power conversion unit including components such as a bus bar for electrically connecting the components and a capacitor for smoothing DC power. In order to multiply the output of the power converter by N, such power conversion units are made N parallel.

  On the other hand, the power semiconductor module in the power conversion device deteriorates with time in internal heat radiation characteristics and the like with long-term operation. For example, under long-term operating conditions, the power load of the power conversion device and the power semiconductor module fluctuates (power cycle), and the power semiconductor module repeats a transition between a high temperature state and a low temperature state.

  At this time, since the power semiconductor module is composed of materials having different thermal expansion coefficients (copper wiring, solder, silicon chip, insulating member such as resin, metal case such as aluminum), the heat due to repeated thermal expansion and contraction The generation of stress causes solder cracks, peeling of the insulating member, and the like, and degrades the insulating characteristics and heat dissipation characteristics (thermal resistance characteristics, etc.) of the power semiconductor module.

  As described above, when thermal fatigue due to the power cycle proceeds, the power semiconductor module is likely to fail. Therefore, in order to extend the life of the power conversion unit and the power semiconductor module, operation control is required so as not to cause thermal fatigue.

  Furthermore, in order to multiply the output power by N, a power conversion device in which a plurality of power semiconductor modules are connected in parallel is operated for a long period of time, depending on the initial characteristics of each power semiconductor module and the difference in ambient temperature distribution. Variations occur in the degree of resistance degradation. If a current equivalent to that of other power semiconductor modules continues to flow through a power semiconductor module whose thermal resistance has deteriorated, element heat generation will increase in some power semiconductor modules, and as a result, thermal fatigue will proceed, and power semiconductors This leads to premature module failure. Therefore, in order to extend the life of the power conversion device, control is required to equalize the thermal resistance degradation caused by thermal fatigue between the power semiconductor modules.

  On the other hand, techniques described in Patent Document 1 and Patent Document 2 are known.

  In the technique described in Patent Document 1, in order to make the effective lifetime of switching elements such as a plurality of transistors operating in parallel, based on the temperature difference between the average temperature of the transistors and the measured temperature of each transistor, The energization current is controlled so that the transistors are thermally balanced.

  Further, in the technique described in Patent Document 2, in order to predict the life against the power cycle, the thermal resistance between the constituent members of the switching element is obtained to evaluate the degree of deterioration of the constituent members, and the deterioration is referred to as temperature / thermal resistance. Judging by the relationship.

Japanese Patent Laying-Open No. 2015-159712 JP 2009-225541 A

  When the technique described in Patent Document 1 is applied to a plurality of power semiconductor modules connected in parallel, the element temperature is affected by a cooler (air cooling fin or fan) outside the power semiconductor module. Since it is difficult to distinguish between the deterioration inside the module and the external deterioration factor, it is difficult to extend the life of the power conversion device.

  Further, in Patent Document 2, it is possible to detect deterioration information of the power semiconductor module with respect to the power cycle, but consideration is not given to life equalization and longer life of the power semiconductor modules connected in parallel.

  Therefore, the present invention provides a power conversion device that can improve the life of power semiconductor modules connected in parallel.

  In order to solve the above problems, a power converter according to the present invention includes a plurality of power semiconductor modules connected in parallel and a control unit that controls the plurality of power semiconductor modules, and the control unit includes: The load current of the power semiconductor module having the largest thermal resistance increase among the plurality of power modules is reduced.

  By reducing the load current of the power semiconductor module having the largest increase in thermal resistance, the progress of deterioration of the power semiconductor module can be suppressed. Thereby, the lifetime of a power converter device can be extended.

  Problems, configurations, and effects other than those described above will become apparent from the following description of embodiments.

It is a circuit diagram of the power converter device which is Example 1 of the present invention. An example of power cycle life characteristics of a power semiconductor module is shown. The inverter block diagram in Example 1 is shown. It is a longitudinal direction sectional view showing a schematic configuration example of a power semiconductor module. The load current adjustment control flow of the power semiconductor module in Example 1 is shown. The example of the relationship of working time, load current imbalance ratio, thermal resistance, and element temperature in Example 1 is shown. It is a circuit diagram of the power converter device which is Example 2 of this invention. It is a circuit diagram of the power converter device which is Example 3 of this invention. It is a circuit diagram of the power converter device which is Example 4 of this invention. The load current adjustment control flow of the power semiconductor module in Example 4 is shown.

  Embodiments of the present invention will be described below with reference to the drawings. In each figure, the same reference numerals indicate the same constituent elements or constituent elements having similar functions.

  Each of the following embodiments is applied to a three-phase inverter circuit, but is not limited thereto, and can be applied to a single-phase inverter circuit, a converter circuit, a DC-DC conversion circuit, and the like.

  FIG. 1 is a circuit diagram of a power conversion apparatus that is Embodiment 1 of the present invention. In addition, the power converter device of the present Example 1 is a three-phase inverter.

  As shown in FIG. 1, the inverter 1030 converts DC power between PNs into three-phase AC power. The U-phase converter 301, the V-phase converter 302, and the W-phase converter 303 include the power semiconductor module 20 that includes power semiconductor devices (21, 22, 23, and 24 in FIG. 1). The DC power supplied from the PN terminal controls the switching timing by the inverter control circuit 304 in the switching element 21 and the rectifying element 23 of the upper arm and the switching element 22 and the rectifying element 24 of the lower arm provided for each phase. Is converted into AC power. Then, AC power is output to each AC terminal 502 (U, V, W) of U-phase converter 301, V-phase converter 302, and W-phase converter 303.

  In the first embodiment, IGBTs (Insulated Gate Bipolar Transistors) are used as the switching elements 21 and 22, and diodes are used as the rectifying elements 23 and 24. In addition, it is also possible to apply not only these power semiconductor devices but other types of elements (the same applies hereinafter). A smoothing capacitor 25 is externally attached to each phase of the power semiconductor module 20.

  The inverter 1030 according to the first embodiment has a basic configuration of a two-level half bridge circuit 20 in which an upper arm switching element 21 and a rectifying element 23 and a lower arm switching element 22 and a rectifying element 24 are connected in series. It is said. Here, in each arm, the switching element and the rectifying element are connected in antiparallel, and the rectifying element functions as a free-wheeling diode. The control means in the first embodiment as described later can also be applied to an inverter, a converter, a booster circuit, etc. having a three-level basic configuration.

  FIG. 2 shows an example of power cycle life characteristics of the power semiconductor module 20.

  As shown in FIG. 2, the power semiconductor module 20 is composed of materials having different coefficients of thermal expansion (insulating members such as copper wiring, solder, silicon chip, resin, metal base made of aluminum, resin case, etc.). The generation of thermal stress due to repeated thermal expansion and contraction causes solder cracks, peeling of the insulating member, and the like, thereby degrading the insulating characteristics and heat dissipation characteristics (thermal resistance characteristics) of the power semiconductor module. At this time, if the temperature change ΔT of the power semiconductor module is large, the internal thermal stress increases, so the number of power cycle life Nc until the characteristics of the power semiconductor module deteriorates decreases.

  FIG. 3 is a configuration diagram of the inverter 1030 according to the first embodiment.

  As shown in FIG. 3, each phase (U-phase converter 301, V-phase converter 302, and W-phase converter 303) constituting the three-phase inverter is configured by two power semiconductor modules 20. The power semiconductor modules PM1, PM2 include a temperature sensor 31 that monitors the chip junction temperature (Tj) of the power semiconductor devices 21, 22, 23, 24 inside the power semiconductor module. Temperature information obtained by the temperature sensor 31 is input to the control unit 304.

  Further, current sensors 32 for detecting the load current of each power semiconductor module are provided at the output terminals of the power semiconductor modules PM1 and PM2 connected in parallel. Load current information obtained by the current sensor is input to the control unit 304.

  FIG. 4 is a longitudinal sectional view showing a schematic configuration example of the power semiconductor module 20.

  As shown in FIG. 4, in the power semiconductor module, an insulating substrate 1003 is placed on a metal base 1002, and the insulating substrate 1003 and the metal base 1002 are bonded by a bonding material such as solder. A power semiconductor device 1004 is mounted on the surface of the insulating substrate 1003, and the power semiconductor device 1004 and the insulating substrate 1003 are bonded together by a bonding material such as solder. In addition, a resin case 1005 is bonded onto the metal base 1002, and the insulating substrate 1003 and the power semiconductor device 1004 are stored in the resin case 1005. The power semiconductor module having such a configuration is placed on the radiation fin 1001. Here, the metal base 1002 is in surface contact with the radiation fins 1001.

  Heat generated by power loss of the power semiconductor device 1004 flows through the power semiconductor device 1004, the insulating substrate 1003, the metal base 1002, and the heat radiation fin 1001 in this order, and is dissipated into the atmosphere. At this time, the thermal resistance (Rth) between the power semiconductor device 1004 and other members (insulating substrate 1003, metal base 1002, radiating fin 1001, air) is the temperature (Tj) of the power semiconductor device 1004 and other members. Can be measured by temperature (T) and power loss (P) (Rth = (Tj−T) / P). When subjected to thermal stress due to power cycle, cracks occur in the bonding material or separation between members occurs, so that thermal resistance increases and heat dissipation performance deteriorates.

  In the power semiconductor module of FIG. 4, a temperature sensor (corresponding to reference numeral 31 in FIG. 2) is provided in the vicinity of the power semiconductor device 1004 in the resin case 1005, and the temperature (Tj) of the power semiconductor device 1004 is measured. Further, a temperature sensor is provided in the vicinity of the metal base 1002 in the radiating fin 1001 to measure the temperature (Tc (case temperature)) of the radiating fin 1001. The power loss (P) is measured based on current information measured by the current sensor 32 (FIG. 2). For example, the relationship between the current information and the power loss information is stored in advance by the control unit 304 (FIG. 2), and the control unit 304 calculates the power loss information from the current information using this relationship. Note that the voltage information of each phase may be detected, and the power loss information may be calculated from the detected voltage information and current information. From these Tj, Tc, and P, the control unit 304 calculates the thermal resistance (Rth (j−c)) between the power semiconductor device 1004 and the metal base 1002 (Rth (j−c) = (Tj−Tc). ) / P).

  Note that the thermal resistance between the power semiconductor device 1004 and another member may be calculated without being limited to the radiating fin 1001. For example, when measuring the thermal resistance between the power semiconductor device 1004 and the atmosphere, air temperature or room temperature may be used as the temperature of other members. When temperature is used, it may be measured by a temperature sensor or weather data may be used.

  FIG. 5 shows a load current adjustment control flow of the power semiconductor modules PM1 and PM2 in the first embodiment.

  First, during initial operation, the power semiconductor modules PM1 and PM2 are controlled so that the load currents of the power semiconductor modules PM1 and PM2 are equal.

  Next, during operation, the control unit 304 of the inverter 1030 measures the thermal resistance of the two power semiconductor modules PM1 and PM2 based on the temperature information and the load current information obtained by the temperature sensor 31 and the current sensor 32, respectively. Is calculated. Furthermore, the control unit 304 compares the calculated measured value of the current thermal resistance with an initial thermal resistance value set in advance in the control unit 304, and uses the two power semiconductor modules PM1, PM1 as an index representing the increase in thermal resistance. The difference (measured value of current thermal resistance−initial thermal resistance value) between the measured value of the current thermal resistance and the initial thermal resistance value in PM2, that is, the thermal resistance increment value is calculated. Here, the initial thermal resistance value may be similarly calculated by the control unit 304 during initial operation, or may be measured in advance by another means and set in the control unit 304. Moreover, you may use the thermal resistance value on specification as an initial thermal resistance value. The control unit 304 determines whether the thermal resistance increment value of any of the power semiconductor modules PM1 and PM2 is greater than or equal to the first specified value (specified value 1).

  When the thermal resistance increment value of at least one power semiconductor module becomes a specified value 1 or more due to long-term operation, that is, the thermal resistance inside the power semiconductor module due to thermal fatigue accompanying power cycle deteriorates (increases), When the specified value is 1 or more (yes), the load current of the power semiconductor module whose thermal resistance is deteriorated is reduced, and the load current unbalanced operation for increasing the load current of the other power semiconductor module is started. . Moreover, when it is not determined that the thermal resistance increment value of any power semiconductor module is equal to or greater than the specified value 1 (no), the load current equalization operation is continued.

  Load current unbalanced operation After shifting to load current unbalanced operation, the thermal resistance increment values of the two power semiconductor modules PM1 and PM2 are compared, and the thermal resistance of the power semiconductor module with the larger thermal resistance increment value deteriorates. It is determined that

  When it is determined that the thermal resistance of the power semiconductor module PM1 is deteriorated, the control unit 304 causes the gate drive voltage Vg (PM1) of the power semiconductor module PM1 to be higher than the gate drive voltage Vg (PM2) of the power semiconductor module PM2. The load current (I_PM1) of the power semiconductor module PM1 and the element temperature (Tj_PM1) of the power semiconductor module PM1 are lower than the load current (I_PM2) of the power semiconductor module PM2 and the element temperature (Tj_PM2) of the power semiconductor module PM2, respectively. Also make it smaller.

  When it is determined that the thermal resistance of the power semiconductor module PM1 is deteriorated, the control unit 304 causes the gate drive voltage Vg (PM1) of the power semiconductor module PM1 to be higher than the gate drive voltage Vg (PM2) of the power semiconductor module PM2. The load current (I_PM1) of the power semiconductor module PM1 and the element temperature (Tj_PM1) of the power semiconductor module PM1 are lower than the load current (I_PM2) of the power semiconductor module PM2 and the element temperature (Tj_PM2) of the power semiconductor module PM2, respectively. Also make it smaller.

  When it is determined that the thermal resistance of the power semiconductor module PM2 is deteriorated, the control unit 304 uses the gate drive voltage Vg (PM2) of the power semiconductor module PM2 as the gate drive voltage Vg (PM1) of the power semiconductor module PM2. The load current (I_PM2) of the power semiconductor module PM2 and the element temperature (Tj_PM2) of the power semiconductor module PM2 are respectively the load current (I_PM1) of the power semiconductor module PM1 and the element temperature (Tj_PM1) of the power semiconductor module PM1. ) Smaller than.

  Further, in the load current unbalanced operation, the control unit 304 determines whether the thermal resistance increment value of any one of the power semiconductor modules PM1 and PM2 is equal to or greater than a second specified value (specified value 2) larger than the specified value 1. Determine. When it is determined that the thermal resistance increment value of at least one power semiconductor module is equal to or greater than the specified value 2 (yes), that is, when the thermal resistance of any of the power semiconductor modules PM1 and PM2 deteriorates until the system specifications are not satisfied, The control unit 304 determines that the power semiconductor module has failed, and executes control at the time of abnormality such as stopping the inverter. Moreover, when it is not determined that the thermal resistance increment value of any power semiconductor module is equal to or greater than the specified value 2 (no), the load current unbalance operation is continued. That is, in the load current unbalanced operation, while the thermal resistance increment value of each power semiconductor module is smaller than the specified value 2, the control unit 304 calculates the thermal resistance increment value of the two power semiconductor modules PM1 and PM2, and described above. Thus, the load currents of the power semiconductor modules PM1 and PM2 are controlled.

  FIG. 6 shows the operating time, the load current unbalance ratio (I_PM2 / I_PM1) of each power semiconductor module, and the thermal resistance (Rjc_PM1, Rjc_PM2) between the power semiconductor device and the radiation fin of each power semiconductor module in the first embodiment. An example of the relationship between the element temperatures (Tj_PM1, Tj_PM2) of each power semiconductor module is shown. Here, it is assumed that the initial values of the thermal resistances of PM1 and PM2 are substantially the same, and the thermal resistance value is used instead of the above-described thermal resistance increment value as an index representing the increase in thermal resistance.

  When the thermal resistances of the power semiconductor modules PM1 and PM2 are both less than or equal to the specified value 1, each power semiconductor module is controlled so that the load current unbalance ratio = 1, that is, the load current equal operation.

  When it is determined that the thermal resistance Rjc_PM1 of the power semiconductor module PM1 exceeds the specified value 1 in a certain control cycle, the operation shifts to a load current unbalance operation in which the load current unbalance ratio> 1. At this time, in the power semiconductor modules PM1 and PM2, the load current (I_PM1) and the element temperature (Tj_PM1) of the power semiconductor module PM1 are smaller than the load current (I_PM2) and the element temperature (Tj_PM2) of the power semiconductor module PM2, respectively. To be controlled.

  Thereby, in the power semiconductor module PM1 in which the load current and the element temperature are reduced, the thermal stress applied to the solder and the insulating substrate inside the power semiconductor module is reduced, and the progress of deterioration of the thermal resistance can be suppressed. On the other hand, in the power semiconductor module PM2, the thermal stress increases, and the thermal resistance deteriorates more than in the power semiconductor module PM1. Accordingly, the thermal resistances of the power semiconductor modules PM1 and PM2 are balanced.

  When it is determined that the thermal resistance Rjc_PM2 of the power semiconductor module PM2 is greater than the thermal resistance Rjc_PM1 of the power semiconductor module PM1 in a certain control cycle after shifting to the load current unbalanced operation where the load current imbalance ratio> 1. Shift to load current unbalanced operation in which current unbalance ratio <1. At this time, the power semiconductor modules PM1 and PM2 are controlled so as to reduce the thermal stress of the power semiconductor module PM2 having a large thermal resistance value and suppress the progress of deterioration of the thermal resistance.

  In the first embodiment, as described above, the load current unbalance ratio is set in advance according to the thermal resistance increment value of the power semiconductor modules PM1 and PM2 or the magnitude relationship between the thermal resistance values, and the load current unbalance ratio is set according to the load current unbalance ratio. The value of the gate voltage is preset. It should be noted that if the thermal resistance increment value is used as an index representing the degree of progress of thermal resistance degradation and indicates the increment of thermal resistance, the progress of thermal resistance degradation can be accurately measured even if the initial value of thermal resistance varies.

  As described above, according to the first embodiment, in the plurality of power semiconductor modules connected in parallel in the power conversion device, the degree of progress of the thermal resistance deterioration varies depending on the initial characteristics of each module and the difference in ambient temperature distribution. Even if it occurs, each power semiconductor caused by thermal fatigue is controlled by reducing the load current of the power semiconductor module with a large degree of deterioration based on information on thermal resistance and suppressing the progress of thermal fatigue. It is possible to equalize the module life and avoid early failure of some power semiconductor modules. Thereby, the lifetime of a power converter device can be extended.

  FIG. 7 is a circuit diagram of a power conversion apparatus that is Embodiment 2 of the present invention. The power conversion device according to the second embodiment is a three-phase inverter as in the first embodiment. FIG. 7 shows a circuit configuration of one phase (U phase) of the three-phase inverter. Hereinafter, differences from the first embodiment will be mainly described.

  As shown in FIG. 7, the control unit 304 includes a load current / voltage-loss data table 305, a thermal resistance storage memory 306, a thermal resistance calculation circuit 307, a load current imbalance determination circuit 308, and a gate drive voltage adjustment. Circuit 309.

  Output load current information and output voltage information from the load current sensor 32 are input to the load current / voltage-loss data table 305. The load current / voltage-loss data table 305 calculates and outputs loss information of the power semiconductor module 20 from the output load current information and the output voltage information.

  The thermal resistance calculation circuit 307 includes loss information output from the load current / voltage-loss data table 305, element temperature information of the power semiconductor modules PM1 and PM2, and power semiconductor module cooling fins included in the power conversion unit 301. Temperature information is input. The thermal resistance calculation circuit 307 calculates and outputs the internal thermal resistance of the power semiconductor module 20 from the loss information, element temperature information, and cooling fin temperature information. Then, the calculated thermal resistance information of the power semiconductor modules PM1 and PM2 is input to the load current imbalance determination circuit 308.

  The load current imbalance determination circuit 308 includes output load current information from the load current sensor 32, thermal resistance information of each of the power semiconductor modules PM1 and PM2 output from the thermal resistance calculation circuit 307, and a thermal resistance storage memory 306. The initial thermal resistance information of the power semiconductor modules PM1 and PM2 is input.

  In the load current unbalance determination circuit 308, according to the load current adjustment control flow shown in FIG. 5, the determination of the transition to the load current unbalance operation and the increase in the thermal resistance increment value during the load current unbalance operation are performed. Select and determine the amount of load current adjustment.

  In the load current equal operation, when the thermal resistance increment value of at least one power semiconductor module becomes a specified value 1 or more due to long-term operation, that is, the thermal resistance inside the power semiconductor module is reduced due to thermal fatigue accompanying power cycle. When the specified value is 1 or more, the load current of one power semiconductor module whose thermal resistance has deteriorated is reduced, and the load current unbalanced operation is increased to increase the load current of the other power semiconductor module. To do.

  Next, the calculated thermal resistance increment values of the two power semiconductor modules PM1 and PM2 are compared, and the load current of the power semiconductor module having a large thermal resistance increment value is reduced. For example, when the thermal resistance increment value of the power semiconductor module PM1 is larger than the thermal resistance increment value of the power semiconductor module PM2, the control unit 304 reduces the gate drive voltage Vg (PM1) of the power semiconductor module PM1 to increase the power The load current (I_PM1) and element temperature (Tj_PM1) of the semiconductor module PM1 are adjusted to be smaller than the load current (I_PM2) and element temperature (Tj_PM2) of the power semiconductor module PM2, respectively.

  Further, in the load current unbalanced operation, when the thermal resistance increment value of at least one power semiconductor module becomes a specified value 2 or more, that is, until the thermal resistance of one of the power semiconductor modules PM1 and PM2 does not satisfy the system specification. When the power semiconductor module deteriorates, it is determined that the power semiconductor module has failed.

  On the other hand, in the load current unbalanced operation, while the thermal resistance increment value of each power semiconductor module is equal to or less than the specified value 2, the control unit 304 calculates the thermal resistance increment value of the two power semiconductor modules PM1 and PM2, and the thermal resistance Control is performed to reduce the load current of the power semiconductor module having a large increment value.

  According to the second embodiment, the thermal resistance of each power semiconductor module can be calculated using the element temperature sensor of the power semiconductor module, the temperature sensor of the power semiconductor module cooler, and the load current / voltage information. Furthermore, even if variations in thermal resistance degradation occur due to differences in the initial characteristics and ambient temperature distribution of each module, power semiconductors that tend to degrade based on thermal resistance increment information with reference to thermal resistance memory memory Module determination is possible. By reducing the load current of power semiconductor modules that tend to deteriorate and controlling the progression of thermal fatigue, the life of each power semiconductor module due to thermal fatigue is equalized, and the early life of some power semiconductor modules Failure can be avoided. Thereby, the lifetime of the power converter device resulting from a power semiconductor module can be improved.

  FIG. 8 is a circuit diagram of a power conversion apparatus that is Embodiment 3 of the present invention. In FIG. 3, the configuration of the gate drive voltage adjustment circuit 309 is shown in detail. The power conversion device according to the third embodiment is a three-phase inverter as in the first embodiment. FIG. 8 shows a circuit configuration of one phase (U phase) of the three-phase inverter. Hereinafter, differences from the first embodiment will be mainly described.

  As shown in FIG. 8, the gate drive voltage adjustment circuit 309 includes a drive circuit 101. The drive circuit 101 includes an interface (I / F) circuit unit 106, a delay circuit unit 103, a gate voltage slope variable circuit unit 104, and a gate. A voltage variable circuit unit 105 is included.

  The load current in the load current equal operation and the load current unbalance operation is controlled by adjusting the gate drive voltage.

  From the load current imbalance determination circuit 308, a gate drive voltage adjustment signal corresponding to the adjustment load current of each power semiconductor module is sent via the interface circuit 106 to the delay circuit unit 103, the gate voltage slope variable circuit unit 104, and the gate voltage variable. Each is input to the circuit unit 105.

  The delay circuit unit 103 adjusts the amount of delay of the gate signal 201 on the wiring, and matches the timing of each gate signal input from the delay circuit 103 to the gate voltage gradient variable circuit unit 104 equally.

  The gate voltage gradient variable circuit unit 104 controls the rising and falling gradients dVge / dt of the gate drive voltage (Vge) input to each power semiconductor module. By adjusting the slope of the gate drive voltage, the amount of switching current or switching loss flowing through each power semiconductor module can be adjusted.

  The gate voltage variable circuit unit 105 controls the peak value of the gate drive voltage input to each power semiconductor module. By adjusting the peak value of the gate drive voltage, the amount of steady current or steady loss flowing through each power semiconductor module can be adjusted.

  Here, during the load current equal operation, the gate drive voltage waveform is controlled by each drive circuit 101 so that the amount of switching current flowing through each power semiconductor module is substantially equal to the amount of steady current.

  Further, during the load current imbalance operation, the gate voltage gradient variable circuit unit 104 determines the rising and falling gradients (dVge / dt) of the gate drive voltage (Vge) input to each power semiconductor module. Is controlled so that the slopes (di / dt) of the switching currents are equal. Furthermore, the gate voltage variable circuit unit 105 controls the peak value of the gate drive voltage input to each power semiconductor module so that the amount of steady current flowing through each power semiconductor module is unbalanced.

  At this time, the amount of steady current flowing through each power semiconductor module is controlled so that the steady current of the power semiconductor module with large thermal resistance degradation is smaller than the steady current of the power semiconductor module with small thermal resistance degradation.

  According to the third embodiment, the gate drive voltages of the two power semiconductor modules PM1 and PM2 can be individually controlled. Thereby, it becomes possible to individually control the switching current and the steady current of the power semiconductor module.

  In the load current unbalanced operation, if an excessive switching current flows through one of the power semiconductor modules, the power semiconductor device may be thermally destroyed or the surge voltage may be increased. Therefore, in load current unbalanced operation, control is performed so that the gradient of the switching current becomes equal, the peak value of the gate drive voltage is unbalanced, and the steady current of each power semiconductor module is adjusted to control the load current. Thus, it is possible to avoid an excessive switching current from flowing through the power semiconductor device.

  FIG. 9 is a circuit diagram of a power conversion apparatus that is Embodiment 4 of the present invention. The power conversion device according to the fourth embodiment is a three-phase inverter as in the first embodiment. Hereinafter, differences from the first embodiment will be mainly described.

  As shown in FIG. 9, each phase (U-phase converter 301, V-phase converter 302, and W-phase converter 303) constituting the three-phase inverter has three power semiconductor modules 20 (PM1, PM2, PM3). Consists of.

  The power semiconductor modules PM1, PM2, and PM3 include a temperature sensor 31 that detects an element temperature (chip junction temperature) of a power semiconductor device inside the power semiconductor module, and temperature information obtained by the temperature sensor 31 is obtained by the control unit 304. Is input.

  The output terminals of the power semiconductor modules PM1 and PM2 connected in parallel are provided with a current sensor 32 that monitors the load current, and the load current information is input to the control unit 304.

  FIG. 10 shows a load current adjustment control flow of the power semiconductor modules PM1, PM2, and PM3 in the fourth embodiment.

  First, during the initial operation, the power semiconductor modules PM1, PM2, and PM3 are controlled so that the load currents of the power semiconductor modules PM1, PM2, and PM3 are equal.

  Next, in operation, the control unit 304 of the inverter 1030 determines the thermal resistance of the three power semiconductor modules PM1, PM2, and PM3 based on the temperature information and the load current information obtained by the temperature sensor 31 and the current sensor 32, respectively. calculate. Further, the control unit 304 compares the calculated current thermal resistance value with the initial thermal resistance value set in the control unit 304 in advance, and the thermal resistance increment value (current heat) in the three power semiconductor modules PM1, PM2, and PM3. Resistance value−initial thermal resistance value) is calculated. Here, the initial thermal resistance value may be similarly calculated by the control unit 304 during initial operation, or may be measured in advance by another means and set in the control unit 304. Moreover, you may use the thermal resistance value on specification as an initial thermal resistance value. The control unit 304 determines whether one of the thermal resistance increment values of the power semiconductor modules PM1, PM2, and PM3 is equal to or greater than a first specified value (specified value 1).

  When the thermal resistance increment value of at least one power semiconductor module becomes a specified value 1 or more due to long-term operation, that is, the thermal resistance inside the power semiconductor module due to thermal fatigue accompanying power cycle deteriorates (increases), When it becomes the specified value 1 or more (yes), the load current of the power semiconductor module in which the thermal resistance is deteriorated is reduced, and the operation shifts to the load current unbalance operation in which the load current of the other power semiconductor module is increased. Moreover, when it is not determined that the thermal resistance increment value of any power semiconductor module is equal to or greater than the specified value 1 (no), the load current equalization operation is continued.

  After shifting to the operation load current unbalanced operation, the thermal resistance increment values of the three power semiconductor modules PM1, PM2, and PM3 are compared, and the thermal resistance of the power semiconductor module having the largest thermal resistance increment value is most deteriorated. It is determined that FIG. 10 shows six typical cases (“thermal resistance PM1> PM2> PM3”, etc.) as determination results. In the following description, the gate drive voltage, the load current, and the element temperature of the power semiconductor module PMn (n = 1, 2, 3) are denoted as Vg (PMn), I_PMn, and Tj (PMn), respectively.

  For example, when the thermal resistance increment value of the power semiconductor module PM1 is larger than the thermal resistance increment value of the power semiconductor module PM2, and the thermal resistance increment value of the power semiconductor module PM2 is larger than the thermal resistance increment value of the power semiconductor module PM3. ("Thermal resistance PM1> PM2> PM3"), the control unit 304 reduces Vg (PM1) from the previous control period, and satisfies Vg (PM3)> Vg (PM2)> Vg (PM1). , Vg (PM1), Vg (PM2), and Vg (PM3) are controlled. Thereby, I_PM1, I_PM2, and I_PM3 are adjusted to satisfy I_PM3> I_PM2> I_PM1. Further, Tj (PM1), Tj (PM2), and Tj (PM3) are adjusted so that Tj (PM3) ≧ Tj (PM2) ≧ Tj (PM1). The same applies to other cases in FIG. 10 (such as “thermal resistance PM1> PM3> PM2”).

  Although not shown, the thermal resistance increment value of the power semiconductor module PM1 is larger than the thermal resistance increment value of the power semiconductor modules PM2 and PM3, and the thermal resistance increment value of the power semiconductor module PM2 and the power semiconductor module PM3 When the thermal resistance increment value is not equal to or greater than the specified value 1, the control unit 304 adjusts I_PM1 to be smaller than I_PM2 and I_PM3 by reducing Vg (PM1) from the previous control period, and Tj (PM1 ) May be adjusted to be smaller than Ti (PM2) and Tj (PM3). The thermal resistance increment value of the power semiconductor module PM2 is larger than the thermal resistance increment value of the power semiconductor modules PM1 and PM3, and the thermal resistance increment value of the power semiconductor module PM1 and the thermal resistance increment value of the power semiconductor module PM3 are defined. When the value is not 1 or more, or the thermal resistance increment value of the power semiconductor module PM3 is larger than the thermal resistance increment value of the power semiconductor modules PM1 and P2, and the thermal resistance increment value of the power semiconductor module PM1 and the power semiconductor module PM2 The same applies to the case where the thermal resistance increment value is not equal to or greater than the specified value 1.

  Furthermore, in the load current unbalanced operation, when the thermal resistance increment value of at least one power semiconductor module becomes a specified value 2 or more, that is, the thermal resistance of any of the power semiconductor modules PM1, PM2, and PM3 satisfies the system specifications. When it is deteriorated until it is not, it is determined that the power semiconductor module has failed.

  On the other hand, in the load current imbalance operation, while the thermal resistance increment value of each power semiconductor module is equal to or less than the specified value 2, the control unit 304 calculates the thermal resistance increment value of the three power semiconductor modules PM1, PM2, and PM3, Control is performed to reduce the load current of the power semiconductor module having a large thermal resistance increment.

  According to the present embodiment, even in the case where variations occur in thermal resistance degradation due to differences in initial characteristics and ambient temperature distribution of each module in a plurality of power semiconductor modules connected in parallel in the power converter, the thermal resistance Based on the incremental information, the load current of power semiconductor modules that tend to deteriorate is reduced, and control to suppress the progression of thermal fatigue is added to equalize the life of each power semiconductor module due to thermal fatigue. An early failure of the power semiconductor module can be avoided, and the life of the power converter resulting from the power semiconductor module can be extended.

  In addition, this invention is not limited to the Example mentioned above, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

  For example, the thermal resistance measurement means is not limited to the above-described means, and various known means can be applied.

DESCRIPTION OF SYMBOLS 20 ... Power semiconductor module 21, 22 ... Switching element 23, 24 ... Rectifier 25 ... Smoothing capacitor 31 ... Temperature sensor 32 ... Current sensor 101 ... Drive circuit 103 ... Delay circuit part 104 ... Gate voltage inclination variable circuit part 105 ... Gate voltage Variable circuit unit 106 ... interface (I / F) circuit unit 201 ... gate signal 301 ... U-phase converter 302 ... V-phase converter 303 ... W-phase converter 304 ... control unit 305 ... load current / voltage-loss data table 306 ... thermal resistance memory 307 ... thermal resistance calculation circuit 308 ... load current imbalance determination circuit 309 ... gate drive voltage adjustment circuit 502 ... AC terminal 1001 ... radiation fin 1002 ... metal base 1003 ... insulating substrate 1004 ... power semiconductor device 1005 ... resin Case 1030 ... Inverter

Claims (15)

A plurality of power semiconductor modules connected in parallel;
A control unit for controlling the plurality of power semiconductor modules;
In a power converter comprising:
The said control part reduces the load current of the power semiconductor module with the largest increment of thermal resistance among these power modules, The power converter device characterized by the above-mentioned. The power conversion device according to claim 1,
The said control part determines the magnitude | size of the increment of the said thermal resistance based on the measured value of thermal resistance, The power converter device characterized by the above-mentioned. The power conversion device according to claim 1,
The said control part determines the magnitude | size of the increment of the said thermal resistance based on the thermal resistance increment value which is the difference of the measured value of thermal resistance, and an initial thermal resistance value, The power converter device characterized by the above-mentioned. In the power converter device according to claim 2 or 3,
The said control part measures the said thermal resistance from the temperature information and power loss information regarding these power semiconductor modules, The power converter device characterized by the above-mentioned. The power conversion device according to claim 4,
The plurality of power semiconductor modules are placed on the fins,
The temperature information is acquired by a temperature sensor provided in each power semiconductor module and a temperature sensor provided in the fin,
The power loss information is obtained based on output current information obtained by a current sensor provided in each power semiconductor module and output voltage information of each power semiconductor module. The power conversion device according to claim 1,
When the controller determines that the increment of the thermal resistance of any of the plurality of power semiconductor modules is equal to or greater than a first specified value, the control unit reduces the load current of the power semiconductor module having the largest increment of the thermal resistance. The power converter characterized by doing. The power conversion device according to claim 6, wherein
The control unit determines the load current of the plurality of power semiconductor modules as the power semiconductor module when the increment of the thermal resistance of any of the plurality of power semiconductor modules is not determined to be greater than or equal to the first specified value. The power converter is controlled so that the load currents are equal. The power conversion device according to claim 6, wherein
The said control part increases the load current of another power semiconductor module, The power converter device characterized by the above-mentioned. The power conversion device according to claim 6, wherein
When the control unit determines that the increment of the thermal resistance of any of the plurality of power semiconductor modules is equal to or greater than a second specified value that is greater than the first specified value, the control unit executes control in an abnormal state. The power converter characterized by the above-mentioned. The power conversion device according to claim 1,
The said control part controls each load current so that the load current of the power semiconductor module with the largest increment of the said thermal resistance may become smaller than the load current of another power semiconductor module, The power converter device characterized by the above-mentioned. The power conversion device according to claim 1,
The said control part controls the load current of these power semiconductor modules according to the magnitude | size of the steady current of these power semiconductor modules, The power converter device characterized by the above-mentioned. The power conversion device according to claim 11,
The said control part controls the magnitude | size of the said stationary current with the peak value of the gate drive voltage given to these power semiconductor modules, The power converter device characterized by the above-mentioned. The power conversion device according to claim 11, wherein the control unit controls load currents of the plurality of power semiconductor modules such that switching currents of the power semiconductor modules are equal to each other. The power conversion device according to claim 13, wherein the control unit controls the switching current according to a slope of a voltage at a rising edge and a falling edge of the gate drive voltage applied to each power semiconductor module. . The power conversion device according to claim 12 or 14,
The said control part matches the timing of the said gate drive voltage given to each power semiconductor module, The power converter device characterized by the above-mentioned.

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