WO2020250445A1

WO2020250445A1 - Power converter, service life diagnosis device for semiconductor chip, and method for diagnosing service life of semiconductor chip

Info

Publication number: WO2020250445A1
Application number: PCT/JP2019/023754
Authority: WO
Inventors: 紀彦奥村
Original assignee: 三菱電機株式会社
Priority date: 2019-06-14
Filing date: 2019-06-14
Publication date: 2020-12-17
Also published as: JPWO2020250445A1; CN113939989B; JP6656501B1; CN113939989A

Abstract

This power converter (1) is equiped with a plurality of semiconductor chips mounted to constituent members by soldering, and controls the operation of one or more bridge circuits containing at least one series circuit electrically connecting in series a first semiconductor chip (IGBT(P)) and a second semiconductor chip (IGBT(P)) from the plurality of semiconductor chips to one another. The power converter (1) measures the electrical characteristics of the first and second semiconductor chips (IGBT(P) and IGBT(N)) in a state of being mounted to the actual machine, and calculates the thermal resistance of the heat-dissipating structure which includes the constituent members on the basis of the measured electrical characteristics. The power converter (1) diagnoses abnormalities or service life by deterioration in the first and second semiconductor chips (IGBT(P) and (IGBT(N)) by comparing the calculated thermal resistance with initial values.

Description

Power conversion device, semiconductor chip life diagnosis device, and semiconductor chip life diagnosis method

The present invention provides a power conversion device for diagnosing the life of a semiconductor chip equipped with a semiconductor switching element for power conversion (hereinafter, abbreviated as "semiconductor element"), a semiconductor chip life diagnosis device, and a semiconductor chip life diagnosis method. Regarding.

In Patent Document 1 below, in a power converter in which a plurality of semiconductor chips are mounted, the number of repetitions of the maximum output current value of the power converter in order to diagnose the life of the semiconductor chip such as thermal cycle life and power cycle life Is disclosed, and a technique for comparing the measured value with a predetermined reference value is disclosed.

Japanese Unexamined Patent Publication No. 2008-206217

However, the life of the semiconductor chip does not depend only on the number of repetitions of the maximum output current value of the power converter, but also on the degree of temperature change of each of the plurality of semiconductor chips mounted on the power converter. It is affected. For this reason, the conventional technique has a problem that accurate life diagnosis cannot be performed.

The present invention has been made in view of the above, and an object of the present invention is to obtain a power conversion device capable of more accurately diagnosing the life of a semiconductor chip.

In order to solve the above-mentioned problems and achieve the object, the power conversion device according to the present invention includes a mounting portion having a first semiconductor chip and a second semiconductor chip mounted on a heat radiating member by a bonding material, and a first. It includes a control unit that controls the operation of a bridge circuit including a series circuit unit in which the first semiconductor chip and the second semiconductor chip are electrically connected in series with each other. The control unit diagnoses the life of the first semiconductor chip based on the thermal resistance calculated based on the electrical characteristics of the first semiconductor chip.

According to the power conversion device according to the present invention, there is an effect that the life diagnosis of the semiconductor chip can be performed more accurately.

Block diagram showing the configuration of the power conversion device according to the first embodiment A circuit diagram showing a detailed configuration of the inverter circuit shown in FIG. The figure which shows typically the heat dissipation structure of a general semiconductor chip The figure which shows the example of the crack which occurred in the solder layer of the heat dissipation structure part shown in FIG. The figure which shows the example of the output characteristic of the insulated gate bipolar transistor (IGBT) which provides the explanation of the life diagnosis method in Embodiment 1. FIG. The figure which shows the example of the temperature characteristic of the IGBT provided in the explanation of the life diagnosis method in Embodiment 1. Circuit diagram of the main part to be used for the explanation of the life diagnosis method in the first embodiment. A time chart provided for explaining the life diagnosis method according to the first embodiment. The circuit diagram for one phase of the three-level inverter shown as the application target of the life diagnosis method in the first embodiment. A flowchart showing a processing procedure according to the life diagnosis method according to the first embodiment. A time chart provided for explaining the life diagnosis method according to the second embodiment. A flowchart showing a processing procedure according to the life diagnosis method according to the second embodiment. The figure which shows the example of the characteristic of the thermal resistance provided to the explanation of the life diagnosis method in Embodiment 3.

The power conversion device, the semiconductor chip life diagnosis device, and the semiconductor chip life diagnosis method according to the embodiment of the present invention will be described in detail with reference to the accompanying drawings below. The present invention is not limited to the following embodiments.

Embodiment 1.
FIG. 1 is a block diagram showing a configuration of the power conversion device 1 according to the first embodiment. As shown in FIG. 1, the power conversion device 1 includes a rectifier circuit 10, an inverter circuit 11, a smoothing capacitor 13, a control unit 14, and a gate drive circuit 15. The power conversion device 1 is a device that supplies AC power 18 as driving power to the electric motor 3 which is a load.

The rectifier circuit 10 rectifies the AC voltage applied from the AC power supply 2 and converts it into a DC voltage. An example of the rectifier circuit 10 is a full-wave rectifier circuit including six diodes connected in a full bridge. An inverter circuit 11 having a plurality of semiconductor chips 12 is connected to the output end of the rectifier circuit 10. The rectifier circuit 10 and the inverter circuit 11 are connected by a DC bus 16 on the high potential side and a DC bus 17 on the low potential side. A smoothing capacitor 13 is arranged between the DC bus 16 and the DC bus 17. The voltage between the DC bus 16 and the DC bus 17 is called the "bus voltage". The smoothing capacitor 13 serves to smooth the bus voltage and stabilize the bus voltage.

The inverter circuit 11 converts the DC voltage smoothed by the smoothing capacitor 13 into an AC voltage and applies it to the motor 3. The electric motor 3 is driven by the AC power 18 supplied from the inverter circuit 11.

The control unit 14 includes a processor 14a and a memory 14b. The processor 14a generates a drive signal 19 for controlling the semiconductor chip 12 of the inverter circuit 11. An example of the drive signal 19 is a pulse width modulation (PWM) signal. Although the details will be described later, the control unit 14 diagnoses the life of the semiconductor chip 12. A semiconductor element is mounted inside the semiconductor chip 12. An example of a semiconductor device is the illustrated IGBT. The semiconductor element may be provided with diodes connected in antiparallel.

The gate drive circuit 15 generates a drive voltage 20 based on the drive signal 19. The drive voltage 20 is a gate drive voltage for driving the semiconductor chip 12 of the inverter circuit 11.

The processor 14a may be referred to as a microprocessor, a microcomputer, a microcomputer, a CPU (Central Processing Unit), or a DSP (Digital Signal Processor).

The memory 14b stores a program read by the processor 14a, parameters referenced by the processor 14a, data obtained by processing of the processor 14a, and the like. The memory 14b is also used as a work area when the processor 14a performs arithmetic processing. The memory 14b is generally a non-volatile or volatile semiconductor memory such as a RAM (Random Access Memory), a flash memory, an EPROM (Erasable Project ROM), or an EEPROM (registered trademark) (Electrically EPROM).

Note that, in FIG. 1, the AC power supply 2 is a three-phase power supply, but the present invention is not limited to this. The AC power supply 2 may be a single-phase power supply. When the AC power supply 2 is a single-phase power supply, the rectifier circuit 10 is configured to match the single-phase power supply. An example of the electric motor 3 is a three-phase motor. When the electric motor 3 is a three-phase electric motor, the inverter circuit 11 also has a three-phase circuit configuration.

FIG. 2 is a circuit diagram showing a detailed configuration of the inverter circuit 11 shown in FIG. The inverter circuit 11 has legs 12A, legs 12B and legs 12C, as shown in FIG. The

legs

12A, 12B and 12C are connected in parallel to each other between the DC bus 16 and the DC bus 17. The leg 12A is a series circuit unit in which the semiconductor chip 12UP of the upper arm and the semiconductor chip 12UN of the lower arm of the U phase are electrically connected in series with each other. The leg 12B is a series circuit unit in which the semiconductor chip 12VP of the upper arm and the semiconductor chip 12VN of the lower arm of the V phase are electrically connected in series with each other. The leg 12C is a series circuit unit in which the semiconductor chip 12WP of the upper arm and the semiconductor chip 12WN of the lower arm of the W phase are electrically connected in series with each other. That is, the inverter circuit 11 is a bridge circuit including three legs which are a series circuit unit.

The semiconductor chip 12UP has a gate terminal 12a, a first terminal 12b, and a second terminal 12c. The gate terminal 12a is a terminal electrically connected to the gate electrode of the IGBT, and is a terminal to which a gate voltage for controlling the continuity of the IGBT is applied. The first terminal 12b is a terminal electrically connected to the source electrode of the IGBT, and is a terminal on the side where the current flowing through the IGBT flows out. The second terminal 12c is a terminal electrically connected to the drain electrode of the IGBT, and is a terminal on the side on which the current flowing through the IGBT flows. Although not shown in FIG. 2, it goes without saying that each of the other semiconductor chips 12UN, 12VP, 12VN, 12WP, and 12WN also has a gate terminal 12a, a first terminal 12b, and a second terminal 12c. ..

Further, in FIGS. 1 and 2, the electric motor 3 which is a load is a three-phase electric motor, but the present invention is not limited to this. The electric motor 3 may be a single-phase electric motor. When the motor 3 is a single-phase motor, a single-phase inverter circuit is used. The single-phase inverter circuit is a bridge circuit including two legs which are a series circuit unit.

Further, in FIGS. 1 and 2, the load is an electric motor, but the load is not limited to this. The load may be a rechargeable storage battery. When the load is a storage battery, a DCDC (Direct Current to Direct Current) converter is used instead of the inverter circuit 11. The minimum configuration of a DCDC converter is a half-bridge circuit with one leg.

Next, the necessity of performing a life diagnosis will be described with reference to FIGS. 3 and 4. FIG. 3 is a diagram schematically showing a heat dissipation structure of a general semiconductor chip. FIG. 4 is a diagram showing an example of cracks generated in the solder layer of the heat dissipation structure portion shown in FIG. In FIG. 4, the portion indicated by reference numeral 22 in FIG. 3 is not shown.

When the semiconductor chip 12 is a semiconductor component for electric power having a large calorific value, the semiconductor chip 12 generally has a structure mounted on a metal base as shown in FIG. In the example shown in FIG. 3, the semiconductor chip 12 is mounted on the insulating substrate 21 and fixed by being soldered to the wiring pattern 22 on the surface of the insulating substrate 21. A metal wire 23 is drawn from the semiconductor chip 12 and connected to another wiring pattern 24 on the insulating substrate 21. The insulating substrate 21 on which the semiconductor chip 12 is mounted is mounted on the metal base 25 and fixed by being soldered to the wiring pattern 26 on the back surface of the insulating substrate 21. As a result, the heat dissipation structure of the semiconductor chip 12 becomes a structure that is electrically connected to the metal base 25 via the solder layer 27 on the front surface of the insulating substrate 21 and the solder layer 28 on the back surface of the insulating substrate 21. .. In the first embodiment, the insulating substrate 21 and the metal base 25 are constituent members for mounting the semiconductor chip 12, and are also heat radiating members for cooling the temperature of the semiconductor chip 12. The structure in which the semiconductor chip 12 is joined to the heat radiating member by the solder layer 27 is called a mounting portion.

As described above, the semiconductor chip 12 is attached to constituent members such as the semiconductor chip 12 and the insulating substrate 21 by soldering. Therefore, when the semiconductor chip 12 is repeatedly energized, the solder layer 27 may have cracks 29 as shown in FIG. 4 due to the thermal stress generated between the semiconductor chips 12 and the constituent members. When the crack 29 is generated, the thermal conductivity is lowered and the heat dissipation performance is deteriorated. If the semiconductor chip 12 is continuously used in a state where the heat dissipation performance is deteriorated, the temperature rise rate of the semiconductor chip 12 increases, which may cause sudden damage. In order to prevent sudden damage to the semiconductor chip 12, it is desired to accurately diagnose the life of the semiconductor chip 12.

The life diagnosis of the semiconductor chip in the present embodiment refers to the life diagnosis of the semiconductor chip affected by the deterioration of the joint portion such as solder as described above.

Next, the main points of the life diagnosis and the method thereof (hereinafter, abbreviated as "life diagnosis method") in the first embodiment will be described with reference to the drawings of FIGS. 5 to 8. FIG. 5 is a diagram showing an example of the output characteristics of the IGBT used for the description of the life diagnosis method in the first embodiment. FIG. 6 is a diagram showing an example of the temperature characteristics of the IGBT used for the description of the life diagnosis method in the first embodiment. FIG. 7 is a circuit diagram of a main part for explaining the life diagnosis method according to the first embodiment. FIG. 8 is a time chart provided for explaining the life diagnosis method according to the first embodiment.

First, the prerequisites will be explained. FIG. 5 shows the output characteristics of the IGBT alone. The horizontal axis shows the collector-emitter voltage, and the vertical axis shows the collector current as a% value of the rated current. Hereinafter, the collector-emitter voltage is referred to as "VCE", and the collector current is referred to as "IC". As shown in the figure, the size of the IC in the IGBT changes depending on the VGE, which is the gate voltage applied between the emitter and the gate of the IGBT. As can be understood from the characteristics of FIG. 5, the size of the IC can be controlled by VGE. Further, the upper limit value of the IC can be controlled by VGE.

Further, in the output characteristics of FIG. 5, the region where the IC increases as the VCE increases is called the "saturation region". On the other hand, a region where IC is saturated and hardly increases even if VCE increases is called an "active region". Simply put, the region where the IC is not saturated with respect to the change in VCE is the "saturated region", and the region where the IC is saturated with respect to the change in VCE is the "active region". Although the details will be described later, in the first embodiment, the life diagnosis is performed using both the saturated region and the active region.

Further, the IGBT has the temperature characteristics as shown in FIG. The horizontal axis is the temperature of the semiconductor chip. The vertical axis shows the collector-emitter saturation voltage and the gate-emitter threshold voltage. Hereinafter, the temperature of the semiconductor chip is referred to as "chip temperature". Further, the saturation voltage between the collector and the emitter is described as "VCE (sat)", and the threshold voltage between the gate and the emitter is described as "VGE (th)".

In FIG. 6, the straight line represented by the solid line represents VCE (sat), and the straight line represented by the alternate long and short dash line represents VGE (th). As shown, both VCE (sat) and VGE (th) are properties that decrease with increasing chip temperature. When the slope of VCE (sat) is represented by "m1" and the slope of VGE (th) is represented by "m2", the absolute value of m1 is generally smaller than the absolute value of m2. It differs depending on the type of IGBT and varies depending on individual differences, but to give an example, it is about m1 = -2 mV / ° C. and m2 = -8 mV / ° C.

FIG. 7 shows a leg for one phase in the inverter circuit 11 as a configuration of a main part for explaining the life diagnosis method in the first embodiment. In FIG. 7, the IGBT of the upper arm is referred to as “IGBT (P)”, and the IGBT of the lower arm is referred to as “IGBT (N)”. The gate drive circuit 15 includes a drive circuit power supply 15a whose voltage can be changed and a drive circuit 15b. One set of the drive circuit power supply 15a and one set of the drive circuit 15b is provided for one IGBT. The drive circuit 15b applies a gate voltage to the IGBT. The magnitude of the gate voltage can be changed by the drive circuit power supply 15a. In FIG. 7, the physical quantities in each IGBT are expressed in alphabets, and the meanings of the respective notations are as follows.

VGE (P): Gate voltage applied to the IGBT (P) VGE (N): Gate voltage applied to the IGBT (N) VCE (P): Voltage generated between the emitter and collector of the IGBT (P) VCE (N) ): Voltage generated between the emitter and collector of the IGBT (N) IC (P): Current flowing through the IGBT (P) (collector current)
IC (N): Current flowing through the IGBT (N) (collector current)
VPN: DC voltage applied to the series circuit section of the IGBT (P) and IGBT (N) In the following description, it is assumed that the VPN is 311V obtained by rectifying the AC voltage having an effective value of 220V.

Next, the specific operation and control flow will be described using the time chart of FIG. FIG. 8 shows a flow of processing for calculating the thermal resistance of the IGBT (P). Each process shown in FIG. 8 is performed in a state of being mounted on the actual machine.

(I) Measurement of VCE (sat) 1 The IGBT (P) is turned on by VGE (P1) and the IGBT (N) is turned on by VGE (N1). Here, there is a relationship of VGE (P1)> VGE (N1) between VGE (P1) and VGE (N1). Further, VGE (P1) is a voltage that can be used in the saturation region of FIG. 5 in which the IC (P) is not saturated with the voltage of VPN. As shown in FIG. 5, the IC is controllable by VGE. Generally, VGE (P1) is about 15V. Further, VGE (N1) is a voltage at which a desired IC (N1) = IC (P1) can be obtained. An example of VGE (N1) is 10V. An example of IC (N1) (= IC (P1)) is a value of 40% of the rated current. The control unit 14 measures the VCE (P) in the IGBT (P) when the IC (P1) is flowing in the IGBT (P), and sets the measured value as the VCE (sat) 1. The VCE (P) is measured by using a voltage detector (not shown). In general, the voltage detector already installed in the inverter circuit 11 may be used. The same applies to the following description.

The measured value of VCE (sat) 1 is stored in the memory 14b of the control unit 14. VCE (sat) 1 is assumed to be about 2V, but is not limited to this. When VCE (sat) 1 is 2V, the collector-emitter voltage of VCE (N1), that is, the IGBT (N) is 309V.

(Ii) Power application Next, the IGBT (P) is turned on by VGE (P2), and the IGBT (N) is turned on by VGE (N2). At this time, there is a relationship of VGE (P2) <VGE (N2) between VGE (P2) and VGE (N2). Further, VGE (N2) is a voltage that can be used in the saturation region of FIG. 5 in which the IC is not saturated with the voltage of VPN. As shown in FIG. 5, the IC can be controlled by VGE. Generally, VGE (N2) is about 15V. Further, VGE (P2) is a voltage at which a desired IC (P2) can be obtained. An example of VGE (P2) is 9V. An example of IC (P2) (= IC (N2)) is a 70% value of the rated current. Further, in this power application phase, the power applied to the IGBT (P) is obtained by IC (P2) × VCE (P2).

(Iii) Measurement of VCE (sat) 2 In this measurement phase, power is applied to the IGBT (P) in the phase (ii) to consume the power, and then the IGBT (i) is subjected to the same conditions as the measurement phase (i). It is intended to measure the VCE (P) in P). The measurement conditions are the same as in (i), and the description here is omitted. The measured value is VCE (sat) 2. The value of VCE (sat) 2 is stored in the memory 14b of the control unit 14. Due to the characteristics of the IGBT, there is a relationship of VCE (sat) 1> VCE (sat) 2 between VCE (sat) 1 and VCE (sat) 2.

(Iv) Calculation of thermal resistance (Rth) In this phase, the thermal resistance Rth of the IGBT (P) is calculated using the following equation.
Rth = [(VCE (sat) 2-VCE (sat) 1) / m1] / (IC (P2) x VCE (P2)) ... (1)
In addition, m1 is the slope of the VCE (sat) curve described above.

(V) Diagnosis In this diagnostic phase, the thermal resistance calculated by the above equation (1) is compared with the initial value thermal resistance. The control unit 14 diagnoses that the IGBT (P) has reached the end of its life when the calculated value of the thermal resistance becomes larger than the first set value. Further, the control unit 14 diagnoses that the IGBT (P) is at an abnormal level when the calculated value of the thermal resistance becomes larger than the second set value. The second set value is a value smaller than the first set value. Further, the control unit 14 predicts the life of the IGBT (P) based on the difference between the first set value and the calculated value of the thermal resistance. The difference between the first set value and the calculated value of thermal resistance indicates the degree of deterioration. Therefore, it is possible to predict the life by grasping the transition of the difference.

In addition, in the above (i) to (v), the process of calculating and diagnosing the thermal resistance of the IGBT (P) has been described, but the IGBT (N) can also calculate and diagnose the thermal resistance by the same process. .. Specifically, the above processing may be performed by exchanging the relationships between the IGBT (P) and the IGBT (N).

Further, the processes (i) to (v) above are generally performed immediately before driving the electric motor 3, which is a load, but are not limited to this. Depending on the application, this may be performed during the operation of the electric motor 3 and during the drive stop period of the electric motor 3.

Further, when the inverter circuit 11 is a three-phase inverter circuit, all phases, that is, three phases may be diagnosed at one time. Alternatively, one phase may be diagnosed at a time, and all phases may be diagnosed three times.

Further, the inverter circuit 11 shown in FIG. 2 has a configuration in which the voltage applied to the electric motor 3 which is a load has two levels, but is not limited to this configuration. It can also be used in an inverter circuit in which the voltage applied to the electric motor 3 is three levels. FIG. 9 is a circuit diagram for one phase of the three-level inverter shown as an application target of the life diagnosis method in the first embodiment.

In the case of a three-level configuration, one leg has a configuration in which four semiconductor chips 12UP1, 12UP2, 12UN1, and 12UN2 are electrically connected in series. Therefore, one leg may be divided into two

series circuit units

12P and 12N, and the above-described processes (i) to (v) may be performed on each of the two

series circuit units

12P and 12N. Thereby, the life diagnosis of each semiconductor chip in the two

series circuit units

12P and 12N can be performed.

As described above, the series circuit portion in which the two semiconductor chips are connected in series is the minimum configuration, but the series circuit portion in which three or more semiconductor chips are connected in series is described above (i). (V) may be performed. For example, when a series circuit unit is formed by connecting the first, second, and third semiconductor chips in series, the first semiconductor chip is an IGBT (P) and the second and third semiconductor chips are IGBTs. By setting (N), the life diagnosis of the first semiconductor chip can be performed. Then, by sequentially switching the roles of the first, second, and third semiconductor chips, the life diagnosis of the second and third semiconductor chips can be performed.

Further, in the above, the case where the semiconductor element of the semiconductor chip 12 is an IGBT is illustrated, but the present invention is not limited to this. The above method can also be applied when the semiconductor element of the semiconductor chip 12 is a metal oxide semiconductor field effect transistor (MOSFET) of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Since the MOSFET is a voltage drive element controlled by the voltage applied to the gate terminal like the IGBT, the control is performed in consideration of the output characteristics shown in FIG. 5 and the temperature characteristics shown in FIG. 6 in the MOSFET. Therefore, the life diagnosis can be performed.

As described above, in the power conversion device according to the first embodiment, the electricity of the first and second semiconductor chips connected in series with each other in a state where the first and second semiconductor chips are mounted on the actual machine. The collector-emitter saturation voltage, which is one of the characteristics, is measured. In addition, the thermal resistance of the heat radiating member is calculated based on the measured collector-emitter saturation voltage. Then, by comparing the calculated thermal resistance with the initial value, an abnormality or a life due to deterioration of the first and second semiconductor chips is diagnosed. That is, the power conversion device according to the first embodiment performs abnormality diagnosis or life diagnosis of the semiconductor chip from the change in the electrical characteristics of the semiconductor element. As a result, it is possible to perform more accurate abnormality diagnosis or life diagnosis as compared with the prior art.

Further, the conventional technique represented by the above-mentioned Patent Document 1 is a method of predicting with a life curve, and has a drawback that machine machine variation cannot be taken into consideration. If the machine stand variation cannot be taken into consideration, the life is diagnosed in the direction of shortening the life in consideration of the risk, so that the accuracy is lowered. Further, the conventional technique is a method of performing a life diagnosis under one condition, and has a drawback that variation due to the usage of the power conversion device cannot be taken into consideration. On the other hand, the life diagnosis in the first embodiment is performed in a state of being mounted on an actual machine, and the electrical characteristics of the semiconductor chip are directly measured. Therefore, it is possible to include variations in the machine base and variations due to the usage of the power conversion device. As a result, it is possible to perform abnormality diagnosis or life diagnosis with higher accuracy than the prior art.

When there are a plurality of legs including the first and second semiconductor chips connected in series with each other, the target of abnormality diagnosis or life diagnosis can be changed by changing the leg for measuring the electrical characteristics.

Further, when it is determined that at least one of the semiconductor chips is at an abnormal level, it is preferable to reduce the frequency of the PWM signal for switching control of the semiconductor chip. By reducing the frequency of the PWM signal, it is possible to prevent the electric motor 3 from stopping unintentionally. Alternatively, the operating electric motor 3 can be safely stopped.

Further, it is preferable to output an alarm when it is determined that at least one of the semiconductor chips is at an abnormal level or has reached the end of its life. By outputting an alarm, it is possible to notify the operator or the administrator of the status of the power conversion device.

Further, when it is determined that at least one of the semiconductor chips has reached the end of its life, it is preferable to stop the control of the semiconductor chip. By stopping the control of the semiconductor chip, it is possible to prevent the electric motor 3 from being stopped unintentionally. Alternatively, the operating electric motor 3 can be safely stopped. Alternatively, it is possible to prevent the failure of the semiconductor chip from extending to other parts.

Next, a more generalized processing procedure in the life diagnosis method according to the first embodiment will be described. FIG. 10 is a flowchart showing a processing procedure according to the life diagnosis method according to the first embodiment. The processing of each of the following steps is performed under the control of the control unit 14.

In step S11, the gate voltage of the first value is applied to the gate terminal of the first semiconductor chip, and the gate voltage of the second value is applied to the gate terminal of the second semiconductor chip to the series circuit portion. The process of passing the current of the current value of 1 is performed.

In the process of step S11 described above, the series circuit unit means a circuit unit in which the first semiconductor chip and the second semiconductor chip are electrically connected in series with each other, and in the configuration of FIG. IGBTs (P) and IGBTs (N) correspond to this. The gate voltage of the first value corresponds to VGE (P1) in the time chart of FIG. The gate voltage of the second value corresponds to VGE (N1) in the time chart of FIG. The first current value corresponds to the IC (P1) and IC (N1) in the measurement phase of VCE (sat) 1 in the time chart of FIG.

In step S12, the first voltage applied to the first semiconductor chip when the current of the first current value flows through the series circuit unit is measured. That is, the first voltage is a voltage generated between the first terminal and the second terminal of the first semiconductor chip, and is an electrical characteristic of the first semiconductor chip. In addition, this electrical characteristic may be referred to as a "first characteristic".

In the process of step S12 above, the first voltage corresponds to VCE (sat) 1 in the time chart of FIG.

In step S13, after step S12, a third value gate voltage is applied to the gate terminal of the first semiconductor chip, and a fourth value gate voltage is applied to the gate terminal of the second semiconductor chip. A process of passing a current having a second current value through the series circuit unit is performed.

In the process of step S13 above, the gate voltage of the third value corresponds to VGE (P2) in the time chart of FIG. The gate voltage of the fourth value corresponds to VGE (N2) in the time chart of FIG. The second current value corresponds to the IC (P2) and IC (N2) in the time chart of FIG.

In step S14, after step S13, the gate voltage of the first value is applied to the gate terminal of the first semiconductor chip, and the gate voltage of the second value is applied to the gate terminal of the second semiconductor chip. A process of passing a current of a third current value through the series circuit unit is performed.

In the process of step S14 described above, the gate voltage of the first value is the VGE (P1) described above, and the gate voltage of the second value is the VGE (N1) described above. The third current value corresponds to the IC (P1) and IC (N1) in the VCE (sat) 2 measurement phase of the time chart of FIG.

In step S15, the second voltage generated between the first terminal and the second terminal when the current of the third current value flows through the series circuit portion is measured. The second voltage is an electrical characteristic of the first semiconductor chip and may be referred to as a "second characteristic".

In the process of step S15 above, the second voltage corresponds to VCE (sat) 2 in the time chart of FIG.

In step S16, the temperature characteristics of the first and second semiconductor chips, the measured value of the first voltage, the measured value of the second voltage, the second current value, and the second current value flow through the first semiconductor chip. The thermal resistance of the first semiconductor chip is calculated based on the voltage generated between the first terminal and the second terminal of the first semiconductor chip.

In the process of step S16 described above, the temperature characteristics of the first and second semiconductor chips correspond to the saturation voltage between the collector and the emitter of the IGBT in FIG. The voltage generated between the first terminal and the second terminal of the first semiconductor chip corresponds to VCE (P2) in the time chart of FIG.

In step S17, the abnormality or life of the first and second semiconductor chips is diagnosed by comparing the thermal resistance calculated in step S16 with the initial value.

As described above, the control unit 14 performs the life diagnosis and the abnormality diagnosis of the first and second semiconductor chips based on the change in the thermal resistance due to the current of the second current value flowing through the series circuit unit. The above processes from step S11 to step S17 are embodied in the form of a program and can be implemented in the control unit 14. This program is stored in the memory 14b as described above and read by the processor 14a. Then, the processing by this program is executed under the control of the processor 14a, and the above-mentioned life diagnosis and abnormality diagnosis are realized.

The life diagnosis and abnormality diagnosis functions of the control unit 14 may be configured as a life diagnosis device of the semiconductor chip separately from the power conversion function of the power conversion device 1. The life diagnosis device of the semiconductor chip may be configured inside the power conversion device 1, or may be configured as a separate device outside the power conversion device 1.

Although the life diagnosis and the abnormality diagnosis have been described as an example in the present embodiment, the life level may be set in a plurality of stages, and the time when the abnormality occurs may be set as the first stage life. By diagnosing the life in multiple stages, the user can appropriately determine the usage conditions or the end-of-use judgment according to the life level.

In the present embodiment, the case of solder as the bonding material has been described, but it goes without saying that other bonding materials containing Ag, Cu, etc. may be used.

Embodiment 2.
In the first embodiment, the case where the temperature characteristic of the first and second semiconductor chips is the saturation voltage between the collector and the emitter of the IGBT has been described. On the other hand, in the second embodiment, the case where the temperature characteristic of the first and second semiconductor chips is the threshold voltage between the gate and the emitter of the IGBT will be described.

FIG. 11 is a time chart provided for explaining the life diagnosis method according to the second embodiment. FIG. 11 shows a flow of processing for calculating the thermal resistance of the IGBT (P). As in FIG. 8, each process shown in FIG. 11 is performed in a state of being mounted on the actual machine.

(I) Measurement of VGE (th) 1 The IGBT (N) is turned on by the VGE (N1), and the VGE applied to the IGBT (P) is increased to allow the IC (P) to flow through the IGBT (P). The VGE (P) when P) becomes IC (P1) is measured. Whether or not the IC (P) becomes the set value IC (P1) is confirmed by using a current detector (not shown). In general, the current detector already installed in the inverter circuit 11 may be used. The same applies to the following description. In the circuit diagram of FIG. 7, the current detector may be arranged on the DC bus 16 on the high potential side or the DC bus 17 on the low potential side. Alternatively, in the leg composed of the IGBT (P) and the IGBT (N) in FIG. 7, between the DC bus 16 on the high potential side and the collector of the IGBT (P), or between the emitter of the IGBT (P) and the IGBT (P). ) May be arranged between the drive circuit 15b and the connection point on the low potential side. Alternatively, between the connection point on the low potential side of the drive circuit 15b in the IGBT (P) and the collector of the IGBT (N), or between the emitter of the IGBT (N) and the low potential side of the drive circuit 15b in the IGBT (N). It may be arranged between the connection point and the connection point of. Alternatively, it may be arranged between the connection point on the low potential side of the drive circuit 15b in the IGBT (N) and the DC bus 17 on the low potential side.

The control unit 14 sets the measured VGE (P) value to VGE (th) 1. The measured value of VGE (th) 1 is stored in the memory 14b of the control unit 14. Here, assuming that the VGE (P) when the IC (P) becomes the IC (P1) is VGE (P1), between VGE (P1) and VGE (N1), VGE (P1) <VGE ( There is a relationship of N1). The VGE (N1) is a voltage that can be used in the saturation region of FIG. 5 in which the IC (N) is not saturated with the VPN voltage. Generally, VGE (N1) is about 15V. The IC (P1) is a specified current and assumes a current of 1 [A] or less, but is not limited to this. Further, VCE (N1) is assumed to be about 2V, but is not limited to this. When the VCE (N1) is 2V, the VCE (P2), which is the collector-emitter voltage of the IGBT (P), becomes 309V.

(Ii) Power application Next, while maintaining the VGE (N1) applied to the gate terminal of the IGBT (N) and keeping the IGBT (N) on, the VGE (P2) is applied to the gate terminal of the IGBT (P). Is applied to pass the current of IC (P2) (= IC (N2)) through the IGBT (P). At this time, there is a relationship of VGE (P2) <VGE (N1) between VGE (P2) and VGE (N1). VGE (P2) is a voltage at which a desired IC (P2) can be obtained. An example of VGE (P2) is about 9 [V]. Further, the IC (P2) (= IC (N2)) is a current in the range of about 5 to 10 A. In this power application period, the power applied to the IGBT (P) is obtained by IC (P2) × VCE (P2). Note that FIG. 11 illustrates a case where there is a relationship of IC (P1) <IC (P2) between IC (P1) and IC (P2), but the present invention is not limited to this example, and IC ( The relationship may be P1) ≧ IC (P2). That is, the magnitude relationship between the IC (P1) and the IC (P2) does not matter. Further, FIG. 11 illustrates a case where there is a relationship of VGE (P2)> VGE (th) 1 between VGE (P2) and VGE (th) 1 measured in the phase (i). However, the relationship is not limited to this example, and the relationship may be VGE (P2) ≤ VGE (th) 1. That is, the magnitude relationship between VGE (P2) and VGE (th) 1 does not matter.

(Iii) Measurement of VGE (th) 2 In this measurement phase, power is applied to the IGBT (P) in the phase (ii) to consume the power, and then the IGBT (i) is subjected to the same conditions as the measurement phase (i). It is intended to measure the VGE (P) in P). The measurement conditions are the same as in (i), and the description here is omitted. The measured value is VGE (th) 2, and the value of VGE (th) 2 is stored in the memory 14b of the control unit 14. Due to the characteristics of the IGBT, there is a relationship of VGE (th) 1> VGE (th) 2 between VGE (th) 1 and VGE (th) 2. Further, FIG. 11 illustrates a case where there is a relationship of VGE (P2)> VGE (th) 2 between VGE (P2) and VGE (th) 2 measured in the phase (i). However, the relationship is not limited to this example, and the relationship may be VGE (P2) ≤ VGE (th) 2. That is, the magnitude relationship between VGE (P2) and VGE (th) 2 does not matter.

(Iv) Calculation of thermal resistance (Rth) In this phase, the thermal resistance Rth of the IGBT (P) is calculated using the following equation.
Rth = [(VGE (th) 2-VGE (th) 1) / m2] / (IC (P2) x VCE (P2)) ... (2)
Note that m2 is the slope of the VGE (th) curve described above.

(V) Diagnosis In this diagnostic phase, the thermal resistance calculated by the above equation (2) is compared with the initial value thermal resistance. The control unit 14 diagnoses that the IGBT (P) has reached the end of its life when the calculated value of the thermal resistance becomes larger than the third set value. Further, the control unit 14 diagnoses that the IGBT (P) is at an abnormal level when the calculated value of the thermal resistance becomes larger than the fourth set value. The fourth set value is smaller than the third set value. Further, the control unit 14 predicts the life of the IGBT (P) based on the difference between the third set value and the calculated value of the thermal resistance. The first set value used in the first embodiment may be used instead of the third set value. Further, instead of the fourth set value, the second set value used in the first embodiment may be used.

Note that the method of the second embodiment can also be used for a three-level inverter circuit as in the first embodiment. Further, the method of the second embodiment can be applied to the case where the semiconductor element of the semiconductor chip 12 is a MOSFET, as in the first embodiment.

As described above, the power conversion device according to the second embodiment is one of the electrical characteristics of the first and second semiconductor chips in a state where the first and second semiconductor chips are mounted on the actual machine. Measure the gate-emitter threshold voltage. In addition, the thermal resistance of the heat dissipation structure including the constituent members is calculated based on the measured threshold voltage between the gate and the emitter. Then, by comparing the calculated thermal resistance with the initial value, an abnormality or a life due to deterioration of the first and second semiconductor chips is diagnosed. That is, the power conversion device according to the second embodiment performs abnormality diagnosis or life diagnosis of the semiconductor chip from the change in the electrical characteristics of the semiconductor element. As a result, it is possible to perform more accurate abnormality diagnosis or life diagnosis as compared with the prior art.

Further, the life diagnosis in the second embodiment is performed in a state of being mounted on an actual machine, and the electrical characteristics of the semiconductor chip are directly measured. Therefore, it is possible to include variations in the machine base and variations due to the usage of the power conversion device. As a result, it is possible to perform abnormality diagnosis or life diagnosis with higher accuracy than the prior art.

Next, a more generalized processing procedure in the life diagnosis method according to the second embodiment will be described. FIG. 12 is a flowchart showing a processing procedure according to the life diagnosis method according to the second embodiment. The processing of each of the following steps is performed under the control of the control unit 14.

In step S21, the gate voltage of the first value for conducting the second semiconductor chip is applied to the gate terminal of the second semiconductor chip, and the gate voltage applied to the gate terminal of the first semiconductor chip is increased. A process is performed in which a current is passed through the series circuit section, and the first voltage applied to the gate terminal of the first semiconductor chip when the current flowing through the series circuit section becomes the first current value is measured.

In the process of step S21 described above, the series circuit unit means a circuit unit in which the first semiconductor chip and the second semiconductor chip are electrically connected in series with each other, and in the configuration of FIG. IGBTs (P) and IGBTs (N) correspond to this. The gate voltage of the first value corresponds to VGE (N1) in the time chart of FIG. The first current value corresponds to the IC (P1) in the measurement phase of VGE (th) 1 in the time chart of FIG.

In step S22, after step S21, the gate voltage of the first value applied to the gate terminal of the second semiconductor chip is maintained, and the gate voltage of the second value is maintained at the gate terminal of the first semiconductor chip. Is applied to pass a current of a second current value through the series circuit unit.

In the process of step S22 above, the gate voltage of the first value is the VGE (N1) described above, and the gate voltage of the second value corresponds to the VGE (P2) in the time chart of FIG. The second current value corresponds to the IC (P2) and IC (N2) in the time chart of FIG.

In step S23, after step S22, the gate voltage of the first value applied to the gate terminal of the second semiconductor chip is maintained, and the application of the gate voltage to the gate terminal of the first semiconductor chip is cut off. Processing is performed.

In the process of step S23 described above, the gate voltage of the first value is VGE (N1) described above.

In step S24, after step S23, the gate voltage of the first value applied to the gate terminal of the second semiconductor chip is maintained, and the gate voltage applied to the gate terminal of the first semiconductor chip is increased. A current is passed through the series circuit section, and the second voltage applied to the gate terminal of the first semiconductor chip when the current flowing through the series circuit section becomes the first current value is measured.

In the process of step S24, the gate voltage of the first value is the above-mentioned VGE (N1), and the gate voltage of the second value is the above-mentioned VGE (P2). The first current value is the IC (P1) described above.

In step S25, the temperature characteristics of the first and second semiconductor chips, the measured value of the first voltage, the measured value of the second voltage, the second current value, and the current of the second current value to the first semiconductor chip. The thermal resistance of the first semiconductor chip is calculated based on the voltage generated between the first terminal and the second terminal of the first semiconductor chip when the current is applied.

In the process of step S25 above, the temperature characteristics of the first and second semiconductor chips correspond to the threshold voltage between the gate and emitter of the IGBT in FIG. The first terminal is a terminal on the side where the first current flows out, and corresponds to 12b in the semiconductor chip 12UP of FIG. The second terminal is a terminal on the side where the first current flows, and corresponds to 12c in the semiconductor chip 12UP of FIG. The voltage generated between the first terminal and the second terminal of the first semiconductor chip corresponds to VCE (P2) in the time chart of FIG.

In step S26, the abnormality or life of the first and second semiconductor chips is diagnosed by comparing the thermal resistance calculated in step S25 with the initial value.

The above processes from step S21 to step S26 are embodied in the form of a program and can be implemented in the control unit 14. This program is stored in the memory 14b as described above and read by the processor 14a. Then, the processing by this program is executed under the control of the processor 14a, and the above-mentioned life diagnosis and abnormality diagnosis are realized.

Embodiment 3.
FIG. 13 is a diagram showing an example of the characteristics of thermal resistance provided for the description of the life diagnosis method in the third embodiment. Specifically, FIG. 13 shows an example of thermal resistance characteristics in the heat dissipation structure shown in FIG. The horizontal axis represents time, and the vertical axis represents the thermal resistance of the heat-dissipating structure portion shown in FIG. 3, including the metal base. Thermal resistance is a physical quantity that expresses the difficulty of transmitting temperature. As a unit of thermal resistance, "° C./W" is generally used. The thermal resistance shown in FIG. 13 indicates the temperature difference when the semiconductor chip 12 consumes 1 W of electric power in the heat dissipation structure portion shown in FIG. The temperature difference referred to here is the difference between the temperature of the semiconductor chip 12 and the ambient temperature.

In the heat dissipation structure of FIG. 3, the heat generated by the semiconductor chip 12 is conducted over time. Therefore, the value of thermal resistance is a function of time as shown in FIG. According to the example of FIG. 13, it increases with time up to about 0.3 s, and becomes a flat characteristic after 0.3 s. In the heat dissipation structure of FIG. 3, it is considered that the influence of the heat generated by the semiconductor chip 12 exceeds the solder layer 28 on the back surface of the insulating substrate 21 and reaches the metal base 25 in the flat characteristic portion in FIG. .. On the other hand, in FIG. 13, it is considered that the influence of the heat generated by the semiconductor chip 12 does not reach the solder layer 28 in the characteristic portion that increases linearly. Considering these characteristics, the heat radiating member that affects the life of the semiconductor chip 12 by controlling the application time (hereinafter, referred to as “power application time”) in the power application phase shown in FIGS. 8 and 11. The structural diagnostic site can be changed.

Based on the above points, in the life diagnosis according to the third embodiment, the power application time for causing the semiconductor chip 12 to consume power is controlled. Specifically, in the flowchart of FIG. 10, the power application time in step S13 is made shorter than the first time. In the flowchart of FIG. 12, the power application time in step S22 is shorter than the first time. In other words, the power application is stopped before the first time elapses. By making the power application time shorter than the first time, cracks in the solder layer 27 on the surface of the insulating substrate 21 can be diagnosed. In the case of the example of thermal resistance shown in FIG. 13, about 0.03 s is set as the first time.

Further, in the flowchart of FIG. 10, the power application time in step S13 is made longer than the second time. In the flowchart of FIG. 12, the power application time in step S22 is made longer than the second time. In other words, the power application is stopped after the second time has elapsed. The second time is longer than the first time. In the case of the example of thermal resistance shown in FIG. 13, about 0.4 s is set as the second time.

The second diagnostic process of making the power application time longer than the second time is used in combination with the first diagnostic process of making the power application time shorter than the first time. The state of the solder layer 27 on the surface of the insulating substrate 21 can be diagnosed from the first diagnostic result obtained by the first diagnostic process. Further, the state of the solder layer 28 on the back surface of the insulating substrate 21 can be diagnosed based on the first diagnosis result and the second diagnosis result obtained by the second diagnosis process.

As described above, in the life diagnosis according to the third embodiment, the power application time for causing the semiconductor chip to consume power is controlled. This makes it possible to change the structural diagnostic site in the heat dissipation structure including the component on which the semiconductor chip is mounted.

The configuration shown in the above embodiment shows an example of the content of the present invention, can be combined with another known technique, and is configured without departing from the gist of the present invention. It is also possible to omit or change a part of.

1 power converter, 2 AC power supply, 3 electric motor, 10 rectifier circuit, 11 inverter circuit, 12, 12UN, 12UN 1, 12UN 2, 12UP, 12UP1, 12UP2, 12VN, 12VP, 12WN, 12WP semiconductor chip, 12A, 12B, 12C leg , 12N, 12P series circuit unit, 12a gate terminal, 12b first terminal, 12c second terminal, 13 smoothing capacitor, 14 control unit, 14a processor, 14b memory, 15 gate drive circuit, 15a drive circuit power supply, 15b drive circuit, 16, 17 DC bus, 18 AC power, 19 drive signal, 20 drive voltage, 21 insulation board, 22, 24, 26 wiring pattern, 23 wires, 25 metal base, 27, 28 solder layer, 29 cracks.

Claims

A mounting portion having a first semiconductor chip and a second semiconductor chip mounted on a heat radiating member by a bonding material,
A control unit for controlling the operation of a bridge circuit including a series circuit unit in which the first semiconductor chip and the second semiconductor chip are electrically connected in series with each other is provided.
The control unit
A power conversion device characterized in that the life of the first semiconductor chip is diagnosed based on the thermal resistance calculated based on the electrical characteristics of the first semiconductor chip.
The electrical characteristic is a first voltage generated in the first semiconductor chip when a current having a first current value flows through the series circuit unit.
The first aspect of the present invention is characterized in that the control unit diagnoses the life of the first semiconductor chip based on a change in the thermal resistance due to a current having a second current value flowing through the series circuit unit. The power converter described.
The first aspect of claim 1, wherein the electrical characteristic is a gate voltage applied to the gate terminal of the first semiconductor chip when the current flowing through the series circuit portion becomes the first current value. Power converter.
The second aspect of the present invention is characterized in that the structural diagnostic site of the heat radiating member, which affects the life of the first semiconductor chip, is changed by controlling the time for passing the current of the second current value. The power converter described.
The power conversion device according to any one of claims 1 to 4, wherein the bridge circuit is a three-phase inverter circuit including three legs.
The present invention according to any one of claims 1 to 5, wherein when it is determined that the life of the first semiconductor chip is at an abnormal level, the frequency of the pulse width modulation signal for controlling the first semiconductor chip is made smaller. Power converter.
The power conversion device according to any one of claims 1 to 6, wherein when it is determined that the first semiconductor chip has reached the end of its life, control of the first semiconductor chip is stopped.
The power conversion device according to any one of claims 1 to 7, which outputs an alarm when it is determined that the first semiconductor chip is at an abnormal level or has reached the end of its life.
The power conversion device according to any one of claims 1 to 8, wherein the life of the first semiconductor chip is predicted based on the transition of deterioration of the first semiconductor chip.
The first and second semiconductor chips are electrically connected to a bridge circuit including at least one series circuit unit in which the first semiconductor chip and the second semiconductor chip are electrically connected in series with each other. It is a semiconductor chip life diagnosis device that diagnoses the life of the first semiconductor chip in the state of being.
The first characteristic which is the electrical characteristic of the first semiconductor chip when the current of the first current value flows through the series circuit part and the current of the first current value flows through the series circuit part. After the measurement and the measurement of the first characteristic, a current having a second current value is passed through the series circuit section, and then a current having a third current value is passed through the series circuit section, and the series circuit section is subjected to the measurement. The second characteristic, which is the electrical characteristic of the first semiconductor chip when a current having a third current value flows, is measured, and the second characteristic is based on the first characteristic and the second characteristic. A device for diagnosing a life of a semiconductor chip, which comprises calculating the thermal resistance of the first semiconductor chip and diagnosing an abnormality or a life of the first semiconductor chip by comparing the calculated thermal resistance with an initial value.
It is applied to a bridge circuit including at least one series circuit unit in which the first semiconductor chip and the second semiconductor chip are electrically connected in series with each other, and the first and second semiconductor chips are electrically connected to each other. A semiconductor chip life diagnosis method for diagnosing the life of the first semiconductor chip in a connected state.
The first step of passing the current of the first current value through the series circuit section,
A second step of measuring the electrical characteristics of the first semiconductor chip when a current of the first current value flows through the series circuit unit, and
After the second step, a third step of passing a current of a second current value through the series circuit unit, and
After the third step, a fourth step of passing a current of a third current value through the series circuit unit, and
A fifth step of measuring the electrical characteristics of the first semiconductor chip when a current of the third current value flows through the series circuit unit, and
The first semiconductor chip is based on the electrical characteristics of the first semiconductor chip measured in the second step and the electrical characteristics of the first semiconductor chip measured in the fifth step. The sixth step to calculate the thermal resistance and
The seventh step of diagnosing the abnormality or life of the first semiconductor chip by comparing the thermal resistance calculated in the sixth step with the initial value,
A method for diagnosing the life of a semiconductor chip including.
The method for diagnosing the life of a semiconductor chip according to claim 11, wherein the second current value is larger than the first current value and the third current value.
The method for diagnosing the life of a semiconductor chip according to claim 11 or 12, wherein the third step includes a process of controlling the time for passing a current having the second current value in the series circuit unit.