JP4827105B2 - Video signal conversion method - Google Patents

Description

  The present invention relates to a liquid crystal display (LCD), and more specifically to an LCD (LIQUID CRYSTAL DISPLAY WITH DISPLAY MODE CONVERSION FUNCTION) having a display mode conversion function.

  As shown in FIG. 13, an active matrix liquid crystal display device in which each pixel is individually blinked (ON / OFF) by a switching element corresponding to each pixel (pixcl) is provided with an LCD controller 20 and an LCD panel 30. Including.

The LCD panel 30 includes an LCD driving device 40. Also, LCD controller 20 converts the analog color signals supplied from the host 10 such as a personal computer into a digital color signal to generate a horizontal output signal H _out and the dot clock signal Dclk. The digital color signal, the dot clock signal and the horizontal output signal respectively output from the LCD control device 20 are provided to an LCD drive circuit 40 mounted in the LCD panel 30.

As apparent from FIG. 14, the conventional LCD controller 20 includes a PLL circuit 21 that receives a horizontal synchronization signal H _sync (horizontal synchronous signal) and generates a horizontal output signal H _out and a dot clock signal Dclk; It includes an ADC circuit 22 that converts analog R (red), G (green), and B (blue) signals provided from the host into digital R, G, and B signals and provides them to the LCD drive circuit 40, respectively. Yes. The horizontal output signal _Hout is a signal corresponding to the horizontal synchronization signal _Hsync , and the frequency thereof is the same as that of the horizontal synchronization signal _Hsync .

Although the polarity of the horizontal synchronizing signal H _sync input to the PLL circuit 21 may change depending on the characteristics of the host, the PLL circuit 21 outputs a horizontal output signal H _out having a predetermined polarity.

For example, in an LCD having a drive circuit 40 which operates in synchronism with the horizontal output signal H _out of negative polarity (negatives polarity), it is provided a horizontal synchronizing signal H _sync of the positive polarity (positives polarity) from the host to the PLL circuit 21 However, the PLL circuit 21 provides a horizontal output signal H _out having a negative polarity to the LCD drive circuit 40. As is well known, the PLL circuit 21 includes a phase detector, a VCO (Voltage Controlled Oscillator), a divider, and an output generator.

  In general, the LCD supports a single display mode. For example, only one of VGA (Video Graphics Array), SVGA (Super VGA), or XGA (Extended Graphics Array) mode is supported.

  Therefore, for example, when a signal for a VGA mode with a total resolution of 800 × 449 is provided to an LCD that supports an XGA mode with a total resolution of 1344 × 806, as shown in FIG. The video is displayed only in a part of the area A on the screen, and the video is not displayed in the other area B. The same applies when an SVGA mode signal with a total resolution of 1056 × 628 is provided to an XGA LCD.

  Thus, conventionally, when a low-resolution display mode signal is provided from a host that supports a low-resolution display mode, and when the LCD supports a high-resolution display mode, the video is displayed. There is a problem in that it is displayed only on a part of the LCD screen.

  Accordingly, an object of the present invention is to provide an LCD capable of displaying an image on the entire LCD screen even when a display mode signal having a resolution lower than that of the LCD display mode is input from a host.

  Another object of the present invention is to provide an LCD controller having a function of converting a low-resolution display mode signal from a host into a high-resolution display mode signal supported by the LCD.

In order to achieve the above object, according to the video signal conversion method of the present invention, a liquid crystal display that converts a first display signal input from a host into a second display signal that displays an image on the entire screen of the liquid crystal display panel. In the video signal conversion method of the apparatus, the liquid crystal display for detecting an input resolution mode of the first display signal, the input resolution mode, and an image displayed on the entire screen of the liquid crystal display panel If the input resolution mode and the display resolution mode are different in the step of comparing the display resolution mode of the panel and the step of comparing, the first display signal having the input resolution mode and the first frame rate is obtained. Converting to the second display signal having the display resolution mode and a second frame rate;
Here, the input resolution mode includes a first horizontal dot number, a first dot clock frequency, a first line number, and a first horizontal synchronization signal frequency, and the display resolution mode includes a second horizontal dot number and a second horizontal dot number. Including a dot clock frequency, a second number of lines, and a second horizontal synchronization signal frequency;
The step of converting the first display signal into the second display signal includes three first display signals for each first horizontal dot signal having the first horizontal dot number according to the first dot clock frequency. Sequentially writing (writing) to any one of the line memories having a horizontal capacity equal to the first horizontal dot number, and selectively from among the three line memories that have not been written. The step of reading out the first horizontal dot signal according to the second dot clock frequency in an overlapping manner, and selectively reading out the first horizontal dot signal as the second display signal according to the second dot clock frequency. An output stage, and
The selective overlapping readout of the first horizontal dot signal is performed by the number of times of the difference between the second line number and the first line number, and the selective overlapping output of the read first horizontal dot signal is The second frame rate is made to coincide with the first frame rate by overlapping the number of times of the difference between the second horizontal dot number and the first horizontal dot number .

Preferably, the first display signal includes the first horizontal synchronization signal and a first vertical synchronization signal having a frequency equal to the first frame rate, and detecting the input resolution mode of the first display signal. Is determined using the first horizontal synchronizing signal and the first vertical synchronizing signal.

Preferably, the first display signal is an analog signal, and the second display signal is a digital signal .

Preferably, the display resolution mode is a maximum resolution supported by the liquid crystal display panel .

  Since the liquid crystal display device of the present invention is configured as described above, an image can be displayed on the entire LCD screen even if a mode signal having a resolution lower than the mode resolution supported by the LCD is input to the LCD. .

  Hereinafter, embodiments of an LCD control device according to the present invention will be described in detail with reference to the accompanying drawings.

First, when a VGA mode signal is input to the LCD controller of the present invention, the frequency of the horizontal sync signal H _{sync and} the frequency of the dot clock signal Dclk are shown in Table 1 while keeping the frequency of the vertical sync signal V _sync the same. Increase by a factor of 0.6 as shown. Thereby, even if the input signal is in the VGA mode, the image on the LCD screen can be displayed with almost the resolution of the XGA mode.

  The resolution in Table 1 indicates the active resolution, and the value in () indicates the total resolution.

  As shown in Table 1, for example, the resolution of 640 × 480 is converted to the resolution of 1024 × 768, so the resolution before conversion: resolution after conversion = 1: 1.6. According to this conversion method, color R, G, B signals for five lines from the host are converted into color R, G, B signals for eight lines.

Next, when the SVGA mode signal is input to the LCD controller of the present embodiment, the frequency of the vertical synchronization signal V _sync remains the same, and the frequency of the horizontal synchronization signal H _{sync and} the frequency of the dot clock signal Dclk are set as follows. Increase by about 0.25 times as shown in Table 2. As a result, even if the input signal is an SVGA mode signal, the video on the LCD screen can be displayed with almost the resolution of the XGA mode. This is shown in FIG.

  The resolution in Table 2 indicates the normal resolution, and the value in () indicates the total resolution.

  As shown in Table 2, for example, the resolution of 800 × 600 is converted to the resolution of 1000 × 750, so the resolution before conversion: resolution after conversion = 1: 1.28. However, in this case, for the convenience of conversion, the resolution before conversion: resolution after conversion = 1: 1.25. According to this conversion method, color signals for four lines from the host are converted into color signals for five lines. In other words, in the present invention, the resolution of the input signal is increased by conversion so that a full screen image of the LCD can be displayed even when a low-resolution signal is input. This is achieved by increasing the number of analog input signals.

  FIG. 2 shows a circuit configuration of the LCD control device of the present invention for converting a VGA or SVGA mode signal into an XGA mode signal.

Referring to FIG. 2, the horizontal synchronization signal H _sync and the vertical synchronization signal V _sync output from the host are input to the microcomputer 100. The microcomputer 100 discriminates a display mode (hereinafter referred to as “host support display mode”) supported by the host from the horizontal synchronization signal H _sync and the vertical synchronization signal V _sync and displays the first and second mode displays indicating the result. Signals MD1 and MD2 are generated.

  When the host support display mode is the SVGA mode, the microcomputer 100 outputs the high-level first mode display signal MD1 and the high-level second mode display signal MD2, and the host support display mode is the VGA mode. The low-level first mode display signal MD1 and the high-level second mode display signal MD2 are output. In addition, when the host support display mode is the XGA mode, the microcomputer 100 outputs a low-level second mode display signal MD2. Based on the change in the output signal, the host support display mode is determined, and the rate of dot clock signal increase to be performed later is made appropriate.

Further, the microcomputer 100 indicates the pulse width of the first data signal TA indicating the number of dots per cycle of the horizontal output signal _Hout which is a horizontal synchronization signal for the XGA mode and the horizontal output signal _Hout. A second data signal PW is provided.

  The dot clock generation circuit 200 includes two PLL circuits 210 and 220. The PLL circuits 210 and 220 receive a write dot clock signal (WDclk) and a read dot clock signal (R Dclk) for a memory write operation and a read operation. Each occurs.

Horizontal output generation circuit 300 generates the horizontal output signal H _out based the first and second data signal TA provided from the vertical synchronizing signal V _sync and microcomputer 100 which is provided by the host, the PW. At this time, the horizontal output signal H _out horizontal synchronizing signal: generating in synchronism with (H _sync hereinafter referred to as 'H _in').

  As shown in FIG. 2, the apparatus of the present invention includes a memory 400 including three memory blocks 410a, 410b, 410c and an output selection unit 420 corresponding to R, G, and B signals, respectively. Each of the memory blocks 410a, 410b, and 410c includes at least three line memories. The reason why the number of line memories is three or more is that a memory for performing an entry operation at a certain moment, a memory for performing a read operation, and a memory on standby are necessary to increase the output signal. This point will be discussed in detail later.

The output of the horizontal synchronizing signal H _in the dot clock generator circuit 200 and the horizontal output generating circuit 300 is provided to the memory control circuit comprising a memory management circuit 500, the memory select control circuit 600 and the flag circuit 700. The memory control circuits 500, 600, and 700 are supplied with the horizontal synchronizing signal H _in and the writing dot clock signal WDclk, thereby controlling the writing operation of the memory 400. Furthermore, the horizontal output signal H _out and read the dot clock signal R Dclk inputted memory control circuit 500, 600, and 700, thereby reading operation of the memory 400 is controlled.

  The flag circuit 500 provides a flag signal for designating a line memory in which a writing operation and a reading operation are performed in a predetermined order in each memory block.

The memory selection control circuit 600 prevents the line operation and the read operation from being performed at the same time in any line memory of each memory block, and selects the line memory for performing the write operation and the read operation.
Sel and RSel are provided.

  The memory management circuit 700 receives instructions from the memory selection control circuit 600 and manages memory access as entry / read operations in the line memory in each memory block.

  Next, embodiments of the LCD control device according to the present invention will be described in more detail with reference to the accompanying drawings.

  As shown in FIG. 2, the memory 400 includes an output selection circuit 420 including three memory blocks 410a, 410b, and 410c and three 3 × 1 multiplexers 420a, 420b, and 420c corresponding to the memory blocks 410a, 410b, and 410c, respectively. ing.

  FIG. 3 shows a detailed configuration of the memory blocks 410a, 410b, and 410c, the multiplexers 420a, 420b, and 420c, and the memory management circuit 700 shown in FIG. The other two memory blocks not shown in FIG. 3 are also connected to the memory management circuit 700 in the same manner as the memory blocks shown in the drawing.

  As is apparent from FIG. 3, each of the memory blocks 410a, 410b, and 410c includes three line memories LM0, LM1, and LM2. Each line memory has a storage capacity of at least 1344 words × 8 bits.

  Next, FIG. 4 shows an embodiment of the output selection circuit 420 shown in FIG. As is apparent with reference to FIG. 4, the three input terminals of each of the three 3 × 1 multiplexers 420a, 420b, and 420c are connected to the data output ports of the line memories LM0, LM1, and LM2 in each memory block ( (Not shown).

Each multiplexer selects any one of data input from the line memories LM0, LM1, and LM2 of each memory block in response to the read memory selection signals R Sel0 and R Sel1 provided from the memory selection control circuit 600. And output. The outputs R _out , G _out , and B _out of the multiplexers 420a, 420b, and 420c are provided to an LCD driving circuit.

  Reference is again made to FIG. The memory management circuit 700 includes an entry / read control unit 710, an address generation unit 720, an address selection unit 730, and a dot clock selection unit 740. The write / read controller 710 controls the write and read operations performed in the line memory of each memory block in response to the write memory selection signal WSel provided from the memory selection control circuit 600.

Address generator 720 generates a fill address W Add and read address R Add for a read operation and the memory fill operation of the memory in response to the horizontal synchronizing signal H _in and a horizontal output signal H _out. The address selection unit 730 is controlled by the entry / read control unit 710, selects the entry address WAAdd and the read address RAdd and provides them to the line memories LM0, LM1, and LM2 of each memory block, respectively.

  The dot clock selection unit 740 is also controlled by the entry / read control unit 710, and selects the entry dot clock WDclk and the read dot clock RDclk and provides them to the line memories LM0, LM1, and LM2 of the respective memory blocks.

  When a mode signal having a resolution lower than the resolution of the LCD of this device is provided from the host to the control device, the writing and reading operations of the line memories LM0, LM1, and LM2 of the memory blocks 410a, 410b, and 410c are as follows. To be carried out.

Associated with each color signal, fill operation of the memory is performed in synchronization with a horizontal synchronization signal H _in, also reading operation of the memory are performed in synchronization with the horizontal output signal H _out. The memory write operation is started from the line memory LM0 of each memory block, and the memory read operation is started from the line memory LM2 of each memory block. Then, the line memory where the writing / reading operation is performed in each memory block is selected in rotation.

  When the line memory read operation during the entry operation is required, the line memory read operation for which the read operation has been completed immediately before is performed once again. As a result, the writing operation and the reading operation are not performed simultaneously in the same memory.

  FIG. 5 is a diagram illustrating the passage of time in order in a line memory in which a write operation and a read operation are performed in a memory block when a VGA mode signal is provided from the host to the LCD of the present embodiment supporting the XGA mode. It shows along.

  Referring to FIG. 5, a 5-line VGA mode color signal is converted into an 8-line XGA mode color signal. When the signal conversion starts, a write operation is performed in the line memory LM0, and a read operation is performed in the line memory LM2.

  The read operation of the line memory LM0 must be performed after the read operation of the line memory LM2, but as shown in FIG. 5, at the time t1 when the read operation of the line memory LM2 is completed, the line memory LM0 It is placed while performing the filling operation. Therefore, after the read operation of the line memory LM2 is completed, the read operation of the line memory LM2 is repeated once more.

  Next, at the time t2 when the reading operation of the second line memory LM2 is completed, the line memory LM1 is placed during the execution of the writing operation. Accordingly, when the second read operation of the line memory LM2 is completed, the third read operation is performed in the line memory LM0.

  Next, after the third read operation in the line memory LM0, the read operation of the line memory LM1 should be performed, but even at the time t3 when the read operation of the fourth memory is started, the line memory LM1. The entry operation is continued. Therefore, after the third read operation is completed, the read operation of the line memory LM0 is repeated once more.

  Thereafter, as described above, the operation is performed so that the writing operation and the reading operation do not occur simultaneously in one line memory. As a result, at the time t4, the fifth memory entry operation is completed, and at the same time, the eighth memory read operation is completed. With the above operation, while a color signal corresponding to 5 lines is input to each memory block, a color signal corresponding to 8 lines is output from the corresponding memory block. This means that the ratio of the output signal to the input signal of the memory block is 1.6. Eventually, the GA mode signal, which is the input signal V of the memory block, is converted into an XGA mode signal.

  In FIG. 6, when the SVGA mode signal is provided to the liquid crystal display device of the present embodiment, the line memory in which the writing operation is performed and the line memory in which the reading operation is performed in each memory block are shown in order. Shown along the street in time series.

  Referring to FIG. 6, while a color signal corresponding to 4 lines is input from each memory block, a color signal corresponding to 5 lines is output from the corresponding memory block according to the memory writing / reading method described above. Is done. As a result, the 4-line SVGA mode color signal is converted into a 5-line XGA mode color signal.

  FIG. 7 shows an embodiment of the horizontal output generation circuit 300. Referring to FIG. 7, the horizontal output generation circuit 300 includes a down counter 301, two comparators 302 and 303, and a JK flip-flop 304.

The down counter 301 loads the 11-bit first data signal TA <10: 0> provided from the microcomputer 100 with the vertical synchronization signal V _sync and raises the rising edge (rising) of the read dot clock R Dclk.
The loaded value is down-counted each time (edge).

  When the output value of the down counter 301 becomes ‘0’, the down counter 301 loads the first data signal TA <10: 0> from the microcomputer 100. The comparator 302 outputs a high level signal when the first data signal TA <10: 0> and the output of the down counter 301 are the same. In this case, a low-level signal is output from the sub output terminal bar Q of the JK flip-flop 304 as shown in FIG.

Comparator 303 uses the lower 3 bits of down counter 301 (3 low order
When the output of bits) is the same as the second data signal PW <2: 0> provided from the microcomputer 100, a high level signal is output. In this case, as shown in FIG. 8, the output of the JK flip-flop 304 is inverted to a high level.

  Thereafter, each time the output of the lower 3 bits of the down counter 301 becomes the same as the second data signal PW <2: 0>, a high level signal is repeatedly output from the comparator 303. However, since the comparator 302 outputs a high level signal only when the first data signal TA <10: 0> is loaded into the down counter 301, as shown in FIG. 8, the JK flip-flop is output. The output of 304 is maintained at a low level.

  FIG. 9 shows an embodiment of the flag circuit 500 shown in FIG. Referring to FIG. 9, the entry flag generation circuit 510 that generates flags Fa, Fb, and Fc for the entry operation and the read flag generation circuit 520 that generates flags Fd, Fe, and Ff for the read operation are the same in configuration. Have That is, each of the flag generation circuits 510 and 520 includes an AND gate and a rotate shift register composed of three D flip-flops.

In this case, the horizontal synchronization signal H _in is simply provided to one input terminal of the AND gate 511 of the entry flag generation circuit 510, and the horizontal output signal H _out is provided to one input terminal of the AND gate 521 of the read flag generation circuit 520. Is done.

Each of the flag generation circuits 510 and 520 has an active high enable signal (Enable) and an active low (active)
low) reset signal Reset is input from the microcomputer 100, respectively. The reset signal Reset is supplied to the set terminals of the flip-flops 512 and 522 and the reset terminals of the other flip-flops 513, 514, 523, and 524.
Are provided respectively.

  Therefore, when the reset signal Reset is at a low level, the flip-flops 512 and 522 are in the set state, and the other flip-flops 513, 514, 523, and 524 are in the reset state. At this time, the flags Fa and Ff are at a high level, and the other flags Fb, Fc, Fd, and Fe are at a low level.

The enable signal (Enable) is high level and the reset signal Reset
Are at the high level, the outputs of the flag generation circuits 510 and 520 at the leading edges of the horizontal synchronization signal H _in and the horizontal output signal H _out are rotated and shifted, respectively. Accordingly, in each memory block, the horizontal synchronization signal H _in and the horizontal output signal H _out
The line memory for writing and the line memory for reading are respectively designated cyclically while being synchronized with each other.

  FIG. 10 shows an embodiment of the memory selection control circuit 600 as shown in FIG. Referring to FIG. 10, the memory selection control circuit 600 includes a selection error supervisor 610, a cyclic error supervisor 620, and a control signal output unit 630.

Monitoring unit 610 of the selection errors are an inverter 611 for inverting the horizontal output signal H _out, read flag Ff in synchronization with the output of the inverter 611, Fd, D flip-flops 612 and 613 for these respective latches accept Fe , 614, AND gates 615, 616, 617 for comparing whether or not the read flags Ff, Fd, Fe and the entry flags Fa, Fb, Fc are the same, and a NOR gate 618.

  As shown in FIG. 10, the write flags Fc and Fb are used as write memory selection signals W Sel0 and W Sel1, and the read flag signals Ff and Fe are used as read memory selection signals RSel0 and R Sel1, respectively.

  The entry memory selection signals W Sel0 and W Sel1 and the read memory selection signals R Sel0 and R Sel1 output from the monitoring unit 610 are provided to the memory management circuit 700 and the output selection circuit 420, respectively.

  The following Tables 3 and 4 are respectively selected as the memory for writing and the memory for reading in each memory block according to the logic levels of the writing memory selection signals W Sel0 and W Sel1 and the reading memory selection signals R Sel0 and R Sel1. The line memory is shown.

  On the other hand, the selection error monitoring unit 610 monitors the line memory that is currently in the write operation, and predicts whether the memory is selected for the next read operation before the completion of the memory write operation. When it is determined that the memory is selected for the next read operation, a read flag control signal RFC1 for disabling the read flag generating circuit 520 is generated.

Can be seen by reference to Figure 11, a line memory for entry is selected by a rising edge of the horizontal synchronizing signal H _in, the line memory for the next read operation is selected by the falling edge of the horizontal output signal H _out .

  For example, the line memory for the write operation during the time interval t1 <t <t4 is determined at time t1, and the line memory for the read operation during the time interval t3 <t <t5 is determined at time t2.

  At time t2, if the line memory for the next read operation matches the line memory on which the current write operation is performed, the selection error monitoring unit 610 generates a low level read flag control signal RFC1. As a result, read flag generation circuit 520 is disabled and its output is not rotated. As a result, the line memory where the current read operation is being performed is used again for the next read operation.

  On the other hand, when the line memory for the next read operation does not coincide with the line memory for which the current write operation is performed at time t2, the selection error monitoring unit 610 generates the high level read flag control signal RFC1. As a result, the read flag generation circuit 520 is enabled and the output of the circuit 520 is rotated and shifted. As a result, the line memory in the next order of the line memories currently being read is used in the next read operation.

  As shown in FIG. 10, the circulation error monitoring unit 620 includes a counter circuit composed of D flip-flops 621, 622, and 623, and a counting range control circuit composed of an AND gate 624 and off gates 625 and 626. circuit), a reset circuit composed of an AND gate 627, and a read flag control circuit composed of a NOR gate 628.

  Counting range control circuits 624, 625, and 626 control the output ranges of the counter circuits 621, 622, and 623 in response to the first mode display signal MD1 provided from the microcomputer 100.

  The reset signal Reset and the second mode display signal MD2 from the microcomputer 100 are input to the reset circuit 627, and the counter circuits 621, 622, and 623 are reset when the XGA mode signal is input to the LCD. . Read flag control circuit 628 generates read flag control signal RFC2 for enabling read flag generation circuit 520.

  When a VGA mode signal is input to the LCD of this embodiment and the outputs of the counter circuits 621, 622, and 623 are '5', the read flag enable control circuit 628 causes the read flag generation circuit 520 to operate. A read flag control signal RFC2 for enabling is generated. When an SVGA mode signal is input, when the outputs of the counter circuits 621, 622, and 623 are '8', the read flag enable control circuit 628 causes the read flag generation circuit 520 to operate. A read flag control signal RFC2 for enabling is generated.

As described above, the circulation error monitoring unit 620 forcibly enables the read flag generation circuit 520 whenever the output of the counter circuits 621, 622, and 623 becomes '5' when the VGA mode signal is input. . When the SVGA mode signal is input, the circulation error monitoring unit 620 forcibly enables the read flag generation circuit 520 every time the outputs of the counter circuits 621, 622, and 623 become “8”. The reason is that the horizontal synchronization signal H _in and the horizontal output signal H _out coincide with each other at each timing, and the device is likely to malfunction at that time.

The control signal output unit 630 includes an OR gate 631 having two input terminals for receiving the output of the selection error monitoring unit 610 and the output of the circulation error monitoring unit 620, respectively, and an output terminal connected to the enable terminal of the read flag generation circuit 520. Become. When the output signal of the control signal output unit 630 is at a low level, the read flag generation circuit 520 is disabled. Therefore, in this case, even if the horizontal output signal _Hout is input, the rotation shift from the output of the read flag generation circuit 520 is not performed.

On the other hand, when the output signal of the control signal output unit 630 is at a high level, the read flag generation circuit 520 is enabled. Therefore, in this case, when the horizontal output signal _Hout is input, the output of the read flag generation circuit 520 is rotated.

  FIG. 11 shows one embodiment of the memory management circuit 700 shown in FIG. As apparent from FIG. 11, the entry / reading control unit 710 includes inverters 711, 712, 714, and 716 and AND gates 713, 715, and 717.

  As shown in Table 3, in each memory block, first, if W Sel0 = 'L' and W Sel1 = 'L', the line memory LM0 is in the write enable state, and the other line memories LM1 , LM2 is in a read enable state. Next, when WSel0 = “L” and W Sel0 = “H”, the line memory LM1 is in the write enable state, and the other line memories LM0 and LM2 are in the read enable state. Finally, if WSel0 = 'H' and W Sel0 = 'L', the line memory LM2 is in the write enable state and the other line memories LM0, LM1 are in the read enable state.

The address generator 720 is initialized by the horizontal synchronization signal H _{in and} is initialized by the horizontal output signal H _out and the write address generator 721 that generates the address W Add for the write operation in synchronization with the write dot clock WDclk. The read address generator 722 generates an address R Add for read operation in synchronization with the read dot clock RDclk. The entry address generator 721 and the read address generator 722 are each composed of an up counter.

  The address selection unit 730 includes three 2 × 1 multiplexers 731, 732, and 733. A write address WAAdd and a read address RADD are provided to the two input terminals of each multiplexer, respectively. The outputs of the multiplexers 731, 732, and 733 are provided to the line memories LM0, LM1, and LM2 of each memory block, respectively. The selection control terminals of the multiplexers 731, 732, and 733 are provided with outputs of AND gates 713, 715, and 717 in the entry / read control unit 710, respectively. The entry / read addresses WAAdd, RAdd are selected by the entry / read control unit 710 and provided to any of the line memories LM0, LM1, LM2 of each memory block.

  The dot clock selector 740 is also composed of three 2 × 1 multiplexers 741, 742, and 743. Entry and readout dot clocks WDclk, RDclk are provided to the two input terminals of each multiplexer, respectively.

  The outputs of the multiplexers 741, 742, and 743 are provided to the line memories LM0, LM1, and LM2 of the respective memory blocks. The selection control terminals of the multiplexers 741, 742, and 743 are provided with outputs of AND gates 713, 715, and 717 in the entry / reading control unit 710, respectively. The entry / read dot clocks WDclk, RDclk are selectively provided to the line memories LM0, LM1, LM2 of each memory block by the entry / read control unit 710, respectively.

  In the above, the present invention has been described using the case where the input signal is an 8-bit color signal as an example. However, the present invention is not necessarily limited to this. That is, it is obvious that those who have ordinary knowledge in this technical field can apply the present invention as it is to a color signal of 16 bits or more. It should be well understood that all the modifications of the present invention within such a range belong to the technical scope of the present invention.

The figure which shows the video display area | region by this invention in case a VGA mode signal is provided to the liquid crystal display device of a XGA mode. The block diagram which shows the circuit structure of the liquid crystal display control apparatus by this invention. FIG. 3 is a block diagram showing a peripheral circuit configuration of the memory block shown in FIG. 2. FIG. 3 is a block diagram showing an embodiment of the output selection circuit shown in FIG. 2. When the VGA mode signal is provided to the liquid crystal display device of the present invention, the line memory in which the writing operation is performed and the line memory in which the reading operation is performed are sequentially shown in time series in each memory block. Figure. When the SVGA mode signal is provided to the liquid crystal display device of the present invention, the line memory in which the writing operation is performed and the line memory in which the reading operation is performed are shown in time sequence in each memory block. Figure. FIG. 3 is a circuit diagram showing an embodiment of a horizontal output generation circuit shown in FIG. 2. The timing diagram of a vertical synchronizing signal and a horizontal output signal. FIG. 3 is a circuit diagram showing an embodiment of the flag circuit shown in FIG. 2. FIG. 3 is a circuit diagram showing an embodiment of a memory selection control circuit shown in FIG. 2. The timing diagram for demonstrating the process in which the line memory for read-out operations is selected according to an entry operation. FIG. 4 is a circuit diagram illustrating a preferred embodiment of the memory management circuit shown in FIG. 3. 1 is a block diagram schematically showing the configuration of an active matrix liquid crystal display device. A block diagram showing a circuit configuration of a conventional liquid crystal display device, The figure which shows the video display area | region by a prior art in case a VGA mode signal is provided to the liquid crystal display device of XGA mode.

Explanation of symbols

100 microcomputer 200 dot clock generation circuit 300 horizontal output generation circuit 400 memory 500 flag circuit 600 memory selection control circuit 700 memory management circuit

Claims (4)

In a method for converting a video signal of a liquid crystal display device, a first display signal input from a host is converted into a second display signal in which a video is displayed on the entire screen of the liquid crystal display panel.
Detecting an input resolution mode of the first display signal;
Comparing the input resolution mode with a display resolution mode of the liquid crystal display panel that allows an image to be displayed on the entire screen of the liquid crystal display panel;
When the input resolution mode and the display resolution mode are different from each other in the comparison, the first display signal having the input resolution mode and the first frame rate is converted to the display resolution mode and the second frame rate. Converting to the second display signal having,
Here, the input resolution mode includes a first horizontal dot number, a first dot clock frequency, a first line number, and a first horizontal synchronization signal frequency, and the display resolution mode includes a second horizontal dot number and a second horizontal dot number. Including a dot clock frequency, a second number of lines, and a second horizontal synchronization signal frequency;
Converting the first display signal to the second display signal comprises:
The first display signal is a line memory having three horizontal capacity equal to the first horizontal dot number for each first horizontal dot signal having the first horizontal dot number in accordance with the first dot clock frequency. To fill in (write) one of the following,
Reading the first horizontal dot signal in accordance with the second dot clock frequency from the line memory that is not written out of the three line memories, selectively and overlappingly;
Outputting the read first horizontal dot signal as the second display signal in accordance with the second dot clock frequency in a selectively overlapping manner,
The selective overlap reading of the first horizontal dot signal is performed by overlapping the number of differences between the second line number and the first line number, and
The selective overlap output of the read first horizontal dot signal is performed by overlapping the number of differences between the second horizontal dot number and the first horizontal dot number,
Match the second Flame late in the first Flame late,
A video signal conversion method characterized by the above. The first display signal includes the first horizontal synchronization signal and a first vertical synchronization signal having a frequency equal to the first frame rate ;
The video signal according to claim 1, wherein the step of detecting the input resolution mode of the first display signal is determined using the first horizontal synchronization signal and the first vertical synchronization signal. Conversion method.   3. The method of claim 2, wherein the first display signal is an analog signal and the second display signal is a digital signal. The method of claim 1, wherein the display resolution mode is a maximum resolution supported by the liquid crystal display panel.

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