KR980010989A - Display device and method for improving resolution - Google Patents

Abstract

The present invention relates to an apparatus and method for improving the resolution of an LCD display, and more particularly, to an apparatus and method for improving the resolution of an LCD display, which converts a VGA and SVGA mode into an XGA mode And more particularly,

The PLL 1 includes a PLL (Phase Locked Loop) 1 for generating a signal for analog / digital conversion and a read / write signal, A memory unit 2 for storing the red, green, and blue digital information generated from the analog / digital conversion unit 2, and an analog / digital conversion unit 2 for converting analog information of green, A memory controller 4 for receiving a read / write signal generated from the PLL 1 and controlling the memory 3 and generating a synchronous signal; And an LCD display unit 5 for scanning the image signal generated in the memory unit 3 according to a signal.

Description

Display device and method for improving resolution

The present invention relates to an apparatus and method for improving the resolution of a display device, particularly a liquid crystal display (LCD) display, and more particularly, to an LCD device for an XGA (Extended Graphics Array) ) And an SVGA (Super Video Graphics Array) signal into an XGA signal and scanning the same to improve the resolution of the screen.

Generally, since the VGA and SVGA modes are not supported for an XGA LCD display used in a notebook computer, there is a problem that a high resolution can not be realized at a low price.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an apparatus and a method for improving the resolution of an LCD display that realizes high-resolution at low cost by converting input VGA and SVGA signals into XGA signals and scanning the LCD display for XGA .

FIG. 1 is an algorithm for implementing a method for improving the resolution of an LCD display according to the present invention, wherein (A) shows an algorithm for converting a VGA mode into an XGA mode, (B) (C) is a block diagram showing a read / write method of three line memories constructed to implement a vertical conversion among the algorithms of FIG. 1A, and FIG. 3 (D) Block memory device.

FIG. 2 is a block diagram showing a configuration of an apparatus for improving the resolution of an LCD display according to the present invention. FIG.

3 is a block diagram showing a total of nine line memories each consisting of three line memories LM0, LM1 and LM2 for storing pixel values of red, green and blue constituting the memory part of FIG.

FIG. 4 is a block diagram showing a configuration of a memory control unit of FIG. 2; FIG.

FIG. 5 is a circuit diagram according to one embodiment for implementing a memory control signal generator of FIG. 4; FIG.

FIG. 6 is an operation timing diagram when the VGA mode is converted into the XGA mode among the circuit operations according to the embodiment of FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

1: PLL 2: analog / digital conversion unit

3: memory unit 4: memory control unit

5: LCD display 40: Sync signal generating unit

400: memory control signal generator 500: line memory write signal generator

510: counter unit 520: first decoding unit

530: first flip flop unit 600: line memory read signal generating unit

610: second flip flop unit 620: second decoding unit

630: Third flip flop part

According to an aspect of the present invention, there is provided an apparatus for improving the resolution of an LCD display, including: a PLL generating a sampling clock signal and a read / write signal for analog / digital conversion; An analog / digital converter for converting analog signals of red (R), green (G), and blue (B) into digital signals according to a clock signal and outputting the digital signals; A memory controller for storing a blue digital signal in each memory, a memory controller for receiving a read / write signal generated from the PLL to control the memory and generating a synchronous signal, And an LCD display unit in which a video signal generated from the memory unit is scanned on a screen do.

According to another aspect of the present invention, there is provided a method of enhancing the resolution of an LCD display, the method comprising: converting an input video signal to an XGA mode when the input video signal is in a VGA mode; The method comprising the steps of:

Hereinafter, an apparatus and method for improving the resolution of an LCD display according to the present invention will be described in detail with reference to the accompanying drawings.

1A is an algorithm for converting a VGA signal input on an LCD display for XGA according to the present invention into an XGA signal and scanning it. In order to convert a VGA mode of 640 × 480 into an XGA mode of 1024 × 768, / Digital conversion unit is increased by 1.6 times and the number of sampling pixels outputted is increased by 1.6 times to increase the number of horizontal pixels to 1024 and the VGA signal is read in units of 5 lines at the time of vertical conversion and the first line The second line scans the read pixel value once, and the third line scans the read pixel value twice on the screen, and the fourth line scans the read pixel value twice. The screen is scanned once, and the fifth line is scanned twice on the screen.

In other words, the number of scanning lines is increased to 768 by scanning the screen by reading it in units of 5 lines and increasing it to 8 lines.

1B is an algorithm for converting an SVGA signal inputted on an LCD display for XGA according to the present invention into an XGA signal and scanning it. In order to convert an SVGA mode 800x600 into an XGA mode 1024x768, The sampling frequency of the digital converter 2 is increased by 1.25 times, the number of sampling pixels output is increased to 1024, the SVGA signal is read in units of 4 lines at the time of vertical conversion, and the first, second and third lines The pixel value read on the screen is scanned once and the fourth pixel is scanned twice on the screen twice to increase the number of scanning lines to 5 lines and the number of scanning lines is expanded to 768 in the XGA mode .

FIG. 1C is a block diagram showing a method of writing / reading three line memories LM0, LM1, and LM2 configured to implement vertical conversion among the algorithms of FIG. 1A, in which the image data generated from the analog / Reading the line memory LM2 twice to scan the picture on the screen and writing the image data generated from the analog / digital conversion unit 2 to the line memory LM1 after the writing operation is performed on the line memory LM0 Writing the image data generated from the analog / digital conversion unit 2 to the line memory LM2 after the writing operation is performed on the line memory LM1 A step of reading the line memory LM1 once and scanning the line memory LM1 on the screen, Converting the image data generated from the conversion unit 2 into the line memory LM0, reading the line memory LM2 twice and scanning the picture data on the screen, and performing analog-to-digital conversion 2) is written to the line memory LM1 and the line memory LM0 is read once and scanned on the screen. After the 5th write operation, 8 times are read and scanned on the screen, so that the image data 8 lines are formed in units of 5 lines by performing write / read operations to 3 line memories, and the number of 480 scanning lines in VGA mode is extended to 768 scanning lines in XGA mode.

FIG. 1D is a block diagram showing a method of writing / reading three line memories LM0, LM1, and LM2 configured to implement a vertical conversion among the algorithms of FIG. 1B. The three line memories constitute the three line memories, The method of writing and reading includes the steps of writing image data generated from the analog / digital conversion unit 2 to the line memory LM0, reading the line memory LM2 once and scanning the image data on the screen, A step of writing the image data generated from the conversion unit 2 to the line memory LM1 and simultaneously reading the line memory LM2 once and scanning the image data on the screen and a step of writing to the line memory LM1, The image data generated from the conversion unit 2 is written to the line memory LM2 and the line memory LM1 is read once The image data generated from the analog / digital conversion unit 2 is written into the line memory LM0, and the line memories LM1 and LM2 are simultaneously connected to the line memory LM2. By scanning the screen 4 times, it writes 5 times after writing to the line memory and scans the screen to write and read the video data so that they do not overlap with each other, and the number of scanning lines in the SVGA mode is extended to the number of scanning lines in the XGA mode.

Tables 1a and 1b show horizontal frequency, vertical frequency, conversion resolution, and clock frequency for converting various VGA and SVGA signals into XGA signals according to the present invention.

FIG. 2 is a block diagram showing a configuration of an apparatus for improving the resolution of an LCD display for implementing the algorithm described in FIGS. 1A to 1D according to the present invention. The clock signal for analog / digital conversion and the read / A phase locked loop (PLL) 1 for generating a write signal and an analog to digital converter for converting red, green and blue analog signals into digital signals according to a clock signal for analog / digital conversion generated from the PLL 1, A memory unit 3 for storing red, green and blue digital signals generated from the analog / digital conversion unit 2 in respective memories; A memory control unit 4 for receiving a read / write signal to control the memory unit 3 and generating a synchronous signal, and a control unit 4 for controlling the memory unit 3 in accordance with a synchronous signal generated by the memory control unit 4, It constitutes the image signal to the LCD display unit 5 to scan on the screen.

Here, the analog / digital conversion unit 2 includes three analog / digital converters for red, green, and blue, and illustration and reference numerals of the respective analog / digital conversion units are omitted.

3, the memory unit 3 includes three line memories LM0, LM1 and LM2 for writing / reading red information, three line memories LM0 and LM1 for writing / reading green information, , LM2, and three line memories LM0, LM1, LM2 for writing / reading blue information, and the reference numerals of the respective line memories are omitted.

Here, the memory control unit 4 receives the horizontal (Hsync) and vertical synchronizing signals (Vsync) generated in the video card (not shown) and receives the read / write start signals WHSTB A synchronizing signal generator 40 for generating a vertical synchronizing signal RHSTB and a vertical synchronizing signal WVSTB according to signals generated from the synchronizing signal generator 40; And a memory control signal generator 400 for generating a control signal.

Here, the memory control signal generator 400 includes a line memory write signal generator 500 for generating a line memory write signal, which is a control signal for writing data generated from the analog / digital converter 2, And a line memory read signal generator 600 for generating a line memory read signal which is a control signal for reading pixel data stored in the line memory at the same time.

The line memory write signal generating unit 500 includes a counter 510 for receiving a line memory write start signal Whstb at a clock terminal Clk and outputting the binary signal to the clock terminal Clk, A first decoder 520 for receiving a binary output, decoding the first binary output according to each bit value and outputting a value of 1, and a second decoder 520 for receiving a 1 value generated from the first decoder 520, And a first flip flop 530 for outputting a line memory write signal LMWE of the line memory.

Here, the line memory read signal generator 600 receives the binary bit value generated by the counter 510 and outputs a line memory read start signal Rhstb in a low level in synchronization with a read clock signal (Read Clock) A second flip flop 610 for enabling a binary bit value and outputting a binary bit value, and a second flip flop 610 for decoding a binary bit value generated in the second flip flop 610 and outputting a 1 value And a third decoding unit 620 for receiving a 1 value generated from the second decoding unit 620 and outputting a line memory read signal LMRE of each line memory in synchronization with the read clock signal, And a flip flop unit 630.

Hereinafter, an operation and a method of an apparatus for improving the resolution of the LCD display according to the present invention will be described in detail.

First, an apparatus and method for converting red, green, and blue red pixel values from VGA mode to XGA mode and scanning the screen are described as follows.

In horizontal conversion, the number of horizontal pixels is increased by 1.6 times, and the vertical conversion is stored in three line memories LM0, LM1 and LM2 in units of five lines. In order to increase the number of lines, 640 × 480 mode is converted to 1024 × 768, which is an XGA mode, so that a high resolution can be obtained. Therefore, in order to increase the number of horizontal pixels according to the horizontal conversion by 1.6 times, a sampling frequency (ADC Clock) Digital converter (not shown) of the analog / digital converter 2, the number of pixels, i.e., the number of pixels, is increased by 1.6 times, Are stored in the three line memories LM0, LM1 and LM2. Here, in the analog / digital conversion section 2 composed of three analog / digital converters (not shown) for converting analog data for red, green and blue, the red analog to digital converter Data is converted into digital data and stored in three line memories LM0, LM1, LM2 for storing red data. Here, in order to store red, green, and blue digital data, the line memories are configured with nine line memories in total, each of which is three, as shown in FIG.

In order to vertically convert the horizontally converted pixel data to increase the number of lines in the XGA mode and scan the screen, the synchronous signal generator 40 of the memory controller 4 generates a horizontal synchronous signal Hsync and a vertical synchronization signal Vsync and generates a line memory write start signal Whstb, a line memory read start signal Rhstb and a vertical synchronization signal Wvstb in synchronization with a read / write clock.

The memory control signal generator 400 receiving the line memory read / write start signal and the vertical synchronizing signal generates a line memory read / write control signal 400, which is a control signal for the three line memories LM0, LM1 and LM2, And a vertical conversion operation for increasing the number of scan lines by generating an enable signal.

That is, when a write vertical start bar (WVSTB) and a write horizontal start bar (WHSTB) for scanning a screen from the sync signal generating unit 40 are generated, Each time the WHSTB signal is input to the clock terminal of the binary counter unit 510, the output (Vcnt) terminal of the binary counter unit 510 becomes 0, 1, 2, 0 , 1, 2 ... ... And outputs the binary value. When the output of the binary counter unit 510 becomes 1 or 1, the counter unit 510 is logically multiplied by the WVSTB signal.

One cycle period of the line memory write start signal is a 1H period for scanning one line of the screen. The first decoding unit 520 decodes the output of the binary counter unit 510, Level line memory write enable signal for writing the pixel value increased by 1.6 times outputted from the analog / digital converting section 2 to the line memory 0 (Line Memory 0, hereinafter referred to as LM0) when the output of the line memory 0 LMWE0) so as to write the generated pixel value to the LM0.

At this time, the WHSTB signal is outputted from the synchronizing signal generator 40 and a line memory read start signal (RHSTB below) is outputted as shown in FIG. 6, and the second flip flop 610 The binary counter value input to the first decoding unit 520 is input to the second decoding unit 620 in synchronization with the read clock signal (Read Clock).

Therefore, by generating the high level line memory lead inble signal LMRE2 for reading the pixel value stored in the line memory 2 (hereinafter referred to as LM2) when the input counter value is 0, Memory Read) to scan the screen two times, that is, two lines.

That is, during the 1H period of the WHSTB, the pixel value increased in the LM0 is written, and the LM2 is read twice and the two lines are scanned on the screen.

Therefore, if the generated WHSTB signal is 2H, 3H, 4H ... ... The counter (VCNT) of the counter 510 counts the binary values 1, 2, 0, 1, 2, 0, 1, 2 ... ... And sequentially outputs the LMWE1, LMWE2, LMWE0 ... ... LMRE1, LMRE2, ..., LMRE2, LMRE3, ... As shown in FIG. 1C, by sequentially outputting the signals, the pixel value is written to the LM1, and the LM0 is read twice and the screen is scanned two times, that is, two lines. A step of scanning one line on the screen by reading the LM1 once, a step of writing one pixel to the LM0 after scanning one line on the screen, and simultaneously reading the LM2 twice, Scanning the two lines, writing the pixel value to the LM1 after scanning the two lines, reading the LM0 once, and scanning the screen one line at a time, thereby repeating the scanning line number of the screen to the XGA level . Green, and blue are performed in the same manner as the red conversion process, the following description will be omitted.

The process of converting the SVGA mode into the XGA mode is also the same as the process of converting the VGA mode into the XGA mode, and therefore, the following description is omitted.

As described above in detail, according to the present invention, by converting VGA and SVGA signals into XGA signals having higher resolution and scanning them on the screen, a new CRT (cathode ray tube) A liquid crystal display can be used as a high resolution monitor.

Claims (13)

A display device comprising means for converting a low resolution signal into a high resolution signal, comprising: a sampling clock signal generating means for generating a sampling clock signal for increasing the number of horizontal pixels in order to convert the low resolution signal into a high resolution signal; An analog / digital converter 2 for converting analog information into digital information in accordance with a signal from the PLL 1; and an analog-to- A memory unit 3 for storing digital information from the digital conversion unit 2 into a line memory and a memory control unit 4 for controlling the memory unit 3 according to a read / write signal generated from the PLL 1, And a display unit (5) for scanning a picture signal generated in the memory unit (3) according to a synchronization signal generated in the memory control unit (4) on the screen The display device. 2. The apparatus according to claim 1, wherein the memory section (3) comprises three line memories for storing red information, three line memories for storing green information, and three line memories for storing blue information Resolution enhancement display. The memory control unit (4) according to claim 1, wherein the memory controller (4) comprises a synchronous signal generator (40) for receiving horizontal and vertical synchronous signals and generating a read / write and a vertical synchronous signal of the line memory, And a memory control signal generator 400 for receiving a signal generated from the memory controller 400 and generating a control signal for controlling the line memory. 4. The semiconductor memory device according to claim 3, wherein the memory control signal generator (400) comprises: a line memory write signal generator (500) for generating a line memory write signal; And a line memory read signal generator (600). 5. The semiconductor memory device according to claim 4, wherein the line memory write signal generating unit comprises: a counter unit for generating a binary output in synchronization with the line memory write start signal (WHSTB); and a decoder for decoding the three output values generated from the counter unit, A first decoding unit for outputting a first value for outputting a write signal, a first decoding unit for outputting a first value for outputting a write signal, a first decoding unit for decoding the line memory write signal output from the first decoding unit, And a display unit for displaying the image. 5. The semiconductor memory device according to claim 4, wherein the line memory read signal generating unit comprises: a second flip flop unit for receiving a binary output value generated from a counter unit of the line memory write signal generating unit, A second decoding unit decoding a binary output generated from the second flip flop and outputting a value of 1; a second decoding unit receiving an output from the second decoding unit and outputting a line memory read enable signal; 3 flip flop unit. And converting the sampling data of the low resolution mode into sampling data of a high resolution mode to convert the number of horizontal pixels into a horizontal level of a high resolution mode and a high resolution mode of the high resolution mode, And a vertical conversion step of reading in a predetermined line memory in which the data of the horizontally-converted scanning line is stored, and scanning the line memory in the number of lines of the high resolution mode. Display device control method. The method as claimed in claim 7, wherein the low resolution mode is a VGA mode, the high resolution mode is an XGA mode, and the sampling data is increased to increase the number of horizontal pixels by 1.6 times. And a vertical conversion step of reading the image data in units of lines and scanning the image on the screen in eight lines. The method as claimed in claim 7, wherein the low resolution mode is an SVGA mode, the high resolution mode is an XGA mode, and the sampling data is increased to increase the number of horizontal pixels by 1.25 times. And a vertical conversion step of reading the image data in units of lines and scanning the image data on the screen in five lines. 9. The display device control method according to claim 8, wherein the vertical conversion step of reading the image data in units of 5 lines and scanning the image data on the screen in 8 lines includes reading and writing image data without overlapping the three line memories. Way. The method as claimed in claim 10, wherein reading and writing the image data without overlapping each other includes writing the image data generated from the analog / digital converter to the line memory 0, reading the line memory 2 twice, A step of writing the image data generated from the analog / digital converter to the line memory 1 and simultaneously reading the line memory 0 twice and scanning the image data to the screen; A step of writing the image data generated from the analog / digital converter to the line memory 2 and reading the line memory 1 once, and scanning the image data to the screen; When writing to memory 0 (writing), line memory 2 is read twice and the screen is scanned And performing the step of writing the image data generated from the analog / digital converter to the line memory 1 while reading the line memory 0 once and scanning the image to the screen by performing the step 5, And the scanning is performed on the screen by reading eight times after the operation. The display device according to claim 9, wherein the vertical conversion step of reading the image data in units of four lines and scanning the image data on the screen in five lines includes reading and writing image data without overlapping the three line memories. Way. The method as claimed in claim 12, wherein the three line memories are constructed so as to read and write image data without overlapping with each other, the image data generated from the analog / digital converter is written to the line memory 0, Scanning the image data generated by the analog / digital converter to the line memory 1 and reading the line memory 2 once to scan the image data on the screen; A step of writing the image data generated from the analog / digital converter to the line memory 2 and reading the line memory 1 once and scanning the image data to the screen, The image data generated from the converter is written to the line memory 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, and 9 are scanned on the screen to read five times after the fourth writing operation and scan the screen. ※ Note: It is disclosed by the contents of the first application.