JPH0830237A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To provide a liquid crystal display device capable of displaying an optimum picture without performing double write of the picture even when the number of line data within one vertical interval in an inputted picture signal are less than the number of pixels of a liquid crystal panel in the vertical direction. CONSTITUTION:The line data of the picture signal PS are written in a memory 5 in response to a write clock signal WC from a first PLL circuit 1. The data are read outer of the memory 5 in response to a read clock signal RC from a second PLL circuit 2. When the number of written line data within one vertical interval are less than the number of pixels of the liquid crystal panel 8 in the vertical direction, the dummy data are read out based on a read reset signal RR within one vertical interval after all line data within the interval are read out. Thus, the number of line data for displaying the optimum picture are secured even when the number of line data within one vertical interval are less than the number of pixels of the liquid crystal panel 8 in the vertical direction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device for displaying an image, and more particularly to a liquid crystal display device for appropriately displaying an image regardless of the number of line data of an input image signal.

[0002]

2. Description of the Related Art In a liquid crystal display device, an image is displayed by synchronizing one dot of dot data included in an image signal with one pixel of a display panel in one horizontal period.
In addition, line data of one line (one scanning line) in an arbitrary number of line data (scanning line data) that the image signal has within one horizontal period is displayed in correspondence with one line in the vertical direction on the display panel. To be done. This line data is a set of dot data.

In such a liquid crystal display device, an image is displayed according to an image signal output from a computer.

In recent years, computers having various specifications have been manufactured. These computers often have different characteristics of image signals when they are of different types. Therefore, a liquid crystal display device that is connected to a computer and displays an image is required to have versatility that is compatible with many types of computers.

FIG. 3 is a block diagram showing the structure of the main part of a conventional liquid crystal display device. Referring to FIG. 3, this liquid crystal display device includes a PLL circuit 20, a microcomputer 3
0, a polarity reversing circuit 70 and a liquid crystal panel 80 are included.

This liquid crystal display device is connected to a computer. Image signal PS input from computer
Is inverted in polarity by the polarity inversion circuit 70, and the liquid crystal panel 8
0 is supplied. The liquid crystal panel 80 includes a plurality of liquid crystal cells arranged in a matrix and shift registers as drivers for the liquid crystal cells in the horizontal and vertical directions.

The PLL circuit 20 includes a frequency dividing circuit (not shown) in the phase locked loop, and the frequency of the oscillating sampling clock signal SC can be changed by changing the frequency dividing ratio of the frequency dividing circuit. Is configured.

The PLL circuit 20 has a horizontal synchronizing signal HS.
In addition to receiving S as a reference signal for phase synchronization, it also receives frequency division ratio data from the microcomputer 3. The frequency division data supplied from the microcomputer 3 is P
The sampling clock signal SC output from the LL circuit 20 and the dot data of the image signal PS are set to values that are synchronized in a one-to-one correspondence.

Such a method of synchronizing the dot data and the sampling pulse signal is called pixel synchronization. The frequency division ratio of the frequency dividing circuit is set based on such frequency division ratio data. As a result, the PLL circuit 20 outputs the sampling clock signal SC capable of achieving pixel synchronization.

In the PLL circuit 20, the output signal of the frequency dividing circuit becomes the comparison target signal with respect to the reference signal. Therefore, the comparison target signal is compared with the horizontal synchronization signal HSS and phase-synchronized with the horizontal synchronization signal HSS.

As described above, the microcomputer 30 supplies the PLL circuit 20 with the data of the frequency division ratio for synchronizing the pixels in accordance with the connected computer.
Then, in the PLL circuit 20, the frequency division ratio of the frequency division circuit is set based on the data of the frequency division ratio supplied from the microcomputer 30. As a result, the PLL circuit 2
0 is a sampling clock signal S capable of pixel synchronization
Output C.

The liquid crystal panel 80 receives the reset pulse signal RP in addition to the image signal and the sampling clock signal SC. The reset pulse signal RP is a signal that determines the line data for starting display from the line data of the image signal.

The reset pulse signal RP is a signal generated based on the vertical synchronizing signal supplied from the computer, and has the same period as that of the vertical synchronizing signal.
These signals may have different phases.

In the display, the liquid crystal panel 80 determines the line data for starting the display on the screen based on the reset pulse signal RP. That is, line data for starting display is determined in response to the generation of one pulse of the reset pulse signal RP.

In the liquid crystal panel 80, the driver receives the image signal, the sampling clock signal SC and the reset pulse signal RP, and the driver drives the liquid crystal cell in response to these signals to display an image.

In the conventional liquid crystal display device having such a configuration, in order to display an optimum image corresponding to various computers having different characteristics of the output image signal, the pixel synchronization is performed and as shown in FIG. As shown, the line data of the image signal and the vertical pixels of the liquid crystal panel 80 are set to 1
It is necessary to correspond on a one-to-one basis.

FIG. 4 is a timing chart of signals of respective parts in the liquid crystal display device of FIG. 3 when the number of line data of the image signal in one vertical period is equal to or more than the number of pixels in the vertical direction of the liquid crystal panel.

In FIG. 4, the image signal PS, the horizontal synchronizing signal HSS, and the comparison target signal PC in the PLL circuit 20 are shown.
S and the reset pulse signal RP are shown. In the following description, the case where the liquid crystal panel 80 has pixels of 640 (the number of pixels in the horizontal direction) × 480 (the number of pixels in the vertical direction) will be described as an example.

Referring to FIG. 4, the image signal PS has 480 or more line data A1, A within one vertical period.
2, A3, ... One vertical period in this case corresponds to one cycle of the reset pulse signal RP.

In this way, the image signal PS changes to the liquid crystal panel 8
When the line data has the number of pixels equal to or more than 0 (480) in the vertical direction, the liquid crystal panel 80 displays as shown in FIG.

FIG. 5 is a schematic diagram showing a display state of the liquid crystal panel based on the image signal of FIG. In FIG. 5, A
1, A2, ..., A480 indicate lines corresponding to the line data of the image signal PS in FIG. 4, respectively.

As shown in FIG. 5, when the image signal PS has a number of line data equal to or larger than the number of pixels in the vertical direction of the liquid crystal panel 80, all 480 lines in the vertical direction are displayed on the liquid crystal panel 80. A normal image is displayed.

[0023]

However, depending on the type of computer, the number of line data in one vertical period in the image signal may be smaller than the number of pixels of the liquid crystal panel 80 in the vertical direction. In such a case, the following problems occur. A specific example of the problem is shown below.

FIG. 6 is a timing chart of signals of respective portions when the number of line data of the image signal PS in one vertical period in the liquid crystal display device of FIG. 3 is smaller than the number of pixels of the liquid crystal panel 80 in the vertical direction. . Also in FIG. 6, the case where the number of pixels in the vertical direction of the liquid crystal panel 80 is 480 pixels is shown as an example. In FIG. 6 as well, signals of the same type as in FIG. 4 are shown.

Referring to FIG. 6, the image signal PS is the line data A less than 480 in one vertical period.
1, A2, ... In this case, the horizontal synchronizing signal HSS in one vertical period has 400 pulses. The numbers above the horizontal sync signal HSS in the figure indicate the numbers of such pulses.

In this way, the image signal PS changes to the liquid crystal panel 8
When the number of line data is smaller than the number of vertical pixels of 0 (480), in the liquid crystal panel 80,
The display as shown in the next FIG. 7 is made.

FIG. 7 is a schematic diagram showing a display state of the liquid crystal panel 80 based on the image signal PS of FIG. Also in FIG. 7, A1, A2, ..., A480 indicate lines corresponding to the line data of the image signal PS in FIG.

As shown in FIG. 7, when the image signal PS has the number of line data smaller than the number of pixels in the vertical direction of the liquid crystal panel 80 within one vertical period, the liquid crystal panel 8
In the first to 400th lines of the 0 screen, the image signal P
All the line data A1 to A400 of S are displayed respectively.

The same line data A1, A2, ... As the line data displayed from the first line to the 80th line are displayed on the remaining 80 lines. That is, the same image is written twice on the screen of the liquid crystal panel 80.

The double writing of such an image is performed by the image signal P.
This occurs because the reset pulse RP is input during the scanning of all the lines of the liquid crystal panel 80 because the number of line data of S is less than 480 lines.

As described above, in the conventional liquid crystal display device, when the number of line data in one vertical period in the image signal is smaller than the number of pixels in the vertical direction of the liquid crystal display device, the image is displayed twice on the liquid panel. There was a problem of being written.

The present invention has been made in order to solve such a problem, in which 1
Provided is a liquid crystal display device capable of displaying an optimum image without writing the image twice even when the number of line data in the vertical period is smaller than the number of pixels in the vertical direction of the liquid crystal panel. The purpose is to do.

[0033]

According to a first aspect of the present invention, there is provided a liquid crystal display device for displaying an image on a liquid crystal panel according to an image signal having an arbitrary number of line data within one vertical period. It includes storage means and read signal generation means.

Line data of an image signal is written in the storage means. The read signal generating means includes a read clock signal for reading data required for display on the liquid crystal panel in one vertical period and the number of line data read from the storage means in one vertical period within one vertical period. The control signal for reading arbitrary information from the storage means as dummy data is supplied to the storage means from the time when the number of line data of the image signal exceeds the end of one vertical period.

According to a second aspect of the present invention, the liquid crystal display device according to the first aspect further includes a write signal generating means.

The write signal generation means supplies a write clock signal for writing line data to the storage means to the storage means. Further, the read cycle by the read clock signal is made shorter than the write cycle by the write clock signal.

[0037]

According to the present invention, the line data of the image signal is written in the storage means. The line data written in the storage means is read in response to the read clock signal supplied from the read signal generating means.

Then, in one vertical period, reading is performed from the time when the number of line data read from the storage means exceeds the number of line data of the image signal in one vertical period to the end of the vertical period. Arbitrary information is output as dummy data from the storage means in response to the control signal supplied from the signal generation means.

Therefore, when the number of line data of the image signal in one vertical period is smaller than the number required for display on the liquid crystal panel, the image signal used for display on the liquid crystal panel includes dummy data in the line data. It becomes the added signal.

Therefore, even if the number of line data of image signals in one vertical period is smaller than the number required for display on the liquid crystal panel, it is possible to obtain the image signal having the number of line data required for display on the liquid crystal panel. Is possible.

According to the second aspect of the present invention, the storage means is supplied with the write clock signal from the write signal generating means and the read clock signal from the read signal generating means. Since the read cycle by the read clock signal is shorter than the write cycle by the write clock signal, the number of line data of the image signal used for display on the liquid crystal panel can be increased.

[0042]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the structure of the main part of a liquid crystal display device according to an embodiment of the present invention.

This liquid crystal display device includes a first PLL circuit 1, a second PLL circuit 2, a microcomputer 3, and A.
A / D conversion circuit 4, a memory 5, a D / A conversion circuit 6, a signal processing circuit 7, a liquid crystal panel 8 and a signal generation circuit 9 are included.

The case where the liquid crystal display device is connected to a computer and receives signals such as image signals and horizontal synchronizing signals from the computer will be described below.

Referring to FIG. 1, the first PLL circuit 1 is
A frequency dividing circuit (not shown) is included in the phase-locked loop, and the frequency of the oscillating write clock signal WC can be changed by changing the frequency dividing ratio of the frequency dividing circuit.

The first PLL circuit 1 receives the horizontal synchronizing signal HSS as a reference signal for phase synchronization and also receives the data of the frequency division ratio from the microcomputer 3. The dividing ratio data supplied from the microcomputer 3 is
Read clock signal W output from the first PLL circuit 1
C and the dot data of the image signal PS are set to values such that they are pixel-synchronized. The frequency division ratio of the frequency dividing circuit is set based on the data of the frequency division ratio.

The first PLL circuit 1 supplies a write clock signal WC which is pixel-synchronized with the image signal PS to the A / D conversion circuit 4 and the memory 5 using the horizontal synchronizing signal HSS as a reference signal. In the first PLL circuit 1, the output signal of the frequency dividing circuit becomes the comparison target signal with respect to the reference signal. Therefore, the comparison target signal is the horizontal synchronization signal H.
It is compared with SS and phase-synchronized with the horizontal synchronizing signal HSS.

The A / D conversion circuit 4 further includes an image signal P
Upon receiving S, the image signal PS is A / D converted and the memory 5
Give to. The writing of the dot data of the image signal PS into the memory 5 is performed by the write clock signal W supplied from the first PLL circuit 1 to each of the A / D conversion circuit 4 and the memory 5.
It is performed in synchronization with C. By writing such dot data, an arbitrary number of line data is written within one vertical period. That is, a set of dot data is line data.

The second PLL circuit 2 includes a frequency dividing circuit (not shown), and the frequency of the oscillating read clock signal RC and sampling clock signal SC is changed by changing the frequency dividing ratio of the frequency dividing circuit. It is configured to be changeable. Further, the second PLL circuit 2 also generates a read reset signal (or read enable signal) for resetting the reading of the memory 5.

The second PLL circuit 2 receives the horizontal synchronizing signal HSS as a reference signal for phase synchronization, and also generates the data of the frequency division ratio from the microcomputer 3 according to the computer and the read reset signal RR. Receive as reset data.

The reset data is data for defining the output timing and output period of the read reset signal RR, and differs depending on the connected computer.

More specifically, as the reset data, the read reset signal RR is output from the time when all the line data of the image signal PS is read within one vertical period to the end of the one vertical period. The output timing and the output period of the read reset signal RR are defined so as to continue. Such read data is predetermined for each computer that may be connected and is stored in the microcomputer 3.

In the PLL circuit 2, the output signal of the frequency dividing circuit becomes the comparison target signal with respect to the reference signal. Therefore, the comparison target signal is compared with the horizontal synchronization signal HSS and phase-synchronized with the horizontal synchronization signal HSS.

The frequencies of the read clock signal RC and the sampling clock signal SC output from the second PLL circuit 2 are set to values higher than the frequency of the write clock signal WC, respectively.

Write clock signal WC is supplied to memory 5 and D / A conversion circuit 6. Read reset signal R
R is supplied to the memory 5. The sampling clock signal SC is supplied to the liquid crystal panel 8.

Reading of data from memory 5 is performed in response to read clock signal RC. And memory 5
Then, the dummy data is read in response to the read reset signal RR. The dummy data is read in a period in which there is no line data to be read in one vertical period. The D / A conversion circuit 6 performs D / A conversion on the data read from the memory 5 and outputs the converted image signal PS.
1 is supplied to the signal processing circuit 7.

The signal processing circuit 7 includes processing circuits such as a polarity inverting circuit and a blanking processing circuit (both not shown). In the signal processing circuit 7, for the image signal PS1,
The polarity inversion and blanking processing is performed, and the processed image signal is supplied to the liquid crystal panel 8.

The blanking process in the signal processing circuit 7 is
This is performed for the dummy data portion within one vertical period of the image signal PS1. As a result, the dummy data portion becomes a blanking period.

In the liquid crystal panel 8, liquid crystal cells (not shown) forming pixels are arranged in a matrix. The liquid crystal panel 8 also includes a driver circuit (not shown) including a shift circuit for driving the liquid crystal cell.

The liquid crystal panel 8 receives a reset pulse signal RP generated from a predetermined signal generating circuit. The reset pulse signal RP is a signal generated based on the vertical synchronizing signal VSS and has the same period as the vertical synchronizing signal but may have a different phase.

In the display, the liquid crystal panel 8 determines the image data (line data) to start the display in the vertical direction of the screen based on the reset pulse signal RP. That is, of the line data included in one vertical period,
In response to the generation of one pulse of the reset pulse signal RP, the line data as the display start data is determined.

Then, the liquid crystal panel 8 samples the image signal based on the sampling clock signal SC and displays the image based on the sampled image signal data.

Next, the operation of the liquid crystal display device of FIG. 1 will be described. FIG. 2 is a timing chart showing the operation of the liquid crystal display device of FIG. In FIG. 2, the image signal PS, the comparison target signal PCS1 of the first PLL circuit 1,
Vertical synchronization signal VSS, comparison target signal PCS2 of second PLL circuit 2, reset pulse signal RP, image signal PS1
And the read reset signal RR is shown.

In FIG. 2, the liquid crystal panel 8 has pixels of 480 dots in the vertical direction, and the image signal PS has 48 pixels.
An example will be described in which the number of line data less than 0 dots is included in one vertical period.

Referring to FIG. 2, the image signal PS has line data A1, A2, ... Of a number smaller than 480 in one vertical period. The dot data of the image signal PS is written in the memory 5 in synchronization with the pixel-synchronized write clock signal WC.

When such dot data writing is continued, one line data is written in one horizontal period,
Then, the number of line data less than 480 is written in one vertical period.

The dot data written in the memory 5 is read at high speed in synchronization with the read clock signal RC having a shorter cycle than the write clock signal WC. If such reading of dot data is continued, 1 dot is set within 1 horizontal period.
One line data is read. Then, all line data less than 480 written corresponding to one vertical period is read out within one vertical period.

When the reading is performed in this manner, the line data (dot data) to be read runs short within one vertical period. This is because the line data of the image signal PS is smaller than 480 which is the number of horizontal pixels of the liquid crystal panel 8.

The read reset signal RR rises to the H level when there is no more line data to read. The read reset signal is held at H level until one vertical period ends. When the read reset signal RR becomes H level, the reading from the memory 5 is reset and the dummy data is read from the memory 5. The dummy data is continuously read until the end of one vertical period.

The dummy data in this case is, for example, data read again in order from the first address of the line data stored in memory 5. The dummy data may be any data as long as it corresponds to the dummy line data.

Therefore, the image signal PS1 within one horizontal period
Is the normal line data A1, A based on the image signal PS.
, 2, ... And dummy data D1, D2 ,.

In order to display an optimal image in which the image is not written twice on the liquid crystal panel 8, 480 lines corresponding to the number of pixels in the vertical direction of the liquid crystal panel 8 in one vertical period. The data needs to be present in the image signal PS1 within one vertical period.

Dummy data is added to the image signal PS1 during a period in which there is no regular line data within one vertical period. Therefore, in the liquid crystal panel 8, the image signal PS having the necessary number of line data within one vertical period is generated.
1 is supplied.

Therefore, the liquid crystal panel 8 can display an image in an optimum state. In the image signal PS1 in this case, the portion of the dummy data is blanked in the signal processing circuit 7, and therefore displayed on the screen of the liquid crystal panel 8 in a black color, for example.

As described above, in this liquid crystal display device, even when the number of line data of the input image signal PS in one vertical period is smaller than the number of pixels of the liquid crystal panel 8 in the vertical direction, the line data of the image signal PS is Dummy data is added to. Therefore, data relating to the image necessary for optimal liquid crystal display in the vertical direction is secured.

Therefore, it is possible to display an image in an optimum state regardless of which computer the liquid crystal display device is connected to.

[0078]

According to the present invention described in claim 1, when the number of line data of the image signal in one vertical period is smaller than the number of line data required for display on the liquid crystal panel, 1 Dummy data is added to the line data of the image signal in the vertical period. Therefore, even when the number of line data in one vertical period is smaller than the number of pixels in the vertical direction of the liquid crystal panel, the optimum image can be displayed without writing the image twice.

According to the second aspect of the present invention, the read cycle in the storage means is shorter than the write cycle.
It is possible to increase the number of line data of image signals used for display on the liquid crystal panel in one vertical period. Therefore, even when the number of line data in one vertical period is smaller than the number of pixels in the vertical direction of the liquid crystal panel, it is possible to display a more optimal image without writing the image twice.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the liquid crystal display device of FIG.

FIG. 3 is a block diagram showing a configuration of a main part of a conventional liquid crystal display device.

FIG. 4 is a timing chart of signals of respective parts when the number of line data included in an image signal in the liquid crystal display device of FIG. 3 is equal to or more than the number of pixels in the vertical direction of the liquid crystal panel.

5 is a schematic diagram showing a display state of a liquid crystal panel based on the image signal of FIG.

FIG. 6 is a timing chart of signals of respective portions when the number of line data included in an image signal in the liquid crystal display device of FIG. 3 is smaller than the number of vertical pixels of the liquid crystal panel.

7 is a schematic diagram showing a display state of a liquid crystal panel based on the image signal of FIG.

[Explanation of symbols]

 1 1st PLL circuit 2 2nd PLL circuit 3 Microcomputer 5 Memory 8 Liquid crystal panel

Claims (2)

[Claims] 1. A liquid crystal display device for displaying an image on a liquid crystal panel according to an image signal having an arbitrary number of line data within one vertical period, and a storage unit in which the line data of the image signal is written. A read clock signal for reading data necessary for display on the liquid crystal panel in one vertical period and the image signal in which the number of line data read from the storage means in one vertical period is within one vertical period. And a read signal generating means for supplying the storage means with a control signal for reading arbitrary information from the storage means as dummy data from the time when the number of line data exceeds the end of one vertical period. Prepared,
Liquid crystal display device. 2. A write signal generating means for supplying a write clock signal for writing the line data to the storage means to the storage means, the read cycle according to the read clock signal being the write clock signal. 2. The liquid crystal display device according to claim 1, wherein the writing cycle is shorter than the writing period.