JP4827040B2 - Plasma display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a plasma display device and a driving method thereof, and is suitable for use in, for example, an AC driven plasma display.
[0002]
[Prior art]
In recent years, flat matrix type display devices such as a plasma display panel (PDP), a liquid crystal display (LCD), and an electro luminescence display (ELD) instead of a CRT due to the advantages of thinness The demand for is increasing. In particular, the AC drive type PDP is a self-luminous display device that has good visibility and is thin and capable of displaying on a large screen. Has been.
[0003]
Conventionally known AC drive type PDPs include a two-electrode type that performs selective discharge (address discharge) and sustain discharge with two electrodes, and a three-electrode type that performs address discharge using a third electrode. There is. Further, also in this three-electrode type, when the third electrode is formed on the substrate on which the first electrode and the second electrode for performing the sustain discharge are disposed, the third electrode is formed on the other substrate facing the third electrode type. May be formed.
[0004]
Since the principle of each type of PDP apparatus described above is the same, in the following, the first and second electrodes for performing the sustain discharge are provided on the first substrate, and separately from the first electrode, A configuration example of a PDP device in which a third electrode is provided on a second substrate facing the substrate will be described.
[0005]
FIG. 99 is a diagram showing an overall configuration of an AC drive type PDP device. In FIG. 99, the AC drive type PDP1 is provided with scanning electrodes Y1 to Yn and a common electrode X which are parallel to each other on one surface, and an address in the direction orthogonal to these electrodes Y1 to Yn and X is provided on the opposite surface. Electrodes A1 to Am are provided. The common electrode X is provided corresponding to each of the scanning electrodes Y1 to Yn and close thereto, and one end thereof is connected in common with each other.
[0006]
The common end of the common electrode X is connected to the output end of the X-side circuit 2, and each scanning electrode Y <b> 1 to Yn is connected to the output end of the Y-side circuit 3. The address electrodes A1 to Am are connected to the output terminal of the address side circuit 4. The X-side circuit 2 is composed of a circuit that repeats discharge, and the Y-side circuit 3 is composed of a circuit that performs line sequential scanning and a circuit that repeats discharge. The address side circuit 4 includes a circuit for selecting a column to be displayed. These X-side circuit 2, Y-side circuit 3 and address-side circuit 4 are controlled by a control signal from the control circuit 5. That is, a cell that performs line-sequential scanning in the address-side circuit 4 and the Y-side circuit 3 determines which cell is lit, and repeats the discharge of the X-side circuit 2 and the Y-side circuit 3 to perform the display operation of the PDP. Do.
[0007]
The control circuit 5 generates the control signal based on the external display data D, the clock CLK indicating the read timing of the display data D, the horizontal synchronization signal HS, and the vertical synchronization signal VS, and generates the X side circuit 2 and the Y side circuit. 3 and the address side circuit 4.
[0008]
FIG. 100A is a diagram illustrating a cross-sectional configuration of the cell Cij in the i-th row and the j-th column, which is one pixel. In FIG. 100A, the common electrode X and the scanning electrode Yi are formed on the front glass substrate 11. A dielectric layer 12 for insulating the discharge space 17 is deposited thereon, and a MgO (magnesium oxide) protective film 13 is further deposited thereon.
[0009]
On the other hand, the address electrode Aj is formed on a rear glass substrate 14 disposed so as to face the front glass substrate 11, and a dielectric layer 15 is deposited thereon, and a phosphor is further deposited thereon. ing. The discharge space 17 between the MgO protective film 13 and the dielectric layer 15 is filled with Ne + Xe Penning gas or the like.
[0010]
FIG. 100B is a diagram for explaining the capacitance Cp of the AC drive type PDP. As shown in FIG. 100 (b), in the AC drive type PDP, there are capacitance components Ca, Cb, Cc in the discharge space 17, between the common electrode X and the scan electrode Y, and in the front glass substrate 11, respectively. The sum of these determines the capacity Cpcell per cell (Cpcell = Ca + Cb + Cc). The total of the capacitance Cpcell of all the cells is the panel capacitance Cp.
[0011]
FIG. 100C is a diagram for explaining light emission of the AC drive type PDP. As shown in FIG. 100 (c), red, blue, and yellow phosphors 18 are arranged and applied to the inner surface of the rib 16 in stripes for each color, and between the common electrode X and the scan electrode Y. The phosphor 18 is excited by the discharge to emit light.
[0012]
FIG. 101 is a voltage waveform diagram showing an example of a driving method of the AC drive type PDP, and shows one subfield of a plurality of subfields constituting one frame. One subfield is divided into a reset period including an entire writing period and an entire erasing period, an address period, and a sustain discharge period.
[0013]
In the reset period, all the scanning electrodes Y1 to Yn are first set to the ground level (0 V), and at the same time, a full-surface writing pulse composed of a voltage Vs + Vw (about 400 V) is applied to the common electrode X. At this time, the potentials of the address electrodes A1 to Am are all Vaw (about 100 V). As a result, regardless of the previous display state, discharge is performed in all cells of all display lines, and wall charges are formed.
[0014]
Next, when the potentials of the common electrode X and the address electrodes A1 to Am become 0V, the voltage of the wall charges themselves exceeds the discharge start voltage in all the cells, and the discharge is started. In this discharge, since there is no potential difference between the electrodes, no wall charge is formed, and the space charge self-neutralizes and the discharge ends. This is so-called self-erasing discharge. By this self-erasing discharge, the state of all the cells in the panel becomes a uniform state without wall charges. This reset period has the effect of making all the cells the same regardless of the lighting state of each cell in the previous subfield, thereby enabling the next address (write) discharge to be performed stably. .
[0015]
Next, in the address period, in order to turn on / off each cell in accordance with display data, address discharge is performed in a line sequential manner. That is, first, a voltage of −Vy level (about −150 V) is applied to the scanning electrode Y1 corresponding to the first display line, and a voltage of −Vsc level (about −50 V) is applied to the scanning electrodes Y2 to Yn corresponding to the other display lines. At the same time, an address pulse of voltage Va (about 50V) is selectively applied to the address electrode Aj corresponding to the cell causing sustain discharge in each of the address electrodes A1 to Am, that is, the cell to be lit.
[0016]
As a result, a discharge occurs between the address electrode Aj of the cell to be lit and the scan electrode Y1, and this is used as a priming (fire) to immediately discharge the common electrode X and the scan electrode Y1 at the voltage Vx (about 50V). Transition. As a result, wall charges of an amount capable of the next sustain discharge are accumulated on the surface of the MgO protective film 13 on the common electrode X and the scan electrode Y1 of the selected cell. Similarly, for the scan electrodes Y2 to Yn corresponding to the other display lines, a voltage of −Vy level is sequentially applied to the scan electrodes of the selected cell, and the voltage of −Vsc level is applied to the remaining scan electrodes of the non-selected cells. By applying the voltage, new display data is written in all the display lines.
[0017]
Thereafter, during the sustain discharge period, the sustain pulses composed of the voltage Vs (about 200 V) are alternately applied to the scan electrodes Y1 to Yn and the common electrode X to perform the sustain discharge, and the video display of one subfield is performed. . Note that the luminance of the video is determined by the length of the sustain discharge period, that is, the number or frequency of sustain pulses.
[0018]
In the AC drive type PDP, the voltage Vf for starting gas discharge on the surface between the common electrode X and the scan electrode Y is generally 220V to 260V. In the address period, for example, in a cell to be displayed, a voltage is applied between the address electrode A and the scan electrode Y to cause gas discharge, and this is used as a trigger to discharge between the common electrode X and the scan electrode Y. Wall charges are left on the common electrode X and the scanning electrode Y.
[0019]
Next, in the sustain discharge period, the wall discharge Vwall generated in the address period and the sustain pulse voltage Vs applied between the common electrode X and the scan electrode Y make | Vs + Vwall | It can be carried out. The value of the voltage Vs does not exceed the discharge start voltage Vf, and a voltage value satisfying | Vs | <| Vf | <| Vs + Vwall |
[0020]
Note that when gas discharge is performed between the common electrode X and the scan electrode Y, the wall charges on the common electrode X and the scan electrode Y in the cell become wall charges having opposite polarities, and the gas Converge the discharge. Next, by applying a sustain pulse voltage Vs having a polarity opposite to that between the common electrode X and the scan electrode Y, the wall charges formed on the common electrode X and the scan electrode Y are utilized, Gas discharge is performed again. By repeating the above operation, gas discharge can be repeated.
[0021]
As an example of the driving method of the AC drive type PDP, as described above, the wall charges of all the cells in the panel are erased in the reset period, and the display cells are selectively discharged in the next address period to accumulate the wall charges. In addition to the “write address method”, on the contrary, wall charges are accumulated in all cells in the panel in the reset period, and non-display cells are selectively discharged in the next address period to erase the wall charges. There is an “erase address method” in which only the wall charge of the display cell is left.
[0022]
FIG. 102 is a diagram illustrating a partial configuration example of a driving device in a conventional PDP device. In FIG. 102, a load 20 is a total capacity of cells formed between one common electrode X and one scan electrode Y. A common electrode X and a scanning electrode Y are formed on the load 20, and each pulse voltage as described in FIG. 101 is applied by the X side circuit 2 and the Y side circuit 3.
[0023]
The X-side circuit 2 includes a power supply circuit 21, a power recovery circuit 22, and a sustainer circuit 23. The power supply circuit 21 includes a diode D1 connected to the power supply line of the sustain pulse voltage Vs, transistors Tr1 and Tr2 connected in series between the power supply line of the write voltage Vw and the ground (GND), and the two A capacitor C1 connected between the common drain of the transistors Tr1 and Tr2 and the output of the diode D1 is provided.
[0024]
When a full write pulse is applied to the common electrode X during the reset period, the transistor Tr1 is turned ON and the transistor Tr2 is turned OFF, so that the sustain pulse voltage Vs that has passed through the diode D1 and the write voltage Vw are added, and the sustainer circuit 23. Further, when a sustain pulse is applied to the common electrode X during the sustain discharge period, the transistor Tr1 is turned off and the transistor Tr2 is turned on, so that the sustain pulse voltage Vs that has passed through the diode D1 is supplied to the sustainer circuit 23 as it is. .
[0025]
The sustainer circuit 23 includes a switch circuit in which a transistor Tr5 and a diode D5 are connected in parallel, two diodes D7 and D8 connected in series to the switch circuit, and a transistor Tr6 and a diode D6 connected in series to the switch circuit in parallel. And a connected switch circuit. The connection between the two diodes D7 and D8 is connected to the common electrode X of the load 20.
[0026]
When the transistor Tr5 is ON and the transistor Tr6 is OFF, the sustain pulse voltage Vs or the full write pulse voltage Vs + Vw supplied from the power supply circuit 21 is applied to the common electrode X. Conversely, when the transistor Tr5 is OFF and the transistor Tr6 is ON, the voltage applied to the common electrode X is at the ground level (0 V).
[0027]
The power recovery circuit 22 includes two coils L1 and L2 connected from the capacitive load 20 of the PDP via the two diodes D7 and D8, a diode D3 connected in series to one coil L1, and a transistor Tr3. And a diode D4 and a transistor Tr4 connected in series to the other coil L2, and a capacitor C2 connected between the common terminal of the two transistors Tr3 and Tr4 and the ground.
[0028]
The capacitive load 20 and the two coils L1 and L2 connected via the two diodes D7 and D8 constitute two series of resonance circuits. That is, the power recovery circuit 22 has two L-C resonance circuits, and charges supplied to the panel due to resonance between the coil L1 and the capacitive load 20 are caused by resonance between the coil L2 and the capacitive load 20. It is to be collected.
[0029]
On the other hand, the Y-side circuit 3 includes a scan driver 31, a sustainer and power supply circuit 32, and a power recovery circuit 33. The scan driver 31 includes two transistors Tr7 and Tr8 connected in series. The connection between the two transistors Tr7 and Tr8 is connected to the scan electrode Y of the load 20, and the scan pulse voltage -Vy, the non-selection pulse voltage -Vsc or the sustain pulse voltage Vs supplied from the power supply circuit 32 described later is scanned. Applied to the electrode Y.
[0030]
The sustainer and power circuit 32 includes transistors Tr9 and Tr10 connected to the power line of the scan pulse voltage −Vy, transistor Tr11 and diode D9 connected to the power line of the non-selection pulse voltage −Vsc, and the sustain pulse voltage. A transistor Tr12 connected to the Vs power supply line, a leakage control transistor Tr13 connected to the ground, and a transistor Tr14 for separating the power supply line of the scan pulse voltage -Vy and the non-selection pulse voltage -Vsc from the GND line. And a diode D14.
[0031]
By appropriately controlling ON / OFF of the transistors Tr7 to Tr14 provided in the sustainer and power supply circuit 32 and the scan driver 31, as shown in FIG. 101, the scan pulse voltage -Vy and the non-selection pulse voltage -Vsc Alternatively, sustain pulse voltage Vs is applied to scan electrode Y.
[0032]
The power recovery circuit 33 includes two coils L3 and L4 connected from the capacitive load 20 through the two transistors Tr7 and Tr8, etc., and a diode D12 and a transistor Tr15 connected in series to one coil L3. A diode D13 and a transistor Tr16 connected in series to the other coil L4, and a capacitor C3 connected between the common terminal of the two transistors Tr15 and Tr16 and the ground.
[0033]
This power recovery circuit 33 also has two L-C resonance circuits, and recovers the electric charge supplied to the capacitive load 20 by the resonance of the coil L4 and the capacitive load 20 by the resonance of the coil L3 and the capacitive load 20. It is.
[0034]
FIG. 103 is a diagram showing a configuration example of a conventional line sequential scanning circuit in the Y-side circuit 3 and a circuit for repeating discharge in the X-side circuit 2 and the Y-side circuit 3.
As shown in FIG. 103, the switches SW1 and SW2 on the common electrode X side are configured by connecting a plurality of FETs in parallel. The switch SW1 is connected to the power source Vs. On the common electrode X side, a power recovery circuit including coils L1 and L2, switches SW3, SW5 and SW6, and a capacitor C1 is provided. Further, a switch SW7 is connected between the power supply Vax and the common electrode X.
[0035]
On the other hand, on the scan electrode Y side, the scan driver including the switches SW20 and SW21 is connected to the scan electrode Y, and the power source Vsc is connected to the switch SW20 side of the scan driver via the switch SW18 and the switch SW11 is connected. Has been. Further, the power source (−Vy) is connected to the switch SW21 side of the scan driver via the switches SW16 and SW17, and is connected to the ground via the switch SW19. Further, a diode D1 and switches SW10 and SW15 are connected to the switch SW21 side between the power source Vs as shown in the figure.
[0036]
Further, a circuit for line sequential scanning (for address) and a circuit for repeating discharge (for sustainer) are provided by the diode D2 provided on the switch SW20 side of the scan driver and the switch SW15 provided on the switch SW21 side of the scan driver. A / S separation circuit for separating the circuit of FIG. On the scanning electrode Y side, a power recovery circuit including coils L3 and L4, switches SW12, SW13, and SW14 and a capacitor C2 is provided.
[0037]
FIG. 104 is a diagram showing a configuration example of a high voltage power source necessary for the circuit shown in FIG. As shown in FIG. 104, high voltages of 180 V, 50 V, −180 V, and −80 V are used as the values of the voltages Vs, Vax, Vy, and Vsc, respectively.
[0038]
FIG. 105 is a timing chart showing the operation of the circuit shown in FIG. During the scanning period, the switches SW16, SW17, and SW18 on the scanning electrode Y side are turned on to apply the voltage Vsc (= 100 V) across the scan driver. Further, by turning on the switch SW21, a voltage (−Vy = −180V) is applied to one scan electrode Y to be scanned, and the voltage is obtained by turning on the switch SW20 on the other scan electrodes Y. (Vsc−Vy = −80V) is applied.
[0039]
In the case of display, for example, at the intersection of a scan pulse of −180 V for one scan electrode Y to be scanned and a plurality of address electrodes A, gas discharge is performed by the voltage Va (= 60 V) applied to the address electrode A. . Using the gas discharge between the address electrode A and the scan electrode Y as a trigger, between the common electrode X (switch SW7 is turned on and voltage Vax is applied) and the scan electrode Y (voltage -180 V is applied). Further, a discharge is generated, and wall charges having different polarities from the applied voltage are formed on the dielectric layer 12 (including the MgO protective surface 13) on the common electrode X and the scan electrode Y shown in FIG. This operation is performed for all the scan electrodes Y.
[0040]
Since the voltage (−Vy) is lower than the ground level in the A / S separation circuit, the diode D1 and the switch SW16 are prevented from being short-circuited by ON, and since the voltage Vsc is lower than the ground level, the switch SW18 and the switch SW11 are parasitic. It is provided to prevent short circuit with the diode. During the above operation, the switch SW15 is turned off. A voltage of 180 V is applied across the switch SW15.
[0041]
In the sustain discharge period, the switches SW12 and SW15 on the scan electrode Y side are turned on, and the switch SW2 on the common electrode X side is turned on. Thereby, using the capacitor C2 whose one side is always grounded as a power source, LC resonance between the coil L3 and the capacitance Cp of the PDP panel is performed, and the voltage on the scanning electrode Y side is raised to near Vs. Next, the switch SW10 is turned on to raise the voltage to Vs, and the voltage applied to the scan electrode Y is set to Vs. At this time, the voltage Vs (= 180 V) is applied to both ends of the switch SW11 that is OFF.
[0042]
As a result, the voltage Vs applied between the common electrode X and the scanning electrode Y and the voltage due to the wall charges generated by the scanning period described above are added, and gas discharge is started. The current at that time flows to the switches SW10, SW15, SW2. At this time, the wall charges are formed again as described above.
[0043]
Next, by turning off the switches SW10 and SW12 on the scan electrode Y side and turning on the switch SW13, the capacitor C2 whose one side is always grounded is used as a power source, and the L− of the coil L4 and the capacitance Cp of the PDP panel C resonance is performed, and the voltage on the scan electrode Y side falls to near the ground level. Next, the switch SW11 is turned on to lower the voltage to the ground level, and the voltage applied to the scan electrode Y is set to the ground level. At this time, the voltage Vs (= 180 V) is applied to both ends of the switch SW10 that is OFF.
[0044]
Next, by turning on the switch SW3 of the common electrode X, LC resonance between the coil L1 and the capacitor Cp of the PDP panel is performed by using the capacitor C1 whose one side is always grounded as a power source, and the common electrode X Side voltage is raised to near Vs. Next, the switch SW1 is turned on to raise the voltage to Vs, and the voltage applied to the common electrode X is set to Vs. At this time, the voltage Vs (= 180 V) is applied to both ends of the switch SW2 that is OFF.
[0045]
As a result, the voltage Vs applied between the common electrode X and the scan electrode Y and the voltage generated by the wall charges generated earlier are added, and gas discharge is started. The current at that time flows through the switches SW1 and SW11. At this time, the wall charges are formed again as described above.
[0046]
Next, by turning off the switches SW1 and SW3 on the common electrode X side and turning on the switch SW6, the capacitor C1 whose one side is always grounded is used as a power source, and the L− of the coil L2 and the capacitance Cp of the PDP panel C resonance is performed, and the voltage on the common electrode X side is lowered to near the ground level. Next, the switch SW2 is turned on to lower the voltage to the ground level, and the voltage applied to the common electrode X is set to the ground level. At this time, the voltage Vs (= 180 V) is applied to both ends of the switch SW1 on the common electrode X side and the switch SW10 on the scan electrode Y side which are OFF.
[0047]
[Problems to be solved by the invention]
The withstand voltages of various elements included in the driving device are determined by the maximum voltage of pulses applied to the elements. In this case, the conventional driving device is configured to apply a fixed voltage supplied from each power supply line to the load. For example, one of the X and Y electrodes is dropped to the ground level and the other is applied to the other. A fixed voltage was applied. Therefore, each element in the driving device is required to have a large withstand voltage corresponding to a fixed voltage.
[0048]
In particular, in the case of the configuration shown in FIG. 102, each element constituting the sustainer circuit 23 in the X-side circuit 2 needs to have a very large breakdown voltage corresponding to the full write pulse voltage Vs + Vw (about 400 V). For this reason, it is necessary to use an expensive and large switching element such as an FET in order to secure a sufficient withstand voltage, and there is a problem that the circuit configuration becomes complicated and the manufacturing cost becomes very high.
[0049]
In the case of the configuration shown in FIG. 103, the breakdown voltage of the FETs constituting the switches SW1, SW2, SW10, SW11, and SW15 requires a large voltage equal to or higher than Vs. The FETs of these switches are switches that handle a gas discharge current, and a low ON voltage is required to stably perform the gas discharge. However, generally, an FET has a high ON voltage when the withstand voltage is high (for example, when the withstand voltage is doubled, it is proportional to 2 3 to the 4th power). Therefore, in order to drive the PDP stably, it is necessary to install FETs in parallel in the switches SW1, SW2, SW10, SW11, and SW15 that handle gas discharge currents and reduce the ON voltage. Therefore, when the withstand voltage is high, the cost of the FET becomes high, and there is a problem that the cost is further increased by providing a plurality of FETs. In addition, in order to realize the drive waveform as shown in FIG. 105 in the circuit shown in FIG. 103, four types of high-voltage power supplies are required, which increases the cost.
[0050]
In addition, the fixed voltage applied to the load is very large, which causes a problem that a very large power loss occurs when charging / discharging the load capacity.
[0051]
The present invention has been made to solve such a problem, and enables the withstand voltage of each element included in the drive device to be kept low, thereby simplifying the circuit configuration and reducing the manufacturing cost. It aims to be able to realize.
Another object of the present invention is to make it possible to reduce power consumption when charging / discharging the capacity of a load.
[0052]
[Means for Solving the Problems]
The plasma display apparatus of the present invention is a plasma display apparatus having a plasma display panel in which a plurality of first and second electrodes for performing a sustain discharge are arranged adjacent to each other, and a reference power source for supplying a reference voltage V3 A power source that generates a first voltage V1 having a level higher than the reference voltage V3, a first electrode drive circuit that drives the first electrode, and a second electrode drive that drives the second electrode A first switch means disposed between the power source and the first voltage supply unit, one terminal is connected to the first voltage supply unit, A first capacitive element having the other terminal connected to the second voltage supply unit, and a second switch for switching conduction / non-conduction between the one terminal of the first capacitive element and the reference power supply Means and the first Third switch means for switching conduction / non-conduction between the other terminal of the quantitative element and the reference power source, and the first voltage V1 to the first electrode via the first voltage supply unit. And a fourth switch means for supplying a second voltage V2 having a level lower than the reference voltage V3 to the first electrode via the second voltage supply unit. And the second electrode drive circuit is connected to the third voltage supply unit, and a sixth switch unit disposed between the power source and the third voltage supply unit. A seventh capacitive element whose other terminal is connected to a fourth voltage supply section, and a seventh capacitive element for switching conduction / non-conduction between the one terminal of the second capacitive element and the reference power source. Switch means, and the other terminal of the second capacitive element and the reference power source. / Eighth switch means for switching non-conduction, ninth switch means for supplying the first voltage V1 to the second electrode via the third voltage supply section, and the second electrode And a tenth switch means for supplying the second voltage V2 via the fourth voltage supply section, the first switch means being conducted and the second switch means being non-conductive. As the conduction, the first voltage V1 is supplied to the first electrode via the first voltage supply unit and the fourth switch means, and the one terminal of the first capacitive element is supplied with the first voltage V1. The first voltage V1 is supplied, the third switch means is turned on, the other terminal of the first capacitive element is used as the reference voltage V3, and the first voltage V1 is used as the first capacitive element. The element is charged and the sixth switch means is turned off. And the seventh switch means is turned on to cut off the supply of the first voltage V1 to the one terminal of the second capacitive element and the one terminal of the second capacitive element. Is set to the reference voltage V3 and the eighth switch means is made non-conductive to cut off the connection between the other terminal of the second capacitive element and the reference voltage V3, and the second voltage V2 In a first state in which the first switch means is made non-conductive and the second switch means is not electrically connected to the second electrode via the fourth voltage supply section and the tenth switch means. The first voltage V1 to the one terminal of the first capacitive element is turned off to cut the supply of the first terminal of the first capacitive element to the reference voltage V3; The first switch means is made nonconductive and the first switch means is nonconductive. The connection between the other terminal of the capacitive element and the reference voltage V3 is cut off, and the second voltage V2 is supplied to the first electrode via the second voltage supply unit and the fifth switch means. And the sixth switch means is turned on and the seventh switch means is turned off to pass the first voltage V1 through the third voltage supply section and the ninth switch means. The second voltage is supplied to the second electrode, the first voltage V1 is supplied to the one terminal of the second capacitive element, and the eighth switch means is turned on to connect the second capacitive element. The second terminal is used as the reference voltage V3, and the second state in which the first capacitive element V1 is charged to the second capacitive element is alternately performed to perform a sustain discharge, and the first electrode One terminal of the drive circuit has the second voltage A third capacitive element connected to the supply unit; a coil, a switching element, and a diode between the other terminal of the third capacitive element and the first electrode; A first power recovery circuit disposed on each of two paths, a path for recovering the electric charge and a path for supplying the electric charge to the first electrode, and one terminal of the second electrode drive circuit is the first 4, a fourth capacitive element connected to the voltage supply unit 4, and a coil, a switching element, and a diode between the other terminal of the fourth capacitive element and the second electrode, And a second power recovery circuit disposed on each of two paths, a path for collecting charges from the electrode and a path for supplying charges to the second electrode.
[0055]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a configuration example of the drive device according to the present embodiment, and here, only the elemental features of the present invention are shown.
The drive device of this embodiment shown in FIG. 1 can be applied to a flat display device such as an AC drive type PDP device, for example. The overall configuration and the cross-sectional configuration of one cell in this case are shown in FIG. It is as shown in FIG.
[0056]
In FIG. 1, reference numeral 42 denotes an A / D converter which A / D converts an AC power supply voltage supplied from an AC power supply 41 to generate a DC power supply voltage. At this time, the A / D converter 42 generates a voltage (Vs / 2) that is half the sustain pulse voltage Vs, for example.
[0057]
Reference numeral 43 denotes a power supply circuit, which switches between positive and negative voltages (+ Vs / 2, −Vs / 2) using the voltage (Vs / 2) supplied from the A / D converter 42 and outputs it. Reference numeral 44 denotes a driver circuit which applies a power supply voltage (± Vs / 2) supplied from the power supply circuit 43 to the load 20.
[0058]
The power supply circuit 43 and the driver circuit 44 are connected by a first signal line OUTA and a second signal line OUTB. The power supply circuit 43 and the driver circuit 44 are connected to the common electrode X side of the load 20 corresponding to the panel of the PDP, and constitute the X-side circuit 2 of FIG.
[0059]
Reference numeral 43 ′ denotes a power supply circuit, and 44 ′ denotes a driver circuit, which includes the same configuration as the power supply circuit 43 and the driver circuit 44. The power supply circuit 43 ′ and the driver circuit 44 ′ are connected by a third signal line OUTA ′ and a fourth signal line OUTB ′. These power supply circuit 43 ′ and driver circuit 44 ′ are connected to the scan electrode Y side of the load 20, and constitute the Y-side circuit 3 of FIG.
[0060]
In this embodiment, the power supply voltage (Vs / 2) and the ground voltage output from the A / D converter 42 are supplied to both the power supply circuit 43 for the common electrode X and the power supply circuit 43 ′ for the scan electrode Y. I am trying to supply. That is, one A / D converter 42 is shared by the two power supply circuits 43 and 43 ′.
[0061]
The operation of the drive device configured as described above is as follows. For example, in the sustain discharge period, the power supply circuit 43 for the common electrode X supplies a voltage (+ Vs / 2, 0) to the first signal line OUTA and a voltage (0, − to the second signal line OUTB. Vs / 2) are alternately output. At this time, the power supply circuit 43 ′ for the scan electrode Y applies a voltage (0, + Vs / 2) to the third signal line OUTA ′ and a voltage (−Vs / 2, to the fourth signal line OUTB ′. 0) are alternately output in the opposite phase to the power supply circuit 43 for the common electrode X.
[0062]
The driver circuit 44 for the common electrode X outputs the voltage output to the first signal line OUTA and the second signal line OUTB to the output line OUTC and applies it to the load 20. The driver circuit 44 ′ for the scan electrode Y applies the voltage output to the third signal line OUTA ′ and the fourth signal line OUTB ′ to the load 20 via the output line OUTC ′.
[0063]
Thus, when the voltage (+ Vs / 2) of the first signal line OUTA is applied to the common electrode X of the load 20 via the output line OUTC, the voltage of the fourth signal line OUTB ′ is applied to the scanning electrode Y. (−Vs / 2) is applied via the output line OUTC ′. Conversely, when the voltage (−Vs / 2) of the second signal line OUTB is applied to the common electrode X of the load 20 via the output line OUTC, the scan electrode Y has the third signal line OUTA ′. A voltage (+ Vs / 2) is applied via the output line OUTC ′.
[0064]
That is, in the present embodiment, the voltage (± Vs / 2) applied to each of the common electrode X and the scanning electrode Y is applied so that the phases are reversed. In this way, the potential difference between the common electrode X and the scan electrode Y can be set to the same voltage Vs as the sustain pulse, and the state shown in the sustain discharge period of FIG. A state similar to the state in which the sustain pulse voltage Vs is alternately applied can be created.
[0065]
In this case, the absolute value of the voltage applied to the power supply circuits 43 and 43 ′ and the driver circuits 44 and 44 ′ is Vs / 2 at the maximum. Therefore, the withstand voltage of each element provided in these circuits may be set to Vs / 2, and the withstand voltage can be suppressed to half of the conventional one. As a result, an inexpensive element having a small configuration can be used, and the circuit configuration can be simplified and the manufacturing cost can be reduced.
[0066]
Further, according to the driving apparatus of the present embodiment, the voltage to be applied to the load is Vs / 2 at the maximum, and may be half the voltage of Vs. Therefore, the period of applying the voltage to the load is twice that of the conventional one. Even if the increase in power consumption due to this is taken into consideration, the power loss as a whole can be reduced as compared with the conventional case where Vs itself is applied to the load 20.
[0067]
Further, according to the driving apparatus of the present embodiment, it is possible to generate a positive / negative power supply voltage (± Vs / 2) based on an output voltage from one A / D power supply. To generate positive and negative power supply voltages simply, it is necessary to prepare a positive voltage power supply and a negative voltage power supply, respectively, but in this embodiment, only one A / D power supply is required. Furthermore, in the present embodiment, the common electrode X side and the scan electrode Y side share one A / D power source, so that the circuit scale can be further reduced.
[0068]
In the example of FIG. 1, the case where the absolute value of the voltage applied to the common electrode X and the absolute value of the voltage applied to the scan electrode Y are the same (both Vs / 2) has been described. If the voltage Vs is applied to both ends, the absolute value of the voltage applied to the common electrode X and the absolute value of the voltage applied to the scanning electrode Y are not necessarily the same. Further, the power supply voltage supplied from the A / D converter 42 to the power supply circuits 43 and 43 ′ is not necessarily a positive voltage.
[0069]
A specific configuration example of the power supply circuits 43 and 43 ′ and driver circuits 44 and 44 ′ shown in FIG. 1 will be described below.
[0070]
(First embodiment)
FIG. 2 is a diagram illustrating a configuration example of the driving apparatus according to the first embodiment, and the same functional blocks as those in FIG. 1 are denoted by the same reference numerals. As described above, the power supply circuit 43 for the common electrode X and the power supply circuit 43 ′ for the scan electrode Y, and the driver circuit 44 for the common electrode X and the driver circuit 44 ′ for the scan electrode Y have the same configuration. Here, only the configuration on the common electrode X side is shown as a representative here.
[0071]
As shown in FIG. 2, the power supply circuit 43 includes a capacitor C1 and three switches SW1, SW2, and SW3. The driver circuit 44 includes two switches SW4 and SW5.
[0072]
The two switches SW1 and SW2 in the power supply circuit 43 are connected in series between the power supply line of the voltage (Vs / 2) generated by the A / D converter 42 in FIG. 1 and the ground (GND). . One terminal of the capacitor C1 is connected from the middle of the two switches SW1 and SW2, and the remaining switch SW3 is connected between the other terminal of the capacitor C1 and GND.
[0073]
Further, the two switches SW4 and SW5 in the driver circuit 44 are connected in series to both ends of the capacitor C1 in the power supply circuit 43. The load 20 is connected from the middle of the switches SW4 and SW5.
[0074]
Hereinafter, an operation example of the drive device configured as shown in FIG. 2 will be described with reference to FIG. FIG. 3 is a time chart showing a detailed example of the drive waveform in the sustain discharge period by the drive device of the present embodiment.
As shown in FIG. 3, on the common electrode X side, first, the two switches SW1 and SW3 are turned on, and the remaining switches SW2, SW4 and SW5 are turned off. At this time, the voltage of the first signal line OUTA becomes a voltage level (+ Vs / 2) given from the A / D converter 42 via the switch SW1, and the voltage of the second signal line OUTB remains at the ground level. Become. The switch SW4 is turned on at the next timing a little later than this, and the switches SW4 ′ and SW2 ′ on the scanning electrode Y side are turned on, so that the voltage (+ Vs / 2) of the first signal line OUTA is changed. Applied to the load 20 via the output line OUTC. The reason why the switches SW4 ′ and SW2 ′ on the scanning electrode Y side are turned on is to apply a voltage of (Vs / 2) between the common electrode X and the scanning electrode Y.
[0075]
At this stage, the switches SW1 and SW3 are turned on and the capacitor C1 is connected to the power source. Therefore, the voltage (A) applied to the capacitor C1 by the switches SW1 and SW3 from the A / D converter 42 ( Charges corresponding to Vs / 2) are accumulated.
[0076]
At the next timing, after the switch SW4 is turned off and the current path when the voltage is applied is cut off, the switch SW5 is turned on in a pulsed manner, so that the voltage of the output line OUTC reaches the ground level. Be lowered. Next, after the switch SW2 is turned on and the remaining four switches SW1, SW3, SW4, SW5 are turned off, the switch SW4 is turned on in a pulsed manner. When the switch SW4 is turned on, it becomes a current path for applying a voltage to the scanning electrode Y side with respect to the common electrode X (ground).
[0077]
Next, the switch SW5 is turned on while the switch SW2 is kept on. At this time, since the power supply voltage is not supplied from the A / D converter 42 to the first signal line OUTA via the switch SW1, the voltage becomes the ground level. On the other hand, with respect to the second signal line OUTB, the switch SW2 is turned on and the first signal line OUTA is grounded, so that the voltage of the second signal line OUTB is changed to the charge accumulated in the capacitor C1. The potential (−Vs / 2) is lowered from the ground level by the corresponding voltage (Vs / 2). At this time, since the switch SW5 is ON, the voltage (−Vs / 2) of the second signal line OUTB is applied to the load 20 via the output line OUTC. At this time, the switches SW3 ′ and SW4 ′ on the scanning electrode Y side are turned ON, and a voltage (−Vs / 2) is applied to the common electrode X side with respect to the scanning electrode Y (Vs / 2).
[0078]
At the next timing, the switches SW2 and SW4 are turned on, and the remaining switches SW1, SW3 and SW5 are turned off. As a result, the voltage of the output line OUTC is raised to the ground level. Thereafter, as in the first stage, the three switches SW1, SW3, SW4 are turned on, the remaining two switches SW2, SW5 are turned off, and so on.
[0079]
Using the drive device having such a configuration, as shown in the output line OUTC of FIG. 3, a positive voltage (+ Vs / 2) and a negative voltage (−Vs / 2) with respect to the common electrode X of the load 20 Are applied alternately. On the other hand, a positive voltage (+ Vs / 2) and a negative voltage (−Vs / 2) are alternately applied to the scan electrode Y of the load 20 by performing the same switching control as that on the common electrode X side. I will do it.
[0080]
At this time, the voltage (± Vs / 2) applied to each of the common electrode X and the scanning electrode Y is applied so that the phases are reversed. That is, when a positive voltage (+ Vs / 2) is applied to the common electrode X, a negative voltage (−Vs / 2) is applied to the scan electrode Y. In this way, the potential difference between the common electrode X and the scan electrode Y can be set to the same voltage Vs as the sustain pulse, and the state shown in the sustain discharge period of FIG. A state similar to the state in which the sustain pulse voltage Vs is alternately applied can be created.
[0081]
FIG. 4 is a time chart showing another example of a driving waveform in the sustain discharge period by the driving apparatus of the present embodiment.
As shown in FIG. 4, first, the three switches SW1, SW3, and SW4 are turned on, and the remaining switches SW2 and SW5 are turned off. At this time, the voltage of the first signal line OUTA becomes a voltage level (+ Vs / 2) given from the A / D converter 42 via the switch SW1, and the voltage of the second signal line OUTB remains at the ground level. Become. Since the switch SW4 is ON, the voltage (+ Vs / 2) of the first signal line OUTA is applied to the load 20 via the output line OUTC.
[0082]
At this stage, the switches SW1 and SW3 are turned on and the capacitor C1 is connected to the power source. Therefore, the voltage (A) applied to the capacitor C1 from the A / D converter 42 via the switch SW1 ( Charges corresponding to Vs / 2) are accumulated.
[0083]
At the next timing, all the five switches SW1 to SW5 are turned off. At this time, the first signal line OUTA becomes high impedance and maintains the voltage (Vs / 2), and the output line OUTC also maintains the voltage (Vs / 2).
[0084]
Next, the two switches SW2 and SW5 are turned on, and the remaining three switches SW1, SW3 and SW4 are kept off. At this time, since the power supply voltage is not supplied from the A / D converter 42 to the first signal line OUTA via the switch SW1, the voltage becomes the ground level.
[0085]
On the other hand, with respect to the second signal line OUTB, the switch SW2 is turned on and the first signal line OUTA is grounded, so that the voltage of the second signal line OUTB is changed to the charge accumulated in the capacitor C1. The potential (−Vs / 2) is lowered from the ground level by the corresponding voltage (Vs / 2). At this time, since the switch SW5 is ON, the voltage (−Vs / 2) of the second signal line OUTB is applied to the load 20 via the output line OUTC.
[0086]
At the next timing, all the five switches SW1 to SW5 are turned off again. Thus, the second signal line OUTB becomes high impedance and maintains the voltage (−Vs / 2), and the output line OUTC also maintains the voltage (−Vs / 2). Thereafter, as in the first stage, the three switches SW1, SW3, SW4 are turned on, the remaining two switches SW2, SW5 are turned off, and so on.
[0087]
As described above, in the driving apparatus according to the first embodiment shown in FIG. 2, the voltage fluctuates between the Vs / 2 level and the ground level according to ON / OFF of the capacitor C1 and the switches SW1 to SW3. A signal line OUTA and a second signal line OUTB whose voltage varies between the ground level and the −Vs / 2 level are provided, and a driver circuit for the load 20 is provided between the first and second signal lines. There is a feature.
[0088]
By using the driving device having such a configuration, the switches SW4 and SW5 in the driver circuit are turned on / off, and as shown by the output line OUTC in FIG. A voltage (+ Vs / 2) and a negative voltage (−Vs / 2) are applied alternately. On the other hand, the scanning electrode Y of the load 20 is also driven by the power supply circuit 43 ′ and the driver circuit 44 ′, so that a positive voltage (+ Vs / 2) and a negative voltage (−Vs / 2) are obtained. Are applied alternately.
[0089]
At this time, the voltage (± Vs / 2) applied to each of the common electrode X and the scanning electrode Y is applied so that the phases are reversed. That is, when a positive voltage (+ Vs / 2) is applied to the common electrode X, a negative voltage (−Vs / 2) is applied to the scan electrode Y. In this way, the potential difference between the common electrode X and the scan electrode Y can be set to the same voltage Vs as the sustain pulse, and the state shown in the sustain discharge period of FIG. A state similar to the state in which the sustain pulse voltage Vs is alternately applied can be created.
[0090]
In this case, the absolute value of the voltage applied to the power supply circuits 43 and 43 ′ and the driver circuits 44 and 44 ′ is Vs / 2 at the maximum. Therefore, the withstand voltage of each element provided in these circuits may be set to Vs / 2, and the withstand voltage can be suppressed to half of the conventional one. As a result, an inexpensive element having a small configuration can be used, and the circuit configuration can be simplified and the manufacturing cost can be reduced.
[0091]
Further, according to the driving apparatus of the present embodiment, the voltage to be applied to the load is Vs / 2 at the maximum, and may be half the voltage of Vs. Therefore, the period of applying the voltage to the load is twice that of the conventional one. Even if the increase in power consumption due to this is taken into consideration, the power loss as a whole can be reduced as compared with the conventional case where Vs itself is applied to the load 20.
[0092]
FIG. 5 is a diagram showing a specific configuration example of the drive device to which the feature of the first embodiment shown in FIG. 2 is applied. In FIG. 5, the same reference numerals as those shown in FIGS. 2 and 102 have the same functions.
[0093]
In FIG. 5, on the common electrode X side, the switches SW1 and SW2 are connected to the power supply line and ground (GND) of the voltage (Vs / 2) generated by the A / D converter 42 of FIG. 1 (not shown in FIG. 5). Connected in series. One terminal of the capacitor C1 is connected from the middle of the two switches SW1 and SW2, and the switch SW3 is connected between the other terminal of the capacitor C1 and GND.
[0094]
The switches SW4 and SW5 are connected in series to both ends of the capacitor C1. The common electrode X of the load 20 is connected from the middle of these two switches SW4 and SW5.
[0095]
On the other hand, on the scan electrode Y side, the switches SW1 ′ and SW2 ′ are connected in series between the power supply line of the voltage (Vs / 2) generated by the A / D converter 42 of FIG. 1 and GND. One terminal of the capacitor C4 is connected between the two switches SW1 ′ and SW2 ′, and the switch SW3 ′ is connected between the other terminal of the capacitor C4 and GND.
[0096]
The switch SW4 ′ connected to one terminal of the capacitor C4 is connected to the cathode of the diode D14, and the anode of the diode D14 and the other terminal of the capacitor C4 are connected. The switch SW5 ′ connected to the other terminal of the capacitor C4 is connected to the anode of the diode D15, and the cathode of the diode D15 and one terminal of the capacitor C4 are connected. A load 20 is connected to the switch SW4 ′ connected to the cathode of the diode D14 and the switch SW5 ′ connected to the anode of the diode D15 via one end of the scan driver 31 ′. Although only one scan driver 31 ′ is shown in FIG. 5, this is actually provided for each of a plurality of display lines provided in the PDP. The other circuits are common circuits provided in common for the plurality of display lines.
[0097]
Here, each of the switches SW1 to SW5 and SW1 ′ to SW5 ′ shown in FIG. 5 is constituted by, for example, a MOSFET and a diode connected to the MOSFET as necessary.
[0098]
For example, the switches SW1 and SW1 ′ are configured by a p-channel or n-channel MOSFET connected to the Vs / 2 power line and a diode in which the drain of the p-channel MOSFET or the source of the n-channel MOSFET is connected to the anode. Is done.
[0099]
The switches SW2 and SW2 ′ are configured to include an n-channel MOSFET connected to the GND power supply line, and a diode having the drain of the n-channel MOSFET connected to the cathode.
[0100]
The switches SW3 and SW3 ′ can be configured in the same manner as the switches SW2 and SW2 ′. However, as shown in FIG. 5, two sets of the above-described MOSFET and diode connected in series are used. And connected in parallel to the ground. Alternatively, for example, as shown in FIG. 6A, the sources of the two MOSFETs may be connected in common, and the common source of the MOSFETs may be connected to the anodes of the two diodes. If the switches SW3 and SW3 ′ are configured as shown in FIG. 5 or FIG. 6A, current can flow in both directions when the switches SW3 and SW3 ′ are ON, and are completely cut off when they are OFF. And more stable operation can be realized.
[0101]
Further, these switches SW1 to SW2, SW1 ′ to SW2 ′ may be configured by IGBT (Insulated Gate Bipolar Transistor) elements as shown in FIG. As for the switches SW3 and SW3 ′, as shown in FIG. 6C, one of the two sets of switching elements composed of a MOSFET and a diode may be constituted by an IGBT element. This IGBT element is a three-terminal bipolar-MOS composite element, and has a smaller operating resistance and less loss than a MOSFET. Further, since the current does not flow in the reverse direction, there is an advantage that it is not necessary to provide a diode.
[0102]
In the drive device configured as described above, the common electrode X and the scan electrode Y are controlled by switching the switches SW1 to SW5 on the common electrode X side and the switches SW1 ′ to SW5 ′ on the scan electrode Y side as described above. On the other hand, positive and negative voltages (± Vs / 2) having opposite phases to each other are applied.
[0103]
In the sustain discharge period, the timing for applying the voltage (+ Vs / 2, −Vs / 2) to the common electrode X and the timing for applying the reverse-phase voltage (−Vs / 2, + Vs / 2) to the scanning electrode Y. May not necessarily be the same timing, and the application timing of both voltages may be slightly shifted. For example, if the voltage applied to one electrode reaches a steady state and then the opposite phase voltage is applied to the other electrode, the sustain discharge can be operated more stably.
[0104]
Also, the time during which the pulse voltage is applied to the electrodes X and Y does not necessarily have to be the same. The voltage application timing and application time for the common electrode X and the scan electrode Y can be adjusted by controlling the ON / OFF timing of the switches SW4, SW4 ′, SW5, SW5 ′, for example.
[0105]
The ON / OFF control of the switches SW1 to SW5 and SW1 ′ to SW5 ′ can be performed according to a program recorded on a recording medium such as a ROM. If it does in this way, the waveform of an applied voltage can be changed freely by replacing ROM.
[0106]
7 to 13 are diagrams showing various examples of drive waveforms of pulse voltages applied to the electrodes X and Y during the sustain discharge period.
The drive waveform shown in FIG. 7 is such that the timing of applying the positive voltage (+ Vs / 2) is always earlier than the timing of applying the negative voltage (−Vs / 2), and the applied positive voltage (+ Vs / In this example, the timing at which 2) is returned to the ground level is always delayed from the timing at which the applied negative voltage (−Vs / 2) is returned to the ground level. That is, after the positive voltage (+ Vs / 2) applied to one electrode of the common electrode X or the scanning electrode Y reaches a steady state, the negative voltage (−Vs / 2) is applied to the other electrode. Further, after the ground level voltage returned from the negative voltage (−Vs / 2) at one electrode reaches the steady state, the voltage of the other electrode is returned from the positive voltage (+ Vs / 2) to the ground level. .
[0107]
Further, in the example of FIG. 7, the pulse width of the negative voltage (−Vs / 2) is made narrower than the pulse width of the positive voltage (+ Vs / 2), and the negative voltage is applied while the positive voltage is applied. The voltage is returned to the ground level. By doing so, the sustain discharge can be operated more stably.
[0108]
The drive waveform shown in FIG. 8 is an example in which positive and negative are opposite to the example shown in FIG. That is, this means that the timing for applying the negative voltage (−Vs / 2) is always earlier than the timing for applying the positive voltage (+ Vs / 2), and the applied negative voltage (−Vs / 2). This is an example in which the timing for returning the voltage to the ground level is always delayed from the timing for returning the applied positive voltage (+ Vs / 2) to the ground level. That is, after the negative voltage (−Vs / 2) applied to one electrode reaches a steady state, the positive voltage (+ Vs / 2) is applied to the other electrode. Further, after the ground level voltage returned from the positive voltage (+ Vs / 2) at one electrode reaches the steady state, the voltage of the other electrode is returned from the negative voltage (−Vs / 2) to the ground level. .
[0109]
Further, in the example of FIG. 8, the pulse width of the positive voltage (+ Vs / 2) is made narrower than the pulse width of the negative voltage (−Vs / 2), and the positive voltage is applied while the negative voltage is applied. The voltage is returned to the ground level. By doing so, the sustain discharge can be operated more stably.
[0110]
The drive waveform shown in FIG. 9 is an example when a negative voltage (−Vs / 2) is used as a reference voltage. That is, the voltage of the electrodes X and Y is both set to (−Vs / 2) at the timing when the sustain pulse is not applied in the sustain discharge period, and the voltage of one electrode is set at the timing when the discharge is actually performed by applying the sustain pulse. Is raised to (+ Vs / 2). In the example of FIG. 9, as in the example of FIG. 8, the pulse width of the negative voltage (−Vs / 2) is wider than the pulse width of the positive voltage (+ Vs / 2).
[0111]
As shown in the drive waveform shown in FIG. 9, when the voltage of one electrode is changed, the voltage of the other electrode is fixed, whereby the sustain discharge can be operated more stably. Moreover, a predetermined voltage can be applied between both electrodes only by changing the voltage of one electrode.
[0112]
The drive waveform shown in FIG. 10 is an example in which positive and negative are opposite to those in the example shown in FIG. 9, and is an example in which a positive voltage (+ Vs / 2) is used as a reference voltage. That is, the voltage of the electrodes X and Y is both set to (+ Vs / 2) at the timing when the sustain pulse is not applied in the sustain discharge period, and the voltage of one electrode is set at the timing when the discharge is actually performed by applying the sustain pulse. The voltage is lowered to (−Vs / 2). In the example of FIG. 10, as in the example of FIG. 7, the pulse width of the positive voltage (+ Vs / 2) is wider than the pulse width of the negative voltage (−Vs / 2).
[0113]
As shown in the driving waveform shown in FIG. 10, when the voltage of one electrode is varied, the voltage of the other electrode is fixed, whereby the sustain discharge can be operated more stably. Moreover, a predetermined voltage can be applied between both electrodes only by changing the voltage of one electrode.
[0114]
The drive waveform shown in FIG. 11 uses the negative voltage (−Vs / 2) as a reference voltage, and the voltage of one electrode is (+ Vs / 2) at the timing of actual discharge, similarly to the drive waveform shown in FIG. ). In the example of FIG. 11, after the discharge is performed, the other electrode is raised to a positive voltage (+ Vs / 2) before returning the voltage of the one electrode to a negative voltage (−Vs / 2). Thereafter, the voltage is returned to a negative voltage (−Vs / 2).
[0115]
For example, the voltage of the common electrode X is increased from the negative voltage (−Vs / 2) to the positive voltage (+ Vs / 2) while maintaining the voltage of the scan electrode Y at a negative voltage (−Vs / 2). As a result, a differential voltage of (Vs) is applied between both electrodes, and discharge is performed. At this time, charges are accumulated in the load 20 in accordance with the applied voltage.
[0116]
After that, before returning the voltage of the common electrode X from the positive voltage (+ Vs / 2) to the original negative voltage (−Vs / 2), the voltage of the scan electrode Y is also raised to (+ Vs / 2), thereby increasing the load. The charge accumulated in 20 is returned to the capacitor C1 on the common electrode X side. As described above, the electric power accumulated in the load 20 due to the discharge is not simply discarded, but can be saved by returning it to the capacitor C1.
[0117]
While the voltage of the common electrode X is maintained at a positive voltage (+ Vs / 2), the voltage of the scan electrode Y is also raised to the positive voltage (+ Vs / 2), whereby a positive voltage is applied to both the common electrode X and the scan electrode Y. (+ Vs / 2) is applied, and both electrodes X and Y have the same potential.
[0118]
At this time, the switches SW1 to SW5 on the common electrode X side are all turned OFF to keep the common electrode X side in a high impedance state, and the applied voltage on the scan electrode Y side is lowered to a negative voltage (−Vs / 2). Then, the voltage on the common electrode X side also follows the voltage on the scan electrode Y side due to the action of the capacitance of the load 20 and decreases to a negative voltage (−Vs / 2). At this time, charging to the load 20 is not performed, and charging power to the load 20 is zero, so there is no power loss and power saving can be achieved.
[0119]
In the drive waveform shown in FIG. 12, the pulse width of the positive voltage (+ Vs / 2) and the pulse width of the negative voltage (−Vs / 2) are the same, but a voltage is applied to the common electrode X and the scan electrode Y. This is an example in which the timings are not simultaneously set. In the example of FIG. 12, the timing for applying a voltage to the common electrode X is always set earlier than the timing for applying a voltage to the scanning electrode Y, but the reverse may be possible. By applying a negative or positive voltage to the other electrode after the positive or negative voltage applied to one electrode reaches a steady state, the instantaneous current flowing through the circuit is suppressed and maintained. It is possible to operate the discharge more stably.
[0120]
In the drive waveform shown in FIG. 13, the reference voltage is the ground level, and a positive and negative voltage (± Vs / 2) is applied to both the common electrode X and the scan electrode Y when discharging. At this time, the timing for applying the negative voltage (−Vs / 2) is always earlier than the timing for applying the positive voltage (+ Vs / 2), and the applied negative voltage (−Vs / 2) is set to the ground level. The timing to return to is always made earlier than the timing to return the applied positive voltage (+ Vs / 2) to the ground level.
[0121]
Further, in the drive waveform shown in FIG. 13, similarly to the drive waveform shown in FIG. 11, after discharging, a positive voltage (+ Vs / 2) is applied to both electrodes so as to have the same potential. After that, by keeping one electrode side at high impedance and returning the voltage of the other electrode to the ground level, the voltage of one electrode is returned to the ground level following the voltage drop of the other electrode. . At this time, charging to the load 20 is not performed, and charging power to the load 20 is zero, so there is no power loss and power saving can be achieved.
[0122]
FIG. 14 is a time chart showing a control example of the switches SW1 to SW5 and SW1 ′ to SW5 ′ for generating drive waveforms for the electrodes X and Y shown in FIG. Note that FIG. 14 is described on the assumption that charges corresponding to the voltage (Vs / 2) are accumulated in the capacitor C1 on the common electrode X side and the capacitor C4 on the scan electrode Y side in the immediately preceding subfield process. Yes.
[0123]
In the sustain discharge period, on the common electrode X side, first, the three switches SW1, SW3, SW4 are turned on, and the remaining switches SW2, SW5 are turned off. At this time, the voltage of the first signal line OUTA becomes a voltage level (+ Vs / 2) given through the switch SW1. The voltage (+ Vs / 2) of the first signal line OUTA is output to the output line OUTC via the switch SW4 and applied to the load 20.
[0124]
At this stage, the switches SW1 and SW3 are turned on and the capacitor C1 is connected to the power source. Therefore, the capacitor C1 has a voltage corresponding to the voltage (Vs / 2) applied through the switch SW1. Charge is accumulated.
[0125]
On the other hand, on the scanning electrode Y side, the switches SW1, SW3, SW4 on the common electrode X side are turned on, and at the same time, the switch SW2 ′ is turned on. Then, after a positive voltage (+ Vs / 2) is applied to the common electrode X side, the switch SW5 ′ is also turned on at an appropriate timing. In this state, the remaining three switches SW1 ′, SW3 ′, SW4 ′ are kept OFF.
[0126]
When the switch SW2 ′ is turned on and the first signal line OUTA ′ is grounded, the voltage of the fourth signal line OUTB ′ is a voltage (Vs / 2) corresponding to the charge accumulated in the capacitor C4. The potential is lowered from the ground level by the amount (−Vs / 2). Then, when the switch SW5 ′ is turned ON at an appropriate timing, the voltage (−Vs / 2) of the fourth signal line OUTB ′ is applied to the load 20 via the output line OUTC ′. As a result, a differential voltage (Vs) is applied between the electrodes X and Y of the load 20, and a sustain discharge is performed.
[0127]
After performing the sustain discharge by applying the differential voltage (Vs) to the load 20, on the common electrode X side, the switch SW4 is turned off to cut off the supply of the voltage (+ Vs / 2), and then the switch SW5 is turned on. As a result, the voltage applied to the common electrode X is returned to the ground level.
[0128]
On the scanning electrode Y side, at a time before the switch SW4 is turned off on the common electrode X side, the switch SW5 ′ is turned off to cut off the supply of voltage (−Vs / 2), and then the switch SW4. Set 'to ON. As a result, the applied voltage to the scan electrode Y is returned to the ground level before the applied voltage to the common electrode X is returned to the ground level.
[0129]
At the next timing, the five switches SW1 to SW5 on the common electrode X side and the five switches SW1 ′ to SW5 ′ on the scanning electrode Y side are all turned off. Next, by performing switching control exactly opposite to the above on the common electrode X side and the scanning electrode Y side, a positive voltage (+ Vs / 2) having a wide pulse width is applied to the scanning electrode Y side, and the scanning is performed. A negative voltage (−Vs / 2) having a narrower pulse width than the electrode Y side is applied to the common electrode X side. Thereafter, similar control is repeated alternately.
[0130]
FIG. 15 is a time chart showing a control example of the switches SW1 to SW5 and SW1 ′ to SW5 ′ for generating drive waveforms for the electrodes X and Y shown in FIG. Note that FIG. 15 is explained on the assumption that charges corresponding to a voltage (Vs / 2) are accumulated in the capacitor C1 on the common electrode X side and the capacitor C4 on the scan electrode Y side in the immediately preceding subfield process. Yes.
[0131]
In the sustain discharge period, on the scanning electrode Y side, first, the two switches SW2 ′, SW5 ′ are turned on, and the remaining switches SW1 ′, SW3 ′, SW4 ′ are turned off. In this way, the switch SW2 ′ is turned on and the first signal line OUTA ′ is grounded, so that the voltage of the fourth signal line OUTB ′ is a voltage (Vs) corresponding to the electric charge accumulated in the capacitor C4. / 2) The potential is lowered from the ground level by the amount (−Vs / 2). At this time, since the switch SW5 ′ is turned ON simultaneously with the switch SW2 ′, the voltage (−Vs / 2) of the fourth signal line OUTB ′ is applied to the load 20 via the output line OUTC ′.
[0132]
On the other hand, on the common electrode X side, the switches SW2 ′ and SW5 ′ on the scanning electrode Y side are turned on and the switches SW1 and SW3 are turned on simultaneously. Then, after a negative voltage (−Vs / 2) is applied to the scanning electrode Y side, the switch SW4 is also turned on at an appropriate timing. In this state, the remaining two switches SW2 and SW5 are kept OFF.
[0133]
Thereby, the voltage of the first signal line OUTA becomes the voltage level (+ Vs / 2) at the timing when the switch SW1 is turned on. Then, the voltage (+ Vs / 2) of the first signal line OUTA is output to the output line OUTC via the switch SW4 which is turned on at an appropriate timing, and is applied to the load 20. Thereby, a differential voltage (Vs) is applied between the electrodes X and Y of the load 20.
[0134]
At this stage, the switches SW1 and SW3 are turned on and the capacitor C1 is connected to the power source. Therefore, the capacitor C1 has a voltage corresponding to the voltage (Vs / 2) applied through the switch SW1. Charge is accumulated.
[0135]
After performing the sustain discharge by applying the differential voltage (Vs) to the load 20, on the scan electrode Y side, the switch SW5 ′ is turned off to cut off the supply of the voltage (−Vs / 2), and then the switch SW4 ′. Is turned ON, the applied voltage to the scan electrode Y is returned to the ground level.
[0136]
On the common electrode X side, at a time before the switch SW5 ′ is turned off on the scanning electrode Y side, the switch SW4 is turned off to cut off the supply of voltage (+ Vs / 2), and then the switch SW5 is turned on. Set to ON. Thereby, the applied voltage to the common electrode X is returned to the ground level before the applied voltage to the scan electrode Y is returned to the ground level.
[0137]
At the next timing, the five switches SW1 to SW5 on the common electrode X side and the five switches SW1 ′ to SW5 ′ on the scanning electrode Y side are all turned off. Next, by performing switching control exactly opposite to the above on the common electrode X side and the scanning electrode Y side, a negative voltage (−Vs / 2) having a wide pulse width is applied to the common electrode X side, and A positive voltage (+ Vs / 2) having a narrower pulse width than the common electrode X side is applied to the scan electrode Y side. Thereafter, similar control is repeated alternately.
[0138]
FIG. 16 is a time chart showing a control example of the switches SW1 to SW5 and SW1 ′ to SW5 ′ for generating drive waveforms for the electrodes X and Y shown in FIG. Note that FIG. 16 illustrates that charges of voltage (Vs / 2) are accumulated in the capacitors C1 and C4 on the common electrode X side and the scan electrode Y side in the processing of the immediately preceding subfield. .
[0139]
In the sustain discharge period, on the common electrode X side, the switches SW1, SW3, SW4 are initially OFF, and the remaining switches SW2, SW5 are ON. As a result, a negative voltage (−Vs / 2) is applied to the common electrode X. Also in the scan electrode Y, the switches SW1 ′, SW3 ′, SW4 ′ are initially OFF, and the remaining switches SW2 ′, SW5 ′ are ON. Thereby, a negative voltage (−Vs / 2) is applied to the scanning electrode Y.
[0140]
At the next timing, on the common electrode X side, the switch SW5 is turned off to cut off the supply of the voltage (−Vs / 2), and then the switch SW4 is turned on. As a result, the voltage applied to the common electrode X is returned to the ground level. Further, after the switches SW2 and SW4 are turned off, the switches SW1, SW3 and SW4 are turned on. At this time, the remaining switches SW2 and SW5 remain off.
[0141]
Thereby, on the common electrode X side, the voltage of the first signal line OUTA becomes the voltage level (+ Vs / 2) given through the switch SW1. The voltage (+ Vs / 2) of the first signal line OUTA is output to the output line OUTC via the switch SW4 and applied to the load 20. At this time, since the negative voltage (−Vs / 2) is still applied to the scanning electrode Y side, the differential voltage (Vs) is applied to both the electrodes X and Y of the load 20 and the sustain discharge is performed.
[0142]
At this stage, the switches SW1 and SW3 are turned on and the capacitor C1 is connected to the power source. Therefore, the capacitor C1 has a voltage corresponding to the voltage (Vs / 2) applied through the switch SW1. Charge is accumulated.
[0143]
After performing the sustain discharge by applying the differential voltage (Vs) to the load 20, on the common electrode X side, the switch SW4 is turned off to cut off the supply of the voltage (+ Vs / 2), and then the switch SW5 is turned on. As a result, the voltage applied to the common electrode X is returned to the ground level. Further, after all the switches SW1 to SW5 are once turned off, the switches SW2 and SW5 are turned on.
[0144]
When the switch SW2 is turned on and the first signal line OUTA is grounded, the voltage of the second signal line OUTB is grounded by a voltage (Vs / 2) corresponding to the charge accumulated in the capacitor C1. The potential drops from the level (−Vs / 2). At this time, since the switch SW5 is ON, the voltage (−Vs / 2) of the second signal line OUTB is applied to the load 20 via the output line OUTC.
[0145]
After the positive voltage (+ Vs / 2) is applied to the common electrode X side and returned to the negative voltage (−Vs / 2) in this way, the same switching control is performed on the scanning electrode Y side. Thereby, also on the scanning electrode Y side, after applying the positive voltage (+ Vs / 2), the operation of returning to the state of applying the negative voltage (−Vs / 2) again is performed. Thereafter, similar control is repeated alternately.
[0146]
FIG. 17 is a time chart showing a control example of the switches SW1 to SW5 and SW1 ′ to SW5 ′ for generating drive waveforms for the electrodes X and Y shown in FIG. Note that FIG. 17 is described on the assumption that charges corresponding to the voltage (Vs / 2) are accumulated in the capacitor C1 on the common electrode X side and the capacitor C4 on the scan electrode Y side in the immediately preceding subfield process. Yes.
[0147]
In the sustain discharge period, on the common electrode X side, the switches SW1, SW3, SW4 are initially turned on and the remaining switches SW2, SW5 are turned off. Accordingly, a positive voltage (+ Vs / 2) is applied to the common electrode X side. Also on the scanning electrode Y side, the switches SW1 ′, SW3 ′, SW4 ′ are initially turned on, and the remaining switches SW2 ′, SW5 ′ are turned off. Thus, a positive voltage (+ Vs / 2) is applied to the scanning electrode Y side.
[0148]
At this stage, the switches SW1 and SW3 on the common electrode X side are turned on and the capacitor C1 is connected to the power source. Therefore, the voltage applied to the capacitor C1 via the switch SW1 (Vs / Charges according to 2) are accumulated. Similarly, since the switches SW1 ′ and SW3 ′ on the scan electrode Y side are turned on and the capacitor C4 is connected to the power source, the voltage (Vs / V) applied to the capacitor C4 via the switch SW1 ′ is set. Charges according to 2) are accumulated.
[0149]
At the next timing, on the common electrode X side, the switch SW4 is turned off to cut off the supply of voltage (+ Vs / 2), and then the switch SW5 is turned on to return the applied voltage to the common electrode X to the ground level. . Further, after all the switches SW1 to SW5 are once turned off, the switches SW2 and SW5 are turned on.
[0150]
When the switch SW2 is turned on and the first signal line OUTA is grounded, the voltage of the second signal line OUTB is grounded by a voltage (Vs / 2) corresponding to the charge accumulated in the capacitor C1. The potential drops from the level (−Vs / 2). At this time, since the switch SW5 is ON, the voltage (−Vs / 2) of the second signal line OUTB is applied to the load 20 via the output line OUTC.
[0151]
At this time, since the positive voltage (+ Vs / 2) is still applied to the scanning electrode Y side, the differential voltage (Vs) is applied to both the electrodes X and Y of the load 20 and the sustain discharge is performed. After performing the sustain discharge by applying the differential voltage (Vs) to the load 20, on the common electrode X side, the switch SW5 is turned off to cut off the supply of the voltage (−Vs / 2), and then the switch SW4 is turned on. And As a result, the voltage applied to the common electrode X is returned to the ground level.
[0152]
Further, after all the switches SW1 to SW5 are turned off, the switches SW1, SW3, and SW4 are turned on. At this time, the remaining switches SW2 and SW5 remain off. Thereby, a positive voltage (+ Vs / 2) is again applied to the common electrode X side.
[0153]
After the negative voltage (−Vs / 2) is applied to the common electrode X in this way and returned to the positive voltage (+ Vs / 2) again, the same switching control is performed on the scanning electrode Y. Thereby, also on the scanning electrode Y side, after applying the negative voltage (−Vs / 2), the operation of returning to the state of applying the positive voltage (+ Vs / 2) again is performed. Thereafter, similar control is repeated alternately.
[0154]
FIG. 18 is a time chart showing a control example of the switches SW1 to SW5 and SW1 ′ to SW5 ′ for generating drive waveforms for the electrodes X and Y shown in FIG. Note that FIG. 18 illustrates that charges of the voltage (Vs / 2) are accumulated in the capacitors C1 and C4 on the common electrode X side and the scan electrode Y side in the immediately preceding subfield processing. .
[0155]
In the sustain discharge period, on the common electrode X side, the switches SW1, SW3, SW4 are initially OFF, and the remaining switches SW2, SW5 are ON. As a result, a negative voltage (−Vs / 2) is applied to the common electrode X. Also in the scan electrode Y, the switches SW1 ′, SW3 ′, SW4 ′ are initially OFF, and the remaining switches SW2 ′, SW5 ′ are ON. Thereby, a negative voltage (−Vs / 2) is applied to the scanning electrode Y.
[0156]
At the next timing, on the common electrode X side, the switch SW5 is turned off to cut off the supply of the voltage (−Vs / 2), and then the switch SW4 is turned on. As a result, the voltage applied to the common electrode X is returned to the ground level. Further, after the switch SW2 is turned off, the switches SW1 and SW3 are turned on. At this time, the switch SW4 remains ON and the switch SW5 remains OFF.
[0157]
Thereby, on the common electrode X side, the voltage of the first signal line OUTA becomes the voltage level (+ Vs / 2) given through the switch SW1. The voltage (+ Vs / 2) of the first signal line OUTA is output to the output line OUTC via the switch SW4 and applied to the load 20. At this time, since the negative voltage (−Vs / 2) is still applied to the scanning electrode Y side, the differential voltage (Vs) is applied to both the electrodes X and Y of the load 20 and the sustain discharge is performed.
[0158]
At this stage, the switches SW1 and SW3 are turned on and the capacitor C1 is connected to the power source. Therefore, the capacitor C1 has a voltage corresponding to the voltage (Vs / 2) applied through the switch SW1. Charge is accumulated.
[0159]
After performing the sustain discharge by applying the differential voltage (Vs) to the load 20, on the scanning electrode Y side, the switch SW5 ′ is turned off to cut off the supply of the voltage (−Vs / 2), and then the switch SW4 ′. Set to ON. As a result, the voltage applied to the scan electrode Y is returned to the ground level. Further, after the switch SW2 ′ is turned off, the switches SW1 ′ and SW3 ′ are turned on. At this time, the switch SW4 ′ remains ON and the switch SW5 ′ remains OFF.
[0160]
Thereby, on the scanning electrode Y side, the voltage of the third signal line OUTA ′ becomes a voltage level (+ Vs / 2) given through the switch SW1 ′. Then, the voltage (+ Vs / 2) of the third signal line OUTA ′ is output to the output line OUTC ′ via the switch SW4 ′ and applied to the load 20. At this time, since the positive voltage (+ Vs / 2) is still applied to the common electrode X side, both electrodes X and Y of the load 20 have the same potential.
[0161]
Next, on the scan electrode Y side, the switch SW4 ′ is turned off to cut off the supply of the voltage (+ Vs / 2), and then the switch SW5 ′ is turned on to return the applied voltage to the scan electrode Y to the ground level. . Further, after the switches SW1 ′ and SW3 ′ are turned off, the switch SW2 ′ is turned on. At this time, the switch SW4 ′ remains OFF and the switch SW5 ′ remains ON.
[0162]
When the switch SW2 ′ is turned on and the first signal line OUTA ′ is grounded, the voltage of the fourth signal line OUTB ′ is a voltage (Vs / 2) corresponding to the charge accumulated in the capacitor C4. The potential is lowered from the ground level by the amount (−Vs / 2). At this time, since the switch SW5 ′ is ON, the voltage (−Vs / 2) of the fourth signal line OUTB ′ is applied to the load 20 via the output line OUTC ′.
[0163]
On the other hand, on the common electrode X side, the supply of the voltage (+ Vs / 2) is cut off by turning off the switch SW4 in synchronization with the switch SW4 ′ being turned off on the scanning electrode Y side. The switch SW5 ′ of the scan electrode Y is turned ON, and the voltage of the scan electrode Y side (+ Vs / 2) is synchronized with the timing when the voltage (+ Vs / 2) falls to the ground level by the action of the load 20 capacitance. Return to ground level. Thereafter, the switches SW1 and SW3 are turned OFF in synchronization with the switches SW1 ′ and SW3 ′ being turned OFF on the scanning electrode Y side.
[0164]
Thereafter, the switch SW2 is turned on in synchronization with the switch SW2 ′ being turned on while the switch SW5 ′ on the scanning electrode Y side is turned on. As a result, the voltage on the common electrode X side decreases to a negative voltage (−Vs / 2) following the voltage on the scan electrode Y side due to the action of the capacitance of the load 20.
[0165]
After the positive voltage (+ Vs / 2) is applied to the common electrode X side in this way and returned to the negative voltage (−Vs / 2) again, the same switching control is performed on the scanning electrode Y as well. Thereby, also on the scanning electrode Y side, after applying the positive voltage (+ Vs / 2), the operation of returning to the state of applying the negative voltage (−Vs / 2) again is performed. Thereafter, similar control is repeated alternately.
[0166]
FIG. 19 is a time chart showing another example relating to the control of the switches SW1 to SW5 and SW1 ′ to SW5 ′ for generating the drive waveforms for the electrodes X and Y shown in FIG. The example shown in FIG. 19 is substantially the same as the example shown in FIG. The only difference is the timing at which the switches SW5 and SW5 ′ are turned on.
[0167]
That is, in the example of FIG. 18, a sustain discharge is performed by applying a differential voltage (Vs) to the electrodes X and Y, the voltage of both electrodes X and Y is set to the Vs level, and then the switch on the common electrode X side is turned OFF. The common electrode X is set to high impedance, and the applied voltage on the common electrode X side is lowered from (+ Vs / 2) to the ground level and from the ground level to (−Vs / 2) following the voltage drop on the scanning electrode Y side. It was. On the other hand, in the example of FIG. 19, the switch on the scanning electrode Y side is turned off to make the scanning electrode Y high impedance, and the applied voltage on the scanning electrode Y side is (+ Vs) following the voltage drop on the common electrode X side. / 2) to the ground level and from the ground level to (−Vs / 2).
[0168]
FIG. 20 is a time chart showing a control example of the switches SW1 to SW5 and SW1 ′ to SW5 ′ for generating drive waveforms for the electrodes X and Y shown in FIG. Note that FIG. 20 is described on the assumption that charges corresponding to the voltage (Vs / 2) are accumulated in the capacitor C1 on the common electrode X side and the capacitor C4 on the scan electrode Y side in the immediately preceding subfield process. Yes.
[0169]
In the sustain discharge period, on the common electrode X side, first, the switches SW1, SW3, SW4 are turned on and the switches SW2, SW5 are turned off. Thereby, the voltage of the first signal line OUTA becomes a voltage level (+ Vs / 2) given through the switch SW1. The voltage (+ Vs / 2) of the first signal line OUTA is output to the output line OUTC via the switch SW4 and applied to the load 20.
[0170]
At this stage, the switches SW1 and SW3 are turned on and the capacitor C1 is connected to the power source. Therefore, the capacitor C1 has a voltage corresponding to the voltage (Vs / 2) applied through the switch SW1. Charge is accumulated.
[0171]
On the other hand, on the scanning electrode Y side, the switch SW2 ′ is turned on at the same time as the switches SW1, SW3, SW4 on the common electrode X side are turned on, and the switch SW5 ′ is also turned on after a while. At this time, the remaining switches SW1 ′, SW3 ′, SW4 ′ are kept OFF.
[0172]
In this way, the switch SW2 ′ is turned on and the first signal line OUTA ′ is grounded, so that the voltage of the fourth signal line OUTB ′ is a voltage (Vs) corresponding to the electric charge accumulated in the capacitor C4. / 2) The potential is lowered from the ground level by the amount (−Vs / 2). Then, the switch SW5 ′ is turned on with a slight delay from the switch SW2 ′, whereby the voltage (−Vs / 2) of the fourth signal line OUTB ′ is applied to the load 20 via the output line OUTC ′. As a result, a differential voltage (Vs) is applied between the electrodes X and Y of the load 20.
[0173]
After performing the sustain discharge by applying the differential voltage (Vs) to the load 20, on the common electrode X side, the switch SW4 is turned off to cut off the supply of the voltage (+ Vs / 2) and the switch SW5 is turned on. . As a result, the voltage applied to the common electrode X is returned to the ground level. At the next timing, all the five switches SW1 to SW5 on the common electrode X side are turned off. Next, the switch SW2 is turned on, and the switch SW5 is also turned on after a while. At this time, the remaining switches SW1, SW3, SW4 are kept OFF.
[0174]
In this way, the switch SW2 is turned on and the first signal line OUTA is grounded, so that the voltage of the second signal line OUTB is a voltage (Vs / 2) corresponding to the charge accumulated in the capacitor C1. The potential is lowered from the ground level by the amount (−Vs / 2). When the switch SW5 is turned on, the voltage (−Vs / 2) of the second signal line OUTB is applied to the load 20 via the output line OUTC.
[0175]
On the other hand, on the inspection electrode Y side, before the switch SW5 is turned on on the common electrode X side, the switch SW5 ′ is turned off to cut off the supply of the voltage (−Vs / 2), and then the switch SW4. By turning on ', the applied voltage to the scan electrode Y is returned to the ground level.
[0176]
Further, by turning on the switches SW1 ′, SW3 ′, and SW4 ′ after a short delay from turning on the switch SW5 on the common electrode X side, the voltage applied to the scan electrode Y is set to a positive voltage (+ Vs / 2). increase. As described above, the timing at which the positive / negative voltage (± Vs / 2) is applied to the common electrode X can always be made earlier than the timing at which the positive / negative voltage (± Vs / 2) is applied to the scanning electrode Y. .
[0177]
FIG. 21 is a time chart showing a control example of the switches SW1 to SW5 and SW1 ′ to SW5 ′ for generating drive waveforms for the electrodes X and Y shown in FIG. Note that FIG. 21 is explained assuming that charges for the voltage (Vs / 2) are accumulated in the capacitor C1 on the common electrode X side and the capacitor C4 on the scan electrode Y side in the immediately preceding subfield processing. Yes.
[0178]
In the sustain discharge period, on the scanning electrode Y side, first, the two switches SW2 ′, SW5 ′ are turned on, and the remaining switches SW1 ′, SW3 ′, SW4 ′ are turned off. In this way, the switch SW2 ′ is turned on and the first signal line OUTA ′ is grounded, so that the voltage of the fourth signal line OUTB ′ is a voltage (Vs) corresponding to the electric charge accumulated in the capacitor C4. / 2) The potential is lowered from the ground level by the amount (−Vs / 2). At this time, since the switch SW5 ′ is turned ON simultaneously with the switch SW2 ′, the voltage (−Vs / 2) of the fourth signal line OUTB ′ is applied to the load 20 via the output line OUTC ′.
[0179]
On the other hand, on the common electrode X side, the switches SW1, SW3, SW5 are initially turned on and the switches SW2, SW4 are turned off. Then, after the switches SW2 ′ and SW5 ′ on the scanning electrode Y side are turned on, the switch SW5 is turned off and the switch SW4 is turned on. That is, the switches SW1, SW3 and SW4 are turned on and the switches SW2 and SW5 are turned off.
[0180]
Thereby, the voltage of the first signal line OUTA becomes a voltage level (+ Vs / 2) given through the switch SW1. Then, the voltage (+ Vs / 2) of the first signal line OUTA is output to the output line OUTC via the switch SW4 which is turned on at an appropriate timing, and is applied to the load 20. As a result, a differential voltage (Vs) is applied between the electrodes X and Y of the load 20 and a sustain discharge is performed.
[0181]
At this stage, the switches SW1 and SW3 are turned on and the capacitor C1 is connected to the power source. Therefore, the capacitor C1 has a voltage corresponding to the voltage (Vs / 2) applied through the switch SW1. Charge is accumulated.
[0182]
After performing the sustain discharge by applying the differential voltage (Vs) to the load 20, on the scanning electrode Y side, the switch SW5 ′ is turned off to cut off the supply of the voltage (−Vs / 2), and then the switch SW4 ′. Set to ON. As a result, the voltage applied to the scan electrode Y is returned to the ground level. Further, after the switch SW2 ′ is turned off, the switches SW1 ′ and SW3 ′ are turned on. At this time, the switch SW4 ′ remains ON and the switch SW5 ′ remains OFF.
[0183]
Thereby, on the scanning electrode Y side, the voltage of the third signal line OUTA ′ becomes a voltage level (+ Vs / 2) given through the switch SW1 ′. Then, the voltage (+ Vs / 2) of the third signal line OUTA ′ is output to the output line OUTC ′ via the switch SW4 ′ and applied to the load 20. At this time, since the positive voltage (+ Vs / 2) is still applied to the common electrode X side, both electrodes X and Y of the load 20 have the same potential.
[0184]
Next, on the scan electrode Y side, the switch SW4 ′ is turned off to cut off the supply of the voltage (+ Vs / 2), and then the switch SW5 ′ is turned on to return the applied voltage to the scan electrode Y to the ground level. .
[0185]
On the other hand, on the common electrode X side, the switch SW4 is turned OFF in synchronization with the switch SW4 ′ being turned OFF on the scanning electrode Y side. At this time, since the switch SW5 is also OFF, the common electrode X is in a high impedance state. By doing so, the voltage on the common electrode X side decreases to the ground level following the voltage on the scan electrode Y side by the action of the capacitance of the load 20.
[0186]
In this way, a negative voltage (−Vs / 2) is applied to the scanning electrode Y side, a positive voltage (+ Vs / 2) is applied to the common electrode X side, and the voltages of both electrodes X and Y are set to the ground level. After returning to, switching control reverse to this is continued. As a result, a positive voltage (+ Vs / 2) is applied to the scanning electrode Y side, and a negative voltage (−Vs / 2) is applied to the common electrode X side. Thereafter, similar control is repeated alternately.
[0187]
FIG. 22 is a time chart showing another example relating to the control of the switches SW1 to SW5 and SW1 ′ to SW5 ′ for generating the drive waveforms for the electrodes X and Y shown in FIG. The example shown in FIG. 22 is almost the same as the example shown in FIG. The only difference is the timing at which the switches SW5 and SW5 ′ are turned on.
[0188]
That is, in the example of FIG. 21, after performing a sustain discharge by applying a differential voltage (Vs) to the electrodes X and Y, the switches SW4 and SW5 of the common electrode X are turned off to set the common electrode X side to high impedance, Following the voltage drop on the scanning electrode Y side, the applied voltage on the common electrode X side is lowered to (−Vs / 2). On the other hand, in the example of FIG. 22, the switches SW4 ′ and SW5 ′ on the scan electrode Y side are turned OFF to set the scan electrode Y side to high impedance, and follow the voltage drop on the common electrode X side to follow the scan electrode Y side. The applied voltage is reduced to (−Vs / 2).
[0189]
FIG. 23 is a diagram illustrating another configuration example of the drive device according to the first embodiment. In FIG. 23, the same reference numerals as those shown in FIG. 2 or FIG. 5 have the same functions, and thus redundant description is omitted. In FIG. 23, only the configuration on the scan electrode Y side is shown in detail as a representative, but the power supply circuit 43 ′ and driver circuit on the scan electrode Y side are also included in the power supply circuit 43 and driver circuit 44 on the common electrode X side. A configuration substantially similar to that of 44 'is provided.
[0190]
This embodiment is different from the example of FIG. 5 in which only one capacitor C4 is used in that two capacitors C4 and C5 are used on the scanning electrode Y side as capacitors for charge storage. For example, an electrolytic capacitor is used for one capacitor C4, and a film capacitor is used for the other capacitor C5. Thus, by using the film capacitor C5 in addition to the electrolytic capacitor C4, a stable operation can be realized even in a high frequency region. Further, even when the electrolytic capacitor C4 is in a low temperature state where it is difficult to function as a capacitor, the operation can be supplemented by the film capacitor C5. In the example of FIG. 5 using only one capacitor C4, either a film capacitor or an electrolytic capacitor may be used as the capacitor C4.
[0191]
FIG. 24 is a time chart showing a detailed example of drive waveforms in the sustain discharge period by the drive device configured as shown in FIG. In FIG. 24, a portion indicated by a double line in the drive waveforms of the third signal line OUTA ′, the fourth signal line OUTB ′, and the output line OUTC ′ is a low impedance period, that is, the switch SW1. This is a period during which any one of “˜SW5” is ON.
[0192]
By the switching operation of the three switches SW1 ′ to SW3 ′, the voltage of the third signal line OUTA ′ is swung between the positive voltage (+ Vs / 2) and the ground level, and the fourth signal line OUTB ′ The voltage is swung between a ground level and a negative voltage (−Vs / 2), and the voltage applied to the first and second signal lines OUTA ′ and OUTB ′ is further switched to the two switches SW4 ′ and SW5. As described above, the signal is selectively output to the output line OUTC 'by the switching operation'. Therefore, detailed description thereof is omitted here.
[0193]
It should be noted in FIG. 24 that after the voltage of the first and second signal lines OUTA ′ and OUTB ′ is fixed by the switching operation of the three switches SW1 ′ to SW3 ′, the switch SW4 ′ or the switch SW5 ′ is turned on. It is a point to be. That is, in the time chart shown in FIG. 24, the timing at which the voltage is actually applied to the load 20 is determined by the timing at which the switches SW4 ′ and SW5 ′ are turned on.
[0194]
FIG. 25 is a time chart showing another example of a drive waveform in the sustain discharge period by the drive device configured as shown in FIG. It should be noted in FIG. 25 that before the voltages of the first and second signal lines OUTA ′ and OUTB ′ are fixed by the switching operation of the three switches SW1 ′ to SW3 ′, the switch SW4 ′ or the switch SW5 ′ is previously set. Is the point that is turned ON.
[0195]
In this way, at the moment when the voltage is output to the first and second signal lines OUTA ′ and OUTB ′ by the switching operation of the three switches SW1 ′ to SW3 ′, any one of the voltages is applied to the load 20. On the other hand, it can be applied immediately. Therefore, it is possible to reduce a useless period in which all of the switches SW1 ′ to SW5 ′ are OFF, and the operation speed can be increased compared to the operation illustrated in FIG.
[0196]
(Second Embodiment)
Next, a second embodiment of the present invention will be described.
FIG. 26 is a diagram illustrating a configuration example of the drive device according to the second embodiment. In FIG. 26, parts having the same functions as those of the driving apparatus shown in FIG.
[0197]
In the driving apparatus shown in FIG. 2, the switch SW4 is provided in the driver circuit 44, and is connected in series with the switch SW5 at both ends of the capacitor C1 in the power supply circuit 43. On the other hand, in the second embodiment shown in FIG. 26, the switch SW4 is provided in the power supply circuit 43 and is connected between one terminal of the capacitor C1 and the first signal line OUTA. Other configurations are the same as those in FIG.
[0198]
In the configuration shown in FIG. 26, when charges are accumulated in the capacitor C1 while applying a positive voltage (+ Vs / 2) to the load 20 via the output line OUTC, the switches SW1, SW3 and SW4 are turned on. Is the same as in the first embodiment. In addition, when applying a negative voltage (−Vs / 2) to the load 20 through the output line OUTC using the electric charge accumulated in the capacitor C1, the switches SW2 and SW5 are also turned on. This is the same as the embodiment. In this case, various patterns can be applied to the driving waveform of the applied voltage to the common electrode X and the scanning electrode Y in the same manner as described in the first embodiment.
[0199]
According to the second embodiment configured as described above, when voltage is applied to the load 20, the total number of voltage drops due to the current passing through the switch can be reduced, and power loss can be suppressed. . That is, when a positive voltage (+ Vs / 2) is applied to the load 20, in the case of the first embodiment, the current passes through the two switches SW1 and SW4, whereas the second embodiment. In this case, a positive voltage (+ Vs / 2) is applied to the load 20 via the output line OUTC only through one switch SW1. Therefore, the voltage drop can be reduced by one switch.
[0200]
FIG. 26 shows a case where both the power supply circuit 43 and the driver circuit 44 are configured as circuits common to all the display lines provided in the PDP. As in the ninth embodiment, it is possible to adopt an LSI configuration in which this is provided for each display line. When the driver circuit 44 has an LSI configuration as described above, the first embodiment requires two switches SW4 and SW5 for each display line. In the second embodiment, the switches necessary for each display line. Requires only one switch SW5, and the total number of switches can be greatly reduced. As a result, the circuit scale can be reduced and the cost can be suppressed.
[0201]
FIG. 27 is a diagram illustrating another configuration example of the driving apparatus according to the second embodiment. In FIG. 27, the same reference numerals as those shown in FIG. 23 have the same functions, and therefore, duplicate description is omitted.
[0202]
In the example of FIG. 27, the switch SW4 ′ is provided in the power supply circuit 43 ′ and is connected between one terminal of each of the capacitors C4 and C5 and the third signal line OUTA ′. As a result, the three switches SW1 ′, SW4 ′, and SW2 ′ are connected in series between the power supply line of the voltage (Vs / 2) and the ground. Other configurations are the same as those in FIG.
[0203]
FIG. 28 is a time chart showing a detailed example of the drive waveform in the sustain discharge period by the drive device configured as shown in FIG.
The basic operation of alternately applying a positive or negative voltage (± Vs / 2) to the output line OUTC ′ by switching control of the five switches SW1 ′ to SW5 ′ is the same as in the first embodiment described above. . Therefore, detailed description is omitted here.
[0204]
It should be noted in FIG. 28 that when the positive voltage (+ Vs / 2) is output to the output line OUTC ′, the three switches SW1 ′, SW3 ′, SW4 ′ are turned on. The timing of turning on is explicitly earlier than the timing of turning on the switches SW1 ′ and SW4 ′.
[0205]
When control is performed so that a plurality of switches are switched simultaneously, the plurality of switches are not always switched simultaneously due to various factors including manufacturing variations of elements, and a slight time difference may occur. In this case, the switch SW3 ′ may be turned on earlier than the switches SW1 ′ and SW4 ′ are turned on. However, if the switch SW3 ′ is turned on, the timing is delayed. The circuit may not work well. Therefore, in the example of FIG. 28, the timing of turning on the switch SW3 ′ is explicitly advanced to ensure that the circuit operates stably.
[0206]
In the example of FIG. 28, when the two switches SW2 ′ and SW5 ′ are turned on to output a negative voltage (−Vs / 2) to the output line OUTC ′, the switch SW2 ′ is turned on. The timing to perform is explicitly made earlier than the timing to turn on the switch SW5 ′.
[0207]
(Third embodiment)
Next, a third embodiment of the present invention will be described.
FIG. 29 is a diagram illustrating a configuration example of the driving apparatus according to the third embodiment. In FIG. 29, parts having the same functions as those of the driving apparatus shown in FIG. 2 are denoted by the same reference numerals, and redundant description is omitted.
[0208]
In the driving apparatus shown in FIG. 2, the switch SW5 is provided in the driver circuit 44, and is connected in series with the switch SW4 to both ends of the capacitor C1 in the power supply circuit 43. On the other hand, in the third embodiment shown in FIG. 29, the switch SW5 is provided in the power circuit 43 and is connected between the other terminal of the capacitor C1 and the second signal line OUTB. Other configurations are the same as those in FIG.
[0209]
In the configuration shown in FIG. 29, when a positive voltage (+ Vs / 2) is applied to the load 20 via the output line OUTC, for example, the switches SW1 and SW4 are turned ON. Further, when a negative voltage (−Vs / 2) is applied to the load 20 via the output line OUTC using the electric charge accumulated in the capacitor C1, the switches SW2 and SW5 are turned on. In this case, various patterns can be applied to the driving waveform of the applied voltage to the common electrode X and the scanning electrode Y in the same manner as described in the first embodiment.
[0210]
According to the third embodiment configured as described above, the total number of voltage drops due to the current passing through the switch can be reduced at the timing of discharging the charge accumulated in the capacity of the load 20, and the power loss can be reduced. Can be suppressed. That is, in order to return the positive voltage (+ Vs / 2) applied to the load 20 to the ground level, when the charge accumulated in the load 20 is caused to flow to the ground, in the case of the first embodiment, the switches SW5 and SW3 Current passes through the two switches. On the other hand, in the third embodiment, discharging can be performed only through one switch SW3. Therefore, the voltage drop can be reduced by one switch compared to the first embodiment.
[0211]
Further, when the driver circuit 44 has an LSI configuration as in the eighth and ninth embodiments described later, the first embodiment requires two switches SW4 and SW5 for each display line. In the third embodiment, only one switch SW4 is required for each display line, and the total number of switches can be greatly reduced. As a result, the circuit scale can be reduced and the cost can be suppressed.
[0212]
FIG. 30 is a diagram illustrating another configuration example of the driving apparatus according to the third embodiment. In FIG. 30, those given the same reference numerals as those shown in FIG. 23 have the same functions, and redundant description is omitted.
[0213]
In the example of FIG. 30, the switch SW5 ′ is provided in the power supply circuit 43 ′, and is connected between the other terminals of the capacitors C4 and C5 and the fourth signal line OUTB ′. Other configurations are the same as those in FIG.
[0214]
FIG. 31 is a time chart showing a detailed example of drive waveforms in the sustain discharge period by the drive device configured as shown in FIG.
The basic operation of alternately applying a positive or negative voltage (± Vs / 2) to the output line OUTC ′ by switching control of the five switches SW1 ′ to SW5 ′ is the same as in the first embodiment described above. . Therefore, detailed description is omitted here.
[0215]
It should be noted in FIG. 31 that when the switches SW1 ′ and SW4 ′ are turned on and a positive voltage (+ Vs / 2) is applied to the load 20, the switches SW3 ′ and SW5 ′ are not turned on and the positive voltage is applied. The switch SW3 ′ and SW5 ′ are turned on when the charge accumulated in the load 20 is discharged by applying (+ Vs / 2) and the applied voltage is returned to the ground level. In the example of FIG. 31, by keeping the switch SW1 ′ in the ON state until the switch SW3 ′ is turned on, the charges are accumulated in the capacitors C4 and C5 at the timing when the charge of the load 20 is discharged. Yes. By doing in this way, switching of each switch SW1'-SW5 'can be performed more efficiently without waste.
[0216]
In the example of FIG. 31, the timing for turning on the switch SW1 ′ is explicitly set earlier than the timing for turning on the switch SW4 ′. As in the second embodiment described with reference to FIG. 28, the switch SW1 ′ and SW4 ′ are not switched at the same time, and the switch SW1 ′ is turned on explicitly earlier. The circuit can operate stably.
[0217]
In the example of FIG. 31 also, when the two switches SW2 ′ and SW5 ′ are turned on in order to output the negative voltage (−1 Vs / 2) to the output line OUTC ′, the switch SW2 ′ is turned on. The timing to perform is explicitly made earlier than the timing to turn on the switch SW5 ′.
[0218]
(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described.
FIG. 32 is a diagram illustrating a configuration example of the drive device according to the fourth embodiment. In FIG. 32, parts having the same functions as those of the driving apparatus shown in FIG. 2 are denoted by the same reference numerals, and redundant description is omitted.
[0219]
The fourth embodiment shown in FIG. 32 further includes an offset circuit 45 in addition to the configuration shown in FIG. The offset circuit 45 is configured to be connected from the ground to the first signal line OUTA via the power supply of the offset voltage Vbp and the switch SW6, and from the ground to the first signal line OUTA via the power supply of the offset voltage Vbn and the switch SW7. And a configuration to be connected to.
[0220]
With such a configuration, when the switch SW6 is ON, a positive voltage (+ Vbp) is output from the offset circuit 45 to the first signal line OUTA. Further, when the switch SW7 is ON, a negative voltage (−Vbn) is output from the offset circuit 45 to the first signal line OUTA. Therefore, a voltage using this offset voltage (+ Vbp or −Vbn) can be applied to the load 20 from the first signal line OUTA via the output line OUTC. In addition, a potential that is lowered from the offset voltage level (+ Vbp or −Vbn) by the voltage (Vs / 2) corresponding to the electric charge accumulated in the capacitor C1 by using the offset voltage is set to the second signal line OUTB. A voltage can also be applied to the load 20 via the output line OUTC.
[0221]
As described above, according to the fourth embodiment, by providing the offset circuit 45, a voltage other than (± Vs / 2) can be output to the first signal line OUTA and the second signal line OUTB. The degree of freedom of the voltage applied to the load 20 can be increased. For example, the offset circuit 45 can generate a voltage used outside the sustain discharge period.
[0222]
FIG. 33 is a diagram illustrating another configuration example of the driving apparatus according to the fourth embodiment. In FIG. 33, those given the same reference numerals as those shown in FIGS. 23 and 32 have the same functions, and thus redundant description is omitted.
In the example of FIG. 33, an offset circuit 45 ′ configured in the same manner as the above-described offset circuit 45 on the common electrode X side is provided on the scanning electrode Y side.
[0223]
FIG. 34 is a time chart showing a detailed example of drive waveforms in the sustain discharge period by the drive device configured as shown in FIG.
Here, in particular, the state of the voltage output to the first and second signal lines OUTA ′ and OUTB ′ when the switches SW6 ′ and SW7 ′ of the offset circuit 45 ′ are turned ON is shown.
[0224]
As shown in FIG. 34, when the voltage of the third signal line OUTA ′ is the ground level and the voltage of the fourth signal line OUTB ′ is (−Vs / 2), the switch SW6 ′ of the offset circuit 45 ′ is turned on. Then, the voltage of the third signal line OUTA ′ transitions to (+ Vbp), and the voltage of the fourth signal line OUTB ′ transitions to (−Vs / 2 + Vbp). When the switch SW6 ′ is turned off and the switch SW7 ′ is turned on thereafter, the voltage of the third signal line OUTA ′ is (−Vbn), and the voltage of the fourth signal line OUTB ′ is (−Vs / 2−Vbn). ).
[0225]
In any case, the potential difference between the third signal line OUTA ′ and the fourth signal line OUTB ′ is always kept at (−Vs / 2).
In the configuration shown in FIG. 32 or FIG. 33, various patterns can be applied to the drive waveform of the voltage applied to the common electrode X and the scan electrode Y in the same manner as described in the first embodiment. .
[0226]
(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described.
In the fifth embodiment, a circuit for applying a write voltage Vw ′ (= Vs / 2 + Vw) to the scan electrode Y during the reset period, and an address for the circuits shown in the first to fourth embodiments. And a circuit for applying a voltage (−Vs / 2) to the scan electrode Y during the period.
[0227]
FIG. 35 is a diagram illustrating a specific configuration example of the drive device according to the fifth embodiment. FIG. 35 is a further application of the circuit shown in the first embodiment, and those given the same reference numerals as those shown in FIG. 5 have the same functions, and thus overlap. Description is omitted. Further, here, for convenience, a combination of an electrolytic capacitor for storing charge and a film capacitor is denoted as C1, C4.
[0228]
In the example shown in FIG. 35, a circuit for applying the write voltage Vw ′ (= Vs / 2 + Vw) is provided on the scanning electrode Y side. That is, the switch SW9 ′ is provided between the Vw power supply line for generating the write voltage and the fourth signal line OUTB ′. The switch SW9 ′ includes a resistor R1.
[0229]
In addition to the above configuration, the scan electrode Y side further includes three transistors Tr21, Tr22, Tr23 and two diodes D16, D17. When the transistor Tr21 is turned ON, the waveform of the pulse voltage applied to the scan electrode Y is blunted by the action of the resistor R2 connected thereto. The transistor Tr21 and the resistor R2 are connected in parallel with the switch SW5 ′.
[0230]
The transistors Tr22 and Tr23 are for applying a potential difference of (Vs / 2) to both ends of the scan driver 31 ′ during the address period. That is, while the switches SW2 ′ and SW5 ′ are turned ON during the sustain discharge period, the voltage on the upper side of the scan driver 31 ′ becomes (−Vs / 2) according to the charge accumulated in the capacitor C4. Because of the action of the diode in the scan driver 31 ′, the lower voltage of the scan driver 31 ′ also becomes (−Vs / 2), and a potential difference of (Vs / 2) cannot be given to both ends of the scan driver 31 ′. is there.
[0231]
On the other hand, during the address period, the switch SW2 ′ and the transistor Tr22 are turned on, whereby the voltage on the upper side of the scan driver 31 ′ is set to the ground level. At this time, when the transistor Tr23 is turned on, the negative voltage (−Vs / 2) output to the fourth signal line OUTB ′ in accordance with the electric charge accumulated in the capacitor C4 is applied to the scan driver 31 ′. A negative voltage (−Vs / 2) can be applied to the scan electrode Y when the scan driver 31 ′ outputs a scan pulse.
[0232]
One diode D16 is used when a current is supplied from the scan driver 31 ′ to the ground at a timing when a positive voltage (+ Vs / 2) is applied to the common electrode X. There are a path through which the current flows from the scan driver 31 ′ to the ground while the switch SW 2 ′ is turned on and a path through which the switches SW 3 ′ and SW 5 ′ are turned on. By providing the diode D16 in the middle, a current is allowed to flow to the ground via the switch SW2 ′. By comprising in this way, the total of the voltage drop by passing through a switch can be decreased, and a power loss can be suppressed.
[0233]
The other diode D17 is used when a current is supplied from the ground to the scan driver 31 ′ at a timing when the positive voltage (+ Vs / 2) applied to the common electrode X is returned to the ground level. As a path through which current flows from the ground to the scan driver 31 ′, the path through the switch SW3 ′, the fourth signal line OUTB ′ and the diode D17, and the switch SW2 ′, the third signal line OUTA ′ and the switch SW4 ′ are provided. Although there is a route through which the current passes, by providing a diode D17 and allowing a current to flow through this route, the total number of voltage drops can be reduced by reducing the number of stages of switches that are routed.
[0234]
FIG. 36 is a time chart showing a drive waveform on the scan electrode Y side by the drive device configured as shown in FIG. 35, and shows only the reset period and the sustain discharge period in one subfield.
[0235]
As shown in FIG. 36, in the reset period, the switches SW1 ′ and SW3 ′ are turned on to store charges corresponding to the voltage (Vs / 2) in the capacitor C4, and then the switches SW1 ′ and SW3 ′ are turned off. When the switch SW9 ′ is turned ON together with the switch SW4 ′, the voltage of the third signal line OUTA ′ is obtained by adding the voltage (Vs / 2) of the capacitor C4 and the voltage Vw of the fourth signal line OUTB ′. Raised to voltage level. Then, the voltage (Vs / 2 + Vw) is applied to the scan electrode Y of the load 20. At this time, the voltage gradually increases as shown in FIG. 36 by the action of the resistor R1 provided in the switch SW9 ′.
[0236]
Further, at this time, by applying a negative voltage (−Vs / 2) to the common electrode X, the potential difference between the common electrode X and the scanning electrode Y becomes (Vs + Vw), and the entire writing pulse shown in the reset period of FIG. The same potential difference can be applied between the common electrode X and the scanning electrode Y. In this case, the voltage applied to the element of the switch SW9 ′ is Vw at the maximum. Therefore, the withstand voltage of this element may be set to Vw, and can be suppressed to be much lower than the conventional withstand voltage.
[0237]
Further, the voltage between the third signal line OUTA ′ and the fourth signal line OUTB ′ and the voltage between the first signal line OUTA and the second signal line OUTB are always Vs / 2 or less. Therefore, the withstand voltages of the switches SW4 ′, SW5 ′, SW4, SW5 and the scan driver 31 ′ may be Vs / 2 or more. Therefore, it becomes possible to apply the voltage (Vs + Vw) of the whole surface writing pulse between the common electrode X and the scanning electrode Y in the low withstand voltage circuit, so that the manufacturing cost can be reduced.
[0238]
On the other hand, during the sustain discharge period, the switch SW9 ′ is not turned on, and the other switches SW1 ′ to SW5 ′ are controlled in the same manner as in the previous embodiments, whereby a positive / negative voltage (± Vs / 2) is applied to the load 20. The scan electrodes Y are alternately applied.
[0239]
FIG. 37 is a diagram illustrating another specific configuration example of the drive device according to the fifth embodiment. Note that in FIG. 37, the same reference numerals as those shown in FIG. 35 have the same functions, and therefore redundant description is omitted.
[0240]
In the example shown in FIG. 37, a circuit for applying the voltage Vw ′ is provided on the scanning electrode Y side. That is, the switch SW9 ′ is provided between the power supply line of the voltage Vw ′ and the fourth signal line OUTB ′. This power supply voltage Vw ′ is larger than the voltage (Vs / 2). For example, the voltage value is the same as the voltage (Vs / 2 + Vw) of the entire writing pulse applied to the load 20 during the reset period.
In such a configuration, when the voltage Vw ′ is applied to the load 20, by turning on the switch SW9 ′, the diode D17 provided in parallel with the transistor Tr23 and the diode path in the scan driver 31 ′. Through which voltage Vw ′ is applied. When this voltage Vw ′ is applied, all the switches of the scanning electrode Y other than the switch SW9 ′ are turned off.
[0241]
FIG. 38 is a time chart showing a driving waveform of the PDP by the driving device configured as shown in FIG. 37, and shows one subfield of a plurality of subfields constituting one frame. In FIG. 38, it is assumed that charges of the voltage (Vs / 2) are accumulated in the capacitor C1 on the common electrode X side and the capacitor C4 on the scan electrode Y side in the immediately preceding subfield process. Yes.
[0242]
In the reset period, first, the switches SW2 and SW5 on the common electrode X side are turned on, and the switches SW1, SW3 and SW4 are turned off. As a result, the voltage of the second signal line OUTB is lowered to (−Vs / 2) in accordance with the electric charge accumulated in the capacitor C1. The voltage (−Vs / 2) is output to the output line OUTC via the switch SW5 and applied to the common electrode X of the load 20.
[0243]
On the other hand, on the scanning electrode Y side, the switch SW9 ′ is turned on and the switches SW1 ′ to SW4 ′ are turned off. As a result, the voltage of the fourth signal line OUTB ′ is raised to the level of the voltage Vw ′ (= Vs / 2 + Vw) given through the switch SW9 ′. The voltage Vw ′ is output to the output line OUTC ′ via the diode D17 and the diode in the scan driver 31 ′, and is applied to the scan electrode Y of the load 20.
[0244]
As a result, the potential difference between the common electrode X and the scan electrode Y becomes (Vs + Vw), and the same potential difference as that of the entire writing pulse shown in the reset period of FIG. 101 can be applied between the common electrode X and the scan electrode Y. In this case, the maximum voltage applied to the element of the switch SW9 ′ is Vw ′ = (Vs / 2 + Vw). Therefore, the withstand voltage of this element may be (Vs / 2 + Vw), which can be kept lower than the conventional withstand voltage.
[0245]
Further, the voltage between the third signal line OUTA ′ and the fourth signal line OUTB ′ and the voltage between the first signal line OUTA and the second signal line OUTB are always Vs / 2 or less. Therefore, the withstand voltages of the switches SW4 ′, SW5 ′, SW4, SW5 and the scan driver 31 ′ may be Vs / 2 or more. Therefore, it is possible to apply the voltage Vw ′ = (Vs + Vw) of the full write pulse between the common electrode X and the scan electrode Y in the low withstand voltage circuit, thereby realizing a reduction in manufacturing cost.
[0246]
In this reset period, the voltage applied to the scan electrode Y with the switch SW9 ′ turned ON is a waveform (this is called an obtuse wave) in which the applied voltage continuously changes over time due to the action of the resistor R1. ). When such a blunt wave is applied, discharge is sequentially performed from the cell in which the pulse voltage during the rise of the blunt wave reaches the discharge voltage. Therefore, each cell substantially has an optimum voltage (a voltage substantially equal to the discharge start voltage). ) Is applied.
[0247]
In addition, an obtuse wave whose rate of change per unit time gradually changes may be applied as a pulse whose applied voltage gradually changes over time, or a triangular wave with a constant rate of change per unit time. Etc. may be applied.
[0248]
Next, the switch SW5 on the common electrode X side is turned off, the switch SW4 is turned on, and the voltage of the common electrode X is set to the ground level. On the other hand, the switch SW9 ′ on the scan electrode Y side is turned off and the switches SW1 ′, SW3 ′, and SW5 ′ are turned on to return the voltage of the scan electrode Y to the ground level. Thereafter, the switches SW2 and SW5 on the common electrode X side are turned off, the switches SW1, SW3, and SW4 are turned on, and the switches SW1 ′, SW3 ′, SW4 ′, SW5 ′, and SW9 ′ on the scan electrode Y side are turned off. SW2 ′ and transistor Tr21 are turned on.
[0249]
As a result, the voltage applied to the common electrode X is raised from the ground level to (Vs / 2), and the voltage applied to the scan electrode Y is lowered to (−Vs / 2). At this time, by turning on the transistor Tr21, the voltage gradually decreases as shown in FIG. As a result, the voltage of the wall charge itself exceeds the discharge start voltage in all the cells, and the discharge is started. Also at this time, a weak discharge is performed by the application of the blunt wave, and the accumulated wall charges are erased except for a part.
[0250]
As for the voltage applied to the common electrode X, if the same configuration as the transistor Tr21 and the resistor R is provided in parallel with the switch SW5 on the common electrode X side, the voltage continues from the ground level to the (−Vs / 2) level. It is possible to move downward.
[0251]
Next, in the address period, in order to turn on / off each cell in accordance with display data, address discharge is performed line-sequentially. At this time, on the common electrode X side, the switches SW1, SW3, and SW4 are turned on and the switches SW2 and SW5 are turned off, so that the voltage of the first signal line OUTA is supplied via the switch SW1 (Vs To 2). The voltage (Vs / 2) is output to the output line OUTC via the switch SW4 and applied to the common electrode X of the load 20.
[0252]
When a voltage is applied to the scan electrode Y corresponding to a certain display line, the voltage on the upper side of the scan driver 31 ′ is set to the ground level by turning on the switch SW2 ′ and the transistor Tr22. At this time, when the transistor Tr23 is turned on, the negative voltage (−Vs / 2) output to the fourth signal line OUTB ′ in accordance with the electric charge accumulated in the capacitor C4 is applied to the scan driver 31 ′. A voltage of (−Vs / 2) level is applied to the scan electrode Y selected by line-sequentially, and a ground level voltage is applied to the scan electrode Y of the load 20 to the non-selected scan electrode Y. .
[0253]
At this time, the address pulse of the voltage Va is selectively applied to the address electrode Aj corresponding to the cell causing the sustain discharge in each of the address electrodes A1 to Am, that is, the cell to be lit. As a result, a discharge occurs between the address electrode Aj of the cell to be lit and the scan electrode Y selected line-sequentially, and this is used as a priming (seeding) to immediately shift to the discharge between the common electrode X and the scan electrode Y. . As a result, wall charges of an amount capable of the next sustain discharge are accumulated on the MgO protective film surface on the common electrode X and the scan electrode Y of the selected cell.
[0254]
Here, the discharge between the address electrode Aj and the scan electrode Y is started by a potential difference (Va + Vs / 2) between the electrodes, and can be started by a voltage lower than the conventional potential difference (Va + Vy). It is. This is adjusted by leaving the wall charges to some extent without completely erasing the wall charges on the scan electrodes Y by applying a blunt wave and performing weak discharge as described above in the reset period. Yes. That is, when the discharge start voltage is reached by the residual wall charge and the actual applied voltage, the discharge can be started.
[0255]
Therefore, according to the driving apparatus of the present embodiment, a power source for generating the voltage −Vy during the address period is not required as in the prior art. Therefore, a switch circuit such as the transistor Tr14 for separating the power supply line of the voltage −Vy as shown in FIG. 38 and 101, the driving apparatus of this embodiment does not require a power source for generating the voltage -Vsc of the non-selection pulse during the address period, and the circuit configuration accordingly. Can be simplified.
[0256]
Thereafter, in the sustain discharge period, voltages (+ Vs / 2, −Vs / 2) having different phases are alternately applied to the common electrode X and the scan electrode Y of each display line to perform a sustain discharge. The field image is displayed.
[0257]
During the sustain discharge period, the potentials of the address electrodes A1 to Am are maintained at the ground level. In general, it is desirable to set the address electrodes A1 to Am to an intermediate potential between the common electrode X and the scan electrode Y during the sustain discharge period. Therefore, in the conventional driving apparatus, as shown in FIG. 101, it is necessary to set the potentials of the address electrodes A1 to Am to (Vs / 2) which is an intermediate potential of the voltage Vs applied to both the electrodes X and Y. . On the other hand, in this embodiment, since the intermediate potential between the electrodes X and Y is at the ground level, it is not necessary to raise the potential of the address electrodes A1 to Am to (Vs / 2), and a circuit for that purpose is not provided. It will be enough.
[0258]
FIG. 39 is a diagram illustrating another specific configuration example of the drive device according to the fifth embodiment. In FIG. 39, components having the same reference numerals as those shown in FIG. 37 have the same functions, and redundant description is omitted.
[0259]
In the example of FIG. 37 described above, a circuit for applying the voltage Vw ′ is provided on the scanning electrode Y side. On the other hand, in the example shown in FIG. 39, on the common electrode X side, a switch SW10 having a resistor R3 is provided between the first signal line OUTA and the output line OUTC, and the first signal line OUTA and the ground are provided. A switch SW11 with a resistor R4 and a power source of a voltage Vwn are provided between them.
[0260]
By turning on the switch SW10, a positive voltage (+ Vs / 2) is gradually applied to the common electrode X of the load 20 by the action of the resistor R3. Further, when the switch SW11 is turned ON, a negative voltage (−Vwn) is gradually applied to the common electrode X of the load 20 by the action of the resistor R4.
[0261]
FIG. 40 is a time chart showing a driving waveform on the common electrode X side by the driving device configured as shown in FIG. 39, and shows only the reset period and the sustain discharge period in one subfield.
[0262]
As shown in FIG. 40, in the reset period, first, the switch SW11 is turned on, so that a negative voltage (-Vwn) is gradually applied to the common electrode X of the load 20. At this time, the switches SW2 and SW5 are also turned on to add the voltage (−Vs / 2) using the charge accumulated in the capacitor C1 and apply the voltage − (Vwn + Vs / 2). Is also possible. Next, the switches SW11 and SW5 are turned off, and the switches SW2 and SW4 are turned on to bring the voltage of the common electrode X to the ground level. Next, a positive voltage (+ Vs / 2) is gradually applied to the common electrode X of the load 20 by turning off the switches SW2, SW4, SW5, SW11 and turning on the switches SW1, SW3, SW10.
[0263]
On the other hand, during the sustain discharge period, the switches SW10 and SW11 are not turned on, and the other switches SW1 to SW5 are controlled in the same manner as in the previous embodiments, so that the positive and negative voltages (± Vs / 2) are supplied to the common electrode X. Alternately applied to
[0264]
(Sixth embodiment)
Next, a sixth embodiment of the present invention will be described.
In the sixth embodiment, a power recovery circuit is further provided for the circuits shown in the first to fifth embodiments.
[0265]
FIG. 41 is a diagram illustrating a specific configuration example of the drive device according to the sixth embodiment. In FIG. 41, as in the fifth embodiment, circuits for applying a voltage Vw other than the voltage (Vs / 2) are provided on the common electrode X side and the scan electrode Y side, and the sustain discharge period In addition, a configuration for performing driving related to the reset period and the address period is also shown. In FIG. 41, components having the same reference numerals as those shown in FIG. 102 have the same functions.
[0266]
In FIG. 41, on the common electrode X side, the switches SW1 and SW2 are connected in series between the power supply line of the voltage (Vs / 2) and the ground (GND). One terminal of the capacitor C1 is connected from the middle of the two switches SW1 and SW2, and the switch SW3 is connected between the other terminal of the capacitor C1 and GND.
[0267]
The switches SW4 and SW5 are connected in series to both ends of the capacitor C1. The common electrode X of the load 20 is connected from the middle of these two switches SW4 and SW5, and the power recovery circuit 22 is connected. Further, a switch SW9 with a resistor R1 is connected between the second signal line OUTB and the power supply line that generates the write voltage Vw.
[0268]
In the power recovery circuit 22 shown in FIG. 102, the coils L1, L2 and the common electrode X (output line OUTC) of the load 20 are separated by the diodes D7, D8 connected to the load 20, but are shown in FIG. In the example, the diodes D7 and D8 are not provided. In the power recovery circuit 22 shown in FIG. 102, the capacitor C2 is connected to the ground, but in the example shown in FIG. 41, it is connected to the second signal line OUTB.
[0269]
On the other hand, on the scan electrode Y side, the switches SW1 ′ and SW2 ′ are connected in series between the power supply line of the voltage (Vs / 2) generated by the A / D converter 42 of FIG. 1 and GND. One terminal of the capacitor C4 is connected between the two switches SW1 ′ and SW2 ′, and the switch SW3 ′ is connected between the other terminal of the capacitor C4 and GND.
[0270]
The switch SW4 ′ connected to one terminal of the capacitor C4 is connected to the cathode of the diode D17, and the anode of the diode D17 is connected to the other terminal of the capacitor C4. The switch SW5 ′ connected to the other terminal of the capacitor C4 is connected to the anode of the diode D16, and the cathode of the diode D16 and one terminal of the capacitor C4 are connected. The load 20 is connected via the scan driver 31 ′ from one end of the switch SW 4 ′ connected to the cathode of the diode D 17 and the switch SW 5 ′ connected to the anode of the diode D 16, and the power recovery circuit 33 It is connected. Further, a switch SW9 ′ with a resistor R1 ′ is connected between the fourth signal line OUTB ′ and the power supply line that generates the write voltage Vw.
[0271]
In the power recovery circuit 33 shown in FIG. 102, the capacitor C3 is connected to the ground, but in the example shown in FIG. 41, it is connected to the fourth signal line OUTB ′.
[0272]
Further, on the scanning electrode Y side, in addition to the above configuration, three transistors Tr21 to Tr23 and two diodes D16 and D17 are further provided. Since the roles of the transistors Tr21 to Tr23 and the diodes D16 and D17 have already been described in the fifth embodiment, redundant description is omitted here.
[0273]
FIG. 42 is a time chart showing a driving waveform of the PDP by the driving apparatus configured as shown in FIG. 41, and shows one subfield of a plurality of subfields constituting one frame. The drive waveform shown in FIG. 42 is substantially the same as the drive waveform shown in FIG. 38, and the difference is only the waveform in the reset period and the sustain discharge period. Therefore, here, the reset period and the sustain discharge period will be described.
[0274]
Note that the waveforms of the voltages applied to the common electrode X and the scan electrode Y in the sustain discharge period differ between FIGS. 38 and 42 depending on the presence or absence of the power recovery circuit. That is, since the circuit of FIG. 37 does not include a power recovery circuit, LC resonance is not performed, and a waveform as shown in FIG. 38 is obtained.
[0275]
Here, assuming that the capacity of the load 20 is Cp, the absolute value of the voltage applied to the load 20 is V, and the frequency when the voltage is applied to the load 20 is f, in the conventional example shown in FIG. The power loss at the time of charging / discharging is represented by 2Cp · V2 · f. On the other hand, in the present embodiment, the absolute value of the voltage applied to the load 20 may be ½ of the conventional value, and instead the frequency when the voltage is applied to the load 20 is doubled. The power loss at the time of charging / discharging the load 20 is represented by 2Cp · (V / 2) 2 · (2f), and can be suppressed to half of the conventional value. Therefore, even if no power recovery circuit is provided, power saving can be realized as compared with the conventional case. However, if a power recovery circuit is provided as in the sixth embodiment, further power saving is realized. be able to.
[0276]
42, in the reset period, first, the switches SW2 and SW5 on the common electrode X side are turned on, and the switches SW1, SW3, SW4, and SW9 are turned off. As a result, the voltage of the second signal line OUTB is lowered to (−Vs / 2) in accordance with the electric charge accumulated in the capacitor C1. The voltage (−Vs / 2) is output to the output line OUTC via the switch SW5 and applied to the common electrode X of the load 20.
[0277]
On the other hand, on the scanning electrode Y side, the switches SW1 ′, SW4 ′, SW9 ′ are turned on, and the switches SW2 ′, SW3 ′, SW5 ′ are turned off. As a result, a voltage obtained by adding the voltage Vw and the voltage (Vs / 2) due to the charge accumulated in the capacitor C4 is applied to the output line OUTC ′. Then, the voltage (Vs / 2 + Vw) is applied to the scan electrode Y of the load 20. At this time, the voltage gradually increases due to the action of the resistor R1 ′ in the switch SW9 ′.
[0278]
As a result, the potential difference between the common electrode X and the scan electrode Y becomes (Vs + Vw), and the same potential difference as that of the entire writing pulse shown in the reset period of FIG. 101 can be applied between the common electrode X and the scan electrode Y.
[0279]
Next, by appropriately controlling each switch, the voltages of the common electrode X and the scan electrode Y are returned to the ground level, and then the opposite state is created on the common electrode X side and the scan electrode Y side. . That is, the switches SW1, SW4, SW9 on the common electrode X side are turned on, the switches SW2, SW3, SW5 are turned off, the switches SW2 ′, SW5 ′ on the scanning electrode Y side are turned on, and the switches SW1 ′, SW3 ′, SW4 are turned on. ', SW9' is turned OFF.
[0280]
As a result, the voltage applied to the common electrode X continuously increases from the ground level to (Vs / 2 + Vw), and the voltage applied to the scan electrode Y is dropped to (−Vs / 2). As a result, the voltage of the wall charge itself exceeds the discharge start voltage in all the cells, and the discharge is started. At this time, a weak discharge is performed by applying a blunt wave, and the accumulated wall charges are erased except for a part.
[0281]
In this reset period, the voltage applied to the scan electrode Y is continuously lowered from the ground level to the (−Vs / 2) level as indicated by a dotted line by turning on the transistor Tr21. Also good. Also, with respect to the voltage applied to the common electrode X, if a configuration similar to that of the transistor Tr21 and the resistor R2 is provided in parallel with the switch SW5 on the common electrode X side, as indicated by the dotted line, (−Vs / 2) It is possible to continuously descend to the level.
[0282]
FIG. 43 is a timing chart showing the state of power recovery in the power recovery circuits 22 and 33 shown in FIG. On the common electrode X side, when the switches SW1 and SW3 are turned on and a positive voltage (+ Vs / 2) is applied to the first signal line OUTA, and the voltage of the second signal line OUTB is at the ground level. When the transistor Tr3 in the power recovery circuit 22 is turned on, the LC resonance is performed by the capacitance of the coil L1 and the load 20 due to the potential difference between the capacitor C2 and the common electrode X at the ground level, and is recovered by the capacitor C2. The charged charges are supplied to the load 20 through the transistor Tr3, the diode D3, and the coil L1.
[0283]
At this time, since the switch SW2 ′ is ON on the scan electrode Y side, the current supplied from the capacitor C2 to the common electrode X via the switch SW3 on the common electrode X side is scanned on the scan electrode Y side. The signal passes through the diode in the driver 31 ′ and the diode D16, and is supplied to the ground through the third signal line OUTA ′ and the switch SW2 ′. With such a current flow, the voltage of the common electrode X gradually increases as shown in FIG. Then, by turning on the switch SW4 in the vicinity of the peak voltage generated at the time of resonance, the voltage of the common electrode X is clamped to (Vs / 2).
[0284]
Next, on the scan electrode Y side, the transistor Tr15 in the power recovery circuit 33 is further turned ON. Thereby, due to the potential difference between the voltage of the capacitor C3 and the voltage of the scan electrode Y at the ground level, LC resonance is performed by the capacitance of the coil L3 and the load 20, and the first switch SW3 on the common electrode X side and the capacitor C1 The current supplied to the common electrode X through the switch SW4 via the signal line OUTA of the first signal passes through the diode in the scan driver 31 ′ on the scan electrode Y side and the diode D12 in the power recovery circuit 33, and further includes a transistor Tr15, a capacitor C3, capacitor C4, and switch SW2 'are supplied to the ground. Due to such a current flow, the voltage of the scan electrode Y gradually decreases as shown in FIG. At this time, a part of the charge can be collected by the capacitor C3. Then, the switch SW5 ′ is further turned ON in the vicinity of the peak voltage generated at the time of resonance, thereby clamping the voltage of the scan electrode Y to (−Vs / 2).
[0285]
Next, in this state, the switch SW2 ′ and the transistor Tr16 in the power recovery circuit 33 are turned on on the scan electrode Y side. As a result, LC resonance is performed by the capacitance of the coil L4 and the load 20 due to the potential difference between the voltage of the capacitor C3 and the voltage of the scan electrode Y (−Vs / 2), and the charge recovered in the capacitor C3 is converted into a transistor. The voltage is supplied to the load 20 through Tr16, the diode D13, the coil L4, and the diode in the scan driver 31 ′.
[0286]
At this time, since the switches SW1, SW3 and SW4 are ON on the common electrode X side, the current supplied from the capacitor C3 to the scan electrode Y via the switch SW2 ′ on the scan electrode Y side and the capacitor C4 is Then, the signal passes through the switch SW4 on the common electrode X side and is supplied to the ground via the first signal line OUTA, the capacitor C1, and the switch SW3. With such a current flow, the voltage of the scan electrode Y gradually rises as shown in FIG. Then, the switch SW4 ′ is turned on in the vicinity of the peak voltage generated at the time of resonance, thereby clamping the voltage of the scan electrode Y to the ground level.
[0287]
Next, on the common electrode X side, the switches SW1 and SW3 and the transistor Tr4 in the power recovery circuit 22 are turned on. Thereby, LC resonance is performed by the capacitance of the coil L2 and the load 20 by the potential difference between the voltage of the capacitor C2 and the voltage of the common electrode X (Vs / 2), and the charge accumulated in the load 20 is transferred to the scan electrode Y. Side switches SW2 ′, SW4 ′, via the diode in the scan driver 31 ′, through the coil L2 and diode D4 in the power recovery circuit 22 on the common electrode X side, and further through the transistor Tr4, capacitor C2, and switch SW3. Supplied to the ground. With such a current flow, the voltage of the common electrode X gradually decreases as shown in FIG. At this time, a part of the charge can be collected in the capacitor C2. Then, by turning on the switch SW5 in the vicinity of the peak voltage generated at the time of resonance, the voltage of the common electrode X is clamped to the ground level.
[0288]
Next, by turning on the switches SW2 and SW4 on the common electrode X side, the voltage of the first signal line OUTA is set to the ground level, and the voltage of the second signal line OUTB is set to the negative voltage (−Vs / 2). To be. Further, by turning on the switches SW1 ′, SW3 ′, SW5 ′ on the scanning electrode Y side, the voltage of the third signal line OUTA ′ is (+ Vs / 2), and the voltage of the fourth signal line OUTB ′ is Swings to ground level.
[0289]
In this state, when the transistor Tr16 in the power recovery circuit 33 is turned on on the scan electrode Y side, the coil L4 and the load 20 are affected by the potential difference between the voltage of the capacitor C3 and the voltage of the scan electrode Y (+ Vs / 2). The LC resonance is performed by the capacitance, and the electric charge recovered in the capacitor C3 is supplied to the load 20 via the transistor Tr16, the diode D13, the coil L4, and the diode in the scan driver 31 ′.
[0290]
At this time, since the switches SW2 and SW4 are ON on the common electrode X side, the current supplied from the capacitor C3 to the scan electrode Y via the switch SW3 ′ on the scan electrode Y side is the common electrode X side. , And is supplied to the ground via the first signal line OUTA and the switch SW2. With such a current flow, the voltage of the scan electrode Y gradually rises as shown in FIG. Then, the switch SW4 ′ is further turned on in the vicinity of the peak voltage generated at the time of resonance, thereby clamping the voltage of the scan electrode Y to (Vs / 2).
[0291]
Next, on the common electrode X side, the switch SW2 and the transistor Tr4 in the power recovery circuit 22 are turned on. Thereby, LC resonance is performed by the capacitance of the coil L2 and the load 20 by the potential difference between the voltage of the capacitor C2 and the voltage of the common electrode X, and the third signal is output from the switch SW3 ′ on the scan electrode Y side and the capacitor C4. The current supplied to the scan electrode Y through the line OUTA ′, the switch SW4 ′, and the diode in the scan driver 31 ′ passes through the coil L2 and the diode D4 in the power recovery circuit 22 on the common electrode X side, and further passes through the transistor Tr4. , The capacitor C2, the capacitor C1, and the switch SW2. With such a current flow, the voltage of the common electrode X gradually decreases as shown in FIG. At this time, a part of the charge can be collected in the capacitor C2. Then, the switch SW5 is further turned on in the vicinity of the peak voltage generated at the time of resonance, whereby the voltage of the common electrode X is clamped to (−Vs / 2).
[0292]
Next, in this state, the switch SW2 and the transistor Tr3 in the power recovery circuit 22 are turned on on the common electrode X side. Thereby, LC resonance is performed by the capacitance of the coil L1 and the load 20 by the potential difference between the voltage of the capacitor C2 and the voltage of the common electrode X (−Vs / 2), and the electric charge recovered in the capacitor C2 is converted into a transistor. It is supplied to the load 20 through Tr3, the diode D3, and the coil L1.
[0293]
At this time, since the switches SW1 ′, SW3 ′, and SW4 ′ are ON on the scanning electrode Y side, the switch C2 is supplied from the capacitor C2 to the common electrode X via the switch SW2 and the capacitor C1 on the common electrode X side. The current passes through the diode in the scan driver 31 ′ on the scan electrode Y side and the diode D16, and is supplied to the ground via the third signal line OUTA ′, the capacitor C4, and the switch SW3 ′. With such a current flow, the voltage of the common electrode X gradually increases as shown in FIG. Then, by turning on the switch SW4 in the vicinity of the peak voltage generated at the time of resonance, the voltage of the common electrode X is clamped to the ground level.
[0294]
Next, on the scan electrode Y side, the switches SW1 ′ and SW3 ′ and the transistor Tr15 in the power recovery circuit 33 are turned on. Thereby, LC resonance is performed by the capacitance of the coil L3 and the load 20 by the potential difference between the voltage of the capacitor C3 and the voltage of the scan electrode Y (Vs / 2), and the charge accumulated in the load 20 is stored in the common electrode X. Through the diodes in the scan driver 31 'on the scan electrode Y side through the switches SW2 and SW4 on the side, and further through the coil L3, diode D12, transistor Tr15, capacitor C3, switch SW3' in the power recovery circuit 33 Supplied to ground. Due to such a current flow, the voltage of the scan electrode Y gradually decreases as shown in FIG. At this time, a part of the voltage can be recovered by the capacitor C3. Then, the switch SW5 ′ is turned on in the vicinity of the peak voltage generated at the time of resonance, whereby the voltage of the scan electrode Y is clamped to the ground level.
[0295]
FIG. 44 is a diagram illustrating another specific configuration example of the drive device according to the sixth embodiment. In FIG. 44, components having the same reference numerals as those shown in FIG. 41 have the same functions, and redundant description is omitted.
[0296]
The common electrode X side will be described. In the drive device shown in FIG. 44, the power recovery circuit 22 is configured by two systems of coils L1 and L2, as in the drive device shown in FIG. The coils L1 and L2 and the common electrode X (output line OUTC) of the load 20 are separated by a plurality of diodes D7 and D8. Diodes D18 and D19 connected between the coil L1 of the power recovery circuit 22 and the second signal line OUTB and between the coil L2 and the first signal line OUTA are respectively connected to the diode D16, It has the same role as D17.
[0297]
Further, the power recovery circuit 22 includes four diodes D20 to D23 as clamping diodes. The diodes D20 and D21 are connected in series between the first signal line OUTA and the second signal line OUTB, and an intermediate node thereof is connected between the cathode of the diode D3 and the coil L1. The diodes D22 and D23 are connected in series between the first signal line OUTA and the second signal line OUTB, and an intermediate node thereof is connected between the anode of the diode D4 and the coil L2.
[0298]
Also, the power recovery circuit 22 shown in FIG. 44 includes two capacitors C2 and C12 as power recovery capacitors. The capacitor C12 newly provided in FIG. 44 is connected between the common connection terminal of the two transistors Tr3 and Tr4 and the first signal line OUTA.
[0299]
When the capacitor C12 is provided and the switch SW2 is turned on to set the voltage of the first signal line OUTA to the ground level, the capacitor C12 is used as it is from the first signal line OUTA without passing through the capacitors C1 and C2. Electric power can be collected and supplied for 20 capacities, and loss can be reduced.
[0300]
That is, as shown in FIG. 41, when the power recovery circuit 22 includes only the capacitor C2, the power recovery is performed by the current flowing through the path of the capacitor C2, the capacitor C1, and the switch SW2, and the two capacitors Via. On the other hand, when the capacitor C12 is also provided as shown in FIG. 44, the power is collected by a current flowing through the path of the capacitor C12 and the switch SW2, and only one capacitor passes through. Therefore, in the case of FIG. 44, the power loss due to the impedance component generated in the capacitor can be reduced, and the power recovery efficiency can be improved.
[0301]
FIG. 45 is a timing chart showing a state of power recovery in the power recovery circuit 22 shown in FIG. When the switches SW1 and SW3 are turned on to apply a positive voltage (+ Vs / 2) to the first signal line OUTA and the voltage of the second signal line OUTB is at the ground level, the capacitors C2 and C12 The voltage at the connection node is Vs / 4.
[0302]
When the transistor Tr3 in the power recovery circuit 22 is turned on in this state, the potential difference (Vs / 4) between the connection node of the capacitors C2 and C12 and the common electrode X at the ground level depends on the capacitance of the coil L1 and the load 20. L-C resonance is performed, and the voltage of the common electrode X gradually rises as shown in FIG. 45 using the charges collected in the capacitors C2 and C12. Then, by turning on the switch SW4 in the vicinity of the peak voltage generated at the time of resonance, the voltage of the common electrode X is clamped to (Vs / 2).
[0303]
Further, in this state, when the transistor Tr3 and the switch SW4 are turned off and the transistor Tr4 in the power recovery circuit 22 is turned on, the voltage (Vs / 4) at the connection node of the capacitors C2 and C12 and the voltage at the common electrode X (Vs / LC resonance is performed by the capacitance of the coil L2 and the load 20 at the potential difference (Vs / 4) from 2), and the voltage of the common electrode X gradually decreases as shown in FIG. At this time, a part of the charges can be collected by the capacitors C2 and C12. Then, by turning on the switch SW5 in the vicinity of the peak voltage generated at the time of resonance, the voltage of the common electrode X is clamped to the ground level.
[0304]
Next, by turning on the switch SW2, the voltage of the first signal line OUTA is set to the ground level, and the voltage of the second signal line OUTB is set to the negative voltage (−Vs / 2). As a result, the voltage at the connection node of the capacitors C2 and C12 becomes (−Vs / 4).
[0305]
When the transistor Tr4 in the power recovery circuit 22 is turned on in this state, the potential difference (Vs / 4) between the connection node of the capacitors C2 and C12 and the common electrode X at the ground level depends on the capacitance of the coil L2 and the load 20. L-C resonance is performed, and the voltage of the common electrode X gradually decreases as shown in FIG. At this time, a part of the charges can be collected by the capacitors C2 and C12. Then, by turning on the switch SW5 in the vicinity of the peak voltage generated at the time of resonance, the voltage of the common electrode X is clamped to (−Vs / 2).
[0306]
Further, in this state, when the transistor Tr4 and the switch SW5 are turned off and the transistor Tr3 in the power recovery circuit 22 is turned on, the voltage (−Vs / 4) at the connection node of the capacitors C2 and C12 and the voltage (− L-C resonance is performed by the capacitance of the coil L1 and the load 20 at the potential difference (Vs / 4) with respect to Vs / 2), and the voltage of the common electrode X is obtained using the charges collected in the capacitors C2 and C12. It gradually rises as shown in FIG. Then, by turning on the switch SW4 in the vicinity of the peak voltage generated at the time of resonance, the voltage of the common electrode X is clamped to the ground level.
[0307]
As described above, according to the configuration example of FIG. 44, two capacitors C2 and C12 are provided between the first signal line OUTA and the second signal line OUTB for power recovery. Staged power recovery can be performed. In addition, since the Q of the current that flows at one time during power recovery is reduced, the power recovery efficiency can be greatly improved. Further, the function of the capacitor C1 can be realized by the two capacitors C2 and C12, and the capacitor C1 can be made unnecessary.
[0308]
The above is the configuration on the common electrode X side, but the configuration on the scanning electrode Y side is the same. That is, the power recovery circuit 33 on the scan electrode Y side includes four diodes D20 ′ to D23 ′ as clamping diodes. The diodes D20 ′ and D21 ′ are connected in series between the third signal line OUTA ′ and the fourth signal line OUTB ′, and an intermediate node thereof is connected between the anode of the diode D12 and the coil L3. . The diodes D22 ′ and D23 ′ are connected in series between the third signal line OUTA ′ and the fourth signal line OUTB ′, and an intermediate node thereof is connected between the cathode of the diode D13 and the coil L4. Is done.
[0309]
Also, the power recovery circuit 33 shown in FIG. 44 includes two capacitors C3 and C13 as power recovery capacitors. The capacitor C13 newly provided in FIG. 44 is connected between the common connection terminal of the two transistors Tr15 and Tr16 and the third signal line OUTA ′.
[0310]
When this capacitor C13 is provided and the switch SW2 ′ is turned on to set the voltage of the third signal line OUTA ′ to the ground level, the capacitor C13 is used as it is from the third signal line OUTA ′ without passing through the capacitors C4 and C3. The power can be collected and supplied to the capacity of the load 20, and the loss can be reduced.
[0311]
That is, as shown in FIG. 41, when the power recovery circuit 33 includes only the capacitor C3, the power recovery is performed by the current flowing through the paths of the capacitor C3, the capacitor C4, and the switch SW2 ′. Via a capacitor. On the other hand, when the capacitor C13 is also provided as shown in FIG. 44, the power is collected by the current flowing through the path of the capacitor C13 and the switch SW2 ′, and only one capacitor passes through. Therefore, in the case of FIG. 44, the power loss due to the impedance component generated in the capacitor can be reduced, and the power recovery efficiency can be improved.
[0312]
In the drive device shown in FIG. 44, the capacitors C12 and C13 may be deleted (opened). Further, the configuration may be such that the capacitors C2 and C3 are deleted (opened). In addition, the capacitors C1 and C4 may be deleted (opened). Further, the capacitance ratio between the capacitors C2 and C12 and the capacitance ratio between the capacitors C3 and C13 may be the same or different. The values of the coils L1 and L2 and the values of the coils L3 and L4 may be the same or different.
[0313]
For example, when the values of the coils L1 and L2 and the values of the coils L3 and L4 are different from each other, the rise time and fall time of the voltage at the time of LC resonance can be made different. That is, the smaller the value of the coil, the larger the slope of the voltage rise / fall. For example, by reducing the values of the coils L1 and L3 used at the time of supplying the recovered power and increasing the values of the coils L2 and L4 used at the time of recovering the power, the voltage rises at the time of supplying the power to accelerate the plasma. In the display panel, it is possible to improve the luminance and suppress the occurrence of noise by relatively slowing down the voltage during power recovery.
[0314]
FIG. 46 is a diagram illustrating another specific configuration example of the driving apparatus according to the sixth embodiment. In FIG. 46, the same reference numerals as those shown in FIG. 44 have the same functions, and thus redundant description is omitted.
46 differs from FIG. 44 only in that the capacitors C12 and C13 do not exist and the wiring of the clamping diodes D20 to D23 and D20 ′ to D23 ′.
[0315]
46, in the power recovery circuit 22 on the common electrode X side, the diodes D20 and D21 are connected in series between the first signal line OUTA and the second signal line OUTB, and the intermediate node thereof. Is connected between the cathode of the diode D4 and the transistor Tr4. The diodes D22 and D23 are connected in series between the first signal line OUTA and the second signal line OUTB, and an intermediate node thereof is connected between the anode of the diode D3 and the transistor Tr3.
[0316]
In the power recovery circuit 33 on the scan electrode Y side, the diodes D20 ′ and D21 ′ are connected in series between the third signal line OUTA ′ and the fourth signal line OUTB ′, and the intermediate node thereof is a diode. It is connected between the anode of D13 and the transistor Tr16. The diodes D22 ′ and D23 ′ are connected in series between the third signal line OUTA ′ and the fourth signal line OUTB ′, and an intermediate node thereof is connected between the cathode of the diode D12 and the transistor Tr15. Is done.
[0317]
FIG. 47 is a diagram showing another specific configuration example of the driving apparatus according to the sixth embodiment. Note that in FIG. 47, the same reference numerals as those shown in FIG. 44 have the same functions, and thus redundant description is omitted.
47 is different from FIG. 44 in that the capacitors C12 and C13 are not present and between the coils L1 and L2 and the common electrode X (output line OUTC) of the load 20 are a plurality of diodes D7, D8, and D18. , D19 is not separated.
[0318]
That is, in the configuration of FIG. 47, the diodes D7, D8, D18, and D19 used in FIG. 44 do not exist on the common electrode X side, and the coils L1 and L2 can be directly seen from the common electrode X side. Yes. In both the common electrode X and the scan electrode Y, the capacitors C12 and C13 used in FIG. 44 may be used.
[0319]
FIG. 48 is a diagram illustrating another specific configuration example of the drive device according to the sixth embodiment. Note that in FIG. 48, the same reference numerals as those shown in FIG. 44 have the same functions, and thus redundant description will be omitted.
[0320]
48 differs from FIG. 44 in that the capacitors C12 and C13 do not exist, the wiring portions of the clamping diodes D20 to D23 and D20 ′ to D23 ′, and the coils L1 and L2 and the load 20 are common. The only difference is that the electrodes X (output line OUTC) are not separated by a plurality of diodes D7 and D8.
[0321]
48, in the power recovery circuit 22 on the common electrode X side, the diodes D20 and D21 are connected in series between the first signal line OUTA and the second signal line OUTB, and the intermediate node thereof. Is connected between the cathode of the diode D4 and the transistor Tr4. The diodes D22 and D23 are connected in series between the first signal line OUTA and the second signal line OUTB, and an intermediate node thereof is connected between the anode of the diode D3 and the transistor Tr3.
[0322]
In the power recovery circuit 33 on the scan electrode Y side, the diodes D20 ′ and D21 ′ are connected in series between the third signal line OUTA ′ and the fourth signal line OUTB ′, and the intermediate node thereof is a diode. It is connected between the anode of D13 and the transistor Tr16. The diodes D22 ′ and D23 ′ are connected in series between the third signal line OUTA ′ and the fourth signal line OUTB ′, and an intermediate node thereof is connected between the cathode of the diode D12 and the transistor Tr15. Is done.
[0323]
On the common electrode X side, the diodes D7, D8, D18, and D19 used in FIG. 44 do not exist, and the coils L1 and L2 are directly visible from the common electrode X side. In both the common electrode X and the scan electrode Y, the capacitors C12 and C13 used in FIG. 44 may be used.
[0324]
FIG. 49 is a diagram showing another specific configuration example of the driving apparatus according to the sixth embodiment. Note that in FIG. 49, the same reference numerals as those shown in FIG. 44 have the same functions, and thus redundant description will be omitted.
[0325]
49 differs from FIG. 44 in that the capacitors C12 and C13 are not present, the power recovery circuit 22 on the common electrode X side is configured by only one system of the coil L1, and the coil L1 and the load. The only difference is that the plurality of diodes D7 and D8 are not separated from the 20 common electrodes X (output line OUTC).
[0326]
49, in the power recovery circuit 22 on the common electrode X side, the diodes D20 and D21 are connected in series between the first signal line OUTA and the second signal line OUTB, and the intermediate node thereof. Is connected between the cathode of the diode D3 and the coil L1. The coil L2 and the diodes D22 and D23 used in FIG. 44 are not used in the configuration of FIG.
[0327]
On the common electrode X side, the diodes D7, D8, D18, and D19 used in FIG. 44 do not exist, and the coils L1 and L2 are directly visible from the common electrode X side. In both the common electrode X and the scan electrode Y, the capacitors C12 and C13 used in FIG. 44 may be used.
Thus, the circuit configuration can be simplified by configuring the power recovery circuit 22 with only one system of the coil L1.
[0328]
FIG. 50 is a diagram illustrating another specific configuration example of the driving apparatus according to the sixth embodiment. Note that in FIG. 50, the same reference numerals as those shown in FIG. 49 have the same functions, and thus redundant description will be omitted.
The configuration of FIG. 50 differs from FIG. 49 in that the power recovery circuit 22 on the common electrode X side uses four diodes D20 to D23 as clamping diodes, the wiring portion thereof, and the scan electrode Y side. Only the wiring portions of the diodes D20 ′ to D23 ′.
[0329]
50, in the power recovery circuit 22 on the common electrode X side, the diodes D20 and D21 are connected in series between the first signal line OUTA and the second signal line OUTB, and the intermediate node thereof. Is connected between the cathode of the diode D4 and the transistor Tr4. The diodes D22 and D23 are connected in series between the first signal line OUTA and the second signal line OUTB, and an intermediate node thereof is connected between the anode of the diode D3 and the transistor Tr3. The configuration on the scanning electrode Y side is exactly the same as in FIG.
[0330]
FIG. 51 is a diagram illustrating another specific configuration example of the driving apparatus according to the sixth embodiment. In FIG. 51, components having the same reference numerals as those shown in FIG. 44 have the same functions, and thus redundant description is omitted. In FIG. 51, in particular, the configuration on the scanning electrode Y side is shown as a representative.
[0331]
In FIG. 51, the switch SW4 ″ serves both as the switch SW4 ′ and the transistor Tr22 in FIG. 44. The switch SW5 ″ serves as both the switch SW5 ′ and the transistor Tr23 in FIG. Furthermore, the two switches SW12 and SW13 constituting the scan driver 31 ′ also function as the transistors Tr16 and Tr15 in FIG. 44, respectively.
[0332]
By switching and controlling each switch including these switches SW4 ″, SW5 ″, SW12, and SW13 at an appropriate timing on the scanning electrode Y side, the negative voltage (−Vs / 2) in the address period shown in FIG. The positive and negative voltages (± Vs / 2) which are alternately repeated in the sustain discharge period can be generated.
[0333]
For example, the negative voltage (−Vs / 2) of the scan electrode Y in the address period can be applied by turning on the switch SW4 ″ (transistor Tr22) and the switch SW5 ″ (transistor Tr23). That is, when the transistor Tr22 is turned on, the third signal line OUTA ′ becomes the ground level, and when the transistor Tr23 is turned on, the fourth signal line OUTB ′ becomes the (−Vs / 2) level, and as a result, the output A negative voltage (−Vs / 2) is applied to the load 20 via the line OUTC ′.
[0334]
Further, the positive / negative voltage (± Vs / 2) of the scan electrode Y during the sustain discharge period can be generated by the switching operation shown in FIG.
FIG. 52 is a time chart showing a control example of each switch for generating a drive waveform for the scan electrode Y in the sustain discharge period in the drive device shown in FIG.
[0335]
First, the switches SW1 ′, SW3 ′, SW12 (transistor Tr16) are turned on. Thereby, LC resonance is performed between the capacitance of the load 20 and the coil L3, and the voltage gradually increased at this time is applied to the scan electrode Y via the output line OUTC ′. Next, the switch SW4 ″ (switch SW4 ′) is further turned on in the vicinity of the peak voltage generated at the time of resonance, and the voltage applied to the scan electrode Y is clamped to (+ Vs / 2).
[0336]
Next, with the switches SW1 ′ and SW3 ′ kept on, the switches SW4 ″ and SW12 are turned off and the switch SW13 (transistor Tr15) is turned on. As a result, the charges accumulated in the capacitance of the load 20 are switched. The voltage of the scan electrode Y is gradually lowered by the LC resonance between the capacitance of the load 20 and the coil L3, which is pulled through the SW 13. The switch SW5 "(switch SW5 ′) is further turned ON, and the voltage applied to the scan electrode Y is clamped to the ground level.
[0337]
Next, after all the switches are turned OFF, the switch SW2 ′ is turned ON, so that the voltage of the third signal line OUTA ′ is changed from (+ Vs / 2) to the ground level, and the fourth signal line OUTB ′. Is swung from the ground level to (−Vs / 2).
[0338]
By turning on the switch SW13 (transistor Tr15) at the same time as turning on the switch SW2 ′, the voltage of the scan electrode Y is reduced to a negative voltage (− by the LC resonance between the capacitance of the load 20 and the coil L3. Gradually lower toward Vs / 2). Thereafter, the switch SW5 ″ (switch SW5 ′) is further turned on in the vicinity of the peak voltage generated at the time of resonance, whereby the voltage applied to the scan electrode Y is clamped to (−Vs / 2).
[0339]
Next, with the switch SW2 ′ kept on, the switches SW5 ″ and SW13 are turned off and the switch SW12 (transistor Tr16) is turned on. As a result, the LC between the capacitance of the load 20 and the coil L3. The voltage of the scan electrode Y is gradually increased by resonance, and the switch SW4 ″ (switch SW4 ′) is further turned on near the peak voltage generated at the time of resonance, and the applied voltage to the scan electrode Y is clamped to the ground level. .
[0340]
As described above, according to the driving apparatus having the configuration shown in FIG. 51, the switching device required for driving in the address period and the switching element required for driving in the sustain discharge period are combined. The number can be reduced and the circuit can be simplified.
[0341]
FIG. 53 is a diagram illustrating another specific configuration example of the drive device according to the sixth embodiment. In FIG. 53, the same reference numerals as those shown in FIG. 41 have the same functions, and thus the duplicate description is omitted. FIG. 54 is a time chart showing a control example of each switch for generating a drive waveform for the scan electrode Y in the scan period and the sustain discharge period in the drive device shown in FIG. 53 and 54 are shown as a comparative example of the present plan with respect to the conventional example shown in FIGS. 103 and 105.
[0342]
In the scanning period, the switch SW2 ′ on the scanning electrode Y side is turned on to set the voltage of the third signal line OUTA ′ to the ground level, and the first charge is stored by the charge (C4 × Vs / 2) stored in the capacitor C4. The voltage of the fourth signal line OUTB ′ is set to (−Vs / 2). Then, by turning on the transistors Tr22 and Tr23, a voltage (Vs / 2) is applied to both ends of the scan driver 31 ′, and a scan pulse of (−90 V) is applied to one scan electrode Y as in FIG. Apply.
[0343]
On the other hand, in the common electrode X, by turning on the switch SW9 in advance, the voltage of the second signal line OUTB is set to Vx (50V), and the first charge is generated by the charge of (C1 × Vs / 2) stored in the capacitor C1. The voltage of the first signal line OUTA is (Vx + Vs / 2 = 140V). When the switch SW4 is turned on, the potential difference between the common electrode X and the scan electrode Y at the time of the scan pulse becomes (Vx + Vs / 2) + Vs / 2 = 230V.
[0344]
At this time, a voltage difference (Vs / 2) between the first signal line OUTA and the second signal line OUTB is applied to the FET (switches SW4 and SW5) that handles the above-described discharge current. May be Vs / 2 or more. That is, it shows that the potential difference 230 V between the electrodes X and Y at the time of the scan pulse shown in FIG. 105 can be realized by the low voltage circuit of this embodiment.
[0345]
The potential difference between the address electrode A and the scan electrode Y during the address period is 150 V because the voltage Va of the address electrode A is 60 V and the scan pulse voltage of the scan electrode Y is (−Vs / 2 = −90 V). . This potential difference is smaller than the potential difference 240V between the same address electrode A and scan electrode Y shown in FIG. 105, but in this regard, during the reset period, wall charges are simply accumulated in the dielectric layer on the address electrode A. it can. In the reset period, wall charges of 240V-150V = 90V are accumulated. As described above, the operation in the scanning period similar to that in FIG. 105 is performed.
[0346]
The operation in the sustain discharge period is the same as that shown in FIG. 42, and the potential difference between the first signal line OUTA and the second signal line OUTB is always Vs / 2. The switches SW4, SW5, SW4 ′, and SW5 ′ that exchange gas discharge currents shown in FIG. 53 are the first signal line OUTA and the second signal line OUTB, or the third signal line OUTA ′ and the fourth signal. Since it is installed in the line OUTB ′, the withstand voltage of the FETs constituting these switches may be Vs / 2 or more.
[0347]
As described above, since the withstand voltage of the FET has been reduced to half that of the conventional one, the ON resistance of the FET can be greatly reduced. Conventionally, it is necessary to provide a plurality of FETs in parallel in order to stably perform gas discharge. Thus, the number of elements can be significantly reduced. In addition, the unit price of the element itself can be reduced due to the decrease in breakdown voltage. Moreover, the high voltage power source required for driving may be two types of Vs / 2 (90 V) and Vx (50 V), and the power supply circuit can be reduced. The costs of the A / S separation circuit used in the conventional example of FIG. 103 and the additional circuit according to the present embodiment are the same. As described above, an inexpensive PDP can be realized.
[0348]
In the above embodiment, the power recovery circuit is provided. However, since the power without the power recovery circuit is proportional to Cp · V 2 · f as described above, the power loss can be suppressed to half of the conventional one. Therefore, the power recovery circuit can be omitted. A circuit diagram realized without a power recovery circuit is shown in FIG. The output waveform in the sustain discharge period is the same as that shown in FIG. The output waveform in the line sequential scanning period is the same as that in FIG.
[0349]
If there is a power recovery circuit, a circuit (switches SW4 ′ and SW5 ′ in FIG. 53) that clamps the power supply after outputting the LC resonance voltage as shown in FIG. 53 is necessary. Since the circuit can be omitted, the charge / discharge current and the gas discharge current to the load capacitor Cp can be passed through the FET of the scan driver including only the switches SW4 ′ and SW5 ′ shown in FIG. When the voltage of the third signal line OUTA ′ is applied to the scan electrode Y during the sustain discharge period, the switch SW4 ′ is turned ON, and when the voltage of the fourth signal line OUTB ′ is applied, the switch SW5 ′ is turned ON.
[0350]
In the operation on the scanning electrode Y side in the line sequential scanning period, the voltage of the third signal line OUTA ′ is set to the ground level and the voltage of the fourth signal line OUTB ′ is set to (−Vs / 2), the voltage across the scan driver is set to the ground level, (−Vs / 2), and the scan pulse voltage (−Vs / 2) is output to the scan electrode Y during scanning.
[0351]
As described above, by omitting the power recovery circuit, the number of circuits can be further reduced in addition to the effect described above by the configuration of FIG. 53, and a lower cost PDP can be realized.
[0352]
(Seventh embodiment)
Next, a seventh embodiment of the present invention will be described.
In the seventh embodiment, a circuit for applying an address period, a reset period, or a scan voltage from an independent power source to the circuits shown in the first to sixth embodiments through switching elements. Is further provided.
[0353]
FIG. 56 is a diagram illustrating a specific configuration example of the drive device according to the seventh embodiment. In FIG. 56, not only the sustain discharge period but also a configuration for performing driving related to the reset period and the address period is shown. In FIG. 56, the same reference numerals as those shown in FIG. 5 or FIG. 35 and the like have the same functions, and redundant description is omitted.
[0354]
In FIG. 56, on the common electrode X side, a switch SW8 is provided between the power supply line for generating the voltage Vx and the second signal line OUTB. On the other hand, on the scanning electrode Y side, a switch SW9 ′ is provided between the power supply line that generates the voltage Vw and the fourth signal line OUTB ′.
[0355]
FIG. 57 is a time chart showing a driving waveform of the PDP by the driving apparatus configured as shown in FIG. 56, and shows one subfield of a plurality of subfields constituting one frame. The drive waveform shown in FIG. 57 is substantially the same as the drive waveform shown in FIG. 38, and the only difference is the magnitude of the positive voltage applied to the common electrode X during the reset period and the address period.
[0356]
In the case of FIG. 57, when a positive voltage is applied to the common electrode X side in the reset period, the switches SW1, SW3, SW4, SW8 are turned on and the switch SW2 is turned off. As a result, the voltage of the output line OUTC is divided into a voltage (Vs / 2) applied to the first signal line OUTA via the switch SW1 and a voltage Vx applied to the second signal line OUTB via the switch SW8. Raised to the added voltage level. Then, the voltage (Vs / 2 + Vx) is applied to the common electrode X of the load 20.
The same applies when a voltage (Vs / 2 + Vx) is applied to the common electrode X during the address period.
[0357]
FIG. 58 is a diagram illustrating another configuration example of the driving apparatus according to the seventh embodiment. In FIG. 58, the same reference numerals as those shown in FIG. 56, FIG. 44, and the like have the same functions, and thus redundant description is omitted.
[0358]
As shown in FIG. 58, a switch similar to the switch SW8 shown in FIG. 56 is connected on the common electrode X side. However, the voltage of the power supply line connected to the switch SW8 in FIG. 56 is a voltage Vx ′ larger than the voltage Vx shown in FIG. The power supply voltage Vx ′ is, for example, the same voltage value as the voltage (Vs / 2 + Vx) applied to the load 20 during the reset period.
[0359]
On the other hand, on the scanning electrode Y side, the switch SW18 is connected between the third signal line OUTA ′ and the ground, and the switch is connected between the fourth signal line OUTB ′ and the power supply line that generates the voltage (−Vy). SW19 is connected. These switches SW18 and SW19 also serve as transistors Tr22 and Tr23, respectively. The transistor Tr21 is connected to a power supply line of voltage (−Vn) through the resistor R2.
[0360]
In the configuration example shown in FIG. 58, the switches SW8, SW9 ′, SW18, and SW19 are switched at appropriate timings in addition to the switches SW1 to SW5, SW1 ′ to SW5 ′, so that they are smaller than the conventional ones. Fine voltage adjustment can be performed for various pulses necessary in the reset period and the address period by using a withstand voltage element, and more reliable display performance can be obtained. This will be described with reference to the timing chart of FIG.
[0361]
FIG. 59 is a time chart showing a driving waveform of the PDP by the driving apparatus configured as shown in FIG. 58, and shows one subfield of a plurality of subfields constituting one frame. The drive waveform shown in FIG. 59 is almost the same as the drive waveform shown in FIG. 57, and the difference is only in the voltage value applied during the reset period, the pulse waveform in the sustain discharge period, and the scan pulse voltage value. is there. Note that the difference in the pulse waveform during the sustain discharge period is due to the presence or absence of the power recovery circuit, and since the details thereof have already been described, redundant description is omitted here.
[0362]
In the reset period, first, the voltage (−Vs / 2) is applied to the common electrode X side of the load 20, and the voltage Vw ′ (= Vs / 2 + Vw) is gradually applied to the scan electrode Y side. Thereby, the potential difference between the common electrode X and the scanning electrode Y becomes (Vs + Vw), and the same potential difference as that of the entire writing pulse in the reset period can be applied between the common electrode X and the scanning electrode Y. The steps so far are the same as those in FIG.
[0363]
Thereafter, the switches SW1 ′, SW3 ′, SW4 ′, SW5 ′, and SW9 ′ on the scanning electrode Y side are turned off, and the switch SW2 ′ and the transistor Tr21 are turned on.
[0364]
On the other hand, the switch SW5 on the common electrode X side is turned off, the switch SW4 is turned on, and the voltage of the common electrode X is set to the ground level. At this time, the switch SW2 is ON. Thereafter, the switch SW2 on the common electrode X side is turned off and the switches SW5 and SW8 are turned on to raise the voltage applied to the common electrode X from the ground level to Vx ′ (= Vs / 2 + Vx). Further, when the transistor Tr21 on the scan electrode Y side is turned on, the voltage applied to the scan electrode Y is gradually lowered to (−Vn). The absolute value of the voltage (−Vn) is slightly smaller than the absolute value of (−Vs / 2), for example, and the amount of wall charges left in the cell due to weak discharge by applying a blunt wave is adjusted by this voltage value. Is possible. Thereafter, the common electrode X and the scanning electrode Y are set to the ground level by appropriate switch control. In addition, the switch SW19 that can independently set the scan pulse voltage during the address period by the (-Vy) power supply is provided, thereby making it possible to obtain more reliable display performance.
[0365]
(Eighth embodiment)
Next, an eighth embodiment of the present invention will be described.
In the eighth embodiment, in one of the first to seventh embodiments described above, one side of the driver circuit that applies a voltage to the load 20 is configured by an LSI such as a scan driver circuit.
[0366]
FIG. 60 is a diagram illustrating a specific configuration example of the drive device according to the eighth embodiment. In FIG. 60, components having the same reference numerals as those shown in FIG. 2 have the same functions, and thus redundant description is omitted.
[0367]
In FIG. 60, the driver circuit 51 ′ on the scan electrode Y side is configured by an LSI such as a scan driver circuit. That is, the driver circuit 51 ′ is provided for every display line included in the PDP. That is, as many switches SW4 ′ and switches SW5 ′ as the number of display lines are provided.
On the other hand, like the power supply circuit 43, the driver circuit 44 on the common electrode X side is configured as a circuit common to all display lines included in the PDP.
[0368]
With this configuration, at least on the scanning electrode Y side, the switches SW4 ′ and SW5 ′ provided for the respective display lines are subjected to switching control during the sustain discharge period, whereby the voltages applied to the display lines are individually controlled. Can be controlled. Further, the transistors Tr22 and Tr23 in each of the above-described embodiments, which are switching elements for applying a voltage (−Vs / 2) during the address period, can be eliminated.
[0369]
FIG. 61 is a diagram illustrating another configuration example of the drive device according to the eighth embodiment. In FIG. 61, components having the same reference numerals as those shown in FIG. 60 have the same functions, and thus redundant description is omitted.
[0370]
In the configuration shown in FIG. 61, the driver circuit 51 ′ on the scan electrode Y side is configured by an LSI such as a scan driver circuit. Further, the switch SW8 connected to the power supply line of the voltage Vx ′ is provided on the common electrode X side, and the switch SW9 ′ connected to the power supply line of the voltage Vw is provided on the scanning electrode Y side. The transistors Tr22 and Tr23 are not necessary on the scanning electrode Y side.
[0371]
FIG. 62 is a time chart showing a driving waveform of the PDP by the driving apparatus configured as shown in FIG. 61, and shows one subfield among a plurality of subfields constituting one frame. The drive waveform shown in FIG. 62 is substantially the same as the drive waveform shown in FIG. This drive waveform includes switches SW1 to SW5, SW8, SW1 ′ to SW3 ′, SW9 ′ provided in common to each display line, and switches SW4 ′ and SW5 ′ in the scan driver 51 ′ on a certain display line i. It is created by ON / OFF control at an appropriate timing.
[0372]
60 and 61, the mounting area of the circuit components can be greatly reduced, so that the apparatus can be downsized and the manufacturing cost can be reduced.
[0373]
60 and 61 show the case where the switches SW4 ′ and SW5 ′ are both in the position as shown in the first embodiment, that is, in the driver circuit, the switch SW4 ′ is in the second embodiment. The present invention can be similarly applied to a position as shown in FIG. 1, that is, in the power supply circuit, or a position where the switch SW5 ′ is located in the power supply circuit as shown in the third embodiment. In the second embodiment, the switch SW5 ′ can be configured by an LSI such as a scan driver circuit, and the switch SW4 ′ in the third embodiment.
[0374]
In this case, even if the driver circuit is configured as an LSI by a scan driver, only one switch SW4 ′ or switch SW5 ′ is required for each display line, and the total number of switches can be greatly reduced. it can. As a result, the circuit scale can be reduced and the cost can be suppressed.
[0375]
(Ninth embodiment)
Next, a ninth embodiment of the present invention will be described. In the ninth embodiment, both sides of the driver circuit for applying a voltage to the load 20, that is, the driver circuits on the common electrode X side and the scanning electrode Y side are configured by LSIs such as a scan driver circuit.
[0376]
FIG. 63 is a diagram illustrating a configuration example of the drive device according to the ninth embodiment. Note that in FIG. 63, the same reference numerals as those shown in FIG. 2 or FIG. 60 have the same functions, and redundant description is omitted.
[0377]
In FIG. 63, the driver circuit 51 on the common electrode X side is configured by an LSI such as a scan driver circuit. That is, unlike the power supply circuit 43 configured as a circuit common to all display lines provided in the PDP, the driver circuit 51 is provided for each display line. That is, the switches SW4 and SW5 are provided by the number of display lines.
[0378]
The driver circuit 51 ′ on the scan electrode Y side is also configured by an LSI such as a scan driver circuit. That is, unlike the power supply circuit 43 ′ configured as a circuit common to all display lines included in the PDP, a driver circuit 51 ′ is provided for each display line. That is, as many switches SW4 ′ and switches SW5 ′ as the number of display lines are provided.
[0379]
With this configuration, on both the common electrode X side and the scan electrode Y side, the switches SW4, SW5, SW4 ′, and SW5 ′ provided for each display line are subjected to switching control during the sustain discharge period. Thus, the voltage applied to each display line can be individually controlled. On the scanning electrode Y side, the transistors Tr22 and Tr23 in the above-described embodiments, which are switching elements for applying a voltage (−Vs / 2) in the address period, can be eliminated.
[0380]
FIG. 64 is a diagram showing another configuration example of the driving apparatus according to the ninth embodiment. In FIG. 64, components having the same reference numerals as those shown in FIG. 63 or FIG. 56 have the same functions, and redundant description is omitted.
[0381]
In the configuration shown in FIG. 64, the driver circuit 51 on the common electrode X side and the driver circuit 51 ′ on the scan electrode Y side are configured by an LSI such as a scan driver circuit. Further, the switch SW8 connected to the power supply line of the voltage Vx ′ is provided on the common electrode X side, and the switch SW9 ′ connected to the power supply line of the voltage Vw is provided on the scanning electrode Y side. The transistors Tr22 and Tr23 are not necessary on the scanning electrode Y side.
[0382]
FIG. 65 is a time chart showing a driving waveform of the PDP by the driving apparatus configured as shown in FIG. 64, and shows one subfield among a plurality of subfields constituting one frame. The drive waveform shown in FIG. 65 is substantially the same as the drive waveform shown in FIG. This drive waveform is generated by the switches SW1 to SW3, SW8, SW1 ′ to SW3 ′, SW9 ′ provided in common to each display line, and the switches SW4, SW5, SW4 in the scan drivers 51, 51 ′ in a certain display line i. ', SW5' is controlled by ON / OFF control at an appropriate timing.
[0383]
63 and 64, it is possible to disperse the heat concentration generated by the power consumption in the common circuit portion and to stabilize the circuit operation. In addition, the degree of freedom of control for each display line can be improved.
[0384]
63 and 64 show the case where the switches SW4, SW5, SW4 ′, and SW5 ′ are in the positions as shown in the first embodiment, that is, in the driver circuit, the switches SW4, SW4 ′. Is the same as that shown in the second embodiment, that is, in the power supply circuit, or when the switches SW5 and SW5 ′ are in the position shown in the third embodiment, that is, in the power supply circuit. Can be applied to.
[0385]
In this case, even if the driver circuit is configured as an LSI by a scan driver, the switch required for each display line on the common electrode X side and the scan electrode Y side is either the switch SW4, SW4 ′ or the switch SW5, SW5 ′. Only one switch is required, and the total number of switches can be greatly reduced. As a result, the circuit scale can be reduced and the cost can be suppressed.
[0386]
(Tenth embodiment)
Next, a tenth embodiment of the present invention will be described.
In each of the above embodiments, the power supply voltage of the common electrode X side and the scanning electrode Y is both (+ Vs / 2), and a voltage of opposite phase is applied to both the electrodes X and Y, whereby a differential voltage is applied across the load 20. Vs was applied. That is, assuming that the power supply voltage on the common electrode X side is V1 and the power supply voltage on the scan electrode Y side is V2, V1 = V2. In contrast, in the tenth embodiment, a voltage V1 <V2 or V1> V2 is used as the power supply voltage on the common electrode X side and the scan electrode Y side.
[0387]
FIG. 66 is a diagram illustrating a configuration example of the drive device according to the tenth embodiment. In FIG. 66, the same reference numerals as those shown in FIG. 23 have the same functions, and thus redundant description is omitted.
[0388]
In FIG. 66, unlike the first embodiment shown in FIG. 23, in the first embodiment, the voltage (Vs / 2) is applied to the power supply circuit 43 on the common electrode X side, and the power supply circuit 43 ′ on the scan electrode Y side is applied. While the voltage (Vs / 2) was supplied (V1 = V2 = Vs / 2), in the tenth embodiment, the voltage (Vs / 3) is applied to the power supply circuit 43 on the common electrode X side, and the scanning electrode Y The voltage (2Vs / 3) is supplied to the power supply circuit 43 ′ on the side (V1 = Vs / 3, V2 = 2Vs / 3). Others are the same as the first embodiment.
[0389]
According to the tenth embodiment configured as described above, the absolute value of the voltage applied to the power supply circuit 43 and the driver circuit 44 on the common electrode X side is Vs / 3 at the maximum. Therefore, the withstand voltage of each element provided in these circuits may be Vs / 3, and the withstand voltage can be suppressed to 1/3 of the conventional one.
[0390]
The absolute value of the voltage applied to the power supply circuit 43 ′ and the driver circuit 44 ′ on the scanning electrode Y side is 2 Vs / 3 at the maximum. Therefore, the withstand voltage of each element provided in these circuits may be 2 Vs / 3, and the withstand voltage can be suppressed to 2/3 of the prior art. As a result, an inexpensive element having a small configuration can be used, and the circuit configuration can be simplified and the manufacturing cost can be reduced.
[0390]
For example, when the driver circuit on the common electrode X side is configured as a circuit common to each display line of the PDP and the driver circuit on the scanning electrode Y side is provided for each display line of the PDP, Heat generated by consumption is distributed to each display line on the scanning electrode Y side, but on the common electrode X side, concentrated heat is generated at one place and large heat is generated. Therefore, by applying a voltage to the common electrode X and the scanning electrode Y in the relationship of V1 <V2, it is possible to alleviate the inconvenience that heat generation is concentrated on the common electrode X side.
[0392]
Further, as described above, the power loss when charging / discharging the load 20 is represented by 2Cp · V 2 · f and is proportional to the square of the magnitude of the applied voltage V. Therefore, of the common electrode X side and the scan electrode Y side, the smaller the applied voltage V can suppress the power loss sufficiently, so that it is not particularly necessary to provide a power recovery circuit. Thereby, it can also be set as the structure provided with an electric power collection | recovery circuit only in any one of the common electrode X side and the scanning electrode Y side.
[0393]
Further, by making the applied voltages on the common electrode X side and the scan electrode Y side different, the applied voltage in the reset period can be appropriately adjusted on both the common electrode X side and the scan electrode Y side.
[0394]
FIG. 67 is a time chart showing a driving waveform of the PDP by the driving apparatus configured as shown in FIG. 66, and shows one subfield of a plurality of subfields constituting one frame. Here, a state in which the voltage Vw (not shown in FIG. 66) is applied by the control of its own switch is also shown. The basic form of the drive waveform shown in FIG. 67 is the same as that of FIG. 42 already described, but the amplitude is different.
[0395]
According to the time chart of FIG. 67, the breakdown voltage of each element provided in the power supply circuit 43 and the driver circuit 44 on the common electrode X side may be Vs / 3 + Vw and Vs / 3, respectively. It can be kept low. Further, the breakdown voltage of each element provided in the power supply circuit 43 ′ and the driver circuit 44 ′ on the scan electrode Y side may be 2Vs / 3 + Vw and 2Vs / 3, respectively.
[0396]
FIG. 68 is a diagram showing another configuration example of the driving apparatus according to the tenth embodiment. In FIG. 68, components having the same reference numerals as those shown in FIG. 66 have the same functions, and thus redundant description is omitted.
[0397]
In the configuration shown in FIG. 68, the voltage V2 applied to the power supply circuit 43 ′ on the scan electrode Y side is kVs, and the voltage V1 applied to the power supply circuit 43 on the common electrode X side is 1Vs (V1 + V2 = nVs). The other points are exactly the same as in FIG. For example, there is a case where it is desired to apply a high voltage between the common electrode X and the scan electrode Y in order to improve the light emission efficiency of gas discharge, and it is possible to set V1 = V2 = Vs (V1 + V2 = 2Vs). In this case, each element provided in the driving device can apply a larger differential voltage between the electrodes X and Y while maintaining the same withstand voltage as in the prior art.
[0398]
In the PDP, the voltage Vs applied between the common electrode X and the scan electrode Y during the sustain discharge period is generally 150V to 190V. This voltage is determined by the type of gas sealed in the PDP, the electrode material, the gap between the X and Y electrodes, and the like. The display brightness of the PDP is determined by how many times the voltage Vs is applied between the common electrode X and the scan electrode Y during the sustain discharge period to cause gas discharge. Further, the power required for the gas discharge when the voltage Vs is applied once is determined by the kind of the gas, the electrode material, the gap between the electrodes, and the like. The ratio of luminance to unit power is called luminous efficiency.
[0399]
In a PDP, there is a demand for high brightness with low power. If the type of gas, electrode material, gap between electrodes, etc. are selected in order to increase the luminous efficiency in order to satisfy this requirement, the voltage Vs increases, the breakdown voltage of the circuit increases, and the cost increases. On the other hand, according to the present embodiment, a high voltage can be applied with the same breakdown voltage as before without increasing the breakdown voltage, and the light emission efficiency can be increased.
[0400]
(Eleventh embodiment)
Next, an eleventh embodiment of the present invention will be described. The eleventh embodiment shows one aspect of the tenth embodiment described above, and V1 = 0, V2 = Vs or V1 = Vs, V2 = 0, and the drive waveform in the sustain discharge period is the common electrode X. Alternatively, the voltage is applied from one side of the scanning electrode Y.
[0401]
FIG. 69 is a diagram illustrating a specific configuration example of the drive device according to the eleventh embodiment. In FIG. 69, the same reference numerals as those shown in FIG. 41 have the same functions, and thus redundant description is omitted. The main difference between FIG. 69 and FIG. 41 is that the power supply voltage to which the switches SW1 and SW1 ′ are connected is Vs / 2 in FIG. 41, but is Vs in FIG. .
[0402]
FIG. 70 is a time chart showing an example of a drive waveform in the sustain discharge period by the drive device shown in FIG. In FIG. 70, the drive waveform on the common electrode X side is the same as the example shown in FIG. 43 except that the level of the voltage to be swung is Vs.
[0403]
On the other hand, on the scanning electrode Y side, the switches SW1 ′, SW3 ′, and SW5 ′ are turned on throughout the series of switching operations on the common electrode X side, and the switches SW2 ′, SW4 ′ and the power recovery circuit 33 are turned on. The transistors Tr15 and Tr16 are kept off. Thereby, the applied voltage of the scan electrode Y through the switch SW3 ′ is always kept at zero (ground level). On the contrary, the voltage applied to the scan electrode Y may be kept at zero by keeping the switches SW2 ′, SW4 ′ on and the switches SW1 ′, SW3 ′, SW5 ′ off.
[0404]
In this way, when the voltage on the scan electrode Y side is fixed to the ground level and Vs is used as the power supply voltage on the common electrode X side, compared to the above-described embodiments in which (Vs / 2) is used as the power supply voltage. The power loss on the common electrode X side becomes large. Therefore, it is desirable to provide the power recovery circuit 22 at least on the common electrode X side.
[0405]
As described above, when the voltage of one electrode (common electrode X) is varied, the circuit operation and the sustain discharge can be more stably performed by fixing the voltage of the other electrode (scanning electrode Y). . Further, a positive / negative voltage (± Vs) can be applied from the scan electrode Y side in a period other than the sustain discharge period.
[0406]
FIG. 71 is a diagram showing another configuration example of the driving apparatus according to the eleventh embodiment. In FIG. 71, the same reference numerals as those shown in FIG. 66 have the same functions, and thus redundant description is omitted. In the configuration shown in FIG. 69, since the voltage on the scan electrode Y side is fixed at the ground level, the configuration on the scan electrode Y side is redundant. Therefore, in the example of FIG. 71, the configuration on one electrode side is omitted, and it is simply connected to the ground.
[0407]
In the configuration shown in FIG. 71, the switch SW9 ′ connected to the power supply line of the voltage Vw is provided on the scanning electrode Y side. A reset circuit including a switch SW20 and a resistor R5 is provided at both ends of the switch SW5 ′ on the scan electrode Y side. Further, in the configuration shown in FIG. 71, the common electrode X side of the load 20 is grounded. Thus, when the common electrode X side is grounded and Vs is used as the power supply voltage on the scan electrode Y side, the scan electrode Y side is compared with the above-described embodiments using (Vs / 2) as the power supply voltage. The power loss at becomes large. Therefore, it is desirable to provide the power recovery circuit 33 on the scan electrode Y side. The configuration of the power recovery circuit 33 is the same as that shown in FIG.
[0408]
FIG. 72 is a time chart showing a driving waveform of the PDP by the driving apparatus configured as shown in FIG. 71, and shows one subfield of a plurality of subfields constituting one frame. In the example of FIG. 72, the drive waveform on the scanning electrode Y side is the same as that of the above-described embodiment (however, the absolute value of the applied voltage is Vs or Vw ′). On the other hand, the voltage of the common electrode X is fixed at the ground level.
[0409]
The address electrode A is fixed to the ground level except that the voltage Va is applied during the address period. In the sustain discharge period, the address electrode A may be kept in a high impedance state.
[0410]
FIG. 73 is a diagram showing still another configuration example of the driving apparatus according to the eleventh embodiment. In FIG. 73, the same reference numerals as those shown in FIG. 71 are given the same functions, and therefore, duplicate description is omitted.
[0411]
In the case of FIG. 71, the common electrode X side of the load 20 is grounded, whereas in the configuration shown in FIG. 73, the common electrode X side of the load 20 is connected to the power line of the voltage Vax. In addition, when the voltage on the common electrode X side is fixed to Vax, the offset voltage Vax is selectively applied to the scan electrode Y so that the potential difference between the common electrode X and the scan electrode Y becomes Vs during the sustain discharge period. A configuration that enables this is necessary.
[0412]
For this purpose, the power supply 55 of the voltage Vax connected to the ground, the switch SW29 connected between the power supply 55 and the third signal line OUTA ′, the power supply 55 and the fourth signal line OUTB ′ The switch SW30 is connected between the two. With such a configuration, when the switch SW29 is ON, a positive voltage (+ Vax) is output to the third signal line OUTA ′. When the switch SW30 is ON, a positive voltage (+ Vax) is output to the fourth signal line OUTB ′. Therefore, a voltage using this offset voltage (+ Vax) can be applied to the load 20 from the third signal line OUTA ′ and the fourth signal line OUTB ′ via the output line OUTC ′.
[0413]
FIG. 74 is a time chart showing a driving waveform of the PDP by the driving apparatus configured as shown in FIG. 73, and shows one subfield of a plurality of subfields constituting one frame. In the example of FIG. 74, the drive waveform on the scan electrode Y side is the same as that in the embodiment described above for the reset period and the address period (however, the absolute value of the applied voltage is Vs or Vw ′).
[0414]
Further, in the sustain discharge period, the switches SW29 and SW30 in FIG. 73 are alternately turned on, so that each of the positive voltage (+ Vs) and the negative voltage (−Vs) applied to the scan electrode Y is applied. The voltage Vax is added as an offset voltage. On the other hand, the voltage of the common electrode X is fixed to Vax. Thus, the potential difference between the common electrode X and the scan electrode Y is always Vs during the sustain discharge period.
[0415]
The address electrode A is fixed to the ground level except that the voltage Va is applied during the address period. In the sustain discharge period, the address electrode A may be kept in a high impedance state.
[0416]
According to the drive device configured as shown in FIG. 71 or 73, the power supply circuit and the driver circuit are not required on the common electrode X side, and the configuration on the common electrode X side can be greatly simplified.
[0417]
FIG. 75 is a diagram showing still another configuration example of the driving apparatus according to the eleventh embodiment. In FIG. 75, components having the same reference numerals as those shown in FIGS. 71 and 73 have the same functions, and thus redundant description is omitted.
[0418]
In the driving apparatus shown in FIG. 75, the common electrode X side of the load 20 is connected to the power line of the voltage Vax via the switch SW21 and grounded via the switch SW22. By turning on either the switch SW21 or the switch SW22, the voltage applied to the common electrode X can be switched to either the ground level or Vax.
[0419]
FIG. 76 is a time chart showing a driving waveform of the PDP by the driving device configured as shown in FIG. In FIG. 76, the drive waveforms of the scan electrode Y and the address electrode A are exactly the same as those in FIGS. 72 and 74. Further, the common electrode X is applied by switching to either the ground level or Vax. That is, the applied voltage of the common electrode X is fixed to the ground level during the reset period and the sustain discharge period, and the applied voltage of the common electrode X is fixed to Vax during the address period.
[0420]
FIG. 77 is a diagram showing still another configuration example of the driving apparatus according to the eleventh embodiment. 71, FIG. 73, and FIG. 75, the applied voltage on the common electrode X side is fixed to the ground level or Vax. However, in the driving device shown in FIG. 77, the common electrode X side is not fixed. The correct voltage is applied. Therefore, on the common electrode X side, a switch SW9 that performs switching for the power line of the voltage Vw ′ and a switch SW14 that performs switching for the power line of the voltage Vax are connected in parallel to the second signal line OUTB. Is done.
[0421]
On the other hand, on the scan electrode Y side, a switch SW18 is connected between the scan driver 31 ′ and the power supply line of the voltage Vsc, and a switch SW19 is connected between the scan driver 31 ′ and the power supply line of the voltage (−Vy). Connected. Further, both ends of the scan driver 31 ′ are connected to switches SW23 and SW24, respectively, and a common connection point of these switches SW23 and SW24 is grounded.
[0422]
FIG. 78 is a time chart showing a driving waveform of the PDP by the driving apparatus configured as shown in FIG. 77, and shows one subfield of a plurality of subfields constituting one frame. As shown in FIG. 78, on the common electrode X side, the switches SW1 to SW5, SW9, and SW14 are ON / OFF controlled at appropriate timing, so that in addition to the voltage (± Vs) in the sustain discharge period, the reset period The pulses of various voltages Vw ′ and Vax necessary in the address period are applied to the load 20.
[0423]
On the other hand, on the scan electrode Y side, in the reset period and the sustain discharge period, the switches SW18 and SW19 are both turned off and the switches SW23 and SW24 are both turned on, so that the applied voltage is fixed at the ground level. In the address period, the switches SW23 and SW24 are kept OFF, and the switches SW18 and SW19 are turned ON, thereby applying the voltage Vsc − (− Vy) to the power supply terminals at both ends of the scan driver 31 ′. The scan driver 31 'is ON / OFF controlled at an appropriate timing, so that a pulse voltage necessary for scanning is applied to the scan electrode Y. As a result, the circuit on the scanning electrode Y side can be further simplified, so that the manufacturing cost can be reduced as compared with the conventional case.
[0424]
The address electrode A is fixed at the ground level except that the voltage Va is applied during the address period. In the sustain discharge period, the address electrode A may be kept in a high impedance state.
[0425]
FIG. 79 is a diagram showing still another configuration example of the driving apparatus according to the eleventh embodiment. In FIG. 79, components having the same reference numerals as those shown in FIG. 77 have the same functions, and thus redundant description is omitted. In FIG. 77, the switches SW23 and SW24 for setting the applied voltage of the scanning electrode Y to the ground level are configured as a circuit common to each display line of the PDP.
[0426]
On the other hand, in the configuration shown in FIG. 79, the switch SW25 for setting the applied voltage of the scan electrode Y to the ground level is incorporated as a part of the scan driver 31 ′, and the switch SW25 is provided for each display line. Thereby, switching control can be performed individually for each display line. In addition, since the circuit on the scanning electrode Y side can be further simplified, the manufacturing cost can be reduced as compared with the conventional case. The drive waveform configured as shown in FIG. 79 is the same as that in FIG.
[0427]
(Twelfth embodiment)
Next, a twelfth embodiment of the present invention will be described.
In the first to eleventh embodiments described above, the voltage applied to the power supply circuit is a positive voltage, and positive and negative voltages are generated from the positive voltage in the first signal line OUTA and the second signal line OUTB. It was. On the other hand, in the twelfth embodiment, the voltage applied to the power supply circuit is a negative voltage, and the negative voltage is applied to the output line OUTC through the first signal line OUTA and the second signal line OUTB. Is to create.
[0428]
FIG. 80 is a diagram illustrating a configuration example of the driving apparatus according to the twelfth embodiment. In FIG. 80, components having the same reference numerals as those shown in FIG. 2 have the same functions, and thus redundant description is omitted. The difference between FIG. 80 and FIG. 2 is that the voltage applied to the power supply circuits 43 and 43 ′ is a positive voltage (+ Vs / 2) in the case of FIG. / 2).
[0429]
Since the polarities of the voltages applied to the power supply circuits 43 and 43 ′ are opposite in this way, the position where the capacitor C1 is connected differs between FIG. 80 and FIG. That is, in the case of FIG. 2, the capacitor C1 is connected between the switch SW2 and the switch SW3, but in the case of FIG. 80, it is connected between the switch SW1 and the switch SW2.
[0430]
FIG. 81 is a time chart showing drive waveforms in the sustain discharge period of the PDP by the drive device configured as shown in FIG. In the first to eleventh embodiments in which a positive voltage is applied to the power supply circuits 43 and 43 ′, the switches SW1, SW3 and SW4 are mainly switched during the period until the electric charge is accumulated in the capacitor C1. A positive voltage is applied to the load 20 by control, and then a negative voltage is applied to the load 20 by switching control of the switches SW2 and SW5.
[0431]
On the other hand, in the twelfth embodiment in which a negative voltage is applied to the power supply circuits 43 and 43 ′, the switches SW1, SW3 and SW5 are mainly switched during the period until the charge is accumulated in the capacitor C1. A negative voltage is applied to the load 20 by control, and then a positive voltage is applied to the load 20 by switching control of the switches SW2 and SW4. Since the other basic portions of the drive waveform are the same as those already described, detailed description thereof is omitted here.
[0432]
As described above, also in the twelfth embodiment in which a negative voltage is applied to the power supply circuits 43 and 43 ′, the breakdown voltage of each element provided in the power supply circuits 43 and 43 ′ and the driver circuits 44 and 44 ′. Can be kept lower than in the past. As a result, an inexpensive element having a small configuration can be used, and the circuit configuration can be simplified and the manufacturing cost can be reduced. In addition, there is also a method of moving the voltage of the output line OUTC shown in FIG. 81 between GND and Vs by applying a positive voltage to the power supply circuits 43 and 43 ′ shown in FIG. 80 of the twelfth embodiment.
[0433]
FIG. 82 is a diagram showing another configuration example of the driving apparatus according to the twelfth embodiment, and the same reference numerals are given to the same configurations as those in FIGS. 80, 77, and 79. That is, the drive device shown in FIG. 82 is a combination of the circuit shown in FIGS. 77 and 79 with the idea shown in FIG. In this way, the circuit on the scan electrode Y side shown in FIGS. 77 and 79 can be reduced. Further, in some cases, it is possible to reduce Vsc power by setting Vsc = Vs.
[0434]
(13th Embodiment)
Next, a thirteenth embodiment of the present invention is described.
FIG. 83 is a diagram illustrating a configuration example of the drive device according to the thirteenth embodiment. The configuration shown in FIG. 83 is a further application of the configuration shown in FIG. 2, and the components corresponding to each other are denoted by the same reference numerals and redundant description is omitted.
[0435]
In FIG. 83, the switches SW1 and SW2 on the common electrode X side are connected in series between a power supply line of a voltage (Vs / 4) generated from an A / D power supply (not shown) and the ground. One terminal of the capacitor C1 is connected from the middle of the two switches SW1 and SW2, and the switch SW3 is connected between the other terminal of the capacitor C1 and the ground.
[0436]
Further, a switch SW27, a capacitor C7 and a switch SW28 are connected in series in parallel with the switches SW1 and SW2 connected between the power line of the voltage (Vs / 4) and the ground. Further, the switch SW26 is connected between the other terminal of the capacitor C1 and one terminal connected to the switch SW27 of the capacitor C7. A driver circuit 44 is connected between one terminal of the capacitor C1 and the other terminal of the capacitor C7. The driver circuit 44 includes two switches SW4 and SW5.
[0437]
Further, the switches SW1 ′ and SW2 ′ on the scanning electrode Y side are connected in series between a power supply line of a voltage (Vs / 4) generated from an A / D power supply (not shown) and the ground. One terminal of a capacitor C4 is connected from the middle of the two switches SW1 ′ and SW2 ′, and a switch SW3 ′ is connected between the other terminal of the capacitor C4 and the ground.
[0438]
In addition, a switch SW27 ′, a capacitor C8, and a switch SW28 ′ are connected in series in parallel with the switches SW1 ′ and SW2 ′ connected between the power line of the voltage (Vs / 4) and the ground. Further, the switch SW26 ′ is connected between the other terminal of the capacitor C4 and one terminal connected to the switch SW27 ′ of the capacitor C8. A driver circuit 44 'is connected between one terminal of the capacitor C4 and the other terminal of the capacitor C8. The driver circuit 44 ′ includes two switches SW4 ′ and SW5 ′.
[0439]
FIG. 84 is a time chart showing a detailed example of the drive waveform in the sustain discharge period by the drive device of this embodiment.
As shown in FIG. 84, on the common electrode X side, first, the five switches SW1, SW3, SW27, SW28, SW5 are turned on, and the remaining switches SW2, SW26, SW4 are turned off. As a result, the voltage of the first signal line OUTA becomes the voltage level (Vs / 4) given through the switch SW1, and the voltage of the second signal line OUTB remains at the ground level. At this time, charges corresponding to the voltage (Vs / 4) are accumulated in the capacitors C1 and C7, respectively. Further, when the switch SW5 is turned off and the switch SW4 is turned on, the voltage (Vs / 4) of the first signal line OUTA is output to the output line OUTC and applied to the common electrode X of the load 20.
[0440]
Next, the switches SW26, SW27, SW28, and SW4 are turned on, and the remaining switches SW1, SW2, SW3, and SW5 are turned off. As a result, the capacitors C1 and C7 are connected in series between the power supply line of the voltage (Vs / 4) and the ground. At this time, the capacitors C1 and C7 store charges corresponding to the voltage (Vs / 4). Therefore, the voltage of the first signal line OUTA is the result of adding the charges of the two capacitors C1 and C7. (Vs / 2). Even in this state, the voltage of the second signal line OUTB remains at the ground level. At this time, since the switch SW5 is OFF and the switch SW4 is ON, the voltage (Vs / 2) of the first signal line OUTA is output to the output line OUTC and applied to the common electrode X of the load 20. .
[0441]
At the next timing, the switches SW1, SW3, SW27, SW28, and SW4 are turned on, and the remaining switches SW2, SW26, and SW5 are turned off. As a result, the voltage (Vs / 4) is supplied to the first signal line OUTA via the switch SW1. Even in this state, the voltage of the second signal line OUTB remains at the ground level. At this time, since the switch SW5 is OFF and the switch SW4 is ON, the voltage (Vs / 4) of the first signal line OUTA is output to the output line OUTC and applied to the common electrode X of the load 20. .
[0442]
Next, SW4 is turned off and switch SW5 is turned on. As a result, the voltage of the second signal line OUTB is output to the output line OUTC, and the voltage applied to the common electrode X of the load 20 is set to the ground level.
[0443]
Thereafter, the switches SW3, SW26, and SW5 are turned on, and the remaining switches SW1, SW2, SW27, SW28, and SW4 are turned off, so that the voltage of the second signal line OUTB corresponds to the charge accumulated in the capacitor C7. (−Vs / 4). At this time, since the switch SW5 is ON, the voltage (−Vs / 4) of the second signal line OUTB is output to the output line OUTC and applied to the common electrode X of the load 20.
[0444]
Next, the switch SW3 is turned off and the switch SW2 is turned on. As a result, the capacitors C1 and C7 are connected in series between the common electrode X and the ground. At this time, since charges of voltage (Vs / 4) are accumulated in the capacitors C1 and C7, the voltage of the second signal line OUTB is obtained as a result of adding the charges of these two capacitors C1 and C7. Is reduced to (−Vs / 2). Further, the voltage of the first signal line OUTA remains at the ground level. At this time, since the switch SW5 is ON, the voltage (−Vs / 2) of the second signal line OUTB is output to the output line OUTC and applied to the common electrode X of the load 20.
[0445]
Thereafter, the switch SW2 is turned off and the switch SW3 is turned on again. As a result, the voltage of the first signal line OUTA is raised to (+ Vs / 4), and the voltage of the second signal line OUTB is raised to (−Vs / 4). At this time, since the switch SW5 is ON, the voltage (−Vs / 4) of the second signal line OUTB is output to the output line OUTC and applied to the common electrode X of the load 20.
[0446]
Next, as in the first state, the five switches SW1, SW3, SW27, SW28, SW5 are turned on, and the remaining switches SW2, SW26, SW4 are turned off. As a result, the voltage of the first signal line OUTA becomes (Vs / 4), and the voltage of the second signal line OUTB becomes the ground level. At this time, the voltage of the second signal line OUTB is output to the output line OUTC, and the voltage applied to the common electrode X of the load 20 is set to the ground level. Thereafter, the same is repeated.
[0447]
Although not shown in FIG. 84, the switches SW1 ′, SW2 ′, SW3 ′, SW26 ′, SW27 ′, SW28 ′, SW4 ′, and SW5 ′ on the scan electrode Y side are the same as on the common electrode X side. Switching control is performed. However, as shown in FIG. 84, switching control is performed so that the output voltage of the output line OUTC on the common electrode X side and the output voltage of the output line OUTC ′ on the scan electrode Y side are in opposite phases.
[0448]
As described above, according to the present embodiment, a drive waveform that alternately repeats positive and negative voltages (± Vs / 2) is output on the output lines OUTC and OUTC ′ from one power source that generates the voltage (Vs / 4). I can make it. The positive and negative voltages (± Vs / 2) created in this way are applied to the output line OUTC on the common electrode X side and the output line OUTC ′ on the scan electrode Y side in opposite phases, so that both of the loads 20 A differential voltage (Vs) can be applied between the electrodes X and Y.
[0449]
As described above, when the capacitive load 20 is driven, the power is 2 Cp · V 2 using the capacitance Cp of the load 20, the drive voltage V of the load 20, and the frequency f when applying a voltage to the load 20. -Represented by f. In the present embodiment, the absolute value of the voltage applied to the load 20 may be ¼ that of the conventional voltage. Instead, the frequency when the voltage is applied to the load 20 is quadrupled, so that the load 20 is driven. The power loss at that time is expressed by 2Cp · (V / 4) 2 · (4f), and can be suppressed to ¼ of the conventional one. Therefore, even if no power recovery circuit is provided, the power use efficiency can be improved compared to the conventional case.
[0450]
Here, positive and negative voltages (± Vs / 2) are applied in opposite phases from both sides of the common electrode X and the scan electrode Y. However, as in the eleventh embodiment, for example, the scan electrode Y side May be connected to the ground, and a positive and negative voltage (± Vs) may be applied to the common electrode X. The configuration in this case is as shown in FIG. In the configuration of FIG. 85, the configuration on the common electrode X side is substantially the same as the configuration shown in FIG. 83, except that the power supply line is not (Vs / 4) but (Vs / 2). In the configuration of FIG. 85, the scanning electrode Y side is connected to the ground. The drive waveform in this case is as shown in FIG.
[0451]
As described above, according to the example of FIG. 85, a drive waveform in which positive and negative voltages (± Vs) are alternately repeated can be produced on the output line OUTC from one power source that generates the voltage (Vs / 2).
[0452]
In the example of FIG. 83, the drive waveform is generated using the A / D power supply of the voltage (Vs / 4), but it has the same configuration as the switches SW26 to SW28 and the capacitor C7 shown in FIG. By adding a low voltage low power circuit unit in series, it is possible to generate a similar drive waveform using an A / D power supply with a smaller voltage (for example, 1/8 Vs, 1/16 Vs,...). Is possible. Therefore, the power loss at the time of driving the load 20 can be further reduced. For example, when the above-described low-voltage low-power circuit unit is placed in n stages in series, the power loss when driving the load 20 is represented by 2Cp · (V / n) 2 · (nf), n can be suppressed.
[0453]
FIG. 87 is a diagram illustrating another configuration example of the drive device according to the thirteenth embodiment. The same components as those of the drive device illustrated in FIG. 83 are denoted by the same reference numerals, and redundant description is omitted. .
[0454]
The driving device shown in FIG. 87 includes a switch SW30 on the common electrode X side and a switch SW30 ′ on the scanning electrode Y side in addition to the configuration shown in FIG. Switch SW30 is connected between one terminal of capacitor C1 and the other terminal of capacitor C7. The switch SW30 ′ is connected between one terminal of the capacitor C4 and the other terminal of the capacitor C8. The switch SW1 is connected between the Vs / 4 power supply line and one terminal of the capacitor C1. The switch SW1 ′ is connected between the Vs / 4 power supply line and one terminal of the capacitor C4. One terminal of the capacitor C7 is connected to the first signal line OUTA, and one terminal of the capacitor C8 is connected to the third signal line OUTA ′.
[0455]
In FIG. 83, the switch SW28 is connected between the second signal line OUTB and the ground, and the switch SW28 ′ is connected between the fourth signal line OUTB ′ and the ground. In this case, the switch SW28 is connected between the second signal line OUTB and the switch SW3, and the switch SW28 ′ is connected between the fourth signal line OUTB ′ and the switch SW3 ′.
[0456]
FIG. 88 is a time chart showing a detailed example of drive waveforms in the sustain discharge period by the drive device shown in FIG.
As shown in FIG. 88, the drive waveform of the first signal line OUTA on the common electrode X side is the same as that shown in FIG. 84 except for the following two points. The first difference is that in the example of FIG. 84, when a positive voltage is applied to the voltage of the first signal line OUTA, the voltage of the second signal line OUTB is fixed to the ground level. In the example of FIG. 88, however, the voltage of the second signal line OUTB is raised to (+ Vs / 4) while the voltage of the first signal line OUTA is set to (+ Vs / 2).
[0457]
The second difference is that in the example of FIG. 84, the voltage of the first signal line OUTA is set to the ground level while the voltage of the second signal line OUTB is set to (−Vs / 2). In this example, the level is lowered to the (−Vs / 4) level. Hereinafter, this second difference will be described in detail.
[0458]
That is, when the switches SW1, SW2, SW4, SW27, and SW28 are turned off and the switches SW3, SW5, and SW26 are turned on to lower the voltage of the second signal line OUTB from the ground level to (−Vs / 4), the switch SW30. Is turned OFF to lower the voltage of the first signal line OUTA from (Vs / 4) to the ground level. Here, the switch SW3 and the switch SW26 are turned on, but the switches SW3 and SW26 may be turned off and the switches SW2 and SW27 may be turned on. Furthermore, if the switch SW28 is also turned on, the capacitor C7 and the capacitor C1 can be connected in parallel, so that the charge charged in the capacitor C1 can be used more effectively.
[0459]
Next, with the voltage of the first signal line OUTA set to the ground level and the voltage of the second signal line OUTB set to (−Vs / 4) in this way, the switch SW2 is turned on and the switch SW3 is turned off. Thus, the voltage of the first signal line OUTA is lowered from the ground level (−Vs / 4), and the voltage of the second signal line OUTB is lowered from (−Vs / 4) to (−Vs / 2).
[0460]
Thereafter, the switch SW2 is turned off and the switch SW3 is turned on again. As a result, the voltage of the first signal line OUTA is raised to the ground level, and the voltage of the second signal line OUTB is raised to (−Vs / 4). Next, as in the first state, the switches SW1, SW3, SW27, SW28, and SW5 are turned on, and the remaining switches SW2, SW26, SW4, and SW30 are turned off. As a result, the voltage of the first signal line OUTA becomes (Vs / 4), and the voltage of the second signal line OUTB becomes the ground level.
[0461]
The same switching control as that on the common electrode X side is performed for each of the switches SW1 ′, SW2 ′, SW3 ′, SW26 ′, SW27 ′, SW28 ′, SW4 ′, SW5 ′, and SW30 ′ on the scanning electrode Y side. However, as shown in FIG. 87, switching control is performed so that the output voltage of the output line OUTC on the common electrode X side and the output voltage of the output line OUTC ′ on the scan electrode Y side are in opposite phases.
[0462]
As described above, also in the configuration example of FIG. 87, a drive waveform that alternately repeats positive and negative voltages (± Vs / 2) is output on the output lines OUTC and OUTC ′ from one power source that generates the voltage (Vs / 4). Can be created. The positive and negative voltages (± Vs / 2) created in this way are applied to the output line OUTC on the common electrode X side and the output line OUTC ′ on the scan electrode Y side in opposite phases, so that both of the loads 20 A differential voltage (Vs) can be applied between the electrodes X and Y. Thus, since the absolute value of the voltage applied to the load 20 is ¼ of the conventional value, the power loss when driving the load 20 can be suppressed to ¼ of the conventional value. Therefore, even if no power recovery circuit is provided, the power use efficiency can be improved compared to the conventional case.
[0463]
The voltage of the output line OUTC (OUTC ′) is set to the ground level by setting the voltage of the first signal line OUTA (OUTA ′) to the ground level and the voltage of the second signal line OUTB (OUTB ′) to (− Vs / 4) and the switch SW4 (SW4 ′) is turned on, but the example shown in FIG. 87 is preferable in order to lengthen the period for charging the capacitors C1, C7, C4, and C8. .
[0464]
Here, positive and negative voltages (± Vs / 2) are applied in opposite phases from both sides of the common electrode X and the scan electrode Y. However, as in the eleventh embodiment, for example, the scan electrode Y side May be connected to the ground, and a positive and negative voltage (± Vs) may be applied to the common electrode X. The configuration in this case is as shown in FIG. In the configuration of FIG. 89, the configuration on the common electrode X side is substantially the same as the configuration shown in FIG. 87, except that the power supply line is not (Vs / 4) but (Vs / 2). In the configuration of FIG. 89, the scan electrode Y side is connected to the ground. The drive waveform in this case is as shown in FIG.
[0465]
As described above, according to the example of FIG. 89, a driving waveform in which positive and negative voltages (± Vs) are alternately repeated can be produced on the output line OUTC from one power source that generates the voltage (Vs / 2).
[0466]
In the example of FIG. 87, the drive waveform is generated using the A / D power supply of the voltage (Vs / 4), but the same configuration as the switches SW26 to SW28 and SW30 and the capacitor C7 shown in FIG. By adding a low-voltage low-power circuit unit having a further in series, a similar driving waveform is generated using an A / D power supply with a smaller voltage (for example, 1/8 Vs, 1/16 Vs,...). It is possible. Therefore, the power loss at the time of driving the load 20 can be further reduced. For example, when the above-described low-voltage low-power circuit unit is placed in n stages in series, the power loss when driving the load 20 is represented by 2Cp · (V / n) 2 · (nf), n can be suppressed.
[0467]
FIG. 91 is a diagram showing another configuration example of the driving apparatus according to the thirteenth embodiment. The same components as those of the driving apparatus shown in FIG. 89 and FIG. Is omitted.
[0468]
The driving device shown in FIG. 91 has two low-voltage low-power circuit sections arranged in series on the common electrode X side as in the example of FIG. 89, and a negative voltage (−Vs) as a power source as shown in FIG. / 2), and as shown in FIG. 77, the scan electrode Y side is constituted by the scan driver 31 ′ and the power supply line of the voltage Vsc, and the voltage (± Vs) is applied to one side of the load 20. It is a combination.
[0469]
With this configuration, a voltage (± Vs) is applied to the load 20 from the common electrode X side, and the circuit on the scan electrode Y side can be simplified. Further, the external power supply voltage is (−Vs / 2), and the power consumption with respect to the load 20 is ½ of that in the prior art. Further, the withstand voltages of the driver circuit 44 and the scan driver 31 ′ may be equal to or higher than Vs / 2 (in the case of Vsc = Vs / 2), and the withstand voltage can be suppressed to ½ of the conventional one.
[0470]
FIG. 92 is a time chart showing a detailed example of drive waveforms in the sustain discharge period by the drive device shown in FIG.
As shown in FIG. 92, the drive waveforms of the output line OUTC on the common electrode X side and the output line OUTC ′ on the scanning electrode Y side are exactly the same as those shown in FIG. Further, in the example of FIG. 90, the drive waveform of the first signal line OUTA and the second signal line OUTB on the common electrode X side is longer in the (Vs / 2) level period than in the ground level period. On the other hand, in the example of FIG. 92, on the contrary, the drive waveforms in both figures are almost the same except that the ground level period is longer than the (Vs / 2) level period.
[0471]
The method of setting the voltage of the output line OUTC to the ground level is a method of setting the voltage of the first signal line OUTA to (Vs / 2), the voltage of the second signal line OUTB to the ground level, and turning on the switch SW5. However, in order to lengthen the period for charging the capacitors C1 and C7, the voltage of the first signal line OUTA is set to the ground level and the voltage of the second signal line OUTB is set as shown in the example shown in FIG. It is preferable to set the switch SW4 to ON by setting it to (−Vs / 2) ground level.
[0472]
In addition, in the example of FIG. 92, as a method of setting the voltage of the first signal line OUTA to (Vs / 2) and the voltage of the second signal line OUTB to the ground level in the first part of the time chart, Although SW30 is turned on, there is also a method of turning on switch SW2 and switch SW28. Furthermore, if the switch SW27 is also turned on, the charge charged in the capacitor C1 can be used more effectively.
[0473]
Although the first to thirteenth embodiments have been described above, these driving devices can be applied to a plasma display device. The configuration of the plasma display device is as shown in FIGS.
[0474]
(Fourteenth embodiment)
Next, a fourteenth embodiment of the present invention is described.
In the fourteenth embodiment, the driving method shown in each of the above embodiments is applied to the driving method described in Japanese Patent No. 2801893 which has already been acquired by the present applicant.
FIG. 93 and FIG. 94 are diagrams illustrating the schematic configuration of the PDP and the schematic configuration of the plasma display device described in Japanese Patent No. 2801893. FIG. 95 is a diagram schematically showing a configuration of a driving apparatus that realizes the driving method described in Japanese Patent No. 2801893.
[0475]
Hereinafter, the driving method described in Japanese Patent No. 2801893 will be briefly described with reference to FIG. In FIG. 95, among the plurality of parallel common electrodes X provided on one surface of the load 20 (PDP), the odd-numbered common electrode Xo is connected to the odd-numbered Xo driver 61, and the even-numbered common electrode Xe is The even-numbered Xe driver 62 is connected.
[0476]
A plurality of parallel scan electrodes Y1 to Yn provided on one surface of the load 20 (PDP) are connected to scan drivers 31′-1 to 31′-n provided for the respective display lines. Among the plurality of scan drivers 31′-1 to 31′-n, the odd-numbered scan drivers 31′-1, 31′-3... Are connected to the odd-numbered Yo common circuit 63, and the even-numbered scan drivers 31′-1 to 31′-n are connected. The drivers 31′-2, 31′-4,... Are connected to the even Ye common circuit 64.
[0477]
At a certain timing t1, the common electrode X and the scanning electrode Y are driven by a combination of the Xo driver 61 and the Yo common circuit 63 and the Xe driver 62 and the Ye common circuit 64. At the next timing t2, the common electrode X and the scanning electrode Y are driven by the combination of the Xo driver 61 and the Ye common circuit 64 and the Xe driver 62 and the Yo common circuit 63.
[0478]
The above operation is performed by dividing the odd-numbered display lines and the even-numbered display lines into separate fields and repeating this alternately to display the entire screen. In the conventional plasma display device shown in FIG. 99, only the driving corresponding to the driving at the timing t1 is performed, whereas in the example of FIG. 95, the driving for interpolating the driving of the display line at the timing t1 is performed at the timing t2. By doing so, the display lines of the PDP are artificially doubled so that the display resolution and brightness can be improved.
[0479]
In the fourteenth embodiment, the configurations described in the first to thirteenth aspects are applied to the Xo driver 61, Xe driver 62, Yo common circuit 63, and Ye common circuit 64 shown in FIG.
That is, the load 20 shown in FIG. 95 is a plasma display panel, and can be described by applying the operations described in FIGS. 56 to 60 to the Xo driver 61, the Xe driver 62, the Yo common circuit 63, and the Ye common circuit 64, for example. The scan driver 31 ′ shown in FIG. 56 can be described by applying to 31′-1, 31′-3,.
[0480]
In this way, it is possible to improve the display resolution and brightness of the PDP while suppressing the breakdown voltage of the element, reducing power consumption by lowering the voltage, and reducing costs by lowering the voltage and lowering the breakdown voltage. Can do.
[0481]
(Fifteenth embodiment)
Next, a fifteenth embodiment of the present invention is described.
FIG. 96 is a further application of the configuration shown in FIG. 2, and the components corresponding to each other are denoted by the same reference numerals. Since the difference from FIG. 2 is only the input voltage of the power supply circuit, the output waveforms of the output lines OUTC and OUTC ′ are as shown in FIG. Details of the operation are the same as in FIG.
[0482]
(Other embodiments)
FIG. 98 is a diagram for explaining another embodiment. FIG. 98 shows another method for applying a voltage to the capacitor C1. That is, a power source VIN is installed on the primary side, and on the secondary side, a voltage nVIN that is arbitrarily n times the input voltage VIN is generated using the coils L1 and L2, and applied to the capacitor C1. And operation | movement of said each embodiment is implement | achieved using switch SW2, SW3. With this configuration, the switch SW1 can be omitted and the power source can be simplified.
[0483]
In each of the embodiments described above, the example in which the driving voltage is applied to the load of the flat panel display device, particularly the AC drive type PDP device has been described. However, the load targeted by the present invention is limited to this example. However, the present invention can be applied to devices other than EL display devices and flat display devices.
[0484]
【The invention's effect】
As described above in detail, according to the present invention, the maximum voltage applied to each element in the drive circuit can be set to a voltage lower than a predetermined voltage to be applied to the plasma display panel. It can be kept low compared to the prior art. As a result, an inexpensive element having a small configuration can be used, and the circuit configuration can be simplified and the manufacturing cost can be reduced.
In addition, according to the present invention, the voltage applied to the plasma display panel may be a voltage whose absolute value is smaller than the predetermined voltage, so that the period of applying the voltage to the plasma display panel is twice that of the conventional case. As a whole, the power loss can be reduced as compared with the conventional case where the predetermined voltage itself is applied to the plasma display panel.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing elemental features of a driving device according to an embodiment;
FIG. 2 is a diagram illustrating a configuration example of a drive device according to the first embodiment.
FIG. 3 is a time chart showing an example of a driving waveform in a sustain discharge period by the driving device shown in FIG. 2;
4 is a time chart showing another example of a drive waveform in a sustain discharge period by the drive device shown in FIG. 2; FIG.
FIG. 5 is a diagram illustrating a specific configuration example of the drive device according to the first embodiment;
6A is a diagram illustrating a configuration example of a switch, FIG. 6A illustrates a configuration example of a switch SW3, FIG. 6B illustrates a configuration example of the switches SW1 and SW2, and FIG. 6C illustrates a configuration example of the switch SW3; FIG.
FIG. 7 is a diagram showing an example of a drive waveform of a pulse voltage applied to electrodes X and Y during a sustain discharge period.
FIG. 8 is a diagram illustrating an example of a drive waveform of a pulse voltage applied to electrodes X and Y during a sustain discharge period.
FIG. 9 is a diagram illustrating an example of a drive waveform of a pulse voltage applied to electrodes X and Y during a sustain discharge period.
FIG. 10 is a diagram showing an example of a drive waveform of a pulse voltage applied to electrodes X and Y during a sustain discharge period.
FIG. 11 is a diagram illustrating an example of a drive waveform of a pulse voltage applied to electrodes X and Y during a sustain discharge period.
12 is a diagram illustrating an example of a driving waveform of a pulse voltage applied to electrodes X and Y during a sustain discharge period. FIG.
FIG. 13 is a diagram showing an example of a drive waveform of a pulse voltage applied to electrodes X and Y during a sustain discharge period.
14 is a time chart showing an example of switching control for generating the drive waveform shown in FIG. 7; FIG.
FIG. 15 is a time chart showing an example of switching control for generating the drive waveform shown in FIG. 8;
FIG. 16 is a time chart showing an example of switching control for generating the drive waveform shown in FIG. 9;
17 is a time chart showing an example of switching control for generating the drive waveform shown in FIG. 10;
18 is a time chart showing an example of switching control for generating the drive waveform shown in FIG. 11. FIG.
FIG. 19 is a time chart showing another example of switching control for generating the drive waveform shown in FIG. 11;
20 is a time chart showing an example of switching control for generating the drive waveform shown in FIG. 12. FIG.
21 is a time chart showing an example of switching control for generating the drive waveform shown in FIG. 13; FIG.
22 is a time chart showing another example of switching control for generating the drive waveform shown in FIG. 13; FIG.
FIG. 23 is a diagram showing another configuration example of the driving apparatus according to the first embodiment.
FIG. 24 is a time chart showing an example of a drive waveform in a sustain discharge period by the drive device configured as shown in FIG.
FIG. 25 is a time chart showing another example of drive waveforms in the sustain discharge period by the drive device configured as shown in FIG.
FIG. 26 is a diagram illustrating a configuration example of a driving apparatus according to a second embodiment.
FIG. 27 is a diagram showing another configuration example of the driving apparatus according to the second embodiment.
FIG. 28 is a time chart showing an example of a drive waveform in a sustain discharge period by the drive device configured as shown in FIG. 27;
FIG. 29 is a diagram illustrating a configuration example of a driving apparatus according to a third embodiment.
FIG. 30 is a diagram showing another configuration example of the driving apparatus according to the third embodiment.
FIG. 31 is a time chart showing an example of a drive waveform in a sustain discharge period by the drive device configured as shown in FIG. 30;
FIG. 32 is a diagram illustrating a configuration example of a driving apparatus according to a fourth embodiment.
FIG. 33 is a diagram showing another configuration example of the driving apparatus according to the fourth embodiment.
FIG. 34 is a time chart showing an example of a drive waveform in a sustain discharge period by the drive device configured as shown in FIG.
FIG. 35 is a diagram illustrating a configuration example of a driving apparatus according to a fifth embodiment.
36 is a time chart showing an example of drive waveforms in the reset period and the sustain discharge period by the drive device configured as shown in FIG. 35. FIG.
FIG. 37 is a diagram showing another configuration example of the driving apparatus according to the fifth embodiment.
FIG. 38 is a time chart showing an example of a drive waveform by the drive device configured as shown in FIG.
FIG. 39 is a diagram showing another configuration example of the driving apparatus according to the fifth embodiment.
40 is a time chart showing an example of drive waveforms in a reset period and a sustain discharge period by the drive device configured as shown in FIG. 39. FIG.
FIG. 41 is a diagram illustrating a configuration example of a driving device according to a sixth embodiment.
FIG. 42 is a time chart showing an example of a drive waveform by the drive device configured as shown in FIG. 41;
43 is a timing chart showing a state of power recovery in the power recovery circuit shown in FIG. 41. FIG.
FIG. 44 is a diagram showing another configuration example of the driving apparatus according to the sixth embodiment.
45 is a timing chart showing a state of power recovery in the power recovery circuit shown in FIG. 44. FIG.
FIG. 46 is a diagram showing another configuration example of the driving apparatus according to the sixth embodiment.
FIG. 47 is a diagram showing another configuration example of the driving apparatus according to the sixth embodiment.
FIG. 48 is a diagram showing another configuration example of the driving apparatus according to the sixth embodiment.
FIG. 49 is a diagram showing another configuration example of the driving apparatus according to the sixth embodiment.
FIG. 50 is a diagram showing another configuration example of the driving apparatus according to the sixth embodiment.
FIG. 51 is a diagram showing another configuration example of the driving apparatus according to the sixth embodiment.
FIG. 52 is a time chart showing an example of a drive waveform in a sustain discharge period by the drive device configured as shown in FIG.
FIG. 53 is a view showing another configuration example of the driving apparatus according to the sixth embodiment.
FIG. 54 is a time chart showing an example of a drive waveform in a sustain discharge period by the drive device configured as shown in FIG. 51;
FIG. 55 is a diagram showing another configuration example of the driving apparatus according to the sixth embodiment.
FIG. 56 is a diagram showing a configuration example of a driving apparatus according to a seventh embodiment.
FIG. 57 is a time chart showing an example of a drive waveform by the drive device configured as shown in FIG. 56;
FIG. 58 is a diagram showing another configuration example of the driving apparatus according to the seventh embodiment.
FIG. 59 is a time chart showing an example of a drive waveform by the drive device configured as shown in FIG.
FIG. 60 is a diagram showing a configuration example of a driving apparatus according to an eighth embodiment.
61 is a view showing another configuration example of the driving apparatus according to the eighth embodiment. FIG.
FIG. 62 is a time chart showing an example of a drive waveform by the drive device configured as shown in FIG. 61;
FIG. 63 is a diagram showing a configuration example of a driving apparatus according to a ninth embodiment.
FIG. 64 is a diagram showing another configuration example of the driving apparatus according to the ninth embodiment.
FIG. 65 is a time chart showing an example of a drive waveform by the drive device configured as shown in FIG. 64;
FIG. 66 is a diagram showing a configuration example of a driving apparatus according to a tenth embodiment.
67 is a time chart showing an example of a drive waveform by the drive device configured as shown in FIG. 66. FIG.
FIG. 68 is a diagram showing another configuration example of the driving apparatus according to the tenth embodiment.
FIG. 69 is a diagram showing a configuration example of a driving apparatus according to an eleventh embodiment.
FIG. 70 is a time chart showing an example of a drive waveform in a sustain discharge period by the drive device configured as shown in FIG. 69;
FIG. 71 is a diagram showing another configuration example of the driving apparatus according to the eleventh embodiment.
72 is a time chart showing an example of a drive waveform by the drive device configured as shown in FIG. 71. FIG.
FIG. 73 is a diagram showing another configuration example of the driving apparatus according to the eleventh embodiment.
74 is a time chart showing an example of a drive waveform by the drive device configured as shown in FIG. 73. FIG.
FIG. 75 is a diagram showing another configuration example of the driving apparatus according to the eleventh embodiment.
FIG. 76 is a time chart showing an example of a drive waveform by the drive device configured as shown in FIG. 75;
77 is a diagram showing another configuration example of the driving apparatus according to the eleventh embodiment. FIG.
78 is a time chart showing an example of a drive waveform by the drive device configured as shown in FIG. 77;
FIG. 79 is a diagram showing another configuration example of the driving apparatus according to the eleventh embodiment.
FIG. 80 is a diagram illustrating a configuration example of a driving apparatus according to a twelfth embodiment.
FIG. 81 is a time chart showing an example of a drive waveform in a sustain discharge period by the drive device configured as shown in FIG.
FIG. 82 is a diagram showing another configuration example of the driving apparatus according to the twelfth embodiment.
FIG. 83 is a diagram showing a configuration example of a driving apparatus according to a thirteenth embodiment.
84 is a time chart showing an example of a drive waveform in a sustain discharge period by the drive device configured as shown in FIG. 83. FIG.
FIG. 85 is a diagram showing another configuration example of the driving apparatus according to the thirteenth embodiment.
FIG. 86 is a time chart showing an example of a drive waveform in a sustain discharge period by the drive device configured as shown in FIG.
87 is a diagram showing another configuration example of the driving apparatus according to the thirteenth embodiment. FIG.
88 is a time chart showing an example of a drive waveform in a sustain discharge period by the drive device configured as shown in FIG. 87. FIG.
FIG. 89 is a diagram showing another configuration example of the driving apparatus according to the thirteenth embodiment.
FIG. 90 is a time chart showing an example of a drive waveform in a sustain discharge period by the drive device configured as shown in FIG.
FIG. 91 is a diagram showing another configuration example of the driving apparatus according to the thirteenth embodiment.
FIG. 92 is a time chart showing an example of a drive waveform in a sustain discharge period by the drive device configured as shown in FIG. 91;
FIG. 93 is a diagram showing a schematic configuration of a PDP according to a fourteenth embodiment.
FIG. 94 is a diagram showing a schematic configuration example of a plasma display device according to a fourteenth embodiment.
FIG. 95 is a diagram showing a configuration example of a driving apparatus according to a fourteenth embodiment.
FIG. 96 is a diagram showing a configuration example of a driving apparatus according to a fifteenth embodiment.
97 is a time chart showing an example of a drive waveform in a sustain discharge period by the drive device configured as shown in FIG. 96. FIG.
FIG. 98 is a diagram illustrating a configuration example of another embodiment.
FIG. 99 is a diagram showing an overall configuration of an AC drive type plasma display device.
Fig. 100 is a diagram illustrating a cross-sectional configuration of a cell Cij in an i-th row and a j-th column that is one pixel.
FIG. 101 is a waveform diagram showing an example of a driving method of a conventional AC driving type PDP.
FIG. 102 is a diagram illustrating a configuration example of a conventional driving device.
FIG. 103 is a diagram showing another configuration example of a conventional driving device.
104 is a diagram showing a configuration of a high voltage power supply necessary for the driving apparatus of FIG. 103.
105 is a time chart showing an example of drive waveforms in an address period and a sustain discharge period by the drive device configured as shown in FIG. 103. FIG.
[Explanation of symbols]
1 AC drive type PDP
2 X side circuit
3 Y side circuit
20 load
22, 33 Power recovery circuit
31 'scan driver
41 AC power supply
42 A / D converter
43 Power supply circuit
44 Driver circuit
SW1 to SW5 switch
OUTA first signal line
OUTB Second signal line
C1, C4 capacitors

Claims (1)

A plasma display device having a plasma display panel in which a plurality of first and second electrodes for performing sustain discharge are arranged adjacent to each other,
A reference power supply for supplying a reference voltage V3;
A power supply for generating a first voltage V1 having a high level relative to the reference voltage V3;
A first electrode driving circuit for driving the first electrode;
A second electrode drive circuit for driving the second electrode,
The first electrode driving circuit includes:
First switch means disposed between the power source and the first voltage supply unit;
A first capacitive element having one terminal connected to the first voltage supply and the other terminal connected to a second voltage supply;
Second switch means for switching conduction / non-conduction between the one terminal of the first capacitive element and the reference power supply;
Third switch means for switching conduction / non-conduction between the other terminal of the first capacitive element and the reference power supply;
Fourth switch means for supplying the first voltage V1 to the first electrode via the first voltage supply unit;
Fifth switch means for supplying the first electrode with a second voltage V2 having a low level relative to the reference voltage V3 through the second voltage supply unit;
The second electrode driving circuit includes:
Sixth switch means disposed between the power source and a third voltage supply unit;
A second capacitive element having one terminal connected to the third voltage supply and the other terminal connected to a fourth voltage supply;
Seventh switch means for switching conduction / non-conduction between the one terminal of the second capacitive element and the reference power supply;
Eighth switch means for switching conduction / non-conduction between the other terminal of the second capacitive element and the reference power supply;
Ninth switch means for supplying the first voltage V1 to the second electrode via the third voltage supply unit;
Tenth switch means for supplying the second electrode with the second voltage V2 via the fourth voltage supply unit;
The first switch means is made conductive and the second switch means is made nonconductive, and the first voltage V1 is supplied to the first electrode through the first voltage supply section and the fourth switch means. And the first voltage V1 is supplied to the one terminal of the first capacitive element, and the third switch means is turned on to connect the other terminal of the first capacitive element. Is used as the reference voltage V3 to charge the first capacitive element to the first capacitive element, the sixth switch means is made non-conductive and the seventh switch means is made conductive to make the second capacitor The supply of the first voltage V1 to the one terminal of the capacitive element is cut off to set the one terminal of the second capacitive element to the reference voltage V3, and the eighth switch means is turned off. In front of the second capacitive element as conduction A first terminal that cuts off the connection between the other terminal and the reference voltage V3 and supplies the second voltage V2 to the second electrode through the fourth voltage supply unit and the tenth switch means. The state of
The first switch means is made non-conductive and the second switch means is made conductive to cut off the supply of the first voltage V1 to the one terminal of the first capacitive element. The one terminal of the capacitive element is set to the reference voltage V3, and the third switch means is made non-conductive to cut off the connection between the other terminal of the first capacitive element and the reference voltage V3. Then, the second voltage V2 is supplied to the first electrode via the second voltage supply unit and the fifth switch means, the sixth switch means is turned on, and the seventh voltage is supplied. And the first voltage V1 is supplied to the second electrode via the third voltage supply unit and the ninth switch means, and the switch of the second capacitive element is turned off. Supply the first voltage V1 to one terminal The second state in which the eighth switch means is turned on to charge the second capacitive element with the second terminal of the second capacitive element as the reference voltage V3. When,
In addition to performing a sustain discharge by alternately performing,
The first electrode driving circuit includes a third capacitive element having one terminal connected to the second voltage supply unit, the other terminal of the third capacitive element, and the first electrode. A first power recovery circuit having a coil, a switching element, and a diode interposed between two paths, a path for recovering charges from the first electrode and a path for supplying charges to the first electrode, respectively. Have
The second electrode driving circuit includes: a fourth capacitive element having one terminal connected to the fourth voltage supply unit; the other terminal of the fourth capacitive element; and the second electrode. A second power recovery circuit having a coil, a switching element, and a diode interposed between two paths, a path for recovering charges from the second electrode and a path for supplying charges to the second electrode, respectively. A plasma display device comprising:

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