JP2000338934A - Driving method and driving circuit of capacitive load - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a load of a switching device, and to aim price reduction of a driving circuit. SOLUTION: In driving of a capacitive load for executing binary control of each electrode potential of an electrode pair, one electrode of the electrode pair is connected to a bias potential line 81 through a primary winding L1 of a transformer M1 and connected to a grounding potential line 82 through a secondary winding L2 of the transformer M1, and simultaneously the other electrode of the electrode pair is connected to the grounding potential line 82, and a capacitance Cp between the electrodes of the electrode pair is charged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and a circuit for driving a capacitive load, and is suitable for display by a plasma display panel (PDP).

[0002] Since cells constituting a screen of a PDP are capacitive loads as viewed from a power supply circuit, charge / discharge of a capacitance occurs with a change in electrode potential. The movement of the charge due to the charge and discharge is a reactive current that does not contribute to light emission. Therefore, in order to reduce power consumption, it is necessary to reuse the power consumed for charging.

[0003]

2. Description of the Related Art In an AC type PDP, a driving method for temporally separating addressing for forming a charge distribution according to display data and sustaining lighting for generating a number of gas discharges corresponding to luminance using wall charges. Sequences are widely adopted. In the lighting sustain period (also referred to as a display period), voltage pulses are alternately applied to a pair of electrodes to periodically invert the potential relationship of the electrode pair. The charge and discharge of the inter-electrode capacitance are repeated with the potential change in addressing and lighting maintenance.

As a method of reducing the power loss associated with charging and discharging the interelectrode capacitance, a capacitor having a sufficient capacitance is provided.
There is a method of repeating the operation of discharging electric charge from the DP to a capacitor, collecting electric charge, returning the electric charge from the capacitor to the PDP, and charging the interelectrode capacitance. By providing an LC resonance circuit by providing an inductor in the current path, charging and discharging can be speeded up, and the voltage amplitude can be increased to increase the power recovery rate.

FIG. 19 is a circuit diagram of a main part of a conventional driving device, and shows a circuit configuration of a portion related to a lighting maintaining operation. FIG. 20 is a time chart of the conventional drive control.
In FIG. 19, PDP 1 represented by an equivalent circuit is driven by X common driver 91 and Y common driver 92. Since the configurations of these drivers are the same, the operation will be described here by focusing on the X common driver 91 as a representative. It is assumed that the potential of an electrode (not shown) connected to the Y common driver 92 is kept at the ground potential.

The X common driver 91 includes switching devices CU, CD, LU, LD, and a recovery capacitor C
r, inductor L, and diodes DU and DD that regulate the direction of conduction. Switching device C
U and CD are elements for binary control of the electrode potential,
Other components are additional components for power recovery.
The switching devices CU, CD, LU, and LD are means for opening and closing a current path, and are specifically composed of a single or parallel-connected FET group. The capacitance value of the capacitor Cr is set to a sufficiently large value that is at least 10 times the sum of the capacitances of all the cells to be driven (this is referred to as the inter-electrode capacitance Cp). As charging and discharging of the PDP 1 are repeated, the capacitor Cr is charged until the voltage between the terminals reaches about half of the lighting sustaining voltage Vs, and thereafter, the voltage between the terminals is kept substantially constant.

When biasing the potential of an electrode (not shown) connected to the X common driver 91 from the ground potential to the lighting sustaining potential (Vs), first, the switching device LU is turned on to transfer the inter-electrode capacitance Cp from the capacitor Cr to the PDP 1. Pass current to charge. Since there is a loss in the resistance Rp, charging cannot be performed up to the target value Vs. Next, the switching device CU is turned on to charge the interelectrode capacitance to the target value Vs.

After reaching the target value Vs, gas discharge occurs between the electrodes. At this time, since the diode DU is in the off state, all of the gas discharge current is switched by the switching device CU.
Flows through.

When returning the potential of the electrode from the lighting sustain potential (Vs) to the ground potential, first, the switching device L
D is turned on to collect the charge of the inter-electrode capacitance Cp into the capacitor Cr. Next, the switching device CD is turned on, the electrodes are connected to the ground potential line, and the inter-electrode capacitance Cp is almost completely discharged.

[0010]

SUMMARY OF THE INVENTION In a conventional drive device,
The circuit for power recovery cannot pass gas discharge current. This is because the terminal potential of the recovery capacitor Cr is lower than the ultimate potential of the pulse applied to the electrode. If the terminal potential of the capacitor Cr is made equal to the ultimate potential, power cannot be recovered. Therefore, there is a problem that the switching devices LU and LD, which are relatively expensive circuit elements, cannot be used effectively. In other words, switching devices CU and CD having a large current capacity must be provided in order to open and close the current supply path for supplying the gas discharge current, and there is a problem that the circuit becomes expensive.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the load on a switching device required for opening and closing a current path and to reduce the cost of a drive circuit.

[0012]

According to the present invention, power recovery relating to inter-electrode capacitance is performed using a transformer. By energizing the transformer even after the inter-electrode capacitance is charged, the transformer can be used for effective power supply to the load, and a plurality of energizing paths between the power supply and the load can be provided. The current capacity required for the opening / closing means of each energizing path may be smaller than that in the case of a single energizing path.

According to a first aspect of the present invention, there is provided a method of driving a capacitive load for controlling each electrode potential of an electrode pair in a binary manner, wherein one electrode of the electrode pair is connected via a primary winding of a transformer. Connected to the bias potential line, and connected to the ground potential line via the secondary winding of the transformer, and the other electrode of the electrode pair is connected to the ground potential line, and the It charges the capacity.

In the driving method according to a second aspect of the present invention, at least a part of a load current flowing through the pair of electrodes while the capacitance is charged is supplied from the bias potential line via the primary winding. It is.

According to a third aspect of the present invention, in the driving method, one electrode of the electrode pair is connected to a bias potential line via a primary winding of a first transformer, and a secondary winding of the first transformer is connected. Connected to a ground potential line via a wire, and the other electrode of the pair of electrodes is connected to the ground potential line to charge a capacitance between the electrodes of the pair of electrodes. The second capacitor is connected to the ground potential line via the primary winding of the second transformer, and is connected to the bias potential line via the secondary winding of the second transformer to discharge the capacitor.

According to a fourth aspect of the present invention, in the driving method, one electrode of the electrode pair is connected to a bias potential line via a primary winding of a first transformer, and a secondary winding of the first transformer is connected. While connected to the ground potential line via a wire and a capacitor, the other electrode of the electrode pair is connected to the ground potential line to charge the capacitance between the electrodes of the electrode pair, and one electrode of the electrode pair is connected to the ground potential line. Connected to the ground potential line via the primary winding of the second transformer, and connected to the ground potential line via the secondary winding of the second transformer and the capacitor. A part of the electric charge is collected by the capacitor.

In the driving method according to a fifth aspect of the present invention, one electrode of the electrode pair is connected to a bias potential line via a primary winding of a first transformer, and the other electrode is connected to a first potential of a second transformer.
Connected to the ground potential line via the next winding, and
The electrodes are connected to each other via the secondary winding of the transformer and the secondary winding of the second transformer to invert the potential polarity of the electrode pair.

In the driving method according to a sixth aspect of the present invention, the direction of energization of the secondary winding is regulated by a diode. In a driving method according to a seventh aspect of the present invention, a reverse current path is provided in parallel with the primary winding.

According to an eighth aspect of the present invention, there is provided a drive circuit for controlling the potential of one electrode of a pair of electrodes constituting a capacitive load in a binary manner, comprising a primary winding and one end of a secondary winding. A first transformer having a common connection, a second end of the primary winding connected to a bias potential line, and a second end of the secondary winding connected to a ground potential line; A switching device for opening and closing a current path between the first winding and the electrode, and one end of a primary winding and one end of a secondary winding are commonly connected, and the other end of the primary winding is connected to the ground potential line. A second transformer having the other end of the secondary winding connected to the bias potential line, and a switching device for opening and closing a current path between the second transformer and the electrode. are doing.

A driving circuit according to a ninth aspect of the present invention provides a driving circuit comprising: a capacitor having one end connected to a ground potential line;
A first transformer having one end of the secondary winding commonly connected, the other end of the primary winding connected to a bias potential line, and the other end of the secondary winding connected to the capacitor; A switching device for opening and closing a current path between a first transformer and the electrode;
A second transformer having one end of the secondary winding commonly connected, the other end of the primary winding connected to the ground potential line, and the other end of the secondary winding connected to the capacitor; A switching device for opening and closing a current path between the second transformer and the electrode.

[0021]

FIG. 1 is a block diagram of a display device according to the present invention. The display device 10 is composed of an AC type PDP 1 which is a thin color display device, and a drive unit 20 for selectively lighting cells arranged vertically and horizontally constituting a screen of M columns and N rows, and is mounted on a wall. It is used as a television receiver and a monitor of a computer system.

In the PDP 1, first and second main electrodes X and Y forming an electrode pair for generating a lighting sustain discharge (also referred to as a display discharge) are arranged in parallel with each other. It has a three-electrode surface discharge structure in which address electrodes A, which are three electrodes, intersect. The main electrodes X and Y extend in the row direction (horizontal direction) of the screen, and among these, the main electrode Y is used as a scan electrode for selecting cells on a row basis at the time of addressing. The address electrodes A extend in the column direction (vertical direction), and are used as data electrodes for selecting cells in column units. The intersection area between the main electrode group and the address electrode group on the substrate surface is a display area (that is, a screen).

The drive unit 20 includes the controller 2
1, a data processing circuit 22, a power supply circuit 23, an X driver circuit 24, a Y driver circuit 26, and an address driver circuit 29. The drive unit 20 is P
Each driver and PDP10 are located on the back side of DP10.
Are electrically connected to each other by a flexible cable (not shown). The drive unit 20 has a TV tuner,
Field data Df for each pixel indicating a luminance level (gradation level) of each color of R, G, and B is input from an external device such as a computer together with various synchronization signals.

The field data Df is temporarily stored in the frame memory 221 of the data processing circuit 22 and then converted into sub-field data Dsf for gradation display. The subfield data Dsf is stored in the frame memory 232, and is serially transferred to the address driver circuit 29 as the display progresses. Each bit value of the subfield data Dsf is information indicating the necessity of lighting of the cell in the subfield, more specifically, information indicating the necessity of the address discharge. The subfield data Dsf is used for switch control in the address driver circuit 29.

The X driver circuit 24 is composed of a plurality of X common drivers 25, one for each of the groups of partitions obtained by dividing the screen in the column direction. Each X common driver 25 has one
The potential of the main electrode X in one section is controlled collectively. The number of lines per section is, for example, 120. The Y driver circuit 26 includes a scan driver 27 and a plurality of Y common drivers 28. The scan driver 27 is a potential control means for selecting a line in addressing.
Each Y common driver 28 collectively controls the potential of the main electrode Y in one section. Also, the address driver circuit 29
Controls the potentials of a total of M address electrodes (data electrodes) A based on the subfield data Dsf. A predetermined power is supplied to these driver circuits from a power supply circuit 23 via a wiring conductor (not shown). The power supply circuit 23 has a capacitor Cs for smoothing.

FIG. 2 is an exploded perspective view showing the internal structure of the PDP according to the present invention. In the PDP 1, the front-side substrate structure 1
Pairs of main electrodes X and Y are arranged in each row on the inner surface of a glass substrate 110 which is a base material of No. 00. A row is a horizontal cell column on the screen. The main electrodes X and Y each include a transparent conductive film 41 and a metal film (bus conductor) 42, and are covered with a dielectric layer 170 made of low melting point glass and having a thickness of about 30 μm. On the surface of the dielectric layer 170, a protective film 180 made of magnesia (MgO) and having a thickness of several thousand angstroms is provided. Address electrode A is
A dielectric layer 2 having a thickness of about 10 μm, which is arranged on the inner surface of a glass substrate 210 which is a base material of the rear-side substrate structure 200.
40. On the dielectric layer 240, one partition 290 having a height of 150 μm and having a linear band shape in a plan view is provided between each address electrode A. These barrier ribs 290 divide discharge space 300 into sub-pixels (unit light emitting regions) in the row direction, and form discharge space 3.
A gap size of 00 is defined. Then, R, G, and B for color display are covered so as to cover the inner surface on the back side including the upper side of the address electrode A and the side surface of the partition wall 290.
Color phosphor layers 28R, 28G, and 28B are provided. The discharge space 300 is filled with a discharge gas in which xenon is mixed with neon as a main component, and the phosphor layers 28R, 2
8G and 28B are locally excited by ultraviolet light emitted by xenon during discharge to emit light. One pixel (pixel) of the display is composed of three sub-pixels arranged in the row direction.
The structure within each sub-pixel is a cell (display element).
Since the arrangement pattern of the barrier ribs 290 is a stripe pattern, a portion corresponding to each column in the discharge space 300 is continuous in the column direction across all rows.

FIG. 3 is a diagram showing an example of the driving sequence. In the figure, letters (1, 2,... N) indicating the arrangement order of the corresponding rows are added to the reference signs of the main electrodes X and Y, and letters indicating the arrangement order of the corresponding columns are added to the reference signs of the address electrodes A. (1 to M) are added.

In the display of a television image, in order to reproduce a gradation by binary lighting control, for example, eight fields f of a time series (the subscript of a reference number represents a display order) are input images. Subframes sf1, sf
2, sf3, sf4, sf5, sf6, sf7, sf8
Divided into That is, each field f forming the frame is replaced with a set of eight subframes sf1 to sf8. When a non-interlaced image such as a computer output is reproduced, each frame is divided into eight. Then, the relative ratio of luminance in these subfields sf1 to sf8 is approximately 1: 2: 4: 8: 1.
The number of lighting sustain discharges in each of the subfields sf1 to sf8 is set by weighting so as to be 6: 32: 64: 128. When 256 levels of luminance settings are made for each color of RGB in a combination of lighting / non-lighting in subfield units,
The number of colors that can be displayed is 256 ³ .

The subfield period allocated to each of the subfields sf1 to sf8 corresponds to a preparation period TR for equalizing the charge distribution on the screen, an address period TA for forming a charge distribution according to display contents, and a gradation level. It consists of a sustain period TS in which the lighting state is maintained to secure the luminance. The lengths of the preparation period TR and the address period TA are constant regardless of the luminance weight, but the length of the sustain period TS increases as the luminance weight increases. That is, the lengths of the eight subfield periods corresponding to one field f are different from each other.

The driving sequence repeated for each subfield
The outline of Kens is as follows. In preparation period TR
All address electrodes A₁~ A_MPulse P
ra1 and pulse Pra2 of the opposite polarity are sequentially applied
And all the main electrodes X₁~ X _NWith the pulse Prx1
Pulses Prx2 of the opposite polarity are sequentially applied, and all
Main electrode Y₁~ Y_NThe pulse Pry1 and its counterpart
The opposite polarity pulse Pry2 is applied in order. Say here
Pulse application refers to temporarily applying an electrode to a reference potential (for example,
(Ground potential). This example
, The pulses Pra1, Pra2, Prx1, Pr
x2, Pry1, Pry2 are the change rates at which the minute discharge occurs.
This is a blunt wave pulse. In addition, the pulses Pra1, Prx
1 has a negative polarity, and the pulse Pry1 has a positive polarity. Pa
By applying Lus Pra2, Prx2, Pry2, wall current
Pressure to a value corresponding to the difference between the firing voltage and the pulse amplitude.
Can be adjusted. Pulses Pra1, Prx1, Pr
y1 is a cell lit in the immediately preceding subfield
And to generate an appropriate wall voltage for cells that did not light up.
Applied for

In the address period TA, wall charges necessary for maintaining lighting are formed only in cells to be lit. In a state where all the main electrodes X _{1 to} X _N and all the main electrodes Y _{1 to} Y _N are biased to a predetermined potential, one main electrode corresponding to the selected row in each row selection period (scan time for one row). A scan pulse Py is applied to Y. At the same time as this row selection, an address pulse Pa is applied only to the address electrode A corresponding to the cell to be turned on. That is, the potentials of the address electrodes A _{1 to} A _M are controlled to 0 or Va based on the subfield data Dsf for M columns of the selected row. In a cell to be turned on, a discharge occurs between the main electrode Y and the address electrode A, which triggers a surface discharge between the main electrodes. These series of discharges are address discharges.

In the sustain period TS, first, a sustain pulse Ps having a predetermined polarity (positive in the example) is applied to all the main electrodes Y _{1 to} Y _N. afterwards,
The sustain pulse Ps is applied alternately to the main electrodes X ₁ to X _N and the main electrode Y ₁ to Y _N. The final sustain pulse Ps in the present embodiment is applied to the main electrode X ₁ to X _N. By applying the sustain pulse Ps, the address period TA
, Surface discharge occurs in the cell where the wall charges remain. Each time a surface discharge occurs, the polarity of the wall voltage between the electrodes is inverted. Note that the address electrodes A _{1 to} A _M are biased to have the same polarity as the sustain pulse Ps in order to prevent unnecessary discharge over the sustain period TS.

With respect to the drive waveform, the amplitude, polarity, and timing can be variously changed. For example, in the preparation period TR, a pulse having a ramp waveform or a staircase waveform may be applied.

Next, the configuration of the driving circuit according to the present invention will be described. [Example applied to potential control of main electrode] The circuit configuration of the Y common driver 28 described above is the same as the circuit configuration of the X common driver 25. Therefore, the configuration and operation of the X common driver 25 will be described below as a representative.

(First Configuration) FIG. 4 is a circuit diagram showing a first example of the X common driver, and FIG. 5 is a time chart of drive control corresponding to FIG. 5 is a time chart of a first example of drive control. In the following circuit diagrams including FIG. 4, components corresponding to those of the conventional example are denoted by the same reference numerals as in FIG. In the following time charts including FIG. 5, it is assumed that main electrode Y is kept at ground potential (0).

The X common driver 25 is a 2
Transformers M1, M2, four switching devices CU, CD, LU, LD, diodes DU, DD for regulating the current direction, and diodes D1, D2 for reducing distortion of the pulse waveform. However, the diodes D1 and D2 may not be provided.

In the transformer M1, one ends of the primary winding L1 and the secondary winding L2 are both connected to the switching device LU, and the other end of the primary winding L1 is connected to the bias potential line 8.
1 and the other end of the secondary winding L2 is a diode D
It is connected to a ground potential line 82 via U. In the transformer M2, one ends of the primary winding L1 and the secondary winding L2 are both connected to the switching device LD, the other end of the primary winding L1 is connected to the ground potential line 82, and
The other end of the next winding L2 is connected to a bias potential line 81 via a diode DD.

In the application of the above-mentioned sustain pulse Ps, first, when the switching device LU is turned on, a current i for charging the inter-electrode capacitance Cp from the bias potential line 81 to the PDP 1 via the primary winding L1 of the transformer M1.
u1 flows. At the same time, an electromotive force is generated in the secondary winding L2 of the transformer M1, and a current i flows from the ground potential line 82 to the PDP1.
u2 flows. The inter-electrode capacitance Cp is determined by the current iu1 and the current iu.
2 is charged. The term “charging” as used herein means the accumulation of a predetermined amount of charge with the main electrode X side being positive. In this charging, the current iu2 flowing through the secondary winding L2 is
The main electrode Y of the inter-electrode capacitance Cp not via the power supply circuit 23 but via the Y common driver 28 and the ground potential line 82
The transfer of positive charge from the side. Therefore, the power supply circuit 23
Is supplied only with the current iu1.
Less than when charging. Charging advances, transformer M
When the potential at the connection point between the primary winding L1 and the secondary winding L2 becomes higher than the bias potential (Vs), the diode connected in parallel to the primary winding L1 so as to be in the opposite direction to the current iu1. D1 is turned on, and a current starts to flow in a loop circuit including the primary winding L1 and the diode D1.
As a result, the current flowing through the primary winding L1 and the current flowing through the secondary winding L2 both decrease, and charging ends.

After the potential of the main electrode X reaches the bias potential (Vs), before the gas discharge starts, the switching device CU is turned on. The gas discharge current flows mainly via the switching device CU. In the conventional configuration, all of the gas discharge current flows via the switching device CU, but in the configuration of the present invention, the switching device LU is connected to the bias potential line 81 via the primary winding L1 of the transformer M1. Therefore, a part of the gas discharge current flows via the switching device LU. Therefore, in the configuration of the present invention, the current supply capability at the time of gas discharge is larger than that of the conventional configuration.

After the gas discharge is completed, the switching devices CU and LU are turned off. Subsequently, the switching device LD is turned on to discharge the inter-electrode capacitance Cp. At the same time as the discharge current id1 flows through the primary winding L1 of the transformer M2, an electromotive force causing the current id2 to flow through the secondary winding L2 is generated, and the current id2 flows into the bias potential line 81. Part of the electric charge flowing out of the power supply circuit 23 during charging returns to the power supply circuit 23 and is collected by the smoothing capacitor Cs.

In order to realize the above operation, the transformer M1
When the current iu1 increases, the current i
An electromotive force having a polarity in which u2 increases is generated. Similarly, when the transformer M2 is connected, an electromotive force having a polarity that increases the current id2 when the current id1 increases is generated.

Specific examples of the collection efficiency are as follows. Here, the recovery efficiency means a ratio of a reduction in the power supply amount when the power recovery circuit is provided to the power supply amount of the power supply when the power recovery circuit is not provided. PDP
It is assumed that 120 rows of 1 are driven collectively. The resistance per row is 100Ω, and the capacitance between electrodes per row is 200
In the case of pF, the load resistance Rp including the ON resistance (for example, 1.6 Ω) of the switching device is 2.4 Ω, and the inter-electrode capacitance Cp is 24 nF. Transformer M1,
The inductance of the primary winding L1 of M2 is 0.1 mH, 2
If the inductance of the secondary winding L2 is 0.42 mH and the mutual inductance is 0.21 mH, the recovery efficiency when the rise time of the sustain pulse Ps is 500 ns is 76%. The recovery efficiency is 78 when the load condition and the pulse rise time are the same as in this example in the conventional configuration.
%, It can be said that the recovery efficiency of this example is almost equal to that of the conventional example.

(Second Configuration) FIG. 6 is a circuit diagram showing a second example of the X common driver. The PDP 1 is driven by an X common driver 25b and a Y common driver 28b having the same configuration. The basic configuration and switching operation of the X common driver 25b are the same as in the example of FIG. X common driver 25
The feature of b is that it has a capacitor Cr for recovery, and the secondary winding L2 of the transformers M1 and M2 is connected to the capacitor Cr via diodes DU and DD. The current iu1 flowing from the bias potential line 81 to the primary winding L1 of the transformer M1 and the secondary winding L2
And the current iu2 ′ flowing into the capacitor C1 charges the inter-electrode capacitance Cp. Also, when discharging the inter-electrode capacitance Cp, the transformer M
The electric power is recovered by the current id2 'flowing through the secondary winding L2 of the second power supply.

The inductance of the primary winding L1 of the transformers M1 and M2 is 0.42 mH, the inductance of the secondary winding L2 is 0.11 mH, and the mutual inductance is 0.21 m.
H, and the pulse rise time is 50
At 0 ns, the recovery efficiency is 77%.

(Third Configuration) FIG. 7 is a circuit diagram showing a third example of the X common driver, and FIG. 8 is a time chart of drive control corresponding to FIG.

The X common driver 25c shown in FIG. 7 is a preferred example when the duty ratio of the sustain pulse Ps is set to 50%, and functions by the complementary operation with the Y common driver 28c. The basic configuration of the X common driver 25c is the same as the example in FIG. The feature of the X common driver 25c is that the secondary winding L2 of the transformer M1x is connected to the Y through the diode DUx.
The secondary winding L2 of the transformer M2x of the common driver 28c is connected to the secondary winding L2 of the transformer M2x, and the secondary winding L2 of the transformer M2x is connected to the transformer M1y of the Y common driver 28c via a diode DUy.
Is connected to the secondary winding L2. As shown in FIG. 8, switching on the charge side of the X common driver 25c and Y
Switching on the discharging side of the common driver 28c is performed simultaneously, and switching on the discharging side of the X common driver 25c and switching on the charging side of the Y common driver 28c are performed simultaneously. When the switching devices LUx and LDy are turned on, the primary windings L1 of the transformers M1x and M2y are turned on.
, And the current i2 flows through the secondary winding L2 of the transformers M1x and M2y. The inter-electrode capacitance Cp is charged by these currents i1 and i2.

Transformers M1x, M2x, M1y, M2y
In the case where the inductance of the primary winding L1 is 2.6 mH, the inductance of the secondary winding L2 is 0.29 mH, the mutual inductance is 0.86 mH, and the pulse rise time is 1 μs under the load conditions described above, the recovery is performed. The efficiency is 75%.

In the example of FIG. 7, the connection terminal of the main electrode X is provided at one end of the glass substrate 11 in the row direction.
If a general electrode wiring pattern in which the connection terminal of the main electrode Y is provided at the other end of the glass substrate 11 is used, the wiring connecting the secondary windings becomes long. Therefore, the connection terminals of the main electrodes X and Y to be driven are connected to the glass substrate 1
It is desirable to arrange them all at one end. [Example applied to potential control of address electrode] FIG. 9 is a schematic diagram of an address driver circuit 29. In the figure, the components having the same function are denoted by the same reference numerals with the same numeral string with lower case letters indicating the arrangement order. However, in the following description, when it is not necessary to distinguish the arrangement order, the suffix may be omitted.

Here, the screen of PDP1 is SXGA specification
(1024 × 1280 pixels). 1 for color reproduction
The pixel is composed of three sub-pixels arranged in the horizontal direction,
One address electrode A is assigned to each subpixel.
Therefore, the total number M of the address electrodes A is 3840 (= 128
0 × 3). In this example, 3840 address electrodes A
₁~ A₃₈₄₀32 drivers with a total of 32 potentials₁~ 32₃₂
Is controlled by Driver 32₁~ 32₃₂Is the accumulation times
Devices, each with 120 address electrodes
Responsible for control of A. In this example, 32 drivers 32₁
~ 32₃₂120 ads, one for each
Power recovery circuit 33 with one electrode per electrode₁~ 33₃₂
Are provided, and 32 address driver circuits 29 are provided.
Driver 32₁~ 32₃₂And 32 power recovery circuits 33
₁~ 33₃₂It is composed of However, multiple drives
The power recovery circuit may be provided at a rate of one per unit. Electric power
Collection circuit 33₁~ 33₃₂Is the address electrode A₁~ A₃₈₄₀
Between the electrodes C associated with_APower consumption
It is a component to reduce. Electrode capacitance C_AIs adjacent
Between address electrodes and between address electrode A and main power
The capacitance between the poles X and Y. Note that each driver 3
The number m of address electrodes A assigned to 2 and the power recovery circuit 33
Is arbitrary within a range satisfying the following relationship.
Can be selected.

1 ≦ m ≦ M (M: total number of address electrodes) 1 ≦ i ≦ k (k: number of drivers 32) k is a value when M / m is an integer, and M / m is a decimal number. In case, it is an integer rounded up after the decimal point.

The configuration of the 32 drivers 32 _{1 to} 32 ₃₂ is the same, and the configuration of the 32 power recovery circuits 33 _{1 to} 33 ₃₂ is also the same. Six exemplary configurations of the driver circuit will be described in order. In the six examples, the configuration of the driver 32 is the same, and only the configuration of the power recovery circuit 33 is different. As described above, the circuit components corresponding to the conventional example are denoted by the same reference numerals in all the examples, so as to avoid complicating the drawings and the description.

(First Configuration) FIG. 10 is a diagram showing a first example of an address driver circuit, and FIG. 11 is a time chart of drive control corresponding to FIG.

The driver 32 has m address electrodes A _1.
~A output terminals of a total of m corresponding one by one to each _m OUT ₁ to OUT _m, 2 pieces of terminal U for connection with the power recovery circuit 33, D, total 2 × m pieces of switches UP ₁ ~ U
P _m , DN _{1 to} DN _m , a switch driver circuit 49, and a total of 4 × m diodes. Each output terminal O
Two switches UP and DN are provided for the UT, and independent conduction control between each output terminal OUT and the power recovery circuit 33 is possible. The switch driver circuit 49 latches the subfield data Dsf in synchronization with the control signal SL from the controller 21, and performs on / off control of the switches UP and DN of the corresponding column according to the subfield data Dsf.

The power recovery circuit 33 includes two transformers M
1, M2, four switching devices CU, CD, L
U, LD, diodes DU, DD for regulating the current direction,
And diode D for reducing pulse waveform distortion
1, D2. The configuration and operation of the power recovery circuit 33 are basically the same as those of the X common driver 24 of FIG. 4 described above. The difference from the X common driver 24 is that the switching devices CU and CD are not connected in series but are individually connected to the terminals U and D of the driver 32 in order to enable individual control of the plurality of address electrodes A. It is.

In the address period TA (see FIG. 3),
The driver 32 and the power recovery circuit 33 operate as follows.
The basic operation of the driver 32 is on / off control of the switches UP and DN independent for each output terminal OUT. In the address period TA, when applying an address pulse Pa to an address electrode A, the switch UP is turned on to close the current path from the terminal U to the output terminal OUT. When the address electrode A is set to the ground potential, the switch DN is turned on and the current path from the output terminal OUT to the terminal D is closed. Prior to turning on / off the switches UP and DN, the four switching devices C of the power recovery circuit 33 are turned on.
U, CD, LU and LD are turned off.

As shown in FIG. 11, after the switches UP and DN are turned on and off, first, the switching devices LU and LD are turned on.
Is turned on to cause charging and discharging of the inter-electrode capacitance C _A. Whether to be charged or discharged is determined by display contents. Charging is performed by the current iu1 flowing through the primary winding L1 and the current iu2 flowing through the secondary winding L1 of the transformer M1. The discharge is caused by the current id1 flowing through the primary winding L1 of the transformer M2.
And the current id2 flowing through the secondary winding L2.
After the charging and discharging are completed, the switching devices CU and CD are turned on before the address discharge (gas discharge) occurs.

Specific examples of the recovery efficiency are as follows. P
It is assumed that 120 columns of DP1 are driven collectively. Resistance per row is 400Ω (including ON resistance of switches UP and DN is 300Ω). Capacitance between electrodes per row is 25p.
In the case of F, the load resistance Rp including the ON resistance (for example, 1.6Ω) of the switching device becomes 8.3Ω,
The inter-electrode capacitance Cp is 3 nF. In the case of power recovery in addressing, the load varies depending on the display contents.
The value here is the maximum value. The inductance of the primary winding L1 of the transformers M1 and M2 is 0.14 mH, and the secondary winding L
2, the recovery efficiency is 51% when the inductance is 0.55 mH, the mutual inductance is 0.27 mH, and the rise time of the address pulse Pa is 200 ns.

(Second Configuration) FIG. 12 is a diagram showing a second example of the address driver circuit, and FIG. 13 is a time chart of drive control corresponding to FIG.

In the power recovery circuit 33b, the switching devices LU and LD in the power recovery circuit 33 of FIG. 10 are omitted. The functions of the switching devices LU and LD are realized by the switches UP and DN of the driver 32.

(Third Configuration) FIG. 14 is a diagram showing a third example of the address driver circuit, and FIG. 15 is a time chart of drive control corresponding to FIG.

In the power recovery circuit 33c, the switching devices LU and LD and the switching devices CU and CD in the power recovery circuit 33 of FIG. 10 are omitted.
The discharge current in the address discharge is smaller than the discharge current in the lighting sustain discharge. Therefore, all of the discharge current can be supplied via the primary winding of the transformer M1, and the switching devices CU and CD can be omitted.

(Fourth Configuration) FIG. 16 is a diagram showing a fourth example of the address driver circuit. The power recovery circuit 33d
Similar to the X common driver 24b shown in FIG. 6, a recovery capacitor Cr is provided, and the secondary winding L2 of the transformers M1 and M2 is connected to the capacitor Cr. The switching devices CU and CD are not connected in series, but are individually connected to terminals U and D of the driver 32.

The inductance of the primary winding L1 of the transformers M1 and M2 is 0.55 mH, the inductance of the secondary winding L2 is 0.14 mH, and the mutual inductance is 0.27 m.
H, the recovery efficiency is 52% when the pulse rise time is 200 ns under the maximum load conditions described above.

(Fifth Configuration) FIG. 17 is a diagram showing a fifth example of the address driver circuit. In the power recovery circuit 33e, the switching devices LU and LD in the power recovery circuit 33d in FIG. 16 are omitted.

(Sixth Configuration) FIG. 18 is a diagram showing a sixth example of the address driver circuit. In the power recovery circuit 33f, the switching devices LU and LD and the switching devices CU and C in the power recovery circuit 33d of FIG.
D is omitted.

In the first to sixth examples described above, after the charging and discharging of the interelectrode capacitance is completed, the primary winding L1 and the diode D
In order to attenuate the current flowing through the loop circuit with D1 and D2 in a short time, an attenuation resistor may be connected in series with the diodes D1 and D2.

[0067]

According to the first to ninth aspects of the present invention,
The load on the switching device required for opening and closing the current path can be reduced, and the cost of the drive circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a display device according to the present invention.

FIG. 2 is an exploded perspective view showing the internal structure of the PDP according to the present invention.

FIG. 3 is a diagram illustrating an example of a driving sequence.

FIG. 4 is a circuit diagram showing a first example of an X common driver.

FIG. 5 is a time chart of drive control corresponding to FIG.

FIG. 6 is a circuit diagram showing a second example of the X common driver.

FIG. 7 is a circuit diagram showing a third example of the X common driver.

FIG. 8 is a time chart of drive control corresponding to FIG. 7;

FIG. 9 is a schematic diagram of an address driver circuit 29.

FIG. 10 is a diagram illustrating a first example of an address driver circuit.

FIG. 11 is a time chart of drive control corresponding to FIG.

FIG. 12 is a diagram illustrating a second example of the address driver circuit.

FIG. 13 is a time chart of drive control corresponding to FIG.

FIG. 14 is a diagram illustrating a third example of the address driver circuit.

15 is a time chart of drive control corresponding to FIG.

FIG. 16 is a diagram illustrating a fourth example of the address driver circuit.

FIG. 17 is a diagram illustrating a fifth example of the address driver circuit.

FIG. 18 is a diagram illustrating a sixth example of the address driver circuit.

FIG. 19 is a circuit diagram of a main part of a conventional driving device.

FIG. 20 is a time chart of a conventional drive control.

[Explanation of symbols]

 1 PDP (load) X, Y Main electrode A Address electrode M1, M2 Transformer L1 Primary winding L2 Secondary winding 81 Bias potential line 82 Ground potential line Cp Interelectrode capacitance LU, LD Switching device

Claims (9)

[Claims] 1. A method of driving a capacitive load for controlling each electrode potential of an electrode pair in a binary manner, wherein one electrode of the electrode pair is connected to a bias potential line via a primary winding of a transformer. And 2 of the transformer
Connected to the ground potential line via the next winding, the other electrode of the electrode pair is connected to the ground potential line,
A method for driving a capacitive load, comprising charging a capacitance between electrodes of the electrode pair. 2. The capacitive load according to claim 1, wherein at least a part of a load current flowing through said pair of electrodes while said capacitor is charged is supplied from said bias potential line via said primary winding. Drive method. 3. A method of driving a capacitive load for controlling each electrode potential of an electrode pair in a binary manner, wherein one electrode of the electrode pair is connected to a bias potential line via a primary winding of a first transformer. And the other electrode of the pair of electrodes is connected to the ground potential line via the secondary winding of the first transformer, and the capacitance between the electrodes of the pair of electrodes is connected. And connecting one electrode of the electrode pair to a ground potential line via a primary winding of a second transformer, and to a bias potential line via a secondary winding of the second transformer. A method for driving a capacitive load, characterized in that the capacitive load is discharged by connection. 4. A method of driving a capacitive load for binary controlling each electrode potential of an electrode pair, wherein one electrode of the electrode pair is connected to a bias potential line via a primary winding of a first transformer. To the ground potential line via the secondary winding of the first transformer and the capacitor, and connect the other electrode of the electrode pair to the ground potential line to connect the electrode of the electrode pair. , And one electrode of the electrode pair is connected to a ground potential line via a primary winding of a second transformer, and is connected via a secondary winding of the second transformer and the capacitor. A method for driving a capacitive load, wherein the capacitor is connected to the ground potential line to collect a part of the accumulated charge of the capacitor by the capacitor. 5. A method of driving a capacitive load for binary controlling each electrode potential of an electrode pair, wherein one electrode of the electrode pair is connected to a bias potential line via a primary winding of a first transformer. Connect the other electrode to the second
Connected to a ground potential line via the primary winding of the transformer of the first transformer, and connected to each other via the secondary winding of the first transformer and the secondary winding of the second transformer. A method for driving a capacitive load, comprising inverting the potential polarity of a pair. 6. The method of driving a capacitive load according to claim 1, wherein a current flowing direction of the secondary winding is regulated by a diode. 7. The method of driving a capacitive load according to claim 1, wherein a reverse current path is provided in parallel with the primary winding. 8. A drive circuit for controlling the potential of one electrode of a pair of electrodes constituting a capacitive load in a binary manner, wherein one end of a primary winding and one end of a secondary winding are commonly connected. A first transformer having the other end of the primary winding connected to a bias potential line, and the other end of the secondary winding connected to a ground potential line; and a first transformer connected between the first transformer and the electrode. A switching device for opening and closing a current path; one end of a primary winding and one end of a secondary winding are commonly connected; the other end of the primary winding is connected to the ground potential line; A drive comprising: a second transformer having the other end of the line connected to the bias potential line; and a switching device for opening and closing a current path between the second transformer and the electrode. circuit. 9. A driving circuit for controlling the potential of one electrode of a pair of electrodes constituting a capacitive load in a binary manner, comprising: a capacitor having one end connected to a ground potential line; A first transformer in which one ends of the secondary windings are commonly connected, the other end of the primary winding is connected to a bias potential line, and the other end of the secondary winding is connected to the capacitor; A switching device for opening and closing a current path between a first transformer and the electrode; one ends of a primary winding and a secondary winding are commonly connected; and the other end of the primary winding is grounded. A second transformer connected to a potential line and having the other end of the secondary winding connected to the capacitor; and a switching device for opening and closing a current path between the second transformer and the electrode. Drive characterized by having Road.