KR100854220B1 - Plasma display module - Google Patents

Abstract

In the plasma display module, the power supply circuit can be reduced in size and miniaturized. A plasma display panel 1 having an address electrode for selecting an address of a display pixel, a Y electrode for selecting a display pixel, and an X electrode for applying a sustain discharge voltage of the selected pixel, an address electrode driving circuit 4, and a Y electrode A plasma display module comprising a driving circuit 2, an X electrode driving circuit 3, a control circuit 5, and a power supply circuit 6, wherein the electrode circuit 6 has an electric field capacitor 61 and 1 unit. An electric double layer capacitor 62 having a capacity capable of accumulating a charge 20 times or more the discharge current of the frame is an electric field capacitor Cd for flowing a high frequency current to the Y electrode driving circuit 2 and the X electrode driving circuit 3, or Ceramic capacitors and / or film capacitors Cf (not shown) were provided between the discharge sustain voltage line Vs and ground G, respectively.

Electrolytic Capacitor, Electrode Driving Circuit, Control Circuit, Address Electrode Driving Circuit, Discharge Sustaining Voltage Line, Ceramic Capacitor

Description

Plasma Display Module {PLASMA DISPLAY MODULE}

The present invention relates to a plasma display module, and more particularly to a power supply circuit for display.

Plasma displays are large / large-capacity flat panel displays, and the market is expanding as flat-panel televisions for home use. However, power consumption, display quality, and cost that are similar to those of CRTs are required.

Plasma displays are pulse drive devices, in which spike-like large currents flow, in particular for display discharge. In order to perform the display stably and to maintain the display luminance at a predetermined level, stabilization of the power supply voltage is required, and a power supply circuit requires a large power element for flowing a peak current. In addition, in the plasma display, since a large current spike current flows, noise is likely to occur from a transformer or the like.

The structure of the conventional AC drive type plasma display module and its control method will be described with reference to FIGS. 6 to 9. 6, the basic configuration of the plasma display module will be described. The plasma display module includes a plasma display panel 1, an X electrode drive (X sustain: X electrode sustain discharge) circuit 3, a Y electrode drive (Y scan) circuit 2, and an address electrode drive circuit (address). Driver) 4, control circuit 5, and power supply circuit 6, respectively.

The plasma display panel 1 includes Y electrodes (scan electrodes: Y buses) Yi in which writing of each pixel is controlled by the Y electrode driving circuit 2, and sustain discharge to each pixel by the X electrode driving circuit 3. An X electrode (hold discharge electrode: X bus) Xi to which a voltage is applied is provided, and an address electrode Aj in which the address of each pixel is controlled by the address electrode driving circuit 4.

The Y electrode drive circuit (scan driver) 2 is configured to scan electrodes Y1, Y2, Y3,... Under the control of the control circuit 5. Supply a predetermined voltage. Scan electrodes Y1, Y2, Y3,... Each of or their generic names is called a scan electrode Yi, and i denotes a subscript.

The X electrode drive circuit (sustained discharge electrode sustain circuit) 3 includes sustain discharge electrodes X1, X2, X3, ...; Supply the same voltage to each. Hereinafter, sustain discharge electrodes X1, X2, X3,... Each or their generic name is called sustain discharge electrode Xi, and i means subscript. Each sustain discharge electrode Xi is interconnected and has the same voltage level.

The address electrode driving circuit 4 includes address electrodes A1, A2, A3,... Supply a predetermined voltage. Hereinafter, address electrodes A1, A2, A3,... Each or their generic name is referred to as address electrode Aj, and j means subscript.

The control circuit 5 controls the Y electrode drive circuit 2, the X electrode drive circuit 3, and the address electrode drive circuit 4.

The power supply circuit 6 is a circuit for applying a driving voltage to the control circuit 5, the X electrode driving circuit 3, the Y electrode driving circuit 2, and the address electrode driving circuit 4.

In the display area set in the PDP panel 1, the scan electrode Yi and the sustain discharge electrode Xi form a row extending in parallel in the horizontal direction, and the column in which the address electrode Aj extends in the vertical direction is formed. Scan electrodes Yi and sustain discharge electrodes Xi are alternately arranged in the vertical direction. A stripe rib structure is formed between each address electrode Aj.

Scan electrode Yi and address electrode Aj form a two-dimensional matrix of i rows and j columns. The display cell Cij is formed by the intersection of the scan electrode Yi and the address electrode Aj and the sustain discharge electrode Xi adjacent thereto correspondingly. This Cij corresponds to a pixel and can display a two-dimensional image in the display area.

FIG. 7A is a diagram showing a cross-sectional structure in a plane parallel to the stretching direction of the address electrode Aj of the display cell Cij in FIG. 6. The sustain discharge electrode Xi and the scan electrode Yi are formed on the front glass substrate 12. A dielectric layer 15 for insulating the discharge space 13 is deposited thereon, and an MgO (magnesium oxide) protective film 16 is further deposited thereon.

On the other hand, the address electrode Aj is formed on the rear glass substrate 11 disposed to face the front glass substrate 12, and a dielectric layer 14 is deposited thereon, and a phosphor is further deposited thereon.

Ne + Xe gas or the like is sealed in the discharge space 13 between the MgO protective film 16 and the dielectric layer 14.

7B is a diagram for explaining the capacitance Cp of the AC drive plasma display. The capacitance Ca is the capacitance of the discharge space 13 between the sustain discharge electrode Xi and the scan electrode Yi. The capacitance Cb is the capacitance of the dielectric layer 15 between the sustain discharge electrode Xi and the scan electrode Yi. The capacitor Cc is the capacitance of the front glass substrate 12 between the sustain discharge electrode Xi and the scan electrode Yi. The capacitance Cp between the electrodes Xi and Yi is determined by the sum of these capacitances Ca, Cb, and Cc.

7C is a cross-sectional view in a plane orthogonal to the stretching direction of the address electrode Aj for explaining light emission of the AC drive plasma display. On the inner surface of the rib 17, red, blue, and green phosphors 18 are arranged and coated in a stripe shape for each color, and used for pixel display between the sustain discharge electrode Xi and the scan electrode Yi (discharge electrode pair). The phosphor 18 is excited by the discharge to generate light 19.

8 is a configuration diagram of one frame FR of an image. An image is formed at 60 frames / second, for example. One frame FR includes a first subframe SF1, a second subframe SF2,... , N-th subframe SFn. This n is 10, for example, and depends on the number of gradation bits. Each of subframes SF1, SF2 and the like or their generic name is hereinafter referred to as subframe SF.

Each subframe SF is composed of a reset period Tr, an address period Ta, and a sustain period (sustain discharge period) Ts. In the reset period Tr, the display cells are initialized. In the address period Ta, lighting or non-lighting of each display cell can be selected by address designation. The selected cell emits light in the sustain period Ts. In the sustain period Ts of each subframe SF, the number of flashes (the number of sustain pulses) varies depending on the brightness of light emission. The luminance of the pixel is determined by the sum of the number of light emission in one frame FR.

9 is a waveform diagram of the subframe SF shown in FIG. 8. Fig. 9 shows an example of waveforms of voltages applied to the X electrode, the Y electrode, and the address electrode in one subframe among a plurality of subframes constituting one frame. One subframe is divided into a reset period Tr consisting of a full surface write period and a full surface erase period, an address period Ta, and a sustain period Ts.

In the sustain period Ts, sustain discharge is performed by alternately applying voltages (+ Vs / 2 and -Vs / 2) having different polarities to the sustain discharge electrode X and the scan electrode Y of each display line, thereby producing an image of one subframe. Display. In addition, the operation | movement applied alternately is called a sustain operation. By the sustain operation, charges of different polarities are accumulated on the sustain discharge electrodes X and the scan electrodes Y at the time of discharge, and when the next sustain discharge voltage is applied, discharge is started at a voltage below the discharge start under the influence of the accumulated charges. Each electrode accumulates reverse polarity charges. This discharge is a discharge in which a large current flows in a very short time.

As described above, the configuration and control method of the plasma display module are already known (see Patent Document 1, for example).

Patent Document 1: Japanese Patent Laid-Open No. 5-265397

<Start of invention>

Problems to be Solved by the Invention

As described above, most of the power consumption of the conventional plasma display is gas discharge power for display, and a spike-shaped discharge current flows by application of a high frequency discharge sustain pulse of about 100 Hz for sustain discharge. In order to display a moving image, 50 frames or 60 frames are rewritten in one second, but subframes such as a case of performing multi-gradation display by the ADS subframe method are rewritten to display. In an AC plasma display, luminance is substantially proportional to the number of discharge sustain pulses, and when the sustain pulse cycles are the same, a period in which a high frequency spike-shaped discharge current flows in each subframe flows, for example, 1/2/4 / 8/16/32 is different.

Each subframe is composed of periods such as reset / address / display. Normally, about three quarters of the display period is required in the reset / address, etc., and the time for which display discharge is performed is about one quarter of the total. Since the discharge current corresponding to the single sustain pulse has a period of about 5 mA at a width of 1 m or less, the current flowing in the single discharge usually flows from a capacitor 61 such as an electrolytic capacitor or a film capacitor of the power supply circuit 6. Although it can supply, since the voltage of a capacitor | condenser falls as the number of discharge increases, it is necessary to supply it from the power supply circuit 6, ie, from a large current rectification / smoothing circuit, when discharge is continuous. Since the discharge period is about one quarter of the total, a large power source capable of supplying a current of about four times the average power is required, and there is a problem that the cost is high and the size / weight becomes large. In addition, since a large current spike current flows, there is a problem that noise is likely to occur from a transformer or the like.

It is an object of the present invention to provide a display device in which a power supply circuit is made low in cost and miniaturized in a plasma display module. Moreover, an object of this invention is to provide the power supply which a noise does not generate | occur | produce.

Means for solving the problem

MEANS TO SOLVE THE PROBLEM In order to solve the said subject, this invention is a plasma display panel which has the address electrode which selects the address of a display pixel, the Y electrode which selects a display pixel, and the X electrode which applies the sustain discharge voltage of a selected pixel, and an address electrode drive. A plasma display module including a circuit, a Y electrode driving circuit, an X electrode driving circuit, a control circuit, and a power supply circuit, the capacitance capable of accumulating 20 times or more of the discharge current of one frame in the electrode circuit. Capacitors were provided between the discharge sustain voltage line and ground.

In addition, in the plasma display module, the capacitor is an electric double layer capacitor, and an electric field capacitor and / or a ceramic capacitor or / and a film capacitor for flowing a high frequency current to a plasma display driving circuit or a power supply circuit are discharge sustain voltage. It was further provided between the line and the ground.

That is, in the plasma display panel or the plasma display module, although there is a change in instantaneous power within one frame, a power supply circuit having an average current / power is sufficient as long as the peak current / power in one frame can be accumulated in a capacitor or the like. In the case of a plasma display, since the peak current of the power supply is about four times the average power, when a capacitor and a parallel capacitor are formed to maintain the power supply voltage so as not to affect the discharge operation or luminance for one frame, the power supply circuit The average power supply can be reduced to about 1/4. Therefore, since the current flowing through the transformer constituting the power supply circuit becomes substantially constant, the generation of noise from the transformer or the like can also be prevented.

Effect of the Invention

According to the present invention, the power supply circuit corresponding to the average power of about 1/4 is sufficient, not the high power supply circuit corresponding to the peak power in one frame, so that the power supply circuit can be reduced in size and downsized, and the noise is reduced. The occurrence of is gone, too. In addition, the instantaneous voltage fluctuation of the applied voltage can be reduced, and stable display can be performed.

BRIEF DESCRIPTION OF THE DRAWINGS The figure explaining the outline | summary of the structure of the plasma display module which concerns on this invention.

2 is a view for explaining the configuration of one display frame in the plasma display module according to the present invention;

FIG. 3 is a diagram schematically showing a relationship between a voltage and a discharge current applied to an X electrode driving circuit and a Y electrode driving circuit in the frame shown in FIG. 2. FIG.

Fig. 4 is a diagram illustrating a relationship between discharge current and power supply current in one frame of the plasma display module according to the present invention.

5 is a diagram illustrating an operation margin of an AC PDP.

6 is a view for explaining an outline of a configuration of a conventional plasma display module.

Fig. 7A is a longitudinal sectional view in a plane parallel to the stretching direction of the address electrode for explaining the structure of the plasma display panel.

7B is an explanatory diagram illustrating the generation of a capacitor in the plasma display panel.

Fig. 7C is a longitudinal sectional view in a plane perpendicular to the stretching direction of the address electrode for explaining the structure of the plasma display panel.

Fig. 8 is a waveform diagram showing an example of the sustain discharge current type of the present invention.

9 is a diagram illustrating an approximation of an applied voltage in a plasma display module.

<Description of the code>

1: plasma display panel

2: Y electrode driving circuit

3: X electrode driving circuit

4: address electrode driving circuit

5: control circuit

6: power circuit

61: electric field capacitor

62: electric double layer capacitor

A: address electrode

X: X electrode (holding discharge electrode)

Y: Y electrode (scan electrode)

<Best Mode for Carrying Out the Invention>

A configuration and control method of the plasma display module according to the present invention will be described with reference to FIG. 1. The plasma display module according to the present invention has a configuration almost similar to that of the plasma display module shown in FIG. 6. That is, the plasma display module according to the present invention includes the plasma display panel 1, the Y electrode driving circuit 2, the X electrode driving circuit 3, the address electrode driving circuit 4, and the control circuit 5. And the power supply circuit 6.

The Y electrode drive circuit 2 and the X electrode drive circuit 3 can generate sustain discharge pulses of the sustain period Ts shown in FIG. 8.

In the present invention, the Y electrode driving circuit 2 and the X electrode driving circuit 3 are formed by combining a plurality of electrolytic capacitors Cd and / or film capacitors Cf and / or ceramic capacitors Cc (not shown), and Countermeasures against a large current pulse are generated by applying a sustain discharge voltage pulse. In addition, in the present invention, the electric double layer capacitor 62 is connected to the power supply circuit 6 in parallel with the electric field capacitor Cd 61 and is connected in parallel to the sustain discharge voltage Vs output.

The current flowing out from the sustain pulse generating circuit of the Y electrode drive circuit 2 is mainly caused by the discharge current generated immediately after the application of each sustain pulse, and a pulse current of about 0.3 ㎲ width flows. When the pulse current flows from the power supply circuit 6, the voltage effect is generated by the impedance of the wiring, so that the electrolytic capacitor Cd / film capacitor Cf / ceramic capacitor Cc and the like are placed near the sustain voltage pulse generating circuit of the Y electrode driving circuit 2. Is formed.

The principle of the luminance expression for each pixel in this invention is demonstrated using FIG. For example, in gray scale display using 8 bits, one frame of 16.7 ms is divided into eight sub-frames SF1 to SF8, and each sub-frame SF has a reset period and an address period of 1.5 ms and sustain. It consists of a discharge period. The luminance is determined by the number of discharge pairs in the sustain discharge period. For example, in SF1, the luminance 1 is represented by two pairs of sustain discharges in the sustain discharge period (0.01 ms), and in SF8, the luminance 128 is represented by the sustain discharge period ( 1.28 mA) by sustain discharge of 256 pairs.

The sustain discharge pulse current and the current waveform flowing from the power supply circuit 6 will be described with reference to FIGS. 3 and 4. In an example of a 42-inch panel, the peak current per line of the sustain discharge pulse is about 200 mA, and the power supply current in the sustain discharge period is about 6 A. The average current of one frame is about 1.5 A (165 V x 1.5 A = about 250 W), but since the total capacitor capacity of the capacitor Cd formed in the power supply is usually about 1000 mA, the current in one frame cannot be accumulated. The current capacity of rectifiers and the like is designed to be 6A or more. Thus, a current capacity of about four times the average power is required. When a large current spike current flows, noise tends to be generated from the transformer. In general, the transformer is impregnated with an insulating resin to reduce the noise.

5 shows display characteristics when the sustain voltage Vs and the address voltage Va of the display panel are changed. In this example, the sustain voltage range (voltage margin) that can be displayed normally is about 8 V, indicating that the display is normally performed when the Vs voltage variation is 5% or less. However, in general, it is preferable that the variation of the Vs voltage be 2% or less in consideration of the temperature variation and the temporal variation of the driving voltage.

Between the output voltage Vs (about 165V) and ground G of the power supply circuit 6, an electric double layer capacitor (20OV / 0.01F) 62 and an electric field capacitor Cd (200V / 270kV) 61 are X electrode drive circuits. An electric field capacitor Cd (200 V / 270 kV) and a film capacitor Cf (200 V / 2 kV) are respectively connected between the discharge sustain voltage Vs (about 160 V) and ground G in (3). In this driving circuit, as shown in Fig. 3, the discharge current corresponding to the sustain voltage pulse is the same as before, and the average current flowing in the discharge sustain period is about 6A and the average current of one frame is about 1.5A. . The charge Qo flowing in one frame is 1.5A × 16.7㎳ ≒ 25mQ, and if the current flows only from the electric double layer capacitor 62, the voltage Vs of the capacitor decreases to (Vs · C-Qo) /C≒0.985Vs. . Since the variation in the discharge holding voltage is about 1.5% and 5% or less, it is normally displayed in the stable operating voltage range.

As shown in Fig. 4, the current flowing from the power supply circuit 6 becomes substantially constant at about 1.5A, and the transformer / rectifier of the power supply circuit may be designed with a current capacity of about 1.5A. In addition, since a current flowing in a power supply circuit such as a transformer is constant, no noise is generated even if the insulating resin is not impregnated.

To achieve a voltage fluctuation of 2% or less that satisfies the long-term stability of the display, (Vs.C-Qo) /Vs.C> 0.98, that is, Vs.C> 50Qo is satisfied. In addition, in order to set the voltage fluctuation to 5% or less, it is necessary to satisfy Vs · C> 20Qo. In other words, in order to suppress the voltage fluctuation, a capacitor having a capacity capable of accumulating at least 20 times, preferably 50 times, of the discharge current of one frame is required. By connecting the electric double layer capacitor 62 having such a capacity to the sustain voltage power supply circuit, even if the output current from the power supply circuit 6 such as a transformer / rectifier circuit varies within one frame, Even when the output current from a power supply circuit such as a transformer / rectifier circuit fluctuates within one frame, the voltage fluctuation becomes 2% or less or 5% or less, respectively, despite the small power supply circuit current capacity, so that normal display can be performed. have.

In order to make such a large capacity only with the electric field capacitor 61, it is necessary to mount a very large and many capacitors, and there is no merit, but when the electric double layer capacitor 62 is used, a small and large capacity capacitor can be realized. Thus, the same design as the embodiment of the present application is possible.

In addition, the said embodiment is only what demonstrated the example of embodiment in implementing this invention, Comprising: The technical scope of this invention should not be interpreted limitedly by these. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

Claims (2)

A plasma display panel having an address electrode for selecting an address of a display pixel, a Y electrode for selecting a display pixel, and an X electrode for applying a discharge sustain voltage of the selected pixel, an address electrode driving circuit, a Y electrode driving circuit, and an X electrode A plasma display module including a driving circuit, a control circuit, and a power supply circuit, And the power supply circuit includes a capacitor having a capacitance capable of accumulating at least 20 times the charge in the amount of charge corresponding to the average discharge current value between frames in the power supply line for the discharge sustain voltage. The method of claim 1, The capacitor includes an electric double layer capacitor and an electrolytic capacitor, and at least one of an electrolytic capacitor, a ceramic capacitor and a film capacitor is connected to a high voltage line of a discharge sustain voltage of each of the Y electrode driving circuit and the X electrode driving circuit. And between the low pressure line and the plasma display module.

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