WO2009118792A1

WO2009118792A1 - Plasma display device

Info

Publication number: WO2009118792A1
Application number: PCT/JP2008/000799
Authority: WO
Inventors: 佐々木孝; 高木彰浩
Original assignee: 株式会社日立製作所
Priority date: 2008-03-28
Filing date: 2008-03-28
Publication date: 2009-10-01

Abstract

A plasma display device comprises a plasma display panel (PDP) and a driving unit. The PDP comprises a first substrate on which a first electrode, a second electrode, and an address electrode are provided and a second substrate on which a division wall is provided. The driving unit comprises first, second, and third driving circuits. For example, during a sustain period, the first driving circuit alternately applies a first voltage and a second voltage to the first electrode and the second driving circuit applies a predetermined voltage having a voltage value between the first voltage and the second voltage to the second electrode. The third driving circuit applies an adjusting voltage higher than the predetermined voltage to the address electrode at least in one of periods in which the second voltage is applied to the first electrode. As a result, the color shade of an image displayed on the PDP can be adjusted.

Description

Plasma display device

The present invention relates to a plasma display device.

The plasma display device (PDP device) has a plasma display panel (PDP) and a drive unit for driving the PDP. A PDP is formed by bonding two glass substrates (a front glass substrate and a back glass substrate) to each other, and generates an image by generating discharge light in a space (discharge space) formed between the glass substrates. indicate. The cells corresponding to the pixels in the image are self-luminous, and are coated with phosphors that generate red, green, and blue visible light in response to ultraviolet rays generated by discharge.

In PDP, in order to display an image with multiple gradations, a field for displaying one screen is composed of a plurality of subfields. For example, the number of sustain discharges in the sustain period of the subfield is sequentially set to 2 n times (n is a positive integer). Then, the subfield used for displaying the image is selected according to the luminance of each color (red, green, and blue) of the image for each cell that generates red, green, and blue visible light. Thereby, a multi-tone color image is displayed.

Generally, in this type of PDP, the hue of an image displayed on the PDP is adjusted by reducing the number of gradations of a specific color. For example, when the red luminance is increased over the entire screen, the maximum number of sustain discharges generated in one field in cells that generate green and blue visible light is reduced compared to cells that generate red visible light. . In this case, the number of gradations of the color image decreases, and the luminance of the image decreases.

In addition, in a PDP having three electrodes, a technique for adjusting the hue of an image displayed on the PDP while maintaining the number of gradations of each color has been proposed (for example, see Patent Document 1). For example, the PDP of Patent Document 1 is synchronized with the pulse applied to the Y electrode during the sustain period on the address electrode of the cell corresponding to the low-luminance color in order to adjust the color of the image displayed on the PDP. Apply pulse at timing.

In a general three-electrode PDP, the X electrode and the Y electrode are arranged on the front glass substrate, and the address electrodes are arranged on the rear glass substrate. In recent years, a PDP in which three electrodes, that is, an X electrode, a Y electrode, and an address electrode are arranged on a front glass substrate has been proposed (see, for example, Patent Document 2). In the PDP of Patent Document 2, the address electrode provided on the front glass substrate is disposed at a position overlapping the partition provided on the rear glass substrate. Further, the X electrode and the Y electrode are constituted by a bus electrode extending in a direction intersecting with the address electrode and a transparent electrode provided in each cell. The transparent electrode of the Y electrode is disposed between the transparent electrode of the X electrode and the address electrode.
Japanese Patent No. 3598790 JP 2005-310785 A

In a PDP in which three electrodes are provided on a front glass substrate, for example, as described above, a transparent electrode of Y electrode is disposed between a transparent electrode of X electrode and an address electrode. Therefore, when a pulse is applied to the address electrode at a timing synchronized with the pulse applied to the Y electrode, the transparent electrode of the Y electrode may function as a shield for the electric field generated from the address electrode to the transparent electrode of the X electrode. is there. In this case, the electric field strength between the address electrode and the Y electrode and the X electrode cannot be efficiently increased, and there is a possibility that the discharge strength of the cell of a specific color cannot be increased. That is, in a PDP having three electrodes on the front glass substrate, a specific number of gradations of each color is maintained even when a pulse is applied to the address electrode at a timing synchronized with the pulse applied to the Y electrode. There is a possibility that the luminance of the color cell cannot be increased.

An object of the present invention is to adjust the hue of an image displayed on a PDP in a state where the number of gradations of each color is maintained in a PDP device having a PDP in which three electrodes are provided on a front glass substrate.

The plasma display device has a plasma display panel (PDP) that displays a color image and a drive unit that drives the PDP. The PDP has a first substrate and a second substrate that face each other through a discharge space. The first substrate extends in the first direction and is spaced apart from each other, and a plurality of address electrodes extending in a second direction intersecting the first direction. have. The second substrate has a plurality of partition walls extending in the second direction and arranged at intervals.

For example, the cell is formed in a region surrounded by the first and second electrodes that make a pair with each other and the partition walls adjacent to each other. The first and second electrodes protrude from the first electrode toward the second electrode for each cell and are adjacent to one of the partition walls constituting the cell, and from the second electrode toward the first electrode. And a second projecting portion disposed between the other of the partition walls constituting the projecting cell and the first projecting portion. Note that the address electrode is disposed between the other of the partition walls constituting the cell and the second protrusion.

The drive unit has a first drive circuit, a second drive circuit, and a third drive circuit. For example, the first driving circuit alternately applies a first voltage and a second voltage lower than the first voltage to the first electrode during a sustain period in which a sustain discharge is generated between the first and second electrodes of the cell. The two-drive circuit applies a predetermined voltage having a voltage value between the first voltage and the second voltage to the second electrode during the sustain period. The third driving circuit applies an adjustment voltage higher than a predetermined voltage to the address electrode in at least one of the periods in which the second voltage is applied to the first electrode during the sustain period.

In the present invention, in a PDP apparatus having a PDP in which three electrodes are provided on the front glass substrate, the hue of an image displayed on the PDP can be adjusted while maintaining the number of gradations of each color.

It is a figure which shows the PDP apparatus in one Embodiment. It is a figure which shows the principal part of PDP shown in FIG. It is a figure which shows the outline | summary of PDP shown in FIG. It is a figure which shows the structural example of the field for displaying the image of 1 screen. It is a figure which shows the outline | summary of the circuit part shown in FIG. It is a figure which shows an example of operation | movement of the color tone adjustment part shown in FIG. FIG. 3 is a diagram illustrating an example of a subfield discharging operation for displaying an image on the PDP illustrated in FIG. 2. It is a figure which shows another example of the discharge operation | movement of the subfield for displaying an image on PDP shown in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. A plasma display device (hereinafter also referred to as a PDP device) includes a plasma display panel 10 having a square plate shape (hereinafter also referred to as a PDP), an optical filter 20 provided on the image display surface 16 side (light output side) of the PDP 10, A front housing 30 disposed on the image display surface 16 side of the PDP 10, a rear housing 40 and a base chassis 50 disposed on the back surface 18 side of the PDP 10, and attached to the rear housing 40 side of the base chassis 50 to drive the PDP 10. A double-sided adhesive sheet 70 for attaching the PDP 10 to the base chassis 50. Since the circuit unit 60 includes a plurality of components, the circuit unit 60 is indicated by a dashed box in the figure.

The PDP 10 includes a front substrate portion 12 (first substrate) that forms the image display surface 16 and a rear substrate portion 14 (second substrate) that faces the front substrate portion 12. A discharge space (cell) (not shown) is formed between the front substrate portion 12 and the rear substrate portion 14. The front substrate unit 12 and the back substrate unit 14 are formed of, for example, a glass substrate. The optical filter 20 is affixed to a protective glass (not shown) attached to the opening 32 of the front housing 30. The optical filter 20 may have a function of shielding electromagnetic waves. The optical filter 20 may be directly attached to the image display surface 16 side of the PDP 10 instead of the protective glass.

FIG. 2 shows details of the main part of the PDP 10 shown in FIG. An arrow D1 in the drawing indicates the first direction D1, and an arrow D2 indicates the second direction D2 orthogonal to the first direction D1 in a plane parallel to the image display surface. As described above, the discharge space DS is formed between the front substrate portion 12 and the rear substrate portion 14 (more specifically, the concave portion of the rear substrate portion 14).

The front substrate portion 12 is provided extending in the first direction D1 on the surface of the glass substrate FS that faces the glass substrate RS (the lower side in the figure), and a plurality of Xs arranged at intervals from each other. A bus electrode XB and a Y bus electrode YB are provided. Further, an X transparent electrode XT (first projecting portion, first display electrode) extending in the second direction D2 from the X bus electrode XB to the Y bus electrode YB is connected to the X bus electrode XB. A Y transparent electrode YT (second projecting portion, second display electrode) extending in the second direction D2 from the Y bus electrode YB to the X bus electrode XB is connected to the Y bus electrode YB. In the illustrated example, the X transparent electrode XT and the Y transparent electrode YT face each other along the second direction D2.

For example, the X bus electrode XB and the Y bus electrode YB are opaque electrodes formed of a metal material or the like, and the X transparent electrode XT and the Y transparent electrode YT are transparent that transmit visible light formed of an ITO film or the like. Electrode. The X electrode XE (first electrode, sustain electrode) is composed of the X bus electrode XB and the X transparent electrode XT, and the Y electrode YE (second electrode, scan electrode) is the Y bus electrode YB and the Y transparent electrode YT. And is paired with the X electrode XE. Then, a discharge (sustain discharge) is repeatedly generated between the X electrode XE and the Y electrode YE paired with each other (more specifically, between the X transparent electrode XT and the Y transparent electrode YT).

The transparent electrodes XT and YT may be disposed on the entire surface between the bus electrodes XB and YB to which the transparent electrodes XT and YT are connected and the glass substrate FS. Further, even if the electrodes (for example, the first and second protrusions) integrated with the bus electrodes XB and YB are formed of the same material (metal material or the like) as the bus electrodes XB and YB, instead of the transparent electrodes XT and YT, Good.

The electrodes XB, XT, YB, YT are covered with the dielectric layer DL. For example, the dielectric layer DL is an insulating film such as a silicon dioxide film formed by a CVD method. A plurality of address electrodes AE extending in a direction perpendicular to the bus electrodes XB and YB (second direction D2) are provided on the dielectric layer DL (lower side in the figure). Thus, the PDP of this embodiment has three electrodes (electrodes XE, YE, AE) on the front substrate portion 12.

The address electrode AE and the dielectric layer DL are covered with a protective layer PL. For example, the protective layer PL is formed of an MgO film having high secondary electron emission characteristics due to cation collision in order to easily generate discharge.

The back substrate portion 14 facing the front substrate portion 12 through the discharge space DS is formed in parallel with each other on the glass base RS and extends in a direction (second direction D2) orthogonal to the bus electrodes XB and YB. It has a partition wall (barrier rib) BR. That is, the barrier ribs BR are provided on the surface of the glass substrate RS that faces the glass substrate FS, extend in the second direction D2 that intersects the first direction D1, and are arranged at intervals. A partition wall BR constitutes a side wall of the cell. Further, visible light of red (R), green (G), and blue (B) is generated on the side surface of the partition wall BR and the glass substrate RS between the adjacent partition walls BR by being excited by ultraviolet rays. Phosphors PHr, PHg, and PHb are respectively applied.

One pixel of the PDP 10 is composed of three cells that generate red, green, and blue light. Here, one cell (one color pixel) is formed in a region surrounded by the bus electrodes XB and YB and the partition wall BR as shown in FIG. 3 described later. As described above, the PDP 10 is configured by arranging cells in a matrix to display a color image and alternately arranging a plurality of types of cells that generate light of different colors. Although not particularly illustrated, a display line is constituted by cells formed along the bus electrodes XB and YB.

The PDP 10 is configured by bonding the front substrate portion 12 and the rear substrate portion 14 so that the protective layer PL and the partition wall BR are in contact with each other, and enclosing a discharge gas such as Ne or Xe in the discharge space DS.

FIG. 3 shows an outline of the PDP 10 shown in FIG. 3 shows the state of the electrodes XB, XT, YB, YT, AE and the partition wall BR as viewed from the image display surface side (upper side in FIG. 2). The meanings of the arrows in the figure are the same as those in FIG.

The cells CLr, CLg, and CLb in the figure indicate cells that generate red, green, and blue visible light, respectively. Hereinafter, the cells CLr, CLg, and CLb are also referred to as cells CL when they are not distinguished for each color. As described above, the cell CL (CLr, CLg, CLb) is in a region (region surrounded by a broken line in the figure) surrounded by the pair of bus electrodes XB, YB and a pair of adjacent barrier ribs BR. It is formed. In addition, address electrodes AEr, AEg, and AEb in the figure indicate address electrodes corresponding to the cells CLr, CLg, and CLb, respectively. Hereinafter, the address electrodes AEr, AEg, and AEb are also referred to as address electrodes AE when they are not distinguished for each color.

As described above, one pixel PX of the PDP 10 includes cells CLr, CLg, and CLb that generate red, green, and blue light. That is, the pixel PX includes a plurality of types of cells CL that respectively generate different colors of light. In addition, the cell group for each color (for example, a red cell group, a green cell group, and a blue cell group) includes cells CL that generate light of the same color. For example, the red cell group includes cells CLr that generate red light.

The bus electrodes XB and YB are formed in parallel along the first direction D1, and are alternately arranged along the second direction D2. In each cell CL, the transparent electrode XT and the address electrode AE (AEr, AEg, AEb) are arranged adjacent to one and the other of the partition walls BR on both sides of the cell CL, respectively, and the transparent electrode YT It arrange | positions between AE and the transparent electrode XT.

That is, the transparent electrode XT is provided for each cell CL, protrudes from the bus electrode XB toward the bus electrode YB paired with the bus electrode XB, and is formed on the barrier ribs BR (the barrier ribs constituting the cell CL) on both sides of the cell CL. It is arranged adjacent to one side. In addition, the transparent electrode YT is provided for each cell CL, protrudes from the bus electrode YB toward the bus electrode XB paired with the bus electrode YB, and the partition BR on both sides of the cell CL (the partition BR constituting the cell CL). It arrange | positions between the other and the transparent electrode XT. In the example shown in the drawing, the tip E2 of the transparent electrode YT is located closer to the bus electrode XB than the tip E1 of the transparent electrode XT.

The address electrode AE extends in the second direction D2 through each cell CL, and is arranged between the other of the partition walls BR on both sides of the cell CL (the one where the transparent electrode XT is not adjacent) and the transparent electrode YT. Has been. Note that when viewed from the image display surface side, the address electrode AE may be disposed at a position that partially overlaps the partition wall BR, or may be disposed at a position that partially overlaps the transparent electrode YT. That is, the address electrode AE is disposed at a position away from the transparent electrode XT and at a position close to the transparent electrode YT.

Thus, in this embodiment, the inter-wiring capacitance between the address electrode AE and the transparent electrode XT can be made smaller than the inter-wiring capacitance between the address electrode AE and the transparent electrode YT. As a result, in this embodiment, power consumption of a circuit for driving the transparent electrode XT (sustain electrode XE) (for example, an X driver XDRV in FIG. 4 described later) can be reduced.

In each cell CL, the transparent electrode YT is opposed to both the address electrode AE and the transparent electrode XT. Therefore, an address discharge can be generated between the address electrode AE and the transparent electrode YT of the target cell CL by applying a voltage between the address electrode AE and the scan electrode YE of the target cell CL. In addition, a sustain discharge can be generated between the transparent electrode XT and the transparent electrode YT of the cell CL selected by the address discharge by applying a voltage between the sustain electrode XE and the scan electrode YE.

FIG. 4 shows a configuration example of the field FLD for displaying an image of one screen. The length of one field FLD is 1/60 second (about 16.7 ms), and is composed of, for example, eight subfields SF (SF1-SF8). In the illustrated example, each subfield SF has a reset period RST, an address period ADR, and a sustain period SUS.

For example, in the reset period RST, the amounts of wall charges accumulated in the electrodes XE, YE, and AE are adjusted in order to match the discharge start voltages (voltages at which address discharge in the address period ADR starts to occur) of all cells. It is a period. Here, the wall charges are, for example, plus charges and minus charges accumulated on the surface of the protective layer PL such as MgO shown in FIG. 2 in each cell.

The address period ADR is a period for selecting a cell to be lit in the sustain period SUS. For example, a cell to be lit in the sustain period SUS is selected by selectively generating an address discharge between the scan electrode YE and the address electrode AE in the address period, as shown in FIG. The sustain period SUS is a period in which a sustain discharge is generated between the sustain electrode XE and the scan electrode YE of the cell (cell to be lit) selected in the address period ADR.

The length of the sustain period SUS varies depending on the subfield SF and depends on the number of discharges (luminance) of the cell. Therefore, it is possible to display a color image with multiple gradations by changing the combination of subfields SF to be lit. In this example, the number of discharge cycles preset in the subfield SF1-8 is 4, 8, 16, 32, 64, 128, 256, and 512, respectively. As shown in FIG. 7 described later, the cell is discharged twice during one discharge cycle (star mark in the figure).

FIG. 5 shows an outline of the circuit unit 60 shown in FIG. In FIG. 5, the description of the voltage applied to the electrodes XE, YE, and AE in the reset period RST is omitted. The circuit unit 60 includes a power supply unit PWR, a memory unit MEM, a control unit CNT, an X driver XDRV (first drive circuit), a Y driver YDRV (second drive circuit), and an address driver ADRV (third drive circuit). Yes. The power supply unit PWR generates power supply voltages Vs, −Vs, Vsc, Vsa and the like to be supplied to the drivers XDRV, YDRV, and ADRV.

The memory unit MEM is formed of, for example, DRAM (Dynamic RAM), SRAM (Static RAM), flash memory, or ROM, and various parameters of the PDP (for example, adjustment data indicating the color of an image displayed on the PDP and screen brightness) Is stored).

For example, the adjustment data indicating the hue of the image displayed on the PDP is data indicating the balance of the brightness of red, green and blue light, and is controlled from the memory unit MEM to the control unit CNT by a color tone adjustment signal TCNT (adjustment signal). (More specifically, it is transmitted to the color tone adjustment unit ADJ). Therefore, the color tone adjustment signal TCNT is a signal indicating the balance of luminance of red, green and blue light, for example.

Note that adjustment data indicating the hue of the image displayed on the PDP is adjusted in the manufacturing process of the PDP and stored in the memory unit MEM. Alternatively, when an operation unit (not shown) such as a remote controller is operated by the user to adjust the hue of the image, adjustment data indicating the hue of the image to be adjusted is stored in the memory unit MEM.

The control unit CNT has a color tone adjustment unit ADJ (adjustment unit) for adjusting the hue of the image displayed on the PDP. For example, the color tone adjustment unit ADJ is an adjustment that is one of color-specific cell groups including cells that generate light of the same color in order to adjust the hue of an image (color image) displayed on the PDP. Select a cell group. Here, the adjustment cell group is a cell group to which an adjustment pulse AJP (adjustment voltage) shown in FIG. 7 described later is applied to the address electrode AE in order to adjust the color of the image. Details of the operation of the color tone adjustment unit ADJ will be described later with reference to FIG.

Also, the control unit CNT controls the operation of the drivers XDRV, YDRV, and ADRV. For example, the control unit CNT sequentially receives the image data R0-7, G0-7, and B0-7, and based on the received image data R0-7, G0-7, and B0-7, the cells constituting the pixel PX The subfield to be used is selected for each CL. Thereby, a multi-tone color image is displayed. Then, for example, the control unit CNT outputs control signals YCNT, XCNT, and ACNT indicating subfields used by each cell CL to the drivers YDRV, XDRV, and ADRV. The control signal ACNT includes a control signal for applying the adjustment pulse AJP to the address electrode AE.

The drivers XDRV, YDRV, and ADRV operate as a drive unit that drives the PDP 10. For example, the X driver XDRV commonly applies a sustain pulse (for example, voltages Vs and −Vs) to the bus electrode XB during the sustain period SUS. Further, the Y driver YDRV maintains the bus electrode YB at a common constant voltage (for example, ground voltage) in the sustain period SUS, and selectively selects the scan pulse (for example, voltage Vsc) for the bus electrode YB in the address period ADR. Apply to.

The address driver ADRV selectively applies an address pulse (for example, a waveform voltage that returns from the voltage Vsa to the voltage Vsa via the ground voltage) to the address electrode AE in the address period ADR. Further, the address driver ADRV applies an adjustment pulse AJP (adjustment voltage, for example, voltage Vsa) shown in FIG. 7 described later to the address electrode AE of the adjustment cell group in the sustain period SUS.

FIG. 6 shows an example of the operation of the color tone adjustment unit ADJ shown in FIG. The process shown in FIG. 6 may be realized only by hardware, or may be realized by controlling the hardware by software.

First, in process 100, the color tone adjustment unit ADJ receives a color tone adjustment signal TCNT for adjusting the hue of an image displayed on the PDP. For example, the color tone adjustment unit ADJ receives a color tone adjustment signal TCNT from the memory unit MEM when a power supply of a PDP (not shown) is turned on. Alternatively, the color tone adjustment unit ADJ receives the color tone adjustment signal TCNT when an operation unit (not shown) such as a remote controller is operated by the user to adjust the hue of the image. Therefore, the color tone adjustment unit ADJ performs the process of FIG. 6 every time it receives the color tone adjustment signal TCNT.

In the process 200, the color tone adjustment unit ADJ selects an adjustment cell group from cell groups for each color (for example, a red cell group, a green cell group, and a blue cell group) based on the color tone adjustment signal TCNT. For example, when the color tone adjustment unit ADJ receives a color tone adjustment signal TCNT indicating that the red luminance is increased over the entire screen and the green luminance is decreased over the entire screen, the red and blue cell groups are adjusted to the adjusted cell group. Select as each. In this case, the adjustment pulse AJP is not applied to the address electrode of the green cell group.

In the process 300, the color tone adjustment unit ADJ sets the number of times (adjustment frequency) of applying the adjustment pulse AJP (adjustment voltage) to the address electrode AE during one field FLD for each adjustment cell group based on the color tone adjustment signal TCNT. . For example, the color tone adjustment unit ADJ sets the number of adjustments 1020 times for the red cell group, and sets the number of adjustments 510 times for the blue cell group. In this example, the blue luminance is set higher than the green luminance and lower than the red luminance.

In process 400, the color tone adjustment unit ADJ is set in process 300 according to the number of sustain discharges set in each subfield SF (for example, the number of discharge cycles shown in FIG. 4 described above) for each adjustment cell group. The adjusted number of adjustments is distributed to each subfield SF. For example, the color tone adjustment unit ADJ distributes the number of adjustments to each subfield SF in accordance with the ratio of the number of discharge cycles of each subfield SF to the number of discharge cycles of one field FLD.

In the configuration example of the field FLD shown in FIG. 4 described above, in the red cell group in which the number of adjustments of 1020 is set, the number of adjustments distributed to the subfields SF1-8 is 4, 8, 16, 32, 64, 128, 256, 512. In the blue cell group in which 510 adjustment times are set, the adjustment times distributed to the subfields SF1-8 are 2, 4, 8, 16, 32, 64, 128, and 256, respectively. In this case, the ratio between the number of discharge cycles and the number of adjustments in each subfield SF is set to be equal to each other.

Note that the ratio between the number of discharge cycles and the number of adjustments in each subfield SF may not be set equal to each other. For example, when the number of adjustments in one field FLD is 64, the number of adjustments distributed to subfields SF1-8 is 0, 1, 1, 2, 4, 8, 16, and 32, respectively. When the number of adjustments in one field FLD is 400, the number of adjustments distributed to the subfields SF1-8 is 2, 3, 6, 13, 25, 50, 100, and 101, respectively.

Note that the information indicating the distributed number of adjustments is included in the control signal ACNT and transmitted to the address driver ADRV as described above. As a result, the red luminance of the image displayed on the PDP can be increased over the entire screen, and the green luminance can be decreased over the entire screen.

Thus, in this embodiment, for example, when the green luminance is lowered over the entire screen, the maximum number of sustain discharges generated in one field FLD of the green cell group is set to the cells of other colors (red, blue). There is no need to reduce it compared to the group. That is, in this embodiment, even when the green luminance is lowered on the entire screen, the number of gradations of green is maintained the same as the number of gradations of other colors (red and blue). In other words, in this embodiment, the hue of the image displayed on the PDP can be adjusted while maintaining the number of gradations of each color.

FIG. 7 shows an example of the discharge operation of the subfield SF for displaying an image on the PDP 10 shown in FIG. FIG. 7 shows an example of the discharge operation of subfield SF1 when the red and blue cell groups are selected as the adjustment cell groups. The star in the figure indicates the occurrence of discharge. Further, the waveform voltages of the electrodes XE, YE, and AE shown in FIG. 7 are applied to the electrodes XE, YE, and AE, for example, by the drivers XDRV, YDRV, and ADRV shown in FIG. In the example shown in the figure, the number of adjustments 1020 times in one field FLD is set in a red cell group, and the number of adjustments 510 times in one field FLD is set in a blue cell group. That is, the numbers of adjustments set in the subfield SF1 of the red and blue cell groups are 4 and 2, respectively.

First, in the reset period RST, a predetermined voltage (the ground voltage GND in the figure) is applied to the sustain electrode XE (the bus electrode XB and the transparent electrode XT), and a negative write voltage (write blunt wave) that gently falls is scanned. Applied to the electrode YE (the bus electrode YB and the transparent electrode YT), the positive voltage Vsa is applied to the address electrode AE (FIG. 7A). Thereby, wall charges are accumulated in the electrodes XE, YE, and AE, respectively, while suppressing the light emission of the cell. For example, negative wall charges, positive wall charges, and negative wall charges are accumulated in sustain electrode XE, scan electrode YE, and address electrode AE, respectively.

Next, sustain electrode XE is maintained at ground voltage GND, and a positive adjustment voltage (adjustment blunt wave) that gradually increases is applied to scan electrode YE, and ground voltage GND is applied to address electrode AE (FIG. 7). (B)). Thereby, the amount of wall charges accumulated in sustain electrode XE, scan electrode YE, and address electrode AE can be adjusted. For example, the maximum value of the adjustment voltage is a voltage lower than the voltage Vs.

In the address period ADR, the sustain electrode XE is maintained at the ground voltage GND, and the positive voltage Vsa is applied to the address electrode AE (FIG. 7C). Then, a scan pulse (voltage Vsc) serving as an anode during address discharge is applied to the scan electrode YE, and an address pulse (ground voltage GND) serving as a cathode during address discharge is applied to the address electrode AE corresponding to the lighted cell. (FIG. 7D). In the cell selected by the scan pulse and the address pulse, a discharge is temporarily generated between the scan electrode YE and the address electrode AE (address discharge), and this discharge is used as a trigger to temporarily stop between the sustain electrode XE and the scan electrode YE. Discharge (address discharge) occurs. Thereby, a cell to be lit in the sustain period SUS is selected.

The sustain electrode XE becomes a cathode with respect to the scan electrode YE at the time of address discharge by the ground voltage GND lower than the voltage Vsc. The address electrode AE becomes a cathode with respect to the scanning electrode YE at the time of address discharge by a ground voltage GND (address pulse which becomes a cathode at the time of address discharge) lower than the voltage Vsc. That is, the scan electrode YE becomes an anode with respect to the sustain electrode XE and the address electrode AE at the time of address discharge by the voltage Vsc (a scan pulse that becomes an anode at the time of address discharge). For this reason, in the cell selected by the address discharge, positive and negative wall charges are accumulated in the sustain electrode XE and the scan electrode YE, respectively.

For example, in this embodiment, the voltage Vsc of the scan pulse is higher than the maximum value of the adjustment voltage. Further, the voltage difference between the voltage Vsc and the voltage Vsa is smaller than the discharge start voltage (the lowest voltage that causes discharge) between the address electrode AE and the scan electrode YE. Thereby, it is possible to prevent erroneous discharge from occurring between the address electrode AE maintained at the voltage Vsa and the scan electrode YE to which the scan pulse (voltage Vsc) is applied. Note that the second address pulse (ground voltage GND) shown in the waveform of the address electrode AE is applied to select a cell in another display line (FIG. 7E).

In the sustain period SUS, first, a positive sustain pulse (first voltage, voltage Vs) is applied to the sustain electrode XE, and a constant voltage Vb (predetermined voltage), which is an intermediate voltage between the voltage Vs and the voltage −Vs, is applied. , And applied to the scan electrode YE, and the ground voltage GND is applied to the address electrode AE (FIG. 7F). For example, the voltage Vb is the ground voltage GND that is an average value of the voltage Vs and the voltage −Vs. The voltage Vb may be a constant voltage having a voltage value between the voltage Vs and the voltage −Vs. In the cell (lighted cell) selected in the address period ADR, positive and negative wall charges are accumulated in the sustain electrode XE and the scan electrode YE, respectively. Therefore, the voltage between the sustain electrode XE and the scan electrode YE is the voltage It becomes larger than Vs.

Thereby, in the lighted cell, the voltage between sustain electrode XE and scan electrode YE becomes larger than the discharge start voltage between sustain electrode XE and scan electrode YE, and discharge (sustain discharge) occurs between sustain electrode XE and scan electrode YE. appear. Then, in the cells where discharge has occurred (lighted cells), negative and positive wall charges are accumulated in the sustain electrode XE to which the voltage Vs is applied and the scan electrode YE to which the ground voltage GND is applied, respectively.

Next, a negative sustain pulse (second voltage, voltage −Vs) is applied to sustain electrode XE, scan electrode YE and address electrode AEg are maintained at ground voltage GND, respectively, and adjustment pulse AJP (adjustment voltage Vsa) Are applied to the address electrodes Ar and AEb, respectively (FIG. 7G). In the cell where the discharge occurred immediately before (figure 7 (f)) (lighted cell), the negative and positive wall charges are accumulated in the sustain electrode XE and the scan electrode YE, respectively. The voltage between the electrodes YE becomes larger than the discharge start voltage. Thereby, in the lighted cell, a discharge (sustain discharge) is generated between the sustain electrode XE and the scan electrode YE, and the discharge state is maintained.

In the red and blue cell groups, as described above, the adjustment pulse AJP is applied to the address electrodes AE (AEr, AEb) in synchronization with the negative sustain pulse (low level period LP1 in FIG. 7). That is, the adjustment voltage Vsa higher than the constant voltage Vb is applied to the address electrodes Ar and AEb in at least one of the periods (low level period LP) in which the voltage −Vs is applied to the sustain electrodes XE. In other words, the adjustment voltage Vsa higher than the constant voltage Vb is one of the adjustment cell groups in the low level period LP1 in which the voltage (voltage −Vs) of the sustain electrode XE is lower than the constant voltage Vb (the ground voltage GND in the figure). Are applied to address electrodes AEr and AEb respectively corresponding to the red and blue cell groups. For example, the adjustment voltage Vsa is the same voltage as the positive voltage Vsa maintained at the address electrode AE during the address period ADR. Thereby, in this embodiment, it is not necessary to newly generate a power supply voltage for the adjustment pulse AJP, and the configuration of the circuit unit 60 (for example, the power supply unit PWR and the address driver ADRV) can be simplified.

Among the red and blue cell groups to which the adjustment voltage Vsa is applied to the address electrode AE, in the cells to be lit, there is an electric field from the address electrode AE to the transparent electrode XT in addition to the electric field from the transparent electrode YT to the transparent electrode XT. appear. That is, in the cells in which the red and blue cell groups are lit, a stronger electric field is generated in the transparent electrode XT than the other color (for example, green) cell groups. Thereby, in the lighted cells of the red and blue cell groups, many cations collide with the protective layer PL on the transparent electrode XT, and a strong discharge is generated.

Here, for example, when the voltage of the transparent electrode YT disposed between the address electrode AE and the transparent electrode XT is higher than the adjustment voltage Vsa, the electric field generated from the adjustment voltage Vsa is directed from the transparent electrode YT to the address electrode AE. Mainly occurs. Thereby, when the voltage of the transparent electrode YT is higher than the adjustment voltage Vsa, even if the adjustment voltage Vsa is applied to the address electrode AE, the electric field from the address electrode AE to the transparent electrode XT is weak, so a strong electric field is applied to the transparent electrode XT. May not occur.

On the other hand, in this embodiment, as described above, since the voltage Vb of the transparent electrode YT is lower than the adjustment voltage Vsa, in the cells that are lit in the adjustment cell group (red and blue cell groups in the example in the figure) The electric field strength between the address electrode AE and the transparent electrode YT and the transparent electrode XT can be increased, and the discharge strength can be increased. As a result, in this embodiment, the brightness of the cells to be lit in the adjustment cell group (red and blue cell groups in the example in the figure) can be increased.

In the cells where discharge has occurred, positive and negative wall charges are accumulated in the sustain electrode XE to which the voltage −Vs is applied and the scan electrode YE to which the ground voltage GND is applied, respectively. In this way, sustain pulses (voltage Vs, voltage -Vs) having different polarities from the voltage Vb (ground voltage GND) applied to the scan electrode YE are alternately applied to the sustain electrode XE (FIG. 7 ( f, g)), the discharge of the cells lit in the sustain period SUS (sustain discharge) is repeatedly performed. As described with reference to FIG. 4 described above, two discharges are performed during one discharge cycle (for example, FIG. 7 (f, g)). For example, the subfield SF1 is composed of four discharge cycles, and eight discharges are performed.

In the second low level period LP2, the adjustment voltage Vsa is applied to the address electrodes AER and AEb corresponding to the red and blue cell groups, respectively, and the address electrode AEg is maintained at the ground voltage GND. Thereby, the brightness | luminance of the cell which the red and blue cell group lights can be made high.

In the third and fourth low level periods LP3 and LP4, the adjustment voltage Vsa is applied to the address electrode AERr corresponding to the red cell group, and the address electrodes AEg and AEb are maintained at the ground voltage GND. Thereby, the brightness | luminance of the cell which a red cell group lights can be made high. Therefore, in the example of the figure, when the luminance of each color when the adjustment pulse AJP is not applied is the same, the application of the adjustment pulse AJP increases the red luminance of the image displayed on the PDP over the entire screen, and The green brightness can be lowered throughout the screen.

Finally, a positive erase pulse that rises slowly is applied to the sustain electrode XE (FIG. 7 (h)). As a result, a discharge is generated to reduce the wall charge of only the lit cell, and the amount of wall charge of the lit cell is reduced.

As described above, in the adjustment cell group, the number of adjustment pulses AJP (adjustment voltage Vsa) indicated by the number of adjustments set by the adjustment unit ADJ is synchronized with the negative sustain pulse (low level period LP) during the sustain period SUS. Then, it is applied to the address electrode AE. That is, the number of low level periods LP to which the adjustment voltage Vsa is applied by the address driver ADRV is equal to the number of adjustments. In the adjustment cell group, a bias voltage (for example, ground voltage GND) equal to or lower than the constant voltage Vb is applied to the address electrode during a period when the adjustment voltage Vsa is not applied to the address electrode AE. In the cell group excluding the adjustment cell group, the address electrode AE is maintained at a bias voltage (for example, the ground voltage GND) equal to or lower than the constant voltage Vb during the sustain period SUS.

As described above, in this embodiment, during the sustain period SUS, the scan electrode YE is maintained at the constant voltage Vb (for example, the ground voltage GND), and the sustain pulse is applied to the sustain electrode XE. Further, in this embodiment, during the sustain period SUS, the number of adjustment pulses AJP (adjustment voltage Vsa higher than the constant voltage Vb) indicated by the number of adjustments set by the adjustment unit ADJ are negative sustain pulses (low level period LP). Synchronously with this, it is applied to the address electrode AE of the adjustment cell group. Thereby, the brightness | luminance of the visible light which the cell of an adjustment cell group emits can be made high in the state which maintained the number of gradations of each color. As a result, in this embodiment, the hue of the image displayed on the PDP can be adjusted while maintaining the number of gradations of each color.

In the above-described embodiment, an example in which one pixel includes three cells (red (R), green (G), and blue (B)) has been described. The present invention is not limited to such an embodiment. For example, one pixel may be composed of four or more cells. Alternatively, one pixel may be composed of cells that generate colors other than red (R), green (G), and blue (B), and one pixel may be red (R), green (G), A cell that generates a color other than blue (B) may be included.

In the above-described embodiment, the example in which the second direction D2 is orthogonal to the first direction D1 has been described. The present invention is not limited to such an embodiment. For example, the second direction D2 may intersect the first direction D1 in a substantially perpendicular direction (for example, 90 ° ± 5 °). Also in this case, the same effect as the above-described embodiment can be obtained.

In the above-described embodiment, an example in which the present invention is applied to a plasma display panel in which one field is composed of eight subfields SF1-8 has been described. The present invention is not limited to such an embodiment. For example, the present invention may be applied to a plasma display panel in which one field is composed of 10 or more subfields. Further, the number of discharge cycles in the subfield is not limited to 2 to the power of n (n = 2 or larger integer). Further, the subfields SF1-8 (FIG. 4) in the field FLD may not be sequentially arranged. For example, subfield SF8 may be arranged near the center of field FLD.

In the above-described embodiment, the example in which the adjustment pulse AJP is applied to the address electrode AE in the low level period LP in the first half of the sustain period SUS when the number of the adjustment pulses AJP is smaller than the number of the low level periods LP has been described. The present invention is not limited to such an embodiment. For example, when the number of adjustment pulses AJP is smaller than the number of low level periods LP, the adjustment pulse AJP is an address electrode in the low level period LP near the center of the sustain period SUS (for example, the low level periods LP2 and LP3 in FIG. 7). The adjustment pulse AJP may be applied to the address electrode AE in the low level period LP (for example, the low level periods LP3 and LP4 in FIG. 7) in the latter half of the sustain period SUS. Alternatively, the adjustment pulse AJP may be applied to the address electrode AE in a discontinuous low level period LP (for example, the low level periods LP2 and LP4 in FIG. 7). Also in this case, the same effect as the above-described embodiment can be obtained.

In particular, in the first half of the sustain period SUS, the sustain discharge may not be stable. Therefore, when the adjustment pulse AJP is applied to the address electrode AE in the low level period LP excluding the first low level period LP1, the sustain discharge is performed. Can be prevented from becoming unstable. Further, when the adjustment pulse AJP is applied to the address electrode AE in the low level period LP excluding the last low level period LP (for example, the low level period LP4 in FIG. 7), for example, the wall charges of only the lighted cells are reduced. A discharge for decreasing (for example, the last discharge in the sustain period SUS in FIG. 7) or the like can be stably generated. When the adjustment pulse AJP is applied to the address electrode AE at intervals (for example, the low level periods LP2 and LP4 in FIG. 7), each sustain discharge can be stably generated.

In the above-described embodiment, an example in which two cell groups among the three cell groups by color are selected as the adjustment cell groups has been described. The present invention is not limited to such an embodiment. For example, among the cell groups by color, only one cell group may be selected as the adjustment cell group, or all the cell groups may be selected as the adjustment cell group. Also in this case, the same effect as the above-described embodiment can be obtained.

In the above-described embodiment, in the address period ADR, the scan pulse (voltage Vsc) serving as the anode during address discharge and the address pulse (ground voltage GND) serving as the cathode during address discharge are applied to the scan electrode YE and the address electrode AE, respectively. An example was described. The present invention is not limited to such an embodiment. For example, as shown in FIG. 8, in the address period ADR, a scan pulse (voltage -Vsc2) that becomes a cathode during address discharge and an address pulse (voltage Vsa2) that becomes an anode during address discharge are applied to the scan electrode YE and the address electrode AE. Each may be applied. Also in this case, the same effect as the above-described embodiment can be obtained.

FIG. 8 shows another example of the subfield discharge operation for displaying an image on the PDP. In the example of FIG. 8, the polarity of the voltage applied between the scan electrode YE and the address electrode AE and the polarity of the voltage applied between the scan electrode YE and the sustain electrode XE are shown in FIG. It is different from the waveform. Detailed description of the same operations as those in FIG. 7 described above will be omitted. The meaning of the asterisk in the figure is the same as in FIG.

First, in the reset period RST, the ground voltage GND is applied to the sustain electrode XE and the address electrode AE, respectively, and a positive write voltage (write blunt wave) that gradually increases is applied to the scan electrode YE (FIG. 8 (a2)). ). As a result, positive wall charges, negative wall charges, and positive wall charges are accumulated in sustain electrode XE, scan electrode YE, and address electrode AE, respectively.

Next, sustain electrode XE and address electrode AE are maintained at ground voltage GND, and a negative adjustment voltage (adjustment blunt wave) that gently falls is applied to scan electrode YE (FIG. 8 (b2)). Thereby, the amount of wall charges accumulated in sustain electrode XE, scan electrode YE, and address electrode AE can be adjusted. For example, the minimum value of the adjustment voltage is a voltage higher than the voltage −Vs.

In the address period ADR, the sustain electrode XE and the address electrode AE are maintained at the ground voltage GND, and a negative bias voltage is applied to the scan electrode YE (FIG. 8 (c2)). Then, a scan pulse (voltage -Vsc2) serving as a cathode during address discharge is applied to the scan electrode YE, and an address pulse (voltage Vsa2) serving as an anode during address discharge is applied to the address electrode AE corresponding to the lighted cell. (FIG. 8 (d2)). For example, the scan pulse voltage −Vsc2 is lower than the minimum value of the adjustment voltage.

In the cell selected by the scan pulse and the address pulse, a discharge is temporarily generated between the scan electrode YE and the address electrode AE (address discharge), and this discharge is used as a trigger to temporarily stop between the sustain electrode XE and the scan electrode YE. Discharge (address discharge) occurs. Thereby, a cell to be lit in the sustain period SUS is selected. In the cell selected by the address discharge, negative and positive wall charges are accumulated in the sustain electrode XE and the scan electrode YE, respectively. Further, the second address pulse (ground voltage GND) shown in the waveform of the address electrode AE is applied to select a cell of another display line (FIG. 8 (e2)).

In the sustain period SUS, a negative sustain pulse (second voltage, voltage −Vs) is first applied to the sustain electrode XE, and a constant voltage Vb having a voltage value between the voltage Vs and the voltage −Vs is scanned. It is applied to the electrode YE (FIG. 8 (f2)). Further, the ground voltage GND is applied to the address electrode AEg, and the adjustment pulse AJP (adjustment voltage Vsa2) is applied to the address electrodes Ar and AEb, respectively (low level period LP1 in FIG. 8). For example, the voltage Vb is a ground voltage GND that is intermediate between the voltage Vs and the voltage −Vs. Further, for example, the adjustment voltage Vsa2 is the same voltage as the address pulse voltage Vsa2 in the address period ADR. Thereby, in this embodiment, it is not necessary to newly generate a power supply voltage for the adjustment pulse AJP, and the configuration of the circuit unit 60 (for example, the power supply unit PWR and the address driver ADRV) can be simplified.

In the cell (lighted cell) selected in the address period ADR, negative and positive wall charges are accumulated in the sustain electrode XE and the scan electrode YE, respectively. For this reason, the voltage between sustain electrode XE and scan electrode YE becomes larger than the discharge start voltage between sustain electrode XE and scan electrode YE, and discharge (sustain discharge) occurs between sustain electrode XE and scan electrode YE. Then, in the cell where the discharge is generated (lighted cell), positive and negative wall charges are accumulated in the sustain electrode XE and the scan electrode YE, respectively.

Of the red and blue cell groups to which the adjustment voltage Vsa is applied to the address electrode AE, in the lighted cell, in addition to the electric field from the transparent electrode YT to the transparent electrode XT, the address electrode AE is directed to the transparent electrode XT. An electric field is generated. Accordingly, in the cells that are lit in the adjustment cell group (red and blue cell groups in the example in the figure), the discharge intensity is increased and visible light with high luminance is generated. As a result, in the example shown in the figure, the brightness of the lighted cells of the red and blue cell groups can be increased.

Next, a positive sustain pulse (first voltage, voltage Vs) is applied to the sustain electrode XE, and the scan electrode YE and the address electrode AE are maintained at the ground voltage GND (FIG. 8 (g2)). In the cell in which discharge occurred immediately before (f2 in FIG. 8) (lighting cell), positive and negative wall charges are accumulated in the sustain electrode XE and the scan electrode YE, respectively. The voltage between the electrodes YE becomes larger than the discharge start voltage. Thereby, in the lighted cell, a discharge (sustain discharge) is generated between the sustain electrode XE and the scan electrode YE, and the discharge state is maintained.

As described above, the sustain pulses (voltage -Vs, voltage Vs) having different polarities with respect to the voltage Vb (ground voltage GND) are alternately applied to the sustain electrodes XE (FIG. 8 (f2, g2)). The discharge of the cells that are lit during the sustain period SUS (sustain discharge) is repeated.

In the second low level period LP2, the adjustment voltage Vsa is applied to the address electrodes AEr and AEb corresponding to the red and blue cell groups, respectively, and the address electrode AEg is maintained at the ground voltage GND. Thereby, the brightness | luminance of the cell which the red and blue cell group lights can be made high. In the third and fourth low level periods LP3 and LP4, the adjustment voltage Vsa is applied to the address electrode AERr corresponding to the red cell group, and the address electrodes AEg and AEb are maintained at the ground voltage GND. Thereby, the brightness | luminance of the cell which a red cell group lights can be made high. Therefore, in the example of the figure, when the luminance of each color when the adjustment pulse AJP is not applied is the same, the application of the adjustment pulse AJP increases the red luminance of the image displayed on the PDP over the entire screen, and Green brightness can be reduced on the entire screen.

Finally, a negative erasing pulse that gradually falls is applied to the sustain electrode XE (FIG. 8 (h2)). As a result, a discharge is generated to reduce the wall charge of only the lit cell, and the amount of wall charge of the lit cell is reduced.

In the example of the discharge operation shown in FIG. 8, the power supply unit PWR shown in FIG. 4 generates the power supply voltages Vsc2 and Vsa2 instead of the power supply voltages Vsc and Vsa. The drivers XDRV, YDRV, and ADRV shown in FIG. 5 described above are the waveforms of the electrodes XE, YE, and AE shown in FIG. 8 instead of the waveform voltages of the electrodes XE, YE, and AE shown in FIG. A voltage is applied to each of the electrodes XE, YE, and AE. Also in this case, the same effect as the above-described embodiment can be obtained.

As described above, the present invention has been described in detail. However, the above-described embodiment and its modification are merely examples of the present invention, and the present invention is not limited thereto. Obviously, modifications can be made without departing from the scope of the present invention.

The present invention can be applied to a plasma display device.

Claims

A plasma display panel for displaying a color image, and a drive unit for driving the plasma display panel,
The plasma display panel is:
A first substrate and a second substrate facing each other through a discharge space;
A plurality of first and second electrodes provided on the first substrate, extending in a first direction and spaced apart from each other;
A plurality of partition walls provided on the second substrate, extending in a second direction intersecting the first direction, and spaced apart from each other;
A plurality of address electrodes provided on the first substrate and extending in the second direction;
The first and second electrodes are directed from the first electrode to the second electrode for each cell formed in a region surrounded by the first and second electrodes paired with each other and the partition walls adjacent to each other. A first protrusion adjacent to one of the partition walls constituting the cell and between the other of the partition walls projecting from the second electrode toward the first electrode and the first protrusion. Each having a second protrusion disposed;
The address electrode is disposed between the other of the partition walls and the second protrusion,
The drive unit is
A first driving circuit that alternately applies a first voltage and a second voltage lower than the first voltage to the first electrode during a sustain period in which a sustain discharge is generated between the first and second electrodes;
A second driving circuit for applying a predetermined voltage having a voltage value between the first voltage and the second voltage to the second electrode during the sustain period;
And a third drive circuit for applying an adjustment voltage higher than the predetermined voltage to the address electrode in at least one of the periods in which the second voltage is applied to the first electrode in the sustain period. A characteristic plasma display device.
The plasma display device according to claim 1, wherein
The plasma display apparatus, wherein the second driving circuit applies a fixed voltage intermediate between the first voltage and the second voltage to the second electrode as the predetermined voltage.
The plasma display device according to claim 1, wherein
The plasma display panel includes pixels composed of a plurality of types of cells that respectively generate light of different colors.
The drive unit includes an adjustment unit that selects an adjustment cell group that is one of the cell groups of different colors configured by the cells that generate light of the same color to adjust the hue of the color image. ,
The adjustment unit selects the adjustment cell group from the cell group for each color based on an adjustment signal for adjusting the hue of the color image, and sets the adjustment voltage to the address electrode for each selected adjustment cell group. Set the number of adjustments that are applied to the
The plasma display apparatus according to claim 3, wherein the number of adjustment voltages applied by the third driving circuit corresponds to the number of adjustments.
The plasma display device according to claim 3, wherein
One field for displaying one screen includes a plurality of subfields having the sustain period in which the number of sustain discharges is set,
For each of the adjustment cell groups, the adjustment unit may determine the number of times the adjustment voltage is applied to the address electrode in the one field according to the number of sustain discharges set in the subfield. A plasma display device.
The plasma display device according to claim 3, wherein
The third driving circuit applies a bias voltage equal to or lower than the predetermined voltage to the address electrodes of the cell group excluding the adjustment cell group during the sustain period, and the adjustment voltage is applied to the address electrode during the sustain period. The plasma display apparatus, wherein the bias voltage is applied to the address electrode of the adjustment cell group during a period in which the bias voltage is not applied.
The plasma display panel device according to claim 3, wherein
2. The plasma display apparatus according to claim 1, wherein each of the pixels includes cells that generate red, green, and blue light.