KR19980023076A - PDP Power Recovery Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power recovery device of a PDP, wherein a high voltage of positive (+,-) is alternately provided to Cp based on pulses P1 and P2 provided from a pulse generator. The external voltage B + is the first external capacitance capacitor C1 through the first inductor L1, the first diode D1, and the third MOSFET T3 based on the pulse P3 from the pulse generator. And a predetermined power source B + / 2 charged to the first external capacitance capacitor C1 based on the pulse P4 from the pulse generator is connected to the second diode D2 through the fourth MOSFET T4. It is provided to Cp 130 via the first inductor L1, and the negative external voltage B- is supplied to the second inductor L2 and the third diode based on the pulse P5 from the pulse generator. The predetermined power source charged in the second external capacitance capacitor C2 through the D3 and the fifth MOSFET T5 and charged in the second external capacitance capacitor C2 based on the pulse P6 from the pulse generator ( B- / 2) 6th MOSFET By providing the Cp through the fourth diode D4 and the second inductor L21 through T6, the PDP can be driven brighter with the same power and the PDP can be driven with the same brightness with less power. In addition, the brightness of the display device using the PDP can be brightened and power consumption can be prevented.

Description

PDP Power Recovery Device

The present invention relates to a PDP (Plasma Display Panel; hereinafter abbreviated as PDP), and more particularly, PDP suitable for being able to recharge the external power provided to the PDP from the outside to supply to the PDP during discharge It relates to a power recovery device of.

Among various display devices that are applied to various fields, cathode ray tubes (hereinafter referred to as CRTs), which have a clear display, colorization, simple operation, and low manufacturing cost, are used in many fields. Since the CRT itself has a Frasco type structure, the CRT is large in size, requires a high operating voltage of approximately 10,000V, and has a big disadvantage of display distortion.

Therefore, there is a strong demand for the emergence of a display device that can replace the above CRT, and research on a so-called flat display device having a large display area and a small volume has been continuously conducted in many fields related thereto.

On the other hand, the flat display device described above includes active devices such as electro luminescence, light emitting diodes, and PDPs, liquid crystal displays, and electro chromic displays. There is a passive element such as a display, and the present invention relates to a display device using a PDP which is substantially one of the active elements.

For reference, the advantages of the above-described PDP display device include a memory function that sustains discharge when the input pulse is input once, and the display point is defined by the matrix structure, so that there is no distortion of the image and the emission frequency is 50-100 kHz. Because it is high, there is no flicker. In addition, since the PDP has a planar structure, it is advantageous for miniaturization, and since the material that reduces the extinguishing due to discharge is used on the surface of the dielectric layer in contact with the discharge, the life is long, and the panel structure mainly composed of the glass plate projects semi-fixed information as a slide It is possible to superimpose on a slide, which is advantageous for simplicity.

On the other hand, PDP is discharged by the discharge of the Penning mixed gas in the discharge space of the PDP based on the high voltage (for example, 180V to 300V) of the positive (+,-) alternately provided from the outside, Such ultraviolet rays excite the phosphor, and light is generated from the phosphor 18.

Here, the penning gas is a mixed gas such as neon (Ne) + argon (Ar) or neon (Ne) + xenon (Xe) based on neon (Ne) or helium (He). When the mixed gas is used, it can be discharged at a lower discharge start voltage than the neon gas.

On the other hand, electrons generated at the time of discharge are blocked by the dielectric material 20 and are not leaked to the outside, but exist as residual electrons in the discharge space. Thus, the remaining electrons in the discharge space can be used to charge electric power. There will be.

3 shows a circuit diagram of a conventional power recovery device for a typical PDP. As shown in the figure, a conventional power recovery device for a PDP includes a sustain pulse generating unit 10, a voltage charging unit 20 and a capacitor (C).

Referring to FIG. 3, the sustain pulse generator 10 is switched according to a pulse of a predetermined level provided from a pulse generator, not shown, to provide a positive external voltage B + to the capacitor C. MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor, hereinafter referred to as MOSFET) (T11, T12).

In addition, the voltage charging unit 20 is switched according to a pulse signal of a predetermined level provided from a pulse generator not shown, and is positively charged from the capacitor C provided through the inductor L and the diodes D11 and D12. ) Consists of two MOSFETs (T13, T14) that provide a high voltage (B +) of the power supply to the external capacitive capacitor (Cs).

On the other hand, as can be seen from Fig. 3 showing the output waveform of point A, in the conventional power recovery device, the MOSFET T13 is turned on and the remaining MOSFETs T11, T12, and T14 are turned off in the period t1. , MOSFET (T11) is turned on in the period t2, MOSFET (T13) is open, the remaining MOSFETs (T12, T14) are turned off, all the MOSFETs (T11, T12, T13, T14) are turned off in the period t3 In the t4 section, the MOSFET T14 is turned on and the remaining MOSFETs T11, T12, and T13 are turned off, thereby recovering and supplying power to the external charging device (external capacitive capacitor Cs), thereby maintaining the sustain pulse. It functions to reduce the sustain pulse current generated when applying.

However, the conventional PDP power recovery apparatus having the above-described configuration has a problem that application of the sustain voltage is not free by performing power recovery and supply to the external capacitive capacitor Cs only in the positive direction of the output voltage. Since the output voltage is made only in the positive direction, when the voltage is applied with the positive polarity of the government, there is a problem that the application of the holding voltage is not free since power recovery and supply are not made in the negative direction.

Accordingly, the present invention is to solve the above problems of the prior art, it is possible to charge the power by the residual electrons present in the discharge to the external charging device with positive and negative polarity voltage and then supply it again at the next discharge. It is an object of the present invention to provide a power recovery device of a PDP.

In order to achieve the above object, the present invention is a device for providing a predetermined external voltage set by the government to the electrode of each unit cell constituting the PDP, the first voltage for providing the external voltage of the government to each electrode of the PDP Generating a pulse and a second pulse, and a fifth pulse and a sixth pulse for supplying the third and fourth pulses for charging the external voltage of the government and the predetermined predetermined voltage to each unit cell of the PDP. A pulse generating means, a holding pulse generating means for providing the PDP with a sustaining pulse due to the external voltage of the government on the basis of the first pulse and the second pulse from the pulse generating means, and the first pulse generating means from the pulse generating means. A constant voltage charging means for charging the positive external voltage based on a third pulse and a fourth pulse to provide each electrode of the PDP at a next discharge, and a fifth pulse from the pulse generating means. And it provides a power recovery device of PDP (PDP), characterized in that consisting of the charging means for providing a negative voltage to the respective electrodes of the PDP at the next discharge by the charging voltage of the external portion on the basis of the sixth pulse.

1 is a schematic block diagram showing a power recovery device of a PDP according to a preferred embodiment of the present invention;

2 is a view for explaining a pulse generated from the pulse generator of FIG.

3 is a circuit diagram of a conventional typical PDP power recovery device

4 is an output waveform diagram of point A of the conventional PDP power recovery device;

* Description of the symbols for the main parts of the drawings *

110: pulse generator 120: sustain pulse generator

130: Cp140: constant voltage charging unit

150: negative voltage charging unit

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a power recovery device of a PDP according to a preferred embodiment of the present invention, a pulse generator 110, sustain pulse generator 120, Cp (130), constant voltage charging unit 140 And a negative voltage charging unit 150.

In the same figure, the pulse generator 110 converts the external voltages B + and B- of the high voltage (eg, 180V to 300V) into the Cp 130 by the positive (+,-) alternately provided from the outside. Pulses P1 and P2 for providing, pulses P3 and P5 for charging such external external voltage and pulses P4 and P6 for providing the charged voltage to Cp 130 are respectively generated.

In addition, the sustain pulse generator 120 may use the first amplifier A1 and the first amplifier A1 to amplify the pulse P1 provided from the pulse generator 110 to a predetermined level. And a first MOSFET (Metal-Oxide Semiconductor Field-Effect Transistor, hereinafter referred to as MOSFET, T1) and a pulse generator 110 that are switched based on the first voltage to provide a positive external voltage B + to the Cp 130. A positive external voltage (B +) is switched on the basis of the second amplifier (A2) for amplifying the pulse P2 provided from the predetermined level to a predetermined level and the pulse (P2) amplified by the second amplifier (A2). ) Is the second MOSFET T2 that provides Cp 130.

In FIG. 1, the constant voltage charging unit 140 may use a third amplifier A3 and a third amplifier A3 for amplifying the pulse P3 provided from the pulse generator 110 to a predetermined level. The positive high voltage B + from Cp 130 supplied through the first inductor L1 and the first diode D1 to the first external capacitive capacitor C1 is switched based on P3). The third MOSFET T3 and the pulse P4 amplified by the fourth amplifier A4 and the fourth amplifier A4 to amplify the pulse P4 provided from the pulse generator 110 to a predetermined level. A fourth MOSFET that is switched based on and supplies predetermined power B + / 2 charged to the first external capacitive capacitor C1 to the Cp 130 through the second diode D2 and the first inductor L1. T4).

Then, the negative voltage charging unit 150 is amplified by the fifth amplifier (A5) and the fifth amplifier (A5) for amplifying the pulse (P5) provided from the pulse generator 110 to a predetermined level. The negative high voltage B- from Cp 130 provided through the second inductor L2 and the third diode D3 is supplied to the second external capacitive capacitor C2. The fifth MOSFET T5 and the pulse P6 amplified by the sixth amplifier A6 and the sixth amplifier A6 for amplifying the pulse P6 provided from the pulse generator 110 to a predetermined level. Based on the sixth MOSFET, the predetermined power B− / 2 charged to the second external capacitive capacitor C1 is supplied to the Cp 130 through the fourth diode D4 and the second inductor L2. T6).

An operation process of the power recovery device of the PDP according to the present invention, which is constituted as described above, will be described in more detail with reference to FIGS. 1 and 2.

Meanwhile, it is assumed that the first external capacitive capacitor C1 is charged with B + / 2 and the second external capacitive capacitor C2 is charged with B− / 2.

First, (a) of FIG. 2 shows the inside of the sustain pulse generator 120 by the pulses P1 and P2 from the pulse generator 110 amplified by the first amplifier A1 and the second amplifier A2. A sustain pulse by an external (+,-) external power source provided by switching the first MOSFET T1 and the second MOSFET T2 is a pulse provided to the Cp 130 through the point A of FIG. 1.

Next, as illustrated in (b) of FIG. 2 in the t1 section of FIG. 2, the pulse P4 from the pulse generator 110 amplified through the fourth amplifier A4 is transferred to the fourth MOSFET T4. Provided, the fourth MOSFET T4 is turned on, and the predetermined power B + / 2 charged in the first external capacitive capacitor C1 is transferred to the second diode D2 and the second diode D4 through the fourth MOSFET T4. It is provided to Cp 130 via one inductor L1.

Next, as illustrated in (c) of FIG. 2 in the t2 section of FIG. 2, the pulse P1 from the pulse generator 110 amplified through the first amplifier A1 is transferred to the first MOSFET T1. The first MOSFET T1 is turned on, and a positive external power source B + is provided to the Cp 130.

In the section t3 of FIG. 2, as illustrated in FIG. 2D, the pulse P3 from the pulse generator 110 amplified through the third amplifier A13 is provided to the third MOSFET T3. The third MOSFET T3 is turned on, and a positive external power supply + B provided to the Cp 130 passes through the first inductor L1 and the second diode D2 and passes through the third MOSFET T3. Is charged into the first external capacitive capacitor C1.

Meanwhile, since no pulses are provided from the pulse generator 110 in the t4 section of FIG. 2, each of the MOSFETs T1, T2, T3, T4, T5, and T6 is turned off, and thus 0V is provided to the Cp 130.

Next, as illustrated in (e) of FIG. 2 in the t5 section of FIG. 2, the pulse P6 from the pulse generator 110 amplified through the sixth amplifier A6 is transferred to the sixth MOSFET T6. Provided to the sixth MOSFET T6 is turned on, and the predetermined power source B- / 2 charged in the second external capacitance capacitor C2 is connected to the fourth diode D4 and the fourth diode D4 through the sixth MOSFET T6. It is provided to the Cp 130 via the two inductors L2.

As shown in FIG. 2 (f) in the section t6 of FIG. 2, the pulse P2 from the pulse generator 110 amplified through the second amplifier A2 is provided to the second MOSFET T2. The second MOSFET T2 is turned on, and a negative external power source B− is supplied to the Cp 130.

Next, as illustrated in (g) of FIG. 2 in the t7 section of FIG. 2, the pulse P5 from the pulse generator 110 amplified through the fifth amplifier A5 is transferred to the fifth MOSFET T5. The fifth MOSFET T5 is turned on, and the negative external power source B- provided to the Cp 130 passes through the second inductor L2 and the third diode D3 to pass through the fifth MOSFET. The second external capacitance capacitor C2 is charged through T5.

As described above, based on the pulses P1 and P2 provided from the pulse generator 110, while the high voltages of the positive and negative parts are alternately provided to the Cp 130, the positive external The voltage B + is applied to the first external capacitance capacitor C1 through the first inductor L1, the first diode D1, and the third MOSFET T3 based on the pulse P3 from the pulse generator 110. After being charged, the predetermined power source B + / 2 charged to the first external capacitance capacitor C1 based on the pulse P4 from the pulse generator 110 is connected to the second diode D2 through the fourth MOSFET T4. ) And the first inductor L1 are provided to the Cp 130, and the negative external voltage B− is applied to the second inductor L2 based on the pulse P5 from the pulse generator 110. ) And the second external capacitance capacitor C2 through the third diode D3 and the fifth MOSFET T5, and then, based on the pulse P6 from the pulse generator 110, the second external capacitance capacitor ( The predetermined power source B- / 2 charged in C2 is discharged through the sixth MOSFET T6. It is provided to the Cp 130 via the fourth diode D4 and the second inductor L21.

Therefore, according to the present invention, the PDP can be driven brighter with the same power, and the PDP can be driven with the same brightness with less power, so that the brightness of the display device using the PDP can be made brighter. By performing the power recovery and supply for the bipolar sustain pulse, the application of the sustain voltage can be made free and the power consumption can be minimized.

Claims (17)

In the apparatus for providing a predetermined external voltage set by the government to the electrode of each unit cell constituting the PDP, A first pulse and a second pulse for supplying the external voltage of the government to each electrode of the PDP, and a third pulse and the fourth pulse for charging the external voltage of the government, and the charged predetermined voltage of the PDP. Pulse generating means (110) for generating a fifth pulse and a sixth pulse for providing each unit cell; Holding pulse generating means (120) for providing the PDP with a holding pulse by an external voltage of the government based on the first pulse and the second pulse from the pulse generating means (110); Constant voltage charging means (140) for charging said positive external voltage based on said third and fourth pulses from said pulse generating means (110) and providing them to each electrode of said PDP at the next discharge; And And a negative voltage charging means 150 which charges the external external voltage based on the fifth and sixth pulses from the pulse generating means 110 and provides them to the electrodes of the PDP at the next discharge. Power recovery device of PDDP. The method of claim 1, The holding pulse generating means is: First amplifying means for amplifying the first pulse to a predetermined level; First switching means for providing said positive external voltage to each electrode of said PDP based on said first pulse amplified by said first amplifying means; Second amplifying means for amplifying the second pulse to a predetermined level; And And a second switching means for providing the negative external voltage to each electrode of the PDP based on the second pulse amplified by the second amplifying means. The method of claim 2, And said first to second switching means are MOSFETs. The method of claim 1, The constant voltage charging means is: Third amplifying means for amplifying the third pulse to a predetermined level; First voltage providing means for providing the first charging means with a positive external voltage provided to each electrode of the PDP based on the third pulse amplified by the third amplifying means; The first charging means for charging the positive external power provided through the first voltage providing means; Fourth amplifying means for amplifying the fourth pulse to a predetermined level; Second voltage providing means for providing a predetermined power supply to each electrode of the PDP based on a fourth pulse amplified by the fourth amplifying means; And A power recovery device of a PDP (PDP) comprising a first inductor to be processed by a predetermined power source charged in the first charging means. The method of claim 4, wherein The first voltage providing means is: First reverse power supply suppressing means for suppressing reverse provision of a predetermined power source charged in said first charging means; And And third switching means for switching the supply of the positive external voltage provided to each electrode of the PDP to the first charging means based on the third pulse amplified by the third amplifying means. PDP power recovery device. The method of claim 5, And said first reverse power source inhibiting means is a diode. The method of claim 5, And said third switching means is a MOSFET. The method of claim 4, wherein The second voltage providing means is: Fourth switching means for switching the provision of predetermined power charged in said first charging means to each electrode of said PDP based on a fourth pulse amplified by said fourth amplifying means; And And a second reverse power suppression means for suppressing a reverse supply of a predetermined power source charged in said first charging means. The method of claim 8, And said fourth switching means is a MOSFET. The method of claim 8, And said second reverse power source suppressing means is a diode. The method of claim 1, The negative voltage charging means: Fifth amplifying means for amplifying the fifth pulse to a predetermined level; Third voltage providing means for providing a negative external power to the second charging means provided to each electrode of the PDP based on the fifth pulse amplified by the fifth amplifying means; The second charging means for charging the external power of the part provided through the third voltage providing means; Sixth amplifying means for amplifying the sixth pulse to a predetermined level; Fourth voltage providing means for providing a predetermined power source charged in said second charging means to each electrode of said PDP based on a sixth pulse amplified by said sixth amplifying means; And And a second inductor resonating by a predetermined power source charged in the second charging means. The method of claim 11, The third voltage providing means is: Third reverse power supply inhibiting means for suppressing reverse provision of a predetermined power source charged in said second charging means; And And fifth switching means for switching the supply of the negative external voltage provided to each electrode of the PDP to the second charging means based on the fifth pulse amplified by the fifth amplifying means. PDP power recovery device. The method of claim 12. And said third reverse power source suppressing means is a diode. The method of claim 12, And said fifth switching means is a MOSFET. The method of claim 11, The fourth voltage providing means is: Sixth switching means for switching the supply of predetermined power charged in said second charging means to each electrode of said PDP based on a sixth pulse amplified by said sixth amplifying means; And And a fourth reverse power inhibiting means for suppressing the reverse supply of the predetermined power charged in the second charging means. The method of claim 15, And said sixth switching means is a MOSFET. The method of claim 15, And said fourth reverse power supply suppressing means is a diode.