JP4802220B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and is suitable for application to the manufacture of a semiconductor laser, a light emitting diode, or an electron transit device using a nitride III-V compound semiconductor, for example.

Nitride III-V compound semiconductors such as GaN, AlGaN, GaInN, and AlGaInN have a larger band gap E _g and direct transition than AlGaInAs III-V compound semiconductors and AlGaInP III-V compound semiconductors. It has the feature of being a semiconductor material. For this reason, these nitride III-V compound semiconductors are semiconductor lasers capable of emitting short-wavelength light from ultraviolet to green, and light-emitting diodes that can cover a wide emission wavelength range from ultraviolet to red and white (LED) has attracted attention as a material constituting semiconductor light emitting devices such as (LED), and is widely considered for applications such as high-density optical discs, full-color displays, and environmental / medical fields.

  Further, these nitride III-V compound semiconductors have a high saturation rate in a high electric field of GaN, for example, can operate at a high temperature up to about 400 ° C., and, for example, MIS (Metal-Insulator- Using AlN as the material of the insulating layer in the (Semiconductor) structure, the semiconductor layer and the insulating layer can be continuously formed by crystal growth. For this reason, these nitride III-V compound semiconductors are also expected as materials constituting high-power high-frequency electronic devices that can operate at high temperatures.

In addition, the following can be cited as the advantages of the nitride III-V compound semiconductor.
(1) The thermal conductivity is higher than that of GaAs-based semiconductors and the like, and it is suitable for high temperature and high output operation devices.
(2) The material is chemically stable, has high hardness, and easily obtains high reliability.
(3) It is a compound semiconductor material with a low environmental load. That is, the AlGaInN-based semiconductor does not contain environmental pollutants and poisons that have a large environmental impact in the constituent materials and raw materials. Specifically, a material corresponding to arsenic (As) in an AlGaAs-based semiconductor, cadmium (Cd) in a ZnCdSSe-based semiconductor, and a raw material thereof (arsine (AsH ₃ )) are not used.

However, conventionally, a device using a nitride III-V compound semiconductor has a problem that there is no appropriate substrate material for obtaining high reliability.
In order to obtain a particularly high-quality crystal as a substrate material for a nitride III-V compound semiconductor, there are the following problems and situations.
(1) The constituent materials GaN, AlGaN, and GaInN are all strain systems having different lattice constants. Therefore, there are design limitations such as suppressing the composition and thickness in a range where no cracks or the like are generated between the nitride-based III-V compound semiconductors and the substrate and a range where a high-quality crystal film is obtained. .
(2) A high quality substrate that lattice matches with GaN has not yet been developed. For example, high-quality GaN substrates are under development, such as high-quality GaAs substrates lattice-matched to GaAs-based semiconductors and GaInP-based semiconductors, and high-quality InP substrates lattice-matched to GaInAs-based semiconductors. A small SiC substrate is expensive, difficult to increase in diameter, and has a problem that a tensile strain is generated in the crystal film, so that a crack is likely to occur. There is no.
(3) As a necessary condition for a substrate material of a nitride III-V compound semiconductor, it may not be altered or corroded at a high crystal growth temperature of about 1000 ° C. and an ammonia atmosphere of a Group V raw material.

For the reasons described above, a sapphire substrate is often used as a nitride-based III-V group compound semiconductor substrate by comprehensive judgment.
The sapphire substrate is stable at the crystal growth temperature of the nitride-based III-V compound semiconductor, and has an advantage that a high-quality 2 or 3 inch substrate is stably supplied. On the other hand, there is a lattice mismatch with GaN. Large (about 13%). For this reason, a buffer layer made of GaN or AlN is formed on the sapphire substrate by low temperature growth, and a nitride III-V compound semiconductor is grown thereon. According to this, it is possible to grow a single crystal nitride III-V compound semiconductor, but the defect density reflects, for example, about 10 ⁸ to 10 ⁹ (cm ⁻² ) reflecting lattice mismatch. For example, it has been difficult to obtain long-term reliability in a semiconductor laser.

  In addition to this, since the sapphire substrate has (1) no cleaving property, it is difficult to stably form a laser end face with high specularity. (2) Since sapphire is insulative, the p-side electrode and the n-side electrode are separated from the top surface of the substrate. Removal is essential. (3) If the crystal growth film is thick, the substrate warpage at room temperature is large due to the difference in thermal expansion coefficient between the nitride III-V compound semiconductor and sapphire, which hinders the device formation process. There is a problem such as.

  In order to improve the quality of a semiconductor crystal grown on a substrate having a different lattice constant such as a sapphire substrate, there is a method using lateral selective overgrowth (ELO). In ELO, a high crystal quality region (lateral growth region) and a low crystal quality or high defect density region (on the seed crystal, its boundary, an association portion, etc.) periodically appear, but the active region of the device (for example, light emission) If the size of the light emitting region in the device and the region in which the electron travels in the electron traveling device) is not large, the period of ELO is larger than the stripe of the semiconductor laser or the emitter region / collector region (or source region / drain region) interval of the transistor. Can take. For example, since the size of the active region of the element is about several μm for an ELO period of 10 to 20 μm, the active region can be designed in a high quality region.

In the case where an element is formed on the sapphire substrate using ELO, there are the following problems in addition to the problems caused by the properties of sapphire itself such as the above-mentioned poor cleavage property.
(1) Since the number of steps required for ELO is large, the yield decreases.
(2) The crystal film thickness increases by an amount necessary for ELO, so that the substrate is greatly warped due to thermal stress, and the controllability of the crystal growth process and the wafer process is lowered.
(3) There is a limit on the element size. In an element having an active region longer than the ELO cycle, for example, several hundred μm square or more, such as an LED, a photodetector (PD), and an integrated device, the entire device region cannot be made a high crystal quality region, so that the effect of ELO is exhibited. Can not.

  The above problems can be solved if a high-quality GaN substrate is obtained, but high-quality and large-diameter GaN substrates have not been obtained so far. This is because GaN cannot stably perform single crystal growth because HVPE (halide vapor phase growth) generally makes it difficult to obtain a high-quality seed crystal by high-temperature (high-pressure) growth. Due to the difficulty of manufacturing.

  Japanese Patent Application Laid-Open No. 2001-102307 proposes a method of manufacturing a single crystal GaN substrate for the purpose of improving this problem. According to this, after forming a GaN seed substrate having a high defect density, a three-dimensional facet (hereinafter referred to as “core”) is formed in part, and the growth is continued under the condition that the facet is not closed. Crystal dislocations are concentrated on the part, and as a result, a high quality substrate is manufactured in a wide area.

JP 2001-102307 A

  However, since the technique disclosed in Japanese Patent Laid-Open No. 2001-102307 reduces threading dislocations in other regions by concentrating threading dislocations in a region where a growth layer is present, the obtained single crystal In the GaN substrate, a low defect density region (core) and a high defect density region are mixed, and the position where the high defect density region is generated cannot be controlled and is generated randomly. For this reason, when a semiconductor device such as a semiconductor laser is manufactured by growing a nitride III-V compound semiconductor layer on this single crystal GaN substrate, a high defect density region is formed in the light emitting region. Inevitably, the emission characteristics and reliability of the semiconductor laser are reduced.

  Accordingly, the problem to be solved by the present invention is to manufacture a semiconductor light emitting device having good characteristics such as light emission characteristics, high reliability and long life, and manufacturing a semiconductor light emitting device capable of easily manufacturing such a semiconductor light emitting device It is to provide a method.

  More generally, the problem to be solved by the present invention is to provide a semiconductor device having good characteristics, high reliability and long life, and a method of manufacturing a semiconductor device capable of easily manufacturing such a semiconductor device There is to do.

  More generally, the problem to be solved by the present invention is to provide various elements having good characteristics, high reliability and long life, and an element manufacturing method capable of easily manufacturing such elements. There is.

  In addition, the problem to be solved by the present invention is that a semiconductor light emitting device having good characteristics such as light emission characteristics and high reliability and a long life or a good characteristics and reliability and a semiconductor device or characteristics having a long life and good characteristics are reliable. It is an object of the present invention to provide a nitride III-V compound semiconductor layer growth method, a semiconductor layer growth method, and a layer growth method that are suitable for use in the manufacture of various types of devices having high properties and long lifetimes.

The present inventor has intensively studied to solve the above problems. The outline is as follows.
The present inventor has succeeded in controlling the position of the high defect density region generated in the low defect density region as a result of improving the technique disclosed in Japanese Patent Application Laid-Open No. 2001-102307. That is, instead of naturally agglomerating and forming a high defect density region during crystal growth, a seed crystal or the like is artificially formed on a suitable substrate such as a GaAs substrate regularly, for example, periodically, for example, periodically. Further, by performing crystal growth thereon, the formation position of the high defect density region can be controlled, and the crystal quality can be improved and the high quality crystal region can be expanded. In this case, the arrangement pattern of the high defect density region can be freely changed by arranging the seed crystal or the like.

  Here, the seed crystal or the like is, for example, polycrystalline, amorphous (single crystal) or single crystal GaN, nitride-based III-V compound semiconductor other than GaN such as AlGaInN, or nitride-based III-V group. Although it is formed of a material other than a compound semiconductor, any structure may be used as long as it is a structure that serves as a nucleus that defines a crystal defect concentration position.

  When a semiconductor light emitting device such as a semiconductor laser, more generally a semiconductor device, is manufactured using such a substrate, it is necessary to eliminate the adverse effect of the high defect density region existing on the substrate on the device. That is, when a semiconductor layer is grown on a substrate, defects are propagated from the high defect density region of the base substrate to the semiconductor layer. Therefore, it is necessary to prevent deterioration of element characteristics and reliability due to the defect. There is.

This problem also occurs when it is difficult to obtain a substrate having the same quality and low defect density as the semiconductor used for the device, and when a semiconductor layer is grown on the same structure as described above. is there. More generally, when it is difficult to obtain a substrate having the same quality and low defect density as the material used for the device, this also occurs when a layer having the same structure as described above is used to grow a layer thereon. It is.
As a result of various studies, the present inventor has found an effective technique capable of solving the above-described problems and has come up with the present invention.

That is, in order to solve the above problem, the first invention of the present invention is:
A nitride system in which a plurality of second regions having a second average dislocation density higher than the first average dislocation density are regularly arranged in a first region made of a crystal having a first average dislocation density. A method of manufacturing a semiconductor light emitting device, wherein a semiconductor light emitting device is manufactured by growing a nitride III-V compound semiconductor layer forming a light emitting device structure on a main surface of a III-V compound semiconductor substrate. And
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

  In order to prevent the nitride-based III-V compound semiconductor layer from coming into direct contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate, specifically, for example, nitride The second region is at least partially removed from the main surface of the nitride III-V compound semiconductor substrate before growing the III-V compound semiconductor layer. More specifically, before growing the nitride III-V compound semiconductor layer, the second region is removed from the main surface of the nitride III-V compound semiconductor substrate to a predetermined depth. Here, the predetermined depth is appropriately selected according to the configuration of the element constituted by the nitride III-V compound semiconductor layer, the growth condition of the nitride III-V compound semiconductor layer, etc. Specifically, the thickness is set to 1 μm or more, preferably about the thickness of the element formed using the nitride III-V compound semiconductor layer (for example, 10 μm or more). The entire second region may be removed before growing the nitride III-V compound semiconductor layer. The removal of the second region is typically performed by etching, specifically, wet etching, dry etching, thermochemical etching, ion milling, or the like.

In order to prevent the nitride III-V compound semiconductor layer from coming into direct contact with the second region on the main surface of the nitride III-V compound semiconductor substrate, the nitride III-V compound semiconductor The surface of the second region may be covered with a covering layer before the layer is grown. As the coating layer, various types can be used as long as it can withstand the growth temperature. Specifically, in addition to an insulating film such as a SiO ₂ film, a Si _x N _y film, and a SOG (Spin on Glass) film, A refractory metal film such as tungsten (W), molybdenum (Mo), tantalum (Ta), or a nitride film thereof can be used. In this case, a coating layer may be simply formed on the second region, but when the second region is removed from the main surface of the nitride-based III-V compound semiconductor substrate to a predetermined depth. The portion from which the second region is removed may be filled with the coating layer. In the former case, the surface of the coating layer is located higher than the main surface of the nitride-based III-V compound semiconductor substrate. In the latter case, the surface of the coating layer can be obtained by using an etch-back technique. Can coincide with the main surface of the nitride III-V compound semiconductor substrate.

  The interval between two adjacent second regions or the arrangement period of the second regions is selected according to the size of the element, etc., but is generally 20 μm or more, 50 μm or more, or 100 μm or more. The upper limit of the interval between the second regions or the arrangement period of the second regions is not necessarily clear, but is generally about 1000 μm. This second region typically penetrates the nitride III-V compound semiconductor substrate. The second region typically has an indefinite polygonal column shape. A third region having a third average dislocation density higher than the first average dislocation density and lower than the second average dislocation density exists as a transition region between the first region and the second region. In this case, the nitride-based III-V compound semiconductor layer may not be in direct contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate. Most preferably, the nitride-based III-V compound semiconductor layer is not in direct contact with these second and third regions on the main surface of the nitride-based III-V compound semiconductor substrate. In the latter case, specifically, for example, before the nitride-based III-V compound semiconductor layer is grown, the second region and the third region are separated from the main surface of the nitride-based III-V compound semiconductor substrate. Remove at least part of it.

  The diameter of the second region is typically 10 μm or more and 100 μm or less, and more typically 20 μm or more and 50 μm or less. When the third region is present, the diameter thereof is typically greater than or equal to 20 μm and less than or equal to 200 μm, more typically greater than or equal to 40 μm and less than or equal to 160 μm, and most typically greater than or equal to 60 μm. Larger than 140 μm.

The average dislocation density in the second region is generally at least 5 times the dislocation density in the first region. Typically, the average dislocation density in the first region is 2 × 10 ⁶ cm ⁻² or less, and the average dislocation density in the second region is 1 × 10 ⁸ cm ⁻² or more. If the third region is present, the average dislocation density that is typically less than 1 × 10 ⁸ cm ^-2, greater than 2 × 10 ⁶ cm ^-2.

  The light emitting region of the semiconductor light emitting element is separated from the second region by 1 μm or more, preferably 10 μm or more, more preferably 100 μm or more in order to prevent adverse effects due to the second region having a high average dislocation density. When the third region exists, it is most preferable that the light emitting region of the semiconductor light emitting element does not include the second region and the third region. More specifically, the semiconductor light emitting element is a semiconductor laser or a light emitting diode. However, in the case of the former semiconductor laser, the region where the drive current flows through the stripe electrode is preferably 1 μm or more from the second region, More preferably, it is 10 μm or more, and more preferably 100 μm or more. When the third region exists, it is most preferable that the region through which the driving current flows through the stripe electrode does not include the second region and the third region. One or a plurality of stripe-shaped electrodes, that is, laser stripes may be provided, and the width thereof may be selected as necessary.

Nitride III-V compound semiconductor substrate or the nitride III-V compound semiconductor layer, most commonly _{Al X B y Ga 1-xyz} In z As u N 1-uv P v ( where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, 0 ≦ u ≦ 1, 0 ≦ v ≦ 1, 0 ≦ x + y + z <1, 0 ≦ u + v <1), and more specifically, Al _{X y y} Ga _1-xyz In _z N (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, 0 ≦ x + y + z <1), typically Al _x Ga _1-xz In _z N (where 0 ≦ x ≦ 1, 0 ≦ z ≦ 1). The nitride-based III-V compound semiconductor substrate is most typically made of GaN.
What has been described in relation to the first invention of the present invention is also valid for the following inventions as long as it is not contrary to the nature thereof.

The second invention of this invention is:
A nitride system in which a plurality of second regions having a second average defect density higher than the first average defect density are regularly arranged in a first region made of a crystal having a first average defect density. A method of manufacturing a semiconductor light emitting device, wherein a semiconductor light emitting device is manufactured by growing a nitride III-V compound semiconductor layer forming a light emitting device structure on a main surface of a III-V compound semiconductor substrate. And
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

  Here, the “average defect density” means the average density of the entire lattice defects that adversely affect the characteristics and reliability of the device, and the defects include all sorts of dislocations, stacking faults, point defects, etc. The same).

The third invention of the present invention is:
A light emitting device on a main surface of a nitride III-V compound semiconductor substrate in which a plurality of second regions having lower crystallinity than the first region are regularly arranged in the first region made of crystal A method for manufacturing a semiconductor light emitting device, wherein a semiconductor light emitting device is manufactured by growing a nitride III-V compound semiconductor layer forming a structure,
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

  Here, typically, the first region made of a crystal is a single crystal, and the second region having lower crystallinity than the first region is a single crystal, polycrystal, amorphous, or two or more thereof. Are mixed (the same applies hereinafter). This corresponds to the case where the average dislocation density or average defect density in the second region is higher than the average dislocation density or average defect density in the first region.

The fourth invention of the present invention is:
A nitride system in which a plurality of second regions having a second average dislocation density higher than the first average dislocation density are regularly arranged in a first region made of a crystal having a first average dislocation density. A method for manufacturing a semiconductor device, wherein a semiconductor device is manufactured by growing a nitride III-V compound semiconductor layer forming an element structure on a main surface of a group III-V compound semiconductor substrate,
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

The fifth invention of the present invention is:
A nitride system in which a plurality of second regions having a second average defect density higher than the first average defect density are regularly arranged in a first region made of a crystal having a first average defect density. A method for manufacturing a semiconductor device, wherein a semiconductor device is manufactured by growing a nitride III-V compound semiconductor layer forming an element structure on a main surface of a group III-V compound semiconductor substrate,
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

The sixth invention of the present invention is:
An element structure on a main surface of a nitride III-V compound semiconductor substrate in which a plurality of second regions having lower crystallinity than the first region are regularly arranged in the first region made of crystal A method for manufacturing a semiconductor device, wherein a semiconductor device is manufactured by growing a nitride III-V compound semiconductor layer forming
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

  In the fourth to sixth aspects of the present invention, the semiconductor element includes a light emitting element such as a light emitting diode and a semiconductor laser, a light receiving element, a field effect transistor (FET) such as a high electron mobility transistor, and a heterogeneous element. An electron transit device such as a junction bipolar transistor (HBT) is included (the same applies hereinafter).

  In the fourth to sixth inventions of the present invention, the active region of the semiconductor element is preferably 1 μm or more from the second region, more preferably, in order to prevent adverse effects due to the second region having a high average dislocation density. Is 10 μm or more, more preferably 100 μm or more. When the third region exists, it is most preferable that the active region of the semiconductor element does not include the second region and the third region. Here, the active region means a light emitting region in a semiconductor light emitting device, a light receiving region in a semiconductor light receiving device, and a region in which electrons travel in an electron traveling device (the same applies hereinafter).

The seventh invention of the present invention is:
A semiconductor substrate in which a plurality of second regions having a second average dislocation density higher than the first average dislocation density are regularly arranged in a first region made of a crystal having a first average dislocation density. A method of manufacturing a semiconductor light emitting device, wherein a semiconductor light emitting device is manufactured by growing a semiconductor layer forming a light emitting device structure on a main surface,
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The eighth invention of the present invention is:
A semiconductor substrate in which a plurality of second regions having a second average defect density higher than the first average defect density are regularly arranged in a first region made of a crystal having a first average defect density. A method of manufacturing a semiconductor light emitting device, wherein a semiconductor light emitting device is manufactured by growing a semiconductor layer forming a light emitting device structure on a main surface,
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The ninth aspect of the present invention is:
A semiconductor layer for forming a light emitting element structure is grown on a main surface of a semiconductor substrate in which a plurality of second regions having lower crystallinity than the first region are regularly arranged in the first region made of crystal A method for manufacturing a semiconductor light emitting device, wherein the semiconductor light emitting device is manufactured by:
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The tenth aspect of the present invention is:
A semiconductor substrate in which a plurality of second regions having a second average dislocation density higher than the first average dislocation density are regularly arranged in a first region made of a crystal having a first average dislocation density. A method of manufacturing a semiconductor element, wherein a semiconductor element is manufactured by growing a semiconductor layer forming an element structure on a main surface,
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The eleventh aspect of the present invention is:
A semiconductor substrate in which a plurality of second regions having a second average defect density higher than the first average defect density are regularly arranged in a first region made of a crystal having a first average defect density. A method of manufacturing a semiconductor element, wherein a semiconductor element is manufactured by growing a semiconductor layer forming an element structure on a main surface,
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The twelfth aspect of the present invention is
A semiconductor layer forming an element structure is grown on a main surface of a semiconductor substrate in which a plurality of second regions having lower crystallinity than the first region are regularly arranged in the first region made of crystals. A method for manufacturing a semiconductor element by manufacturing a semiconductor element,
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

  In the tenth to twelfth inventions of the present invention, the material of the semiconductor substrate or semiconductor layer may be a nitride III-V compound semiconductor, a wurtzit structure, or more generally a hexagonal crystal system. Other semiconductors having a crystal structure, such as ZnO, α-ZnS, α-CdS, α-CdSe, and the like, and various semiconductors having other crystal structures may be used.

The thirteenth invention of the present invention is
A main substrate in which a plurality of second regions having a second average dislocation density higher than the first average dislocation density are regularly arranged in a first region made of a crystal having a first average dislocation density. A device manufacturing method for manufacturing a device by growing a layer forming a device structure on a surface,
The layer is not directly in contact with the second region on the main surface of the substrate.

The fourteenth aspect of the present invention is:
A main substrate in which a plurality of second regions having a second average defect density higher than the first average defect density are regularly arranged in a first region made of a crystal having a first average defect density. A device manufacturing method for manufacturing a device by growing a layer forming a device structure on a surface,
The layer is not directly in contact with the second region on the main surface of the substrate.

The fifteenth aspect of the present invention is:
By growing a layer forming an element structure on the main surface of the substrate in which a plurality of second regions having lower crystallinity than the first region are regularly arranged in the first region made of crystals An element manufacturing method for manufacturing an element,
The layer is not directly in contact with the second region on the main surface of the substrate.

  In the thirteenth to fifteenth aspects of the present invention, the element is a semiconductor element (light emitting element, light receiving element, electron transit element, etc.), piezoelectric element, pyroelectric element, optical element (secondary using a nonlinear optical crystal). Harmonic generating elements), dielectric elements (including ferroelectric elements), superconducting elements, and the like. In this case, as the material of the substrate or layer, various semiconductors as described above can be used in the semiconductor element, and in the piezoelectric element, pyroelectric element, optical element, dielectric element, superconducting element, etc., for example, oxide Various materials can be used. There are many oxide materials such as those disclosed in Journal of the Society of Japan Vol. 103, No. 11 (1995) pp. 1099-1111 and Materials Science and Engineering B41 (1996) 166-173. There is.

The sixteenth invention of the present invention is
A plurality of second regions having a second average dislocation density higher than the first average dislocation density in the first region made of a crystal having the first average dislocation density at a first interval in the first direction. On the main surface of the nitride-based III-V group compound semiconductor substrate regularly arranged and regularly arranged in a second direction orthogonal to the first direction at a second interval smaller than the first interval A method for manufacturing a semiconductor light emitting device, wherein a semiconductor light emitting device is manufactured by growing a nitride III-V compound semiconductor layer forming a light emitting device structure on the substrate,
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

The seventeenth aspect of the present invention is:
A plurality of second regions having a second average defect density higher than the first average defect density in the first region made of a crystal having the first average defect density at a first interval in the first direction. On the main surface of the nitride-based III-V group compound semiconductor substrate regularly arranged and regularly arranged in a second direction orthogonal to the first direction at a second interval smaller than the first interval A method for manufacturing a semiconductor light emitting device, wherein a semiconductor light emitting device is manufactured by growing a nitride III-V compound semiconductor layer forming a light emitting device structure on the substrate,
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

According to an eighteenth aspect of the present invention,
A plurality of second regions having poorer crystallinity than the first region are regularly arranged in the first direction at a first interval in the first region made of crystals, and are perpendicular to the first direction. Nitride III-V group forming a light emitting device structure on a main surface of a nitride III-V compound semiconductor substrate regularly arranged in a direction 2 with a second interval smaller than the first interval A method of manufacturing a semiconductor light emitting device, wherein a semiconductor light emitting device is manufactured by growing a compound semiconductor layer,
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

The nineteenth invention of the present invention is
A plurality of second regions extending in a straight line having a second average dislocation density higher than the first average dislocation density in the first region made of a crystal having the first average dislocation density are arranged in parallel with each other. A semiconductor light emitting device is manufactured by growing a nitride III-V compound semiconductor layer that forms a light emitting device structure on a main surface of a nitride-based III-V compound semiconductor substrate that is arranged in a regular manner. A method for manufacturing a semiconductor light emitting device, comprising:
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

The twentieth invention of the present invention is
A plurality of second regions extending in a straight line having a second average defect density higher than the first average defect density in the first region made of a crystal having the first average defect density are arranged in parallel with each other. A semiconductor light emitting device is manufactured by growing a nitride III-V compound semiconductor layer that forms a light emitting device structure on a main surface of a nitride-based III-V compound semiconductor substrate that is arranged in a regular manner. A method for manufacturing a semiconductor light emitting device, comprising:
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

The twenty-first aspect of the present invention is
A nitride-based III-V group compound in which a plurality of second regions extending in a straight line having poorer crystallinity than the first region are regularly arranged in parallel with each other in the first region made of crystals A method for manufacturing a semiconductor light emitting device, wherein a semiconductor light emitting device is manufactured by growing a nitride III-V compound semiconductor layer forming a light emitting device structure on a main surface of a semiconductor substrate,
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

According to a twenty-second aspect of the present invention,
A plurality of second regions having a second average dislocation density higher than the first average dislocation density in the first region made of a crystal having the first average dislocation density at a first interval in the first direction. On the main surface of the nitride-based III-V group compound semiconductor substrate regularly arranged and regularly arranged in a second direction orthogonal to the first direction at a second interval smaller than the first interval A method of manufacturing a semiconductor device, wherein a semiconductor device is manufactured by growing a nitride III-V compound semiconductor layer forming an element structure on the substrate,
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

The twenty-third aspect of the present invention provides
A plurality of second regions having a second average defect density higher than the first average defect density in the first region made of a crystal having the first average defect density at a first interval in the first direction. On the main surface of the nitride-based III-V group compound semiconductor substrate regularly arranged and regularly arranged in a second direction orthogonal to the first direction at a second interval smaller than the first interval A method of manufacturing a semiconductor device, wherein a semiconductor device is manufactured by growing a nitride III-V compound semiconductor layer forming an element structure on the substrate,
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

The twenty-fourth aspect of the present invention provides
A plurality of second regions having poorer crystallinity than the first region are regularly arranged in the first direction at a first interval in the first region made of crystals, and are perpendicular to the first direction. Nitride-based III-V compound forming an element structure on the main surface of a nitride-based III-V compound semiconductor substrate regularly arranged at a second interval smaller than the first interval in the direction 2 A method for manufacturing a semiconductor element, wherein a semiconductor element is manufactured by growing a semiconductor layer,
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

According to a twenty-fifth aspect of the present invention,
A plurality of second regions extending in a straight line having a second average dislocation density higher than the first average dislocation density in the first region made of a crystal having the first average dislocation density are arranged in parallel with each other. Semiconductor device is manufactured by growing a nitride III-V compound semiconductor layer forming an element structure on the main surface of a nitride III-V compound semiconductor substrate that is arranged in a regular manner A method for manufacturing an element, comprising:
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

According to a twenty-sixth aspect of the present invention,
A plurality of second regions extending in a straight line having a second average defect density higher than the first average defect density in the first region made of a crystal having the first average defect density are arranged in parallel with each other. Semiconductor device is manufactured by growing a nitride III-V compound semiconductor layer forming an element structure on the main surface of a nitride III-V compound semiconductor substrate that is arranged in a regular manner A method for manufacturing an element, comprising:
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

According to a twenty-seventh aspect of the present invention,
A nitride-based III-V group compound in which a plurality of second regions extending in a straight line having poorer crystallinity than the first region are regularly arranged in parallel with each other in the first region made of crystals A method for manufacturing a semiconductor device, wherein a semiconductor device is manufactured by growing a nitride III-V compound semiconductor layer forming an element structure on a main surface of a semiconductor substrate,
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

According to a twenty-eighth aspect of the present invention,
A plurality of second regions having a second average dislocation density higher than the first average dislocation density in the first region made of a crystal having the first average dislocation density at a first interval in the first direction. A semiconductor in which a light emitting element structure is formed on a main surface of a semiconductor substrate that is regularly arranged and regularly arranged at a second interval smaller than the first interval in a second direction orthogonal to the first direction A method of manufacturing a semiconductor light emitting device, wherein a semiconductor light emitting device is manufactured by growing a layer,
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The 29th aspect of the present invention is:
A plurality of second regions having a second average defect density higher than the first average defect density in the first region made of a crystal having the first average defect density at a first interval in the first direction. A semiconductor in which a light emitting element structure is formed on a main surface of a semiconductor substrate that is regularly arranged and regularly arranged at a second interval smaller than the first interval in a second direction orthogonal to the first direction A method of manufacturing a semiconductor light emitting device, wherein a semiconductor light emitting device is manufactured by growing a layer,
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The 30th invention of the present invention is
A plurality of second regions having poorer crystallinity than the first region are regularly arranged in the first direction at a first interval in the first region made of crystals, and are perpendicular to the first direction. A semiconductor light emitting device is manufactured by growing a semiconductor layer forming a light emitting device structure on a main surface of a semiconductor substrate regularly arranged at a second interval smaller than the first interval in the direction of 2. A method for manufacturing a semiconductor light emitting device, comprising:
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The thirty-first aspect of the present invention is
A plurality of second regions extending in a straight line having a second average dislocation density higher than the first average dislocation density in the first region made of a crystal having the first average dislocation density are arranged in parallel with each other. A method of manufacturing a semiconductor light emitting device, wherein a semiconductor light emitting device is manufactured by growing a semiconductor layer forming a light emitting device structure on a main surface of a semiconductor substrate that is arranged in a regular manner,
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The thirty-second invention of the present invention is
A plurality of second regions extending in a straight line having a second average defect density higher than the first average defect density in the first region made of a crystal having the first average defect density are arranged in parallel with each other. A method of manufacturing a semiconductor light emitting device, wherein a semiconductor light emitting device is manufactured by growing a semiconductor layer forming a light emitting device structure on a main surface of a semiconductor substrate that is arranged in a regular manner,
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The thirty-third aspect of the present invention
Light is emitted on the main surface of the semiconductor substrate in which a plurality of second regions extending in a straight line having poorer crystallinity than the first region are regularly arranged in parallel in the first region made of crystals A method of manufacturing a semiconductor light emitting device, wherein a semiconductor light emitting device is manufactured by growing a semiconductor layer forming an element structure,
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The 34th invention of the present invention is
A plurality of second regions having a second average dislocation density higher than the first average dislocation density in the first region made of a crystal having the first average dislocation density at a first interval in the first direction. A semiconductor layer that is regularly arranged and forms an element structure on a main surface of a semiconductor substrate that is regularly arranged at a second interval smaller than the first interval in a second direction orthogonal to the first direction A method of manufacturing a semiconductor device, wherein a semiconductor device is manufactured by growing
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The 35th invention of the present invention is
A plurality of second regions having a second average defect density higher than the first average defect density in the first region made of a crystal having the first average defect density at a first interval in the first direction. A semiconductor layer that is regularly arranged and forms an element structure on a main surface of a semiconductor substrate that is regularly arranged at a second interval smaller than the first interval in a second direction orthogonal to the first direction A method of manufacturing a semiconductor device, wherein a semiconductor device is manufactured by growing
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The thirty-sixth aspect of the present invention provides
A plurality of second regions having poorer crystallinity than the first region are regularly arranged in the first direction at a first interval in the first region made of crystals, and are perpendicular to the first direction. A semiconductor device manufactured by growing a semiconductor layer forming an element structure on a main surface of a semiconductor substrate regularly arranged at a second interval smaller than the first interval in the direction of 2. A method for manufacturing an element, comprising:
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The thirty-seventh aspect of the present invention provides
A plurality of second regions extending in a straight line having a second average dislocation density higher than the first average dislocation density in the first region made of a crystal having the first average dislocation density are arranged in parallel with each other. A method for manufacturing a semiconductor element, wherein a semiconductor element is manufactured by growing a semiconductor layer that forms an element structure on a main surface of a semiconductor substrate that is arranged in order,
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The thirty-eighth aspect of the present invention is
A plurality of second regions extending in a straight line having a second average defect density higher than the first average defect density in the first region made of a crystal having the first average defect density are arranged in parallel with each other. A method for manufacturing a semiconductor element, wherein a semiconductor element is manufactured by growing a semiconductor layer that forms an element structure on a main surface of a semiconductor substrate that is arranged in order,
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The 39th invention of this invention is
A plurality of second regions extending in a straight line having poorer crystallinity than the first region in the first region made of crystals are arranged on the main surface of the semiconductor substrate regularly arranged in parallel to each other. A method for manufacturing a semiconductor element, wherein a semiconductor element is manufactured by growing a semiconductor layer forming a structure,
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The 40th invention of this invention is
A plurality of second regions having a second average dislocation density higher than the first average dislocation density in the first region made of a crystal having the first average dislocation density at a first interval in the first direction. A layer forming an element structure is grown on the main surface of the substrate regularly arranged and regularly arranged at a second interval smaller than the first interval in a second direction orthogonal to the first direction. A method for manufacturing an element by manufacturing an element,
The layer is not directly in contact with the second region on the main surface of the substrate.

The forty-first aspect of the present invention is
A plurality of second regions having a second average defect density higher than the first average defect density in the first region made of a crystal having the first average defect density at a first interval in the first direction. A layer forming an element structure is grown on the main surface of the substrate regularly arranged and regularly arranged at a second interval smaller than the first interval in a second direction orthogonal to the first direction. A method for manufacturing an element by manufacturing an element,
The layer is not directly in contact with the second region on the main surface of the substrate.

The forty-second invention of this invention
A plurality of second regions having poorer crystallinity than the first region are regularly arranged in the first direction at a first interval in the first region made of crystals, and are perpendicular to the first direction. A device manufacturing method for manufacturing a device by growing a layer forming a device structure on a main surface of a substrate regularly arranged at a second interval smaller than the first interval in the direction of 2. Because
The layer is not directly in contact with the second region on the main surface of the substrate.

The 43rd invention of the present invention is
A plurality of second regions extending in a straight line having a second average dislocation density higher than the first average dislocation density in the first region made of a crystal having the first average dislocation density are arranged in parallel with each other. A device manufacturing method for manufacturing a device by growing a layer for forming a device structure on a main surface of a substrate that is arranged in a mechanical manner,
The layer is not directly in contact with the second region on the main surface of the substrate.

The 44th aspect of the present invention is
A plurality of second regions extending in a straight line having a second average defect density higher than the first average defect density in the first region made of a crystal having the first average defect density are arranged in parallel with each other. A device manufacturing method for manufacturing a device by growing a layer for forming a device structure on a main surface of a substrate that is arranged in a mechanical manner,
The layer is not directly in contact with the second region on the main surface of the substrate.

The 45th aspect of the present invention provides
An element structure on a main surface of a substrate in which a plurality of second regions extending in a straight line having poorer crystallinity than the first region are regularly arranged in parallel with each other in the first region made of crystal A device manufacturing method for manufacturing a device by growing a layer for forming
The layer is not directly in contact with the second region on the main surface of the substrate.

  In the sixteenth to forty-fifth aspects of the present invention, the interval between the second regions in the first direction (first interval) or the interval between the second regions extending linearly is the first region of the present invention. This is the same as the interval of the second areas or the arrangement interval of the second areas described in relation to the invention. In addition, the interval between the second regions in the first direction (first interval) or the interval between the second regions extending linearly is typically 50 μm or more. This is the same as the interval of the second regions or the arrangement interval of the second regions described in relation to the first invention. In the sixteenth to eighteenth, twenty-second to twenty-fourth, twenty-eighth to thirty-fourth, thirty-fourth to thirty-sixth, and forty-fourth to forty-second inventions of the present invention, the interval between the second regions in the second direction is basically In general, it can be freely selected within a range smaller than the first interval, and is generally 10 μm or more and 1000 μm or less, typically 20 μm or more and 200 μm or less, depending on the size of the second region. It is. Furthermore, the region that will eventually become a chip by scribing the substrate (hereinafter referred to as “element region”) typically has a second region extending in a row or a straight line of the second region in the second direction. This area is substantially not included in seven or more. Here, the upper limit of the number of second regions in the second direction or the number of second regions extending in a straight line is set to seven because the number of rows or straight lines in the second direction in the second direction is seven. Depending on the distance between the second regions extending in the shape, about 7 may be included in the element region in relation to the chip size of the element. In general, the number of second regions extending in a row or in a straight line in the second direction in the second direction is typically 3 or less in a semiconductor light emitting device having a small chip size.

  In the sixteenth to forty-fifth aspects of the present invention, the matters other than those described above are valid in relation to the first to fifteenth aspects of the present invention unless they are contrary to the nature thereof.

The 46th aspect of the present invention is
A nitride-based III-V group compound semiconductor substrate having a second region having a second average dislocation density higher than the first average dislocation density in a first region made of a crystal having a first average dislocation density. A method for growing a nitride III-V compound semiconductor layer, wherein a nitride III-V compound semiconductor layer is grown on a main surface,
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

The 47th aspect of the present invention is
A nitride-based III-V group compound semiconductor substrate having a second region having a second average defect density higher than the first average defect density in a first region made of a crystal having a first average defect density A method for growing a nitride III-V compound semiconductor layer, wherein a nitride III-V compound semiconductor layer is grown on a main surface,
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

The 48th aspect of the present invention is
Nitride-based III-V compound semiconductor layer on the main surface of a nitride-based III-V compound semiconductor substrate having a second region having a crystallinity worse than that of the first region in the first region made of crystal A method for growing a nitride-based III-V compound semiconductor layer, wherein
The nitride-based III-V compound semiconductor layer is not directly in contact with the second region on the main surface of the nitride-based III-V compound semiconductor substrate.

The 49th aspect of the present invention is
A semiconductor layer is grown on a main surface of a semiconductor substrate having a second region having a second average dislocation density higher than the first average dislocation density in a first region made of a crystal having a first average dislocation density. A method for growing a semiconductor layer, comprising:
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The 50th aspect of the present invention is
A semiconductor layer is grown on a main surface of a semiconductor substrate having a second region having a second average defect density higher than the first average defect density in a first region made of a crystal having a first average defect density. A method for growing a semiconductor layer, comprising:
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The fifty-first aspect of the present invention is
A method for growing a semiconductor layer, wherein a semiconductor layer is grown on a main surface of a substrate having a second region having lower crystallinity than the first region in the first region made of crystal,
The semiconductor layer is not directly in contact with the second region on the main surface of the semiconductor substrate.

The 52nd aspect of the present invention is
A layer is grown on a major surface of a substrate having a second region having a second average dislocation density higher than the first average dislocation density in a first region made of a crystal having a first average dislocation density. A layer growth method,
The layer is not directly in contact with the second region on the main surface of the substrate.

The 53rd invention of the present invention is
A layer is grown on a major surface of a substrate having a second region having a second average defect density higher than the first average defect density in a first region comprising a crystal having a first average defect density. A layer growth method,
The layer is not directly in contact with the second region on the main surface of the substrate.

According to a 54th aspect of the present invention,
A method for growing a layer in which a layer is grown on a main surface of a substrate having a second region having a lower crystallinity than the first region in the first region composed of crystals,
The layer is not directly in contact with the second region on the main surface of the substrate.

In the forty-sixth to fifty-fourth aspects of the present invention, the nitride-based III-V compound semiconductor substrate, the nitride-based III-V compound semiconductor layer, the semiconductor substrate, the semiconductor layer, the substrate, and the material of the layer are described in the present invention. This is the same as described in relation to the first to fifteenth inventions.
In the present invention configured as described above, a nitride III-V compound semiconductor layer, a semiconductor layer, or a layer made of various materials forming the light emitting element structure or the element structure is a nitride III- Do not directly contact the V group compound semiconductor substrate, or the semiconductor substrate or the main surface of the substrate with the second region having a higher average dislocation density, higher average defect density, or poor crystallinity than the first region. Therefore, the light-emitting element structure or the nitride-based III-V compound semiconductor layer forming the element structure, or the semiconductor layer, or a layer made of various materials can be prevented from being adversely affected by the second region. Can do.

  According to the present invention, a nitride III-V compound semiconductor layer, a semiconductor layer, or a layer made of various materials forming a light emitting element structure or an element structure is a nitride III-V compound semiconductor substrate, Alternatively, on the semiconductor substrate or on the main surface of the substrate, the average dislocation density is higher than that of the first region, or the average defect density is high, or the second region having poor crystallinity is not directly contacted. The element structure or the nitride III-V compound semiconductor layer forming the element structure, the semiconductor layer, or the layer made of various materials can be prevented from being adversely affected by the second region. For this reason, semiconductor light-emitting elements with good characteristics such as light emission characteristics and high reliability and long life, or various semiconductor elements with good characteristics and high reliability and long life, or various elements with good characteristics and high reliability and long life Can be realized.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings of the embodiments, the same or corresponding parts are denoted by the same reference numerals.
1 and 2 show a GaN substrate 1 used in the first embodiment of the present invention, FIG. 1A is a perspective view, FIG. 1B is a cross-sectional view of a region B in the closest direction, and FIG. 2 is a plan view. The GaN substrate 1 is n-type and has a (0001) plane (C plane) orientation. However, the GaN substrate 1 may have an R-plane, A-plane, or M-plane orientation. In the GaN substrate 1, regions B made of crystals having a high average dislocation density are periodically arranged in a hexagonal lattice pattern in regions A made of crystals having a low average dislocation density. Here, the region B generally has an indeterminate polygonal column shape, but in FIG. 1A, it is simplified to have a cylindrical shape (the same applies hereinafter). In this case, the straight line connecting the closest regions B coincides with the <1-100> direction of GaN and the equivalent direction. However, the straight line connecting the closest regions B may coincide with the <11-20> direction of GaN and the equivalent direction. Region B penetrates GaN substrate 1. The thickness of the GaN substrate 1 is, for example, 200 to 600 μm. Note that the broken lines in FIG. 2 are merely for showing the relative positional relationship of the region B, and are not actual (physically meaningful) lines (the same applies hereinafter).

The arrangement period of the region B (the distance between the centers of the closest regions B) is, for example, 400 μm, and the diameter thereof is, for example, 20 μm. Further, the average dislocation density in the region A is 2 × 10 ⁶ cm ⁻² , for example, and the average dislocation density in the region B is 1 × 10 ⁸ cm ⁻² , for example. An example of the distribution of dislocation density in the radial direction from the center of region B is shown in FIG.
The GaN substrate 1 can be manufactured, for example, as follows using a crystal growth technique.
The basic crystal growth mechanism used in the manufacture of the GaN substrate 1 is to grow with a sloped facet plane, and to maintain the facet slope to grow, dislocations propagate, and gather at a predetermined position. It is something to be made. A region grown by this facet surface becomes a low-density defect region due to dislocation movement. At the lower part of the facet slope, growth is performed with a high density defect region with a clear boundary, and dislocations gather at the boundary of the high density defect region or inside, and disappear or accumulate there. To do.
The shape of the facet surface varies depending on the shape of the high-density defect region. When the defect area is dot-like, the facet surface is surrounded with the dot as the bottom, and a pit composed of the facet surface is formed. Further, when the defect region has a stripe shape, a triangular prism-shaped facet surface is formed with the stripe as a valley bottom, facet surface slopes on both sides thereof, and tilted sideways.
Thereafter, the surface of the growth layer is ground and polished, so that the surface can be flattened and used as a substrate.
In addition, the high-density defect area may have several states. For example, it may be made of polycrystal. Moreover, although it is a single crystal, it may be slightly inclined with respect to the surrounding low density defect area | region. Further, the C axis may be inverted with respect to the surrounding low density defect region. Thus, this high density defect region has a clear boundary and is distinguished from the surroundings.
By growing with this high-density defect region, the growth can proceed while maintaining the facet surface without embedding the surrounding facet surface.
This high-density defect region can be generated by previously forming seeds in a place where the high-density defect region is formed when GaN is crystal-grown on the base substrate. As the seed, an amorphous or polycrystalline layer is formed. Then, by growing GaN, a high-density defect region can be formed in that kind of region.
A specific method for manufacturing the GaN substrate 1 is as follows. First, a base substrate is prepared. Various substrates can be used as the base substrate, and a general sapphire substrate may be used, but it is preferable to use a GaAs substrate that can be easily removed in consideration of removal in a later step. Then, a seed made of, for example, a SiO ₂ film is formed on the base substrate. This type of shape can be, for example, a dot or stripe. This species is regular and can be formed in large numbers. More specifically, in this case, the seed is formed in an arrangement corresponding to the arrangement of the region B shown in FIG. Thereafter, GaN is grown in a thick film by, for example, hydride vapor phase epitaxy (HVPE). After the growth, a facet surface corresponding to the pattern shape of the seed is formed on the surface of the GaN thick film layer. In the case where the seed is a dot-like pattern as in the first embodiment, pits composed of facet surfaces are regularly formed. On the other hand, when the seed is a stripe pattern, a prismatic facet surface is formed.
Thereafter, the base substrate is removed, and the GaN thick film layer is ground and polished to flatten the surface. Thereby, the GaN substrate 1 can be manufactured. Here, the thickness of the GaN substrate 1 can be freely set.
The GaN substrate 1 manufactured in this manner has a C-plane as a main surface, and a substrate in which high-density defect regions in a dot shape (or stripe shape) of a predetermined size, that is, regions B are regularly formed. It has become. The single crystal region other than the region B, that is, the region A has a lower dislocation density than the region B.

  FIG. 4 schematically shows dislocations existing in the region B of the GaN substrate 1 with broken lines. When a GaN-based semiconductor layer L is grown on such a GaN substrate 1 as shown in FIG. 5, dislocation propagates from the region B of the underlying GaN substrate 1 to the GaN-based semiconductor layer L and the quality is deteriorated. .

  Therefore, in the first embodiment, as shown in FIG. 6, the upper portion of the region B is removed by the depth D by etching. The depth D is, for example, 1 to 10 μm. By doing so, the surface of the region B can be sufficiently separated from the main surface of the GaN substrate 1. Then, as shown in FIG. 7, a GaN-based semiconductor layer L that forms an element structure is grown on the GaN substrate 1 by a metal organic chemical vapor deposition (MOCVD) method or the like. Dislocations propagate from the region B to the portion of the GaN-based semiconductor layer L grown on the region B, but the region through which this dislocation propagates is limited to a very small portion. It is possible to prevent the GaN-based semiconductor layer L grown in this way from being adversely affected by the region.

  The etching of the region B can be performed as follows. In general, nitride-based III-V compound semiconductors such as GaN are chemically stable, and wet etching is not possible near room temperature except for high temperatures such as strong alkalis such as sodium hydroxide and acids such as strong hydrochloric acid and phosphoric acid. Does not happen. However, in the GaN substrate 1, the region B has a much higher dislocation density, more generally a defect density, than the region A. In the region B where the defect density is high, the bonding state of the atoms constituting the crystal is incomplete compared to the region A, and the etching rate is faster than the region A close to the complete crystal. Can be etched. This etching may be performed by masking the surface of the region A with a resist or the like, but only the region B can be selectively etched by etching the entire surface of the GaN substrate 1. In order to increase the etching rate, etching may be performed by increasing the temperature of the etchant. As the etching solution, for example, potassium hydroxide (KOH) can be used as the alkaline solution, and phosphoric acid can be used as the acid. To give a specific example of the etching method, the KOH solution placed in the etching tank is heated and held at 75 ° C., the GaN substrate 1 is immersed in it for 10 minutes, and after the etching is completed, the GaN substrate 1 is taken out and washed with pure water. Drying is performed by blowing dry nitrogen. By this etching, the region B can be removed to a depth of about 5 μm. Here, for the purpose of preventing the back surface of the GaN substrate 1 from being etched and causing surface roughness during this etching, for example, a Ti film having a thickness of 20 nm and a thickness of 300 nm are formed on the back surface of the GaN substrate 1 as necessary. A Ti / Pt film in which the Pt films are sequentially stacked may be formed by a vacuum deposition method or the like to form a protective film, and then etching may be performed. The Ti / Pt film can be removed by etching with aqua regia, for example.

  The etching of the region B may be performed by dry etching such as reactive ion etching (RIE) in addition to the above-described wet etching, and is heated and held at a temperature of 800 ° C. or higher for a certain time in a hydrogen atmosphere or an ammonia atmosphere. You may carry out by the thermochemical etching by.

  Next, an example of a specific manufacturing process of a GaN semiconductor laser using the GaN substrate 1 shown in FIG. 6 will be described. Here, a GaN-based semiconductor laser having a ridge structure and a SCH (Separate Confinement Heterostructure) structure will be described.

That is, as shown in FIG. 8, after the surface of the GaN substrate 1 is first cleaned by thermal cleaning or the like, the n-type GaN buffer layer 5, the n-type AlGaN cladding layer 6, the n-type GaN are formed thereon by MOCVD. optical waveguide layer 7, undoped _{Ga 1-x in x N /} Ga 1-y in y N active layer 8 of the multi-quantum well structure, undoped InGaN deterioration preventive layer 9, p-type AlGaN cap layer 10, p-type GaN optical guide The layer 11, the p-type AlGaN cladding layer 12, and the p-type GaN contact layer 13 are sequentially epitaxially grown.

Here, the n-type GaN buffer layer 5 has a thickness of, for example, 0.05 μm and is doped with, for example, Si as an n-type impurity. The n-type AlGaN cladding layer 6 has a thickness of, for example, 1.0 μm, is doped with, for example, Si as an n-type impurity, and has an Al composition of, for example, 0.08. The n-type GaN optical waveguide layer 7 has a thickness of, for example, 0.1 μm and is doped with, for example, Si as an n-type impurity. The active layer 8 of the undoped In _x Ga _{1 -x} N / In _y Ga _{1 -y} N multiple quantum well structure has, for example, a thickness of In _x Ga _{1 -x} N layer as a well layer of 3.5 nm and x = The thickness of the In _y Ga _1-y N layer as the barrier layer is 7 nm, y = 0.02, and the number of wells is 3.

The undoped InGaN degradation preventing layer 9 has a graded structure in which the In composition gradually monotonously decreases from the surface in contact with the active layer 8 toward the surface in contact with the p-type AlGaN cap layer 9. The In composition on the surface in contact with the In layer is the same as the In composition y of the In _y Ga _1-y N layer as the barrier layer of the active layer 8, and the In composition on the surface in contact with the p-type AlGaN cap layer 10 is 0. The thickness of the undoped InGaN deterioration preventing layer 9 is, for example, 20 nm.

  The p-type AlGaN cap layer 10 has a thickness of 10 nm, for example, and is doped with, for example, magnesium (Mg) as a p-type impurity. The p-type AlGaN cap layer 10 has an Al composition of 0.2, for example. The p-type AlGaN cap layer 10 prevents the In from detachment from the active layer 8 during the growth of the p-type GaN optical waveguide layer 11, the p-type AlGaN cladding layer 12, and the p-type GaN contact layer 13, and deteriorates. This is to prevent the overflow of carriers (electrons) from the active layer 8. The p-type GaN optical waveguide layer 11 has a thickness of, for example, 0.1 μm and is doped with, for example, Mg as a p-type impurity. The p-type AlGaN cladding layer 12 has a thickness of, for example, 0.5 μm, is doped with, for example, Mg as a p-type impurity, and has an Al composition of, for example, 0.08. The p-type GaN contact layer 13 has a thickness of 0.1 μm, for example, and is doped with, for example, Mg as a p-type impurity.

Further, the n-type GaN buffer layer 5, the n-type AlGaN cladding layer 6, the n-type GaN optical waveguide layer 7, the p-type AlGaN cap layer 10, the p-type GaN optical waveguide layer 11, and the p-type AlGaN cladding, which are layers not containing In. The growth temperature of the layer 12 and the p-type GaN contact layer 13 is, for example, about 1000 ° C., and the growth of the active layer 8 having a Ga _1-x In _x N / Ga _1-y In _y N multiple quantum well structure, which is a layer containing In. The temperature is, for example, 700 to 800 ° C., for example, 730 ° C. The growth temperature of the undoped InGaN degradation preventing layer 9 is set to, for example, 730 ° C. at the start of growth, similarly to the growth temperature of the active layer 8, and then increased, for example, linearly, and the p-type AlGaN cap layer 10 is grown at the end of growth. The temperature is set to 835 ° C., for example.

The growth raw materials of these GaN-based semiconductor layers are, for example, trimethylgallium ((CH ₃ ) ₃ Ga, TMG) as a Ga raw material, trimethylaluminum ((CH ₃ ) ₃ Al, TMA) as an Al raw material, In As a raw material, trimethylindium ((CH ₃ ) ₃ In, TMI) is used, and as a raw material of N, NH ₃ is used. As the carrier gas, for example, H ₂ is used. As for the dopant, for example, monosilane (SiH ₄ ) is used as an n-type dopant, and bis = methylcyclopentadienylmagnesium ((CH ₃ C ₅ H ₄ ) ₂ Mg) or bis = cyclopentadienyl is used as a p-type dopant. Magnesium ((C ₅ H ₅ ) ₂ Mg) is used.

Next, the GaN substrate 1 on which the GaN-based semiconductor layer has been grown as described above is taken out from the MOCVD apparatus. Then, an SiO ₂ film (not shown) having a thickness of, for example, 0.1 μm is formed on the entire surface of the p-type GaN contact layer 13 by, for example, CVD, vacuum deposition, sputtering, or the like, and is then formed on the SiO ₂ film. A resist pattern (not shown) having a predetermined shape corresponding to the shape of the ridge portion is formed by lithography, and using this resist pattern as a mask, for example, wet etching using a hydrofluoric acid-based etching solution, or CF ₄ or CHF ₃ The SiO ₂ film is etched by the RIE method using an etching gas containing fluorine such as to have a shape corresponding to the ridge portion.

Next, etching is performed to a predetermined depth in the thickness direction of the p-type AlGaN cladding layer 12 by the RIE method using this SiO ₂ film as a mask, thereby extending in the <1-100> direction as shown in FIG. The ridge 14 to be formed is formed. The width of the ridge 14 is 3 μm, for example. As this RIE etching gas, for example, a chlorine-based gas is used.

Next, after the SiO ₂ film used as an etching mask is removed by etching, an insulating film 15 such as a SiO ₂ film having a thickness of 0.3 μm is formed on the entire surface of the substrate by, for example, CVD, vacuum deposition, sputtering, or the like. Form a film. This insulating film 15 is for electrical insulation and surface protection.

Next, a resist pattern (not shown) that covers the surface of the insulating film 15 in a region excluding the p-side electrode formation region is formed by lithography.
Next, the insulating film 15 is etched using this resist pattern as a mask to form an opening 15a.

  Next, for example, a Pd film, a Pt film, and an Au film are sequentially formed on the entire surface of the substrate by, for example, a vacuum deposition method with the resist pattern remaining, and then a resist pattern is formed on the Pd film and the Pt film formed thereon. And removed together with the Au film (lift-off). As a result, the p-side electrode 16 in contact with the p-type GaN contact layer 13 through the opening 15a of the insulating film 15 is formed. Here, the thicknesses of the Pd film, the Pt film, and the Au film constituting the p-side electrode 16 are, for example, 10 nm, 100 nm, and 300 nm, respectively. Next, the alloy process for making the p-side electrode 16 ohmic contact is performed.

  Next, for example, a Ti film, a Pt film, and an Au film are sequentially formed on the back surface of the GaN substrate 1 by, for example, a vacuum deposition method to form an n-side electrode 17 having a Ti / Pt / Au structure. Here, the thicknesses of the Ti film, Pt film, and Au film constituting the n-side electrode 17 are, for example, 10 nm, 50 nm, and 100 nm, respectively. Next, the alloy process for making the n side electrode 17 ohmic-contact is performed.

  Next, as shown in FIG. 10, scribing of the GaN substrate 1 on which the laser structure is formed as described above is performed by cleaving along the outline of the element region 2 (one section surrounded by a thick solid line). Then, the laser bar 4 is processed to form both resonator end faces. Next, after end face coating is performed on the end faces of these resonators, scribing of the laser bar 4 is performed again by cleavage or the like to form chips.

  In FIG. 10, a gray rectangle represents one GaN-based semiconductor laser, and a straight line drawn in the vicinity of the center is the laser stripe 3, which corresponds to the position of the light emitting region. Further, a rectangle drawn by a broken line connecting them represents the laser bar 4, and the long side of the laser bar 4 corresponds to the end face of the resonator.

  In the example shown in FIG. 10, the size of the GaN-based semiconductor laser is, for example, 600 μm × 346 μm, the horizontal direction (long side direction) is along a straight line connecting the regions B, and the vertical direction (short side direction) is the region B. Each substrate is scribed along a straight line that does not pass to separate the GaN-based semiconductor lasers of that size.

In this case, since the region B exists only at the end face portion of the long side of each GaN-based semiconductor laser, the element design is made so that the laser stripe 3 is positioned in the vicinity of the straight line connecting the midpoints of the short sides. By doing so, it is possible to avoid the influence of the region B from reaching the light emitting region.
The resonator mirror is formed on the end face by scribing the substrate along the vertical straight line in FIG. 10 by cleaving or the like, but the straight line does not pass through the region B. Will not be affected. Therefore, it is possible to obtain a GaN-based semiconductor laser with good light emission characteristics and high reliability.
As a result, as shown in FIG. 11, a GaN-based semiconductor laser having the target ridge structure and SCH structure is manufactured.

  As described above, according to the first embodiment, a region of the GaN substrate 1 in which the regions B having a high average dislocation density are periodically arranged in a hexagonal lattice pattern in the regions A having a low average dislocation density. Since the upper part of B is removed by etching and the surface of region B is separated from the main surface of GaN substrate 1, a GaN-based semiconductor layer forming a laser structure is grown on GaN substrate 1, so that the laser structure It is possible to prevent the GaN-based semiconductor layer used for forming the region B from being adversely affected. For this reason, it is possible to realize a GaN-based semiconductor laser having good light emission characteristics, high reliability, and long life.

  In addition, according to the first embodiment, the undoped InGaN deterioration preventing layer 9 is provided in contact with the active layer 8, and the p-type AlGaN cap layer 10 is provided in contact with the undoped InGaN deterioration preventing layer 9. Therefore, the undoped InGaN degradation preventing layer 9 can significantly relieve the stress generated in the active layer 8 by the p-type AlGaN cap layer 10, and Mg used as the p-type dopant of the p-type layer is added to the active layer 7. It is possible to effectively suppress diffusion.

Next explained is the second embodiment of the invention.
As shown in FIG. 12, in the second embodiment, the entire region B of the GaN substrate 1 is removed by etching, and the portion is completely hollowed out. Then, as shown in FIG. 13, a GaN-based semiconductor layer L is grown on the GaN substrate 1 by MOCVD or the like.
Since other than the above is the same as that of the first embodiment, the description is omitted.
According to the second embodiment, the same advantages as those of the first embodiment can be obtained.

Next explained is the third embodiment of the invention.
As shown in FIG. 14, in the third embodiment, the upper portion of the region B of the GaN substrate 1 is removed by etching as in the first embodiment. In this case, this etching is performed by dry etching such as RIE, for example. To do. Thereafter, utilizing the fact that the crystallinity of the region B is worse than the crystallinity of the region A, growth occurs on the region A, but growth does not occur on the region B. The semiconductor layer L is grown. As a result, the GaN-based semiconductor layer L can be grown only on the main surface of the GaN substrate 1, that is, the region A.
Since other than the above is the same as that of the first embodiment, the description is omitted.
According to the third embodiment, the same advantages as those of the first embodiment can be obtained.

Next explained is the fourth embodiment of the invention.
As shown in FIG. 15, in the fourth embodiment, the upper part of the region B of the GaN substrate 1 is removed by etching as in the first embodiment. Thereafter, by utilizing the fact that the crystallinity of the region B is worse than the crystallinity of the region A, the GaN-based semiconductor layer L is grown under the growth conditions such that the growth occurs on the region A but does not occur on the region B. Grow horizontally. As a result, the GaN-based semiconductor layer L grows laterally from the main surface of the GaN substrate 1, that is, on the region A, and associates above the region B, and finally the surface can be flattened. However, the GaN-based semiconductor layer L may not be associated and flattened.
Since other than the above is the same as that of the first embodiment, the description is omitted.
According to the fourth embodiment, the same advantages as those of the first embodiment can be obtained.

Next explained is the fifth embodiment of the invention.
As shown in FIG. 16, in the fifth embodiment, an insulating film 18 such as a SiO ₂ film is formed so as to completely cover the region B of the main surface of the GaN substrate 1. The insulating film 18 may have any shape as long as it can completely cover the region B. For example, the insulating film 18 may have a circular shape according to the shape of the region B, a quadrilateral including the region B, or other polygons. Furthermore, it is good also as stripe shape which completely covers the area | region B located in a line, and the area | region A of the part in between. Next, as shown in FIG. 17, a GaN-based semiconductor layer L is grown on the GaN substrate 1 by MOCVD or the like. At this time, since the insulating film 18 serves as a growth mask, the GaN-based semiconductor layer L grows only on the main surface of the GaN substrate 1 in a portion not covered with the insulating film 18.
Since other than the above is the same as that of the first embodiment, the description is omitted.
According to the fifth embodiment, the same advantages as those of the first embodiment can be obtained.

Next, a sixth embodiment of the present invention will be described.
As shown in FIG. 18, in the sixth embodiment, as in the fifth embodiment, an insulating film such as a SiO ₂ film so as to completely cover the region B of the main surface of the GaN substrate 1. 18 is formed. Next, through the process shown in FIGS. 18 and 19, a GaN-based semiconductor layer L is laterally grown on the GaN substrate 1 by ELO using MOCVD or the like. At this time, the GaN-based semiconductor layers L that grow laterally on the insulating film 18 are associated. However, the GaN-based semiconductor layer L may not be associated.
Since other than the above is the same as that of the first embodiment, the description is omitted.
According to the sixth embodiment, the same advantages as those of the first embodiment can be obtained.

Next explained is the seventh embodiment of the invention.
As shown in FIG. 20, in the seventh embodiment, the upper portion of the region B of the GaN substrate 1 is removed by etching as in the first embodiment. Next, an insulating film 18 such as a SiO ₂ film is formed on the entire surface of the GaN substrate 1 to fill the removed portion of the region B. Next, as shown in FIG. 21, the insulating film 18 is etched back by, for example, the RIE method, so that the insulating film 18 is left only in the removed portion of the region B. Thereafter, a GaN-based semiconductor layer L is grown on the GaN substrate 1 as in the fifth or sixth embodiment.
Since other than the above is the same as that of the first embodiment, the description is omitted.
According to the seventh embodiment, the same advantages as those of the first embodiment can be obtained.

Next, an eighth embodiment of the invention will be described.
As shown in FIG. 22, in the eighth embodiment, the upper part of the region B of the GaN substrate 1 is removed by etching as in the first embodiment. Next, an insulating film 18 such as a SiO ₂ film is formed on the entire surface of the GaN substrate 1. At this time, it is assumed that the thickness of the insulating film 18 is so small that the removed portion of the region B is not completely filled. Next, the insulating film 18 on the region A is removed by etching back the insulating film 18 by, for example, the RIE method. Thereafter, a GaN-based semiconductor layer L is grown on the GaN substrate 1 as in the fifth or sixth embodiment.
Since other than the above is the same as that of the first embodiment, the description is omitted.
According to the eighth embodiment, the same advantages as those of the first embodiment can be obtained.

Next, a ninth embodiment of the invention will be described.
As shown in FIG. 23, in the ninth embodiment, the upper part of the region B of the GaN substrate 1 is removed by etching as in the first embodiment. Next, an insulating film 18 such as a SiO ₂ film is formed on the entire surface of the GaN substrate 1 and the removed portion of the region B is filled, and then the insulating film 18 is patterned into the same shape as in the fifth embodiment by etching. . Thereafter, a GaN-based semiconductor layer L is grown on the GaN substrate 1 as in the fifth or sixth embodiment.
Since other than the above is the same as that of the first embodiment, the description is omitted.
According to the ninth embodiment, the same advantages as those of the first embodiment can be obtained.

Next explained is the tenth embodiment of the invention.
As shown in FIG. 24, in the tenth embodiment, the upper portion of the region B of the GaN substrate 1 is removed by etching as in the first embodiment. In this case, the etching depth is sufficiently large, for example, It is about several tens of μm. Next, as shown in FIG. 25, an insulating film 18 such as a SiO ₂ film is formed on the entire surface of the GaN substrate 1. At this time, since the removed portion of the region B is deep, the removed portion is not completely filled with the insulating film 18, and a cavity is formed inside. Next, the insulating film 18 on the region A is removed by etching back the insulating film 18 by, for example, the RIE method. Thereafter, a GaN-based semiconductor layer L is grown on the GaN substrate 1 as in the fifth or sixth embodiment.
Since other than the above is the same as that of the first embodiment, the description is omitted.
According to the tenth embodiment, the same advantages as those of the first embodiment can be obtained.

Next, an eleventh embodiment of the present invention will be described.
As shown in FIG. 27, in the eleventh embodiment, the regions B are periodically arranged in a hexagonal lattice pattern in the region A of the GaN substrate 1 as in the first embodiment. However, the first implementation is that a region C having an average dislocation density intermediate between the average dislocation density in region A and the average dislocation density in region B is formed as a transition region between region A and region B. Different from form. Specifically, the average dislocation density of the region A 2 × 10 ⁶ cm ^-2 or less, the average dislocation density of the regions B is 1 × 10 ⁸ cm ^-2 or more, the average dislocation density of the regions C is 1 × 10 ⁸ cm ^{- It} is smaller than ^{2 and} larger than 2 × 10 ⁶ cm ⁻² , for example, (1-2) × 10 ⁷ cm ⁻² . The arrangement period of the region B (the distance between the centers of the closest regions B) is, for example, 300 μm, and the diameter is, for example, 20 μm. Further, the diameter of the region C is, for example, 120 μm.

In the eleventh embodiment, the upper portion of the region B of the GaN substrate 1 is removed by etching in the first embodiment, whereas the upper portions of both the region B and the region C of the GaN substrate 1 are removed by etching. To do.
Since other than the above is the same as that of the first embodiment, the description is omitted.
According to the eleventh embodiment, the same advantages as those of the first embodiment can be obtained.

Next, a twelfth embodiment of the invention is described.
In the twelfth embodiment, the entire region B of the GaN substrate 1 is removed by etching in the second embodiment, whereas both the region B and the region C of the GaN substrate 1 are removed by etching. To do.
Since the other than the above is the same as in the first and eleventh embodiments, the description thereof is omitted.
According to the twelfth embodiment, the same advantages as those of the first embodiment can be obtained.

Next, a thirteenth embodiment of the invention is described.
In the thirteenth embodiment, the upper portion of the region B of the GaN substrate 1 is removed by etching in the third embodiment, whereas the upper portions of both the region B and the region C of the GaN substrate 1 are removed by etching. To do.
Since the other than the above is the same as in the first and eleventh embodiments, the description thereof is omitted.
According to the thirteenth embodiment, the same advantages as those of the first embodiment can be obtained.

Next, a fourteenth embodiment of the invention is described.
In the fourteenth embodiment, the upper portion of the region B of the GaN substrate 1 is removed by etching in the fourth embodiment, whereas the upper portions of both the region B and the region C of the GaN substrate 1 are removed by etching. To do.
Since the other than the above is the same as in the first and eleventh embodiments, the description thereof is omitted.
According to the fourteenth embodiment, the same advantages as those of the first embodiment can be obtained.

Next, a fifteenth embodiment of the invention is described.
In the fifteenth embodiment, the region B of the GaN substrate 1 is covered with the insulating film 18 in the fifth embodiment, whereas both the region B and the region C of the GaN substrate 1 are covered with the insulating film 18. .
Since the other than the above is the same as the first, fifth and eleventh embodiments, the description thereof will be omitted.
According to the fifteenth embodiment, the same advantages as those of the first embodiment can be obtained.

Next, a sixteenth embodiment of the invention is described.
In the sixteenth embodiment, the region B of the GaN substrate 1 is covered with the insulating film 18 in the sixth embodiment, whereas both the region B and the region C of the GaN substrate 1 are covered with the insulating film 18. .
Since the other than the above is the same as the first, fifth and eleventh embodiments, the description thereof will be omitted.
According to the sixteenth embodiment, the same advantages as those of the first embodiment can be obtained.

Next, a seventeenth embodiment of the invention is described.
In the seventeenth embodiment, the upper portion of the region B of the GaN substrate 1 is removed by etching in the seventh embodiment, whereas the upper portions of both the region B and the region C of the GaN substrate 1 are removed by etching. To do.
Since the other than the above is the same as the first, fifth and eleventh embodiments, the description thereof will be omitted.
According to the seventeenth embodiment, the same advantages as those of the first embodiment can be obtained.

Next, an eighteenth embodiment of the invention is described.
In the eighteenth embodiment, the upper portion of the region B of the GaN substrate 1 is removed by etching in the eighth embodiment, whereas the upper portions of both the region B and the region C of the GaN substrate 1 are removed by etching. To do.
Since the other than the above is the same as the first, fifth and eleventh embodiments, the description thereof will be omitted.
According to the eighteenth embodiment, the same advantages as those of the first embodiment can be obtained.

Next, a nineteenth embodiment of the present invention is described.
In the nineteenth embodiment, the upper portion of the region B of the GaN substrate 1 is removed by etching in the ninth embodiment, whereas the upper portions of both the region B and the region C of the GaN substrate 1 are removed by etching. To do.
Since the other than the above is the same as the first, fifth and eleventh embodiments, the description thereof will be omitted.
The nineteenth embodiment can provide the same advantages as those of the first embodiment.

Next, a twentieth embodiment of the invention is described.
In the twentieth embodiment, the upper portion of the region B of the GaN substrate 1 is removed by etching in the tenth embodiment, whereas the upper portions of both the region B and the region C of the GaN substrate 1 are removed by etching. To do.
Since the other than the above is the same as the first, fifth and eleventh embodiments, the description thereof will be omitted.
According to the twentieth embodiment, the same advantages as those of the first embodiment can be obtained.

Next, a twenty-first embodiment of the present invention will be described.
As shown in FIG. 28, in the twenty-first embodiment, unlike the first embodiment, the outline of the rectangular element region 2 is a straight line connecting the centers of the region B with the long side and the short side. Consists of. Also in this case, the position of the laser stripe 3 is on a line connecting the midpoints of the short sides of the element region 2. By doing so, it is possible to avoid the influence of the region B from reaching the light emitting region.

In the twenty-first embodiment, the first embodiment is that a resonator mirror is formed by scribing by cleavage along the contour line of the element region 2, which is a straight line connecting the centers of the regions B. It is different from the form.
Here, it is considered that the region B is more fragile than the region A because there are many dislocations. Therefore, when scribing is performed along a straight line connecting the regions B, the region B plays a role like a perforation, and the region A is also cleaved cleanly. At this time, the end surface of the region B is not necessarily flat because there are many dislocations, but the end surface of the region A in between is flat.

Flatness is required for the end face portion of the laser stripe 3, but with the arrangement as shown in FIG. 28, the end face of the portion of the region B does not adversely affect the light emission characteristics.
Since other than the above is the same as that of the first embodiment, the description is omitted.
According to the twenty-first embodiment, the same advantages as those of the first embodiment can be obtained.

Next, a twenty-second embodiment of the present invention is described.
FIG. 29 is a plan view showing a GaN substrate used in the twenty-second embodiment. As shown in FIG. 29, in the twenty-second embodiment, the element region 2 is defined so that the region B is not included in the laser stripe 3. Here, the laser stripe 3 is separated from the region B by 50 μm or more. In this case, the element region 2 includes two regions B.
Since other than the above is the same as that of the first embodiment, the description is omitted.
According to the twenty-second embodiment, advantages similar to those of the first embodiment can be obtained.

Next, a twenty-third embodiment of the present invention is described.
FIG. 30 is a plan view showing a GaN substrate used in the twenty-third embodiment. This GaN substrate 1 is n-type and has a C-plane orientation. However, the GaN substrate 1 may have an R-plane, A-plane, or M-plane orientation. In this GaN substrate 1, regions B made of crystals with a high average dislocation density are periodically arranged in the GaN <11-20> direction at intervals of 400 μm, for example, in regions A made of crystals with a low average dislocation density. For example, they are periodically arranged at intervals of 20 to 100 μm in the <1-100> direction orthogonal to the <11-20> direction. However, the <11-20> direction and the <1-100> direction may be interchanged.

In the twenty-third embodiment, as shown in FIG. 31, a pair of end faces parallel to the laser stripe 3 pass through the columns of the regions B in the <1-100> direction, and the laser stripes 3 The element region 2 is defined so as to be located near the center of the region between the columns. In this case, the element region 2 does not substantially include the column of the region B.
Since other than the above is the same as that of the first embodiment, the description is omitted.
According to the twenty-third embodiment, the same advantages as those of the first embodiment can be obtained.

Next, a twenty-fourth embodiment of the present invention is described.
As shown in FIG. 32, in the twenty-fourth embodiment, a GaN substrate 1 similar to that in the twenty-third embodiment is used, but one end face parallel to the laser stripe 3 is a region B in the <1-100> direction. This is different from the twenty-third embodiment in that the other end face passes a position away from the row of the region B. In this case, the element region 2 does not substantially include the column of the region B.
Since the other than the above is the same as that of the 23rd and 1st embodiments, explanation is omitted.
According to the twenty-fourth embodiment, the same advantages as those of the first embodiment can be obtained.

Next, a twenty-fifth embodiment of the present invention is described.
As shown in FIG. 33, in the twenty-fifth embodiment, a GaN substrate 1 similar to that in the twenty-third embodiment is used, but a pair of end faces parallel to the laser stripe 3 are both in the <1-100> direction. This is different from the twenty-third embodiment in that the element region 2 is defined so as to be positioned between the columns of the region B and so that the laser stripe 3 is positioned near the center of the region between the columns of the region B. . In this case, the element region 2 does not substantially include the column of the region B.
Since the other than the above is the same as that of the 23rd and 1st embodiments, explanation is omitted.
According to the twenty-fifth embodiment, the same advantages as those of the first embodiment can be obtained.

Next, a twenty-sixth embodiment of the invention is described.
As shown in FIG. 34, in the twenty-sixth embodiment, a GaN substrate 1 similar to that in the twenty-third embodiment is used, but one end face parallel to the laser stripe 3 is a region B in the <1-100> direction. The other end face is located between the column of the region B immediately adjacent to the column of the region B and the column of the next region B, and the laser stripe 3 is 50 μm or more from the column of the region B It differs from the twenty-third embodiment in that it passes through a distant position. In this case, the element region 2 includes one column of the region B.
Since the other than the above is the same as that of the 23rd and 1st embodiments, explanation is omitted.
According to the twenty-sixth embodiment, advantages similar to those of the first embodiment can be obtained.

Next, a twenty-seventh embodiment of the invention is described.
As shown in FIG. 35, in the twenty-seventh embodiment, a GaN substrate 1 similar to that in the twenty-third embodiment is used, but one end face parallel to the laser stripe 3 is a region B in the <1-100> direction. The other end face is located between the row of the region B immediately adjacent to the row of the region B and the row of the next region B, and the laser stripe 3 is located in the region B. It differs from the twenty-third embodiment in that it passes through a position separated by 50 μm or more from the row. In this case, the element region 2 includes one column of the region B.
Since the other than the above is the same as that of the 23rd and 1st embodiments, explanation is omitted.
According to the twenty-seventh embodiment, advantages similar to those of the first embodiment can be obtained.

Next, a twenty-eighth embodiment of the present invention is described.
FIG. 36 is a plan view showing the GaN substrate 1 used in the twenty-eighth embodiment. This GaN substrate 1 is the same as the GaN substrate 1 used in the tenth embodiment, except that the regions B are periodically arranged at intervals of, for example, 200 μm in the <11-20> direction of GaN. In this case, the element region 2 includes two columns of the region B.

As shown in FIG. 36, in the twenty-eighth embodiment, the laser stripes 3 are located near the center of the region between adjacent columns of the region B, and a pair of end faces parallel to the laser stripe 3 are provided. Are located in the vicinity of the center of the region between the row of the region B and the row of the region B immediately outside thereof.
Since the other than the above is the same as that of the 23rd and 1st embodiments, explanation is omitted.
According to the twenty-eighth embodiment, the same advantages as those of the first embodiment can be obtained.

Next, a twenty-ninth embodiment of the present invention is described.
FIG. 37 is a plan view showing a GaN substrate used in the twenty-ninth embodiment. This GaN substrate 1 is n-type and has a C-plane orientation. However, the GaN substrate 1 may have an R-plane, A-plane, or M-plane orientation. In this GaN substrate 1, a region B made of a crystal having a high average dislocation density in a region A made of a crystal having a low average dislocation density and extending linearly in the <1-100> direction of GaN is <1. For example, they are periodically arranged at intervals of 400 μm in the <11-20> direction orthogonal to the −100> direction. However, the <1-100> direction and the <11-20> direction may be interchanged.

In the twenty-ninth embodiment, as shown in FIG. 38, a pair of end faces parallel to the laser stripe 3 pass through the region B, and the laser stripe 3 is located near the center of the region between the regions B. Thus, the element region 2 is defined. In this case, the element region 2 does not substantially include the column of the region B.
Since other than the above is the same as that of the first embodiment, the description is omitted.
According to the twenty-ninth embodiment, advantages similar to those of the first embodiment can be obtained.

Next, a thirtieth embodiment of the present invention is described.
As shown in FIG. 39, in the thirtieth embodiment, a GaN substrate 1 similar to that in the twenty-ninth embodiment is used, but one end face parallel to the laser stripe 3 passes through the region B and the other end face is This is different from the twenty-ninth embodiment in that it passes a position away from the row of the region B. In this case, the element region 2 does not substantially include the column of the region B.
Since the other than the above is the same as that of the 29th and 1st embodiment, description is abbreviate | omitted.
According to the thirtieth embodiment, advantages similar to those of the first embodiment can be obtained.

Next, a thirty-first embodiment of the present invention is described.
As shown in FIG. 40, in the thirty-first embodiment, the GaN substrate 1 similar to the twenty-ninth embodiment is used, but a pair of end faces parallel to the laser stripe 3 are located between the regions B. In addition, the second embodiment is different from the twenty-ninth embodiment in that the element region 2 is defined so that the laser stripe 3 is located near the center of the region between the regions B. In this case, the element region 2 does not substantially include the column of the region B.
Since the other than the above is the same as that of the 29th and 1st embodiment, description is abbreviate | omitted.
According to the thirty-first embodiment, advantages similar to those of the first embodiment can be obtained.

Next, a thirty-second embodiment of the present invention is described.
As shown in FIG. 41, in the thirty-second embodiment, a GaN substrate 1 similar to that in the twenty-ninth embodiment is used, but one end face parallel to the laser stripe 3 passes through the region B and the other end face is This is different from the twenty-ninth embodiment in that it is located between a region B immediately adjacent to the row of regions B and the next region B, and the laser stripe 3 passes a position separated from the region B by 50 μm or more. . In this case, the element region 2 includes one region B.
Since the other than the above is the same as that of the 29th and 1st embodiment, description is abbreviate | omitted.
According to the thirty-second embodiment, the same advantages as those of the first embodiment can be obtained.

Next, a thirty-third embodiment of the present invention is described.
As shown in FIG. 42, in this 33rd embodiment, the same GaN substrate 1 as in the 29th embodiment is used, but one end face parallel to the laser stripe 3 passes through a position away from the region B, The twenty-ninth embodiment is characterized in that the other end face is located between a region B immediately adjacent to this region B and the next region B, and the laser stripe 3 passes a position separated by 50 μm or more from the region B. And different. In this case, the element region 2 includes one column of the region B.
Since the other than the above is the same as that of the 29th and 1st embodiment, description is abbreviate | omitted.
According to the thirty-third embodiment, advantages similar to those of the first embodiment can be obtained.

Next, a thirty-fourth embodiment of the present invention is described.
FIG. 43 is a plan view showing the GaN substrate 1 used in the thirty-fourth embodiment. This GaN substrate 1 is the same as the GaN substrate 1 used in the twenty-ninth embodiment, except that the regions B are periodically arranged at intervals of, for example, 200 μm in the <11-20> direction of GaN. In this case, the element region 2 includes two columns of the region B.

As shown in FIG. 43, in the thirty-fourth embodiment, the laser stripe 3 is located near the center of the region between the adjacent regions B, and a pair of end faces parallel to the laser stripe 3 are these regions. It is located near the center of the region between B and their immediate outer region B.
Since the other than the above is the same as that of the 29th and 1st embodiment, description is abbreviate | omitted.
According to the thirty-fourth embodiment, advantages similar to those of the first embodiment can be obtained.

  As mentioned above, although embodiment of this invention was described concretely, this invention is not limited to the above-mentioned embodiment, The various deformation | transformation based on the technical idea of this invention is possible.

  For example, the numerical values, structures, substrates, raw materials, processes, and the like given in the above-described embodiments are merely examples, and different numerical values, structures, substrates, raw materials, processes, and the like may be used as necessary.

  Specifically, for example, in the above-described embodiment, the case where the present invention is applied to the manufacture of a GaN-structured semiconductor laser having an SCH structure has been described. However, the present invention is, for example, a GaN-structure having a DH (Double Heterostructure) structure. Of course, it may be applied to the manufacture of GaN-based light-emitting diodes, as well as to the manufacture of semiconductor lasers, and also nitride-based III-V such as GaN-based FETs and GaN-based heterojunction bipolar transistors (HBTs). You may apply to the electron transit element using a group compound semiconductor.

  In the above-described embodiment, the GaN substrate 1 may be provided on a different substrate such as a sapphire substrate.

  In the above-described embodiment, the MOCVD method is used for the growth of the GaN-based semiconductor layer. For the growth of the GaN-based semiconductor layer, hydride vapor phase epitaxial growth, halide vapor phase epitaxial growth (HVPE), or molecular beam epitaxy ( Other growth methods such as the MBE method may be used.

Furthermore, in the above-described embodiment, H ₂ gas is used as a carrier gas when performing growth by MOCVD, but other carrier gases such as H ₂ and N ₂ or He, Ar gas are used as necessary. A mixed gas such as may be used.
Further, in the above-described embodiment, the resonator end surface is formed by cleavage, but the resonator end surface may be formed by dry etching such as RIE.

It is the perspective view and sectional drawing which show the GaN board | substrate used in 1st Embodiment of this invention. It is a top view which shows the GaN substrate used in 1st Embodiment of this invention. It is a basic diagram which shows an example of distribution of the dislocation density in the vicinity of the area | region B of the GaN board | substrate used in 1st Embodiment of this invention. It is sectional drawing for demonstrating the comparative example with 1st Embodiment of this invention. It is sectional drawing for demonstrating the comparative example with 1st Embodiment of this invention. It is sectional drawing which shows the GaN substrate used in 1st Embodiment of this invention. It is sectional drawing which shows the state which grew the GaN-type semiconductor layer on the GaN substrate in 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the GaN-type semiconductor laser by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the GaN-type semiconductor laser by 1st Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the GaN-type semiconductor laser by 1st Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the GaN-type semiconductor laser by 1st Embodiment of this invention. It is sectional drawing which shows the GaN board | substrate used in 2nd Embodiment of this invention. It is sectional drawing which shows the state which grew the GaN-type semiconductor layer on the GaN substrate in 2nd Embodiment of this invention. It is sectional drawing which shows the state which grew the GaN-type semiconductor layer on the GaN substrate in 3rd Embodiment of this invention. It is sectional drawing which shows the state which grew the GaN-type semiconductor layer on the GaN substrate in 4th Embodiment of this invention. It is sectional drawing which shows the GaN board | substrate used in 5th Embodiment of this invention. It is sectional drawing which shows the state which grew the GaN-type semiconductor layer on the GaN substrate in 5th Embodiment of this invention. It is sectional drawing which shows the state which grew the GaN-type semiconductor layer on the GaN substrate in 6th Embodiment of this invention. It is sectional drawing which shows the state which grew the GaN-type semiconductor layer on the GaN substrate in 6th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the GaN board | substrate used in 7th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the GaN board | substrate used in 7th Embodiment of this invention. It is sectional drawing which shows the GaN board | substrate used in 8th Embodiment of this invention. It is sectional drawing which shows the GaN board | substrate used in 9th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the GaN board | substrate used in 10th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the GaN board | substrate used in 10th Embodiment of this invention. It is sectional drawing for demonstrating the manufacturing method of the GaN board | substrate used in 10th Embodiment of this invention. It is a top view which shows the GaN board | substrate used in 11th Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the GaN-type semiconductor laser by 21st Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the GaN-type semiconductor laser by 22nd Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the GaN-type semiconductor laser by 23rd Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the GaN-type semiconductor laser by 23rd Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the GaN-type semiconductor laser by 24th Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the GaN-type semiconductor laser by 25th Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the GaN-type semiconductor laser by 26th Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the GaN-type semiconductor laser by 27th Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the GaN-type semiconductor laser by 28th Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the GaN-type semiconductor laser by 29th Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the GaN-type semiconductor laser by 29th Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the GaN-type semiconductor laser by 30th Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the GaN-type semiconductor laser by 31st Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the GaN-type semiconductor laser by 32nd Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the GaN-type semiconductor laser by 33rd Embodiment of this invention. It is a top view for demonstrating the manufacturing method of the GaN-type semiconductor laser by 34th Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... GaN substrate, 2 ... Element area | region, 3 ... Laser stripe, 5 ... n-type GaN buffer layer, 6 ... n-type AlGaN clad layer, 7 ... n-type GaN optical waveguide Layer, 8 ... active layer, 9 ... undoped InGaN degradation prevention layer, 10 ... p-type AlGaN cap layer, 11 ... p-type GaN optical waveguide layer, 12 ... p-type AlGaN cladding layer, 13 ... p-type GaN contact layer, 14 ... ridge, 15, 18 ... insulating film, 16 ... n-side electrode, 17 ... p-side electrode

Claims (21)

  A seed composed of an amorphous or polycrystalline layer is regularly formed on the base substrate at intervals of 50 μm or more, and a nitride III-V compound semiconductor is faceted on the base substrate on which the seed is formed. The dislocations are propagated by growing while maintaining the inclined surface consisting of the facet plane, and the base substrate is removed after the dislocations are aggregated in the region of the above kind, and further the nitride A second average higher than the first average dislocation density in a first region made of a single crystal having a first average dislocation density manufactured by planarizing the surface of a group III-V compound semiconductor. A plurality of second regions having a dislocation density are regularly arranged, the second region is polycrystalline, a single crystal slightly tilted with respect to the first region, or the first region It consists of a single crystal with the C-axis reversed. A nitride III-V compound semiconductor substrate in which the second region penetrates the nitride III-V compound semiconductor substrate and forms a device structure on the main surface. When the group III compound semiconductor layer is grown, at least one of the second regions is etched from the main surface of the group III-V compound semiconductor substrate by etching before the nitride III-V group compound semiconductor layer is grown. A method of manufacturing a semiconductor device in which a part is removed.   The second region is removed from the main surface of the nitride III-V compound semiconductor substrate to a predetermined depth before growing the nitride III-V compound semiconductor layer. A method for producing a semiconductor device according to 1.   The method for manufacturing a semiconductor device according to claim 2, wherein the predetermined depth is 1 μm or more.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second region is completely removed before the nitride III-V compound semiconductor layer is grown.   The method of manufacturing a semiconductor device according to claim 1, wherein the etching is wet etching.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the etching is dry etching.   The method of manufacturing a semiconductor device according to claim 1, wherein the etching is thermochemical etching.   A seed composed of an amorphous or polycrystalline layer is regularly formed on the base substrate at intervals of 50 μm or more, and a nitride III-V compound semiconductor is faceted on the base substrate on which the seed is formed. The dislocations are propagated by growing while maintaining the inclined surface consisting of the facet plane, and the base substrate is removed after the dislocations are aggregated in the region of the above kind, and further the nitride A second average higher than the first average dislocation density in a first region made of a single crystal having a first average dislocation density manufactured by planarizing the surface of a group III-V compound semiconductor. A plurality of second regions having a dislocation density are regularly arranged, the second region is polycrystalline, a single crystal slightly tilted with respect to the first region, or the first region It consists of a single crystal with the C-axis reversed. A nitride III-V compound semiconductor substrate in which the second region penetrates the nitride III-V compound semiconductor substrate and forms a device structure on the main surface. When the group III compound semiconductor layer is grown, the surface of the second region is covered with an insulating film, a refractory metal film, or a refractory metal nitride film before the nitride III-V compound semiconductor layer is grown. A method for manufacturing a semiconductor element covered with a semiconductor.   9. The method of manufacturing a semiconductor device according to claim 8, wherein the second region is removed from the main surface of the nitride-based III-V compound semiconductor substrate to a predetermined depth.   The method for manufacturing a semiconductor element according to claim 9, wherein the portion from which the second region has been removed is filled with the covering layer.   The method of manufacturing a semiconductor element according to claim 8, wherein a surface of the covering layer is positioned higher than a main surface of the nitride III-V compound semiconductor substrate.   9. The method of manufacturing a semiconductor element according to claim 8, wherein a surface of the covering layer is coincident with a main surface of the nitride III-V compound semiconductor substrate.   9. The method of manufacturing a semiconductor device according to claim 1, wherein the nitride III-V compound semiconductor substrate has a C-plane orientation.   9. The method for manufacturing a semiconductor device according to claim 1, wherein an interval between two adjacent second regions is 100 [mu] m or more.   9. The method of manufacturing a semiconductor element according to claim 1, wherein the second region has a diameter of 10 [mu] m to 100 [mu] m. 9. The method of manufacturing a semiconductor element according to claim 1, wherein the average dislocation density in the second region is 1 × 10 ⁸ cm ⁻² or more. 9. The semiconductor element manufacturing according to claim 1, wherein the average dislocation density of the first region is 2 × 10 ⁶ cm ⁻² or less, and the average dislocation density of the second region is 1 × 10 ⁸ cm ⁻² or more. Method.   9. The method of manufacturing a semiconductor device according to claim 1, wherein the nitride III-V compound semiconductor substrate is made of GaN.   9. The method of manufacturing a semiconductor element according to claim 1, wherein the semiconductor element is a semiconductor light emitting element.   The method of manufacturing a semiconductor device according to claim 19, wherein the semiconductor light emitting device is a semiconductor laser.   The method of manufacturing a semiconductor device according to claim 19, wherein the semiconductor light emitting device is a light emitting diode.

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