JP4798102B2 - Vertical Hall element - Google Patents

Description

The present invention is used, for example, a magnetic sensor or the like, about the vertical Hall element for detecting a horizontal magnetic field component to the substrate surface (chip surface) by utilizing the Hall effect.

  As is well known, since the Hall element can detect the angle without contact, it is mounted on a so-called Hall IC or the like and used as an angle detection sensor such as a throttle valve opening sensor of an in-vehicle internal combustion engine as a magnetic sensor, for example. It is done. First, the magnetic detection principle of the Hall element will be described with reference to FIG.

  When a magnetic field (magnetism) perpendicular to the current flowing in the material is applied, an electric field (voltage) is generated in a direction perpendicular to both the current and the magnetic field. This phenomenon is called the Hall effect, and the voltage generated here is called the Hall voltage.

For example, when considering a Hall element (conductor) 100 as shown in FIG. 41, the width of the magnetic detection part (Hall plate) of the element is W, the length is L, the thickness is d, and the element and magnetic field If the angle formed is θ, the applied magnetic flux density is B, and the supply (drive) current (current flowing between the terminals TI and TI ′) is I, the Hall voltage (voltage generated between the terminals TV _{H and} TV _H ′) V _H is
V _H = (R _H IB / d) cos θ, R _H = 1 / (qn)
It can be expressed as Here, R _H is the Hall coefficient, q is the charge, and n is the carrier concentration.

As can be seen from the above relational expression, the Hall voltage V _H changes according to the angle θ formed by the Hall element and the magnetic field. Therefore, by using this, the angle can be detected. Thus, the above-described angle detection sensor can be realized by using the Hall element.

  As a general Hall element, for example, a Hall element as described in Non-Patent Document 1, a so-called horizontal Hall element is known. This horizontal Hall element detects a magnetic field component perpendicular to the substrate surface (chip surface).

  Hereinafter, this Hall element (horizontal Hall element) will be further described with reference to FIG. FIG. 42A is a plan view of the Hall element, and FIG. 42B is a cross-sectional view taken along line L1-L1 in FIG.

As shown in FIGS. 42 (a) and 42 (b), this Hall element is largely formed on, for example, an epitaxial growth on a semiconductor layer (P-sub) 21 made of, for example, P-type silicon. The semiconductor region 22 is made of N-type silicon. Such a semiconductor region 22 (N ⁻ layer) is generally set to a concentration of “1.0 × 10 ^{14 to} 1.0 × 10 ¹⁷ / cm ³ ”.

Further, in the semiconductor region 22, for example, a P-type diffusion layer (P-type diffusion isolation wall) 24 is formed so as to be connected to the semiconductor layer 21 in order to isolate the Hall element from other elements. . A region (active region) 22a on the surface of the semiconductor region 22 and surrounded by the diffusion layer 24 has a contact region (N ⁺ diffusion layer) 23a so that the impurity concentration on the surface is selectively increased. ˜23d are formed, and a good ohmic contact is formed between the contact regions 23a-23d and the electrodes (wirings) disposed therein. More specifically, the contact regions 23a and 23b and the contact regions 23c and 23d are arranged at four corners of the region (active region) 22a so as to be orthogonal to each other, and via electrodes (wirings) disposed in these regions. Are electrically connected to terminals S and G and terminals V1 and V2, respectively.

Here, for example, when a constant drive current flows from the terminal S to the terminal G, the current flows from the contact region 23a to the contact region 23b in the semiconductor region 22. That is, in this case, a current mainly containing a component parallel to the same surface (chip surface) flows in the vicinity of the substrate surface. At this time, when a magnetic field including a component perpendicular to the substrate surface (chip surface) is applied to the current (for example, a magnetic field indicated by an arrow B in FIG. 42), the terminal V1 and the terminal V2 are caused by the Hall effect described above. A Hall voltage corresponding to the magnetic field is generated between Therefore, by detecting the generated Hall voltage signal through these terminals V1 and V2, the magnetic field component to be detected based on the previous relational expression “V _H = (R _H IB / d) cos θ” shown in FIG. That is, a magnetic field component perpendicular to the surface (chip surface) of the substrate used for the Hall element is required. In this Hall element, it is also possible to detect a Hall voltage signal at terminals S and G by passing a drive current through terminals V1 and V2. For this reason, a driving method that offsets an offset voltage (unbalanced voltage) generated in the same element by, for example, periodically replacing the electrodes by using such electrode replacement has been put into practical use.

  In recent years, in addition to the horizontal Hall element, as described in Patent Document 1, for example, a Hall element that detects a magnetic field component parallel to the substrate surface (chip surface), a so-called vertical Hall element has also been proposed. Since this vertical Hall element has a feature that two elements that detect different phases (angles) can be integrated on one chip, the two vertical Hall elements are arranged at an angle of “90 °”. Thus, a rotation sensor or the like that can obtain a linear output (voltage signal) in an angle range of “0 ° to 360 °” can be realized. Hereinafter, an example of the vertical Hall element will be described with reference to FIG. 43A is a plan view of the Hall element, FIG. 43B is a cross-sectional view taken along line L1-L1 in FIG. 43A, and FIG. 43C is FIG. It is sectional drawing along the L2-L2 line of a).

  As shown in FIGS. 43A to 43C, this Hall element is formed on a semiconductor substrate having an epitaxial layer, a so-called epitaxial substrate. Specifically, this Hall element includes a semiconductor layer (P-sub) 31 made of, for example, P-type silicon, and a buried layer BL formed in such a manner that an N-type conductivity impurity is introduced into this surface. Further, the semiconductor region 32 is made of N-type silicon formed by epitaxial growth thereon. The buried layer BL functions as a lower electrode, and its impurity concentration is set higher than that of the semiconductor region 32. In this Hall element, the depth dimension 3a of the semiconductor region 32 is set to, for example, “9.5 μm”, and the depth dimension 3b to the buried layer BL of the semiconductor region 32 is set to, for example, “5.5 μm”. The thickness dimension of the buried layer BL is set to “6.0 μm”, for example.

In the semiconductor region 32, for example, a P-type diffusion layer (P-type diffusion isolation wall) 34 is formed so as to be connected to the semiconductor layer 31 in order to isolate the Hall element from other elements. . Further, in the region (active region) that is on the surface of the semiconductor region 32 and surrounded by the diffusion layer 34, the contact region (N ⁺ diffusion layer) is formed in such a manner that the impurity concentration (N-type) on the surface is selectively increased. ) 33a to 33e are formed, and a good ohmic contact is formed between the contact regions 33a to 33e and the electrodes (wirings) disposed thereon. These contact regions 33a to 33e are electrically connected to terminals S, G1, G2, V1, and V2, respectively, through respective electrodes (wirings) disposed there.

  In addition, as shown in FIG. 43A, the region (active region) surrounded by the diffusion layer 34 has a P-type diffusion layer (P-type diffusion separation wall) 34a and a pn junction isolation by each diffusion layer. 34b is divided into regions 32a to 32c that are separated from each other. As shown in FIGS. 43B and 43C, in these regions 12a to 12c, electrically partitioned regions are formed even inside the substrate.

  More specifically, in these regions, the contact regions 33a, 33d, and 33e are formed in the region (element region) 32a, the contact region 33b is formed in the region 32b, and the contact region 33c is formed in the region 32c. The contact region 33a is arranged so as to be sandwiched between both the contact regions 33b and 33c and the contact regions 33d and 33e orthogonal to the contact regions. That is, the contact region 33a is arranged to face each of the contact regions 33b and 33c with the diffusion layers 34a and 34b interposed therebetween.

  In this Hall element, a region sandwiched between the contact regions 33d and 33e in a region electrically partitioned inside the substrate of the region 32a is a so-called magnetic detection part (hole plate) HP. That is, in this Hall element, a Hall voltage signal corresponding to the magnetic field applied here is generated.

Here, for example, when a constant drive current is passed from the terminal S to the terminal G1 and from the terminal S to the terminal G2, the current flows from the contact region 33a formed on the surface of the substrate to the magnetic detection unit HP. It flows through the layer BL to the contact regions 33b and 33c, respectively. That is, in this case, a current mainly including a component perpendicular to the substrate surface (chip surface) flows through the magnetic detection unit HP. For this reason, in the state where this driving current is applied, a magnetic field (for example, a magnetic field indicated by an arrow B in FIG. 43) including a component parallel to the substrate surface (chip surface) is applied to the magnetic detection unit HP of the Hall element. If so, a Hall voltage corresponding to the magnetic field is generated between the terminal V1 and the terminal V2 by the Hall effect described above. Therefore, by detecting the generated Hall voltage signal through these terminals V1 and V2, the magnetic field component to be detected based on the previous relational expression “V _H = (R _H IB / d) cos θ” shown in FIG. That is, a magnetic field component parallel to the surface (chip surface) of the substrate used for the Hall element is required. Incidentally, in this Hall element, the dimension d shown in FIG. 43A corresponds to the thickness of the magnetic detection part (Hall plate) (“d” in the above relational expression). In addition, the direction in which the drive current flows in the Hall element is arbitrary, and the magnetic field (magnetism) can be detected with the direction of the drive current being reversed.

There is also a vertical Hall element having a structure as shown in FIG. 44 in order to increase the sensitivity of the vertical Hall element. As shown in FIG. 44, in this Hall element, the width of the effective current path of the magnetic detection unit HP is narrowed by narrowing the width of the buried layer BL, so that the magnetic detection sensitivity (so-called product sensitivity) is reduced. Has been increased. In FIG. 44, the same elements as those shown in FIG. 43 are denoted by the same reference numerals.
Ichisuke Maenaka, 3 others, "Integrated 3D magnetic sensor", IEEJ Transactions C, 1989, Vol. 109, No. 7, p483-490 Japanese Patent Laid-Open No. 1-251763

  As described above, in the vertical Hall element illustrated in FIG. 43 or 44, the magnetic field component applied to the magnetic detection unit (Hall plate) HP, that is, the magnetic field component horizontal to the substrate surface (chip surface) can be detected. It becomes possible. Further, in these vertical Hall elements, since the buried layer BL is provided, a current path is reliably ensured near the bottom surface of the semiconductor region 32. Further, as seen in the vertical Hall element exemplified in FIG. 44, if the width of the buried layer BL is reduced, the sensitivity as a magnetic detection element can be improved. However, such a vertical Hall element has a structure in which an epitaxial substrate must be used as a semiconductor substrate, and the degree of freedom in selecting a substrate to be used is greatly limited.

This invention has been made in view of these circumstances, and an object thereof is to provide a vertical Hall element that can increase the flexibility in selection of a substrate used in formation of said Hall element.

In order to achieve such an object, according to the first aspect of the present invention, a semiconductor region having a predetermined conductivity type is formed in a semiconductor substrate, and ends of the current supply pair and the voltage output pair are formed on the surface of the semiconductor region. And a magnetic field component parallel to the surface of the substrate is detected in the state where a current including a component perpendicular to the surface of the substrate is supplied from one end of the current supply pair to the magnetic detection unit in the semiconductor region. In a vertical Hall element that outputs a Hall voltage signal corresponding to the magnetic field component to both ends of the voltage output pair when applied to the part, the semiconductor region is doped with a conductive impurity and diffused. consisted of a diffusion layer formed in Rukatachi, a semiconductor region made of the diffusion layer, and those formed with the concentration change in the depth direction, the said semiconductor region, electrically different from the semiconductor region A diffusion layer of a mold, disposed between one end of the voltage output pair and the current supply pair sandwiched between the voltage output pair and the other end of the current supply pair, and near the bottom surface of the semiconductor region A diffusion separation wall that selectively narrows to form a current path is formed, and the magnetic detection unit is electrically partitioned by the diffusion separation wall.
According to a second aspect of the present invention, the semiconductor region is composed of a diffusion layer formed by adding and diffusing conductive impurities to the semiconductor substrate, and the semiconductor region composed of the diffusion layer is In the semiconductor region, the voltage output pair and one end of the current supply pair sandwiched between the voltage output pair and the other end of the current supply pair are formed in the semiconductor region. And a diffusion separation wall made of a diffusion layer of a conductivity type different from that of the semiconductor region is formed with a diffusion depth shallower than that of the semiconductor region, and the magnetic detection unit is electrically partitioned by the diffusion separation wall. It shall be.
In the invention according to claim 5, the semiconductor region is formed of a diffusion layer formed by adding and diffusing conductive impurities to the semiconductor substrate, and the semiconductor region including the diffusion layer is The semiconductor region has an STI (Shallow Trench Isolation) structure, and has one end of the voltage output pair and the current supply pair sandwiched between the voltage output pair. An insulating separation wall is formed between the other end of the current supply pair and selectively narrows the vicinity of the bottom surface of the semiconductor region to form a current path. The magnetic detection unit is formed by the insulating separation wall. It shall be electrically partitioned.
In the invention according to claim 6, the semiconductor region is formed of a diffusion layer formed by adding and diffusing conductive impurities to the semiconductor substrate, and the semiconductor region including the diffusion layer is In the semiconductor region, the voltage output pair and the one end of the current supply pair sandwiched between the voltage output pair and the other end of the current supply pair are formed in the semiconductor region. An insulating isolation wall having an STI (Shallow Trench Isolation) structure is formed with a shallower depth than the semiconductor region, and the magnetic detection unit is electrically partitioned by the insulating isolation wall And

  As described above, the semiconductor region is formed of a diffusion layer (well), so that it can be easily formed by, for example, ion implantation. A substrate, an SOI (Silicon On Insulator) substrate, or the like can be used as a substrate (semiconductor substrate) of the Hall element. That is, it is possible to greatly increase the degree of freedom in selecting a substrate used for forming the Hall element.

  In addition, it is effective that the semiconductor region formed of the diffusion layer is formed with a concentration change in the depth direction. According to such a structure, it is possible to select and set a preferable path as a current path in the semiconductor region in response to a user request based on the use of the Hall element and the like.

  The substrate has a current supply pair and a voltage output pair on the surface of the semiconductor region, and the substrate includes a component perpendicular to the surface of the substrate that is supplied from one end of the current supply pair and flows to the magnetic detection unit. When a magnetic field component parallel to the surface of the electrode is applied, a Hall voltage signal corresponding to the magnetic field component is output to both ends of the voltage output pair, so that the element can be manufactured and magnetically detected. In terms of performance as an element, a vertical Hall element is realized in a form suitable for practical use. Furthermore, if one end of the current supply pair is arranged so as to be sandwiched between the voltage output pair, the Hall voltage generated with respect to the current flowing through the magnetic detection unit can be reliably captured through the voltage output pair. become.

In these structures, the magnetic detection part (hole plate) is partitioned and formed in the semiconductor region by the diffusion separation wall and the insulation separation wall, and a current path is reliably ensured near the bottom surface of the semiconductor region. become. As a result, the original function as a vertical Hall element that detects a magnetic field component parallel to the substrate surface (chip surface) is maintained high. Moreover, in such a structure, the diffusion separation wall and the insulation separation wall can be easily formed by a normal CMOS (Complementary Metal Oxide Semiconductor) process. Therefore, the semiconductor region, the diffusion separation wall or the insulation separation wall, and thus the Hall element itself can be easily manufactured by a normal CMOS process.

In the vertical Hall element according to the first or second aspect , as defined in the third aspect of the invention, the diffusion separation wall formed of a diffusion layer having a conductivity type different from that of the semiconductor region is at least “2 μm”. By forming with the above diffusion depth, the spread of the current flowing in the magnetic detection part (Hall plate) in the lateral direction (direction parallel to the substrate surface) is effectively suppressed, and the magnetic detection element As a result, the sensitivity can be improved. More preferably, the diffusion depth of the diffusion separation wall is set to “3 μm” or more.

Furthermore, with respect to the vertical Hall element according to any one of claims 1 to 3 , as in the invention according to claim 4 , a diffusion separation wall composed of a diffusion layer of a conductivity type different from that of the semiconductor region, It is effective to form the semiconductor substrate in such a manner that it has the highest concentration on the surface of the semiconductor substrate and decreases in concentration as it proceeds from the front surface to the back surface side.

  When a diffusion layer is formed by adding impurities from the surface of the semiconductor substrate and diffusing it, the width of the diffusion layer formed thereby becomes narrower as it becomes deeper from the surface of the substrate. For this reason, in the vertical Hall element in which the magnetic detection unit is partitioned by such a diffusion layer, the current flowing through the magnetic detection unit spreads as it goes deeper, leading to a decrease in sensitivity as the magnetic detection element. There was a problem. In this regard, in the above-described structure, the diffusion separation wall that partitions the magnetic detection unit is formed in a concentration distribution that has the highest concentration on the surface of the semiconductor substrate, and the concentration decreases toward the back side from the surface. . When the diffusion separation wall forms the magnetic detection part in the semiconductor region, a depletion layer is formed between the diffusion separation wall and the semiconductor region. At this time, the width of the depletion layer depends on the impurity concentration of the p · n region forming the depletion layer, and becomes larger (broader) as the concentration becomes lower (lower). It is divided along a direction substantially perpendicular to. As a result, the spread of the current in the magnetic detection unit is suppressed, and the current component flowing through the magnetic detection unit in the direction perpendicular to the substrate surface can be relatively increased. As a result, the sensitivity (so-called product) of the magnetic detection element can be increased. (Sensitivity) is improved.

On the other hand, in the vertical Hall element according to the fifth or sixth aspect , as in the invention according to the seventh aspect , the trench inner wall of the insulating isolation wall having the STI structure has a conductivity type different from that of the semiconductor region. It is effective to have a structure in which an impurity layer made of is formed.

By the way, when a trench is formed in a semiconductor substrate, a damaged layer is usually formed on the inner wall of the trench, where carrier recombination is likely to occur. In this regard, according to the above-described structure in which the impurity layer is provided on the inner wall of the trench, the recombination of the carriers is suppressed by the impurity layer, and the carrier mobility of the semiconductor region is maintained high. Further, since a depletion layer of a pn junction formed between this impurity layer and the semiconductor region also enters the inside of the element, the thickness of the magnetic detection part (hole plate) (the relationship shown in FIG. 41) The dimension corresponding to “d” in the formula is also substantially narrowed. That is, according to such a structure, high sensitivity as a magnetic detection element can be achieved.
In the vertical Hall element according to any one of claims 1 to 7, as in the invention according to claim 8, the current supply pair is sandwiched between the voltage output pair at one end, By assuming that the other end is arranged symmetrically with respect to the voltage output pair, the Hall voltage generated with respect to the current flowing in the lateral direction (current component flowing parallel to the substrate surface) through the magnetic detection unit (Hall plate). Is canceled, and the magnetic field component to be detected, that is, the magnetic field component parallel to the substrate surface (chip surface) can be detected with high accuracy.
On the other hand, in order to simplify the structure as a vertical Hall element, according to the invention of claim 9, one end of the current supply pair is sandwiched between the voltage output pair and the other end is the voltage. It is effective to arrange the output pair only on one side.
Furthermore, regarding the vertical Hall element according to any one of the first to ninth aspects, as in the invention according to the tenth aspect, the current supply pair and the voltage output pair are orthogonal to each other. It is effective to make the arrangement (layout) arranged. That is, according to such a layout, good element characteristics can be obtained with a simple element design.
According to an eleventh aspect of the present invention, in the vertical Hall element according to any one of the first to tenth aspects, each end of the current supply pair and the voltage output pair is connected to the surface of the semiconductor substrate. It is assumed that it is arranged as a portion where the impurity concentration in is selectively increased.
According to such a structure, a good ohmic contact is formed between the electrodes (wirings) disposed at the respective end portions, and thus more excellent electrical characteristics can be obtained.
In the vertical Hall element according to any one of claims 1 to 11, according to the invention according to claim 12, the Hall voltage signal has a resistance value at least at one end of the voltage output pair. It is effective to have a structure in which the signal is output through a wiring that can be changed. According to such a structure, the resistance value of the wiring with respect to the Hall voltage signal is adjusted.
Through the adjustment of the Hall voltage signal, the offset voltage can be corrected and reduced.
Specifically, for example, according to the invention described in claim 13, the wirings having variable resistance values are connected to each other in such a manner that a plurality of wirings having different resistance values can be temporarily or permanently disconnected. Assume that they are electrically connected in parallel. In this case, any one or a combination of the plurality of wirings connected in parallel can be arbitrarily selected through, for example, a switching element or trimming. For this reason, when some output voltage, that is, an offset voltage is generated when a magnetic field is not applied, the offset voltage is set to a desired resistance value with the wiring at at least one end of the voltage output pair through the selection. Correction can be made so as to approach “0V”. That is, the offset voltage described above can be corrected and reduced.
Further, according to the vertical Hall element according to any one of claims 1 to 13, as in the invention according to claim 14, the semiconductor region formed of the diffusion layer has the highest concentration on the surface of the semiconductor substrate. And a current that includes a component perpendicular to the surface of the substrate that is supplied to the magnetic detection unit due to the concentration gradient. It is effective to adopt a structure in which the detector is guided so as to flow in an oblique direction with respect to the surface of the substrate.
The original function as a vertical Hall element to detect a magnetic field component parallel to the substrate surface (chip surface) is satisfied and maintained if a current containing a component perpendicular to the substrate surface can be passed through the magnetic detection unit. It is not indispensable to flow a current consisting only of a component perpendicular to the substrate surface (or a current mainly including this component) to the magnetic detection unit. Therefore, if the above-described structure according to the present invention is adopted, an original function as a vertical Hall element is obtained by supplying a current including a component perpendicular to the substrate surface (current in an oblique direction) to the magnetic detection unit. This also greatly increases the degree of design freedom for the elements that have been constrained so far by the flow of a current perpendicular to the substrate surface.
According to a fifteenth aspect of the present invention, the semiconductor region composed of the diffusion layer is formed in such a manner that the concentration is the lowest on the surface of the semiconductor substrate and the concentration is increased from the front surface to the back surface side. In this case, the current component flowing in the direction perpendicular to the substrate surface in the magnetic detection unit (hole plate) can be relatively increased, and as a result, the sensitivity (so-called product sensitivity) of the magnetic detection element can be increased. Improvement comes to be achieved.
Further, according to the invention of claim 16, the semiconductor region composed of the diffusion layer has a maximum concentration at a predetermined depth of the semiconductor substrate, and decreases to the substrate surface side and the substrate rear surface side from there. Similarly, the current component flowing in the direction perpendicular to the substrate surface in the magnetic detection unit (Hall plate) can be relatively increased, and as a result, as a magnetic detection element The sensitivity of the camera can be improved.
According to another aspect of the present invention, a diffusion stopper film is provided in a semiconductor region made of the diffusion layer, and the semiconductor region is formed at a maximum concentration in a portion facing the diffusion stopper film. If the structure formed in such a manner that the concentration becomes lower as the distance from the substrate is adopted, diffusion of conductive impurities is suppressed by the diffusion stopper film, and the depth direction of the semiconductor region formed of the diffusion layer is suppressed. It is possible to easily form a change in density with respect to the density distribution with a high degree of design freedom. In particular, it is effective to use this structure in combination with the structure described in claim 15.
Further, in order to simplify the structure of the vertical Hall element according to any one of Claims 1 to 17, the semiconductor region according to the invention according to Claim 18 is provided with the semiconductor region. It is effective that the semiconductor region has a structure different from that of the substrate and that the semiconductor region is formed so as to be surrounded by the semiconductor substrate. According to such a structure, a pn junction is formed between the semiconductor substrate and the semiconductor region, and the semiconductor region having the magnetic detection part (hole plate) therein is electrically separated from the surrounding region. It becomes an area. That is, even if the Hall element has a simple structure that does not have an isolation wall made of a diffusion layer, an insulating film, or the like, the element can be suitably isolated from surrounding peripheral circuits.

Further, in the vertical Hall element according to any one of claims 1 to 18 , as in the invention according to claim 19 , a planar electrode is provided on the surface of the semiconductor substrate via an insulating film. It is effective to have a structure provided with a material. According to such a structure, the potential distribution of the semiconductor substrate can be fixed or made variable by using the flat electrode material.

Specifically, for example, as in the invention described in claim 20 , the electrode material is provided so as to cover at least the magnetic detection portion, and the electrode material is further provided with a predetermined wiring via an appropriate wiring. It shall be fixed to the potential.

  Incidentally, movable ions such as sodium (Na) exist in an interlayer insulating film formed on the surface of the element in this type of Hall element. For this reason, when the movable ions move as the Hall element is energized or temperature changes, the potential near the voltage output end on the substrate surface becomes unstable, and the extremely small Hall voltage output from the Hall element The signal may be staggered. This is called time-dependent fluctuation or drift, and causes an error in the detection of a magnetic field based on the same voltage. Especially when the Hall element is used as an angle detection sensor, deterioration of the sensor characteristics is unavoidable and serious. .

  In this regard, according to the above-described structure in which the electrode material is provided so as to cover at least the magnetic detection unit, at least the surface potential of the magnetic detection unit is fixed, and the periphery thereof is also placed in a stable potential environment. become. For this reason, the movement of the movable ions in the interlayer insulating film is suppressed, the variation with time due to the movable ions is reduced, and as a result, the detection accuracy as the magnetic detection element is maintained high. Furthermore, it is possible to shield (shield) noise from above the substrate and protect the Hall element from noise.

Further, for example, as in the invention described in claim 21 , the electrode material is configured such that the resistance distribution of the magnetic detection unit is variable according to the applied voltage.
In this type of Hall element, the resistance bridge as an equivalent circuit of the resistance component inside the element becomes unbalanced due to misalignment during manufacturing or application of stress during packaging. An imbalance (unbalance) may occur in the potential distribution. When the current path inside the element is biased, some output voltage, so-called offset voltage (unbalanced voltage) is generated in the Hall element even though no magnetic field is applied. Become.

  In this regard, according to the above-described structure, by applying an appropriate voltage to the electrode material, the potential distribution inside the element is changed to adjust and balance the unbalance (unbalance) that causes the offset voltage. It becomes possible. That is, the offset voltage can be adjusted and reduced without using a simple circuit configuration or a correction circuit, and the circuit scale of the configuration including a correction circuit for calculating and correcting the offset voltage can be reduced. Reduction will be achieved.

In the vertical Hall element according to any one of claims 1 to 18 , as in the invention according to claim 22 , a field oxide film (LOCOS oxide film) having a LOCOS structure is formed on the surface of the semiconductor substrate. It is effective to have a structure in which the film is provided so as to cover at least the semiconductor region.

  As described above, the behavior of mobile ions contained in the interlayer insulating film on the element surface affects the detection accuracy of the Hall element. In this regard, according to the above structure, the element surface is covered with the LOCOS film to protect the element surface, and the influence of the movable ions, that is, the decrease in detection accuracy is suppressed. In addition, since the surface of the element is protected by the LOCOS film, even if the entire surface of the substrate is subjected to, for example, an ion implantation process or a plasma process as a manufacturing process of the peripheral circuit after the element is formed, As a result, damage to the Hall element is reduced. Such a LOCOS film can also be easily formed by a normal CMOS process.

Further, in the vertical Hall element according to any one of claims 1 to 18 , an impurity having a conductivity type different from that of the semiconductor region is formed on the surface of the semiconductor substrate, as in the invention according to claim 23. It is also effective to have a structure in which the layer is formed so as to cover at least the semiconductor region. Also in this case, for example, when the element is placed in a state where a reverse bias voltage is applied between the impurity layer and the semiconductor region, the element surface is formed by a depletion layer near the pn junction formed by the application of the voltage. Will be protected. Thus, the influence of the movable ions, that is, a decrease in detection accuracy is suppressed.

As for the vertical Hall element according to any one of claims 1 to 23 , as in the invention according to claim 24 ,
A structure in which the semiconductor substrate is N-type and the semiconductor region is P-type,
Or like invention of Claim 25 ,
A structure in which the semiconductor substrate is P-type and the semiconductor region is N-type,
It is preferable to adopt such a structure.

Furthermore, in the vertical Hall element according to any one of claims 1 to 25 including these structures, the semiconductor substrate is caused by a piezoresistive effect as in the invention according to claim 26. By making the cut surface in a plane orientation that makes the resistance change accompanying the applied stress smaller than other plane orientations, for example, the above-mentioned phenomenon caused by stress application (piezoresistive effect) during packaging or the like This is also suitably reduced for the offset voltage.

For example, when the semiconductor substrate is a silicon substrate, as the substrate according to the invention described in claim 27 , by adopting a substrate whose cut surface is a (100) surface, the stress can be applied. The occurrence of the offset voltage due to this is suitably suppressed.

Moreover, regarding the material of the semiconductor substrate in the vertical Hall element according to any one of claims 1 to 26 , for example, according to the invention of claim 28 ,
・ One of silicon and germanium,
Alternatively, according to the invention of claim 29 ,
・ Compound semiconductors,
And so on. Furthermore, with regard to the material according to claim 29 , as in accordance with the invention according to claim 30 ,
Any one of GaAs and InSb and InAs,
Is desirable. These materials are excellent in temperature characteristics and the like, and are particularly effective for increasing the sensitivity of the Hall element.

Further, in the invention according to claim 31, in the vertical Hall element according to any one of the preceding claims 1 to 30, a plurality of elements that are electrically connected in series are integrated into a single chip magnetic Let the sensor be configured.

  By connecting a plurality of Hall elements in series in this way, the output voltage (Hall voltage signal) of the entire sensor is increased, and the magnetic detection sensitivity (so-called product sensitivity) of the magnetic sensor is greatly increased. .

On the other hand, in the invention according to claim 32 , in the vertical Hall element according to any one of claims 1 to 30 , a plurality of elements that are electrically connected in parallel are integrated on one chip to generate a magnetic field. Let the sensor be configured.

  By connecting a plurality of Hall elements in parallel in this way, the output voltage (Hall voltage signal) as a whole sensor and further the offset voltage (unbalanced voltage) are averaged, and the magnetic detection accuracy as the magnetic sensor is increased. It will be kept high.

In addition, the vertical Hall element according to any one of claims 1 to 32 is paired with another element arranged in an opposing manner as in the invention according to claim 33. By integrating them into a single chip to form a magnetic sensor, the output voltages (Hall voltages) of the Hall elements that are arranged opposite to each other and that are paired with each other can be averaged, and the output of these Hall elements It is possible to increase the detection accuracy as a magnetic sensor by switching between and the like.

Also, in this case, as in the invention described in claim 34 , the two elements forming the pair are both inclined by 45 ° with respect to the side surface of the substrate cut out as a chip. It becomes difficult to be affected by various stresses applied from the outside of the element. Thereby, the offset voltage of each Hall element is suitably reduced, and the detection accuracy as a magnetic sensor is further enhanced.

As for the vertical Hall element according to any one of the claims 1 to 34, such as by the invention of claim 35, the plurality of elements are integrated into one chip, and a plurality of these It is effective to have a structure in which the elements are arranged in a crystal orientation that makes the atomic arrangement of the semiconductor substrate equal.

  Usually, the output voltage (Hall voltage signal) of the Hall element is proportional to the carrier mobility of the magnetic detector (Hall plate). Such carrier mobility tends to depend on the crystal structure (more specifically, atomic arrangement). The influence of the piezoresistive effect accompanying the application of stress from the outside of the element also tends to depend on the crystal structure. For this reason, when a plurality of Hall elements are integrated on one chip (the same substrate), it is important to arrange the Hall elements in which crystal orientation (plane orientation) of the substrate. In this regard, if the Hall elements are arranged in a crystal orientation that makes the atomic arrangement of the semiconductor substrate equal as in the above-described structure, good pairing can be obtained for these Hall elements. In other words, variations in the output voltage (Hall voltage signal) and resistance change accompanying the application of stress due to the piezoresistive effect are suppressed among these Hall elements, so that high detection accuracy can be obtained as a magnetic sensor. Become.

In the vertical Hall element according to any one of claims 1 to 35 , as in the invention according to claim 36 , a plurality of elements are integrated in one chip close to each other, and By adopting a structure in which trench isolation is provided in such a manner as to surround the plurality of adjacent devices, the influence of various mechanical stresses applied from the outside of the device is mitigated by the surrounding trench isolation. Thus, better pairing can be obtained.

Further, regarding the vertical Hall element according to any one of claims 1 to 36 , for example, according to the invention of claim 37 ,
A structure in which a magnetic sensor is configured by integrating a plurality of elements on one chip in a manner to detect magnetic fields applied from different angles,
Alternatively, according to the invention of claim 38 ,
-Three-dimensional magnetism for detecting magnetic fields from three axes orthogonal to each other by integrating two orthogonally arranged elements together with a horizontal Hall element that detects a magnetic field component perpendicular to the surface of the semiconductor substrate. A structure to configure the sensor,
A required magnetic sensor can be realized with such a structure.

According to the invention of claim 39 , the vertical Hall element according to any one of Claims 1 to 38 is subjected to predetermined signal processing for the Hall voltage signal output from the Hall element. If the signal processing circuit that integrates the signal processing circuit and the signal processing circuit are integrated on a single chip to form a magnetic sensor that detects a magnetic field applied from a predetermined direction, the required magnetic sensor has a simple structure as a so-called Hall IC. Can be formed.

According to the invention of claim 40 , it is effective that the vertical Hall element according to any one of claims 1 to 39 has a CMOS circuit as a peripheral circuit.
As described above, these structures have a feature that they can be easily formed by a normal CMOS process. For this reason, it is desirable that the peripheral circuit provided around the element according to the application and function as, for example, a signal processing circuit, an offset voltage correction circuit, a temperature compensation circuit, or the like is realized by a CMOS circuit .

A first embodiment of a vertical Hall element and a method for manufacturing the same according to the present invention will be described below.
First, the schematic structure of the vertical Hall element according to this embodiment will be described with reference to FIG. In FIG. 1, FIG. 1 (a) is a plan view schematically showing the planar structure of the Hall element, and FIG. 1 (b) is a cross-sectional view taken along line L1-L1 in FIG. 1 (a). 1 (c) is a cross-sectional view taken along line L2-L2 of FIG. 1 (a).

  As shown in FIGS. 1A to 1C, this Hall element is formed on a P-type silicon substrate (P-sub) having a (100) plane as a cut surface, that is, from a single conductivity type. Formed on the semiconductor substrate. Specifically, the Hall element is formed as a diffusion layer (well) by introducing, for example, a semiconductor layer (P-sub) 11 made of, for example, P-type silicon, and an N-type conductive impurity into the substrate surface. An N type semiconductor region (N well) 12 is included. More specifically, the semiconductor region 12 is formed so as to be surrounded by the semiconductor substrate (semiconductor layer 11).

  By the way, in the silicon substrate, the plane orientation (100) corresponds to a plane orientation that makes a resistance change accompanying stress application caused by the piezoresistance effect smaller than other plane orientations. For this reason, as described above, by adopting a silicon substrate having a (100) plane as a semiconductor substrate as a semiconductor substrate, offset voltage generated due to application of stress (piezoresistive effect), for example, during packaging. Will be reduced.

In addition, since a semiconductor material such as silicon has a higher carrier mobility in a semiconductor made of N-type than a semiconductor made of P-type, an N-type semiconductor material (for example, silicon) is used as the material of the semiconductor region 12. It is desirable. However, it is also possible to employ a P-type semiconductor material (P ⁻ layer) in accordance with the manufacturing process and structural conditions. Further, as the impurity concentration in the semiconductor region 12 is lower (thinner), the carrier mobility in the same region is increased. Therefore, in order to increase sensitivity as a magnetic detection element, that is, to obtain a large voltage as an output voltage, the same semiconductor It is desirable to reduce (thinner) the impurity concentration of the region 12. However, on the other hand, as the carrier mobility of the semiconductor region 12 increases, the temperature characteristics of the Hall voltage generated here deteriorates conversely (the voltage change accompanying the temperature change increases). It is more desirable to set the concentration to an optimum value in consideration of these. The impurity concentration of the semiconductor region 12 is set to, for example, “1.0 × 10 ¹⁴ / cm ^{3 to} 1.0 × 10 ¹⁷ / cm ³ ”.

Also in this Hall element, a P-type diffusion layer (P-type diffusion separation wall) 14 is formed in the semiconductor layer 11 so as to isolate the Hall element from other elements. Then, in the region (active region) surrounded by the diffusion layer 14 on the surface of the semiconductor region 12, the contact region (N ⁺ diffusion layer) is formed in such a manner that the impurity concentration (N type) on the surface is selectively increased. ) 13a to 13e are formed. As a result, a good ohmic contact is formed between each of these contact regions and the electrode (wiring) disposed there. These contact regions 13a to 13e are electrically connected to terminals S, G1, G2, V1, and V2, respectively, through respective electrodes (wirings) disposed there. In this Hall element, the contact regions 13b and 13c are paired with the contact region 13a to form a current supply pair. On the other hand, the contact regions 13d and 13e are connected to each end of the voltage output pair. It corresponds to the part.

  In addition, as shown in FIG. 1A, the region (active region) surrounded by the diffusion layer 14 is formed by a P-type diffusion layer (P-type diffusion separation wall) 14a and pn junction isolation by each diffusion layer. 14b is divided into regions 12a to 12c that are separated from each other. Here, the diffusion layers 14a and 14b have a diffusion depth shallower than that of the semiconductor region 12, and selectively narrow the vicinity of the bottom surface of the semiconductor region 12 to form a current path. As shown in FIG. 1C, in the regions 12a to 12c, regions that are electrically partitioned are formed even inside the substrate.

  More specifically, in these regions, the contact regions 13a, 13d and 13e are formed in the region (element region) 12a, the contact region 13b is formed in the region 12b, and the contact region 13c is formed in the region 12c. The contact region 13a is arranged so as to be sandwiched between both the contact regions 13b and 13c and the contact regions 13d and 13e orthogonal to the contact regions. That is, the contact region 13a is arranged to face each of the contact regions 13b and 13c with the diffusion layers 14a and 14b interposed therebetween.

  In this Hall element, a region that is electrically partitioned inside the substrate of the region 12a and is sandwiched between the contact regions 13d and 13e is a so-called magnetic detection unit (hole plate) HP. That is, in this Hall element, a Hall voltage signal corresponding to the magnetic field applied here is generated. Here, the contact region 13a corresponding to one end of the current supply pair is sandwiched between the contact regions 13d and 13e corresponding to the voltage output pair, and the contact regions 13b and 13c corresponding to the other end of the current supply pair are The output pairs are arranged in line symmetry. As a result, the Hall voltage generated with respect to the current flowing in the lateral direction in the magnetic detection unit HP (current component flowing in parallel to the substrate surface) is canceled out, and as a result, the magnetic field component to be detected, that is, the magnetic field component parallel to the substrate surface. Can be detected with high accuracy. Further, since the diffusion layers 14a and 14b are provided, the current in the lateral direction (direction parallel to the substrate surface) is blocked by these, thereby improving the detection accuracy.

Here, for example, when a constant driving current is passed from the terminal S to the terminal G1 and from the terminal S to the terminal G2, the current flows from the contact region 13a formed on the substrate surface to the magnetic detection unit HP and the diffusion layer. It flows to the contact regions 13b and 13c through the lower part of 14a and 14b, respectively. That is, in this case, a current including a component perpendicular to the substrate surface (chip surface) flows through the magnetic detection unit HP. For this reason, in the state where this driving current is applied, a magnetic field (for example, a magnetic field indicated by an arrow B in FIG. 1) including a component parallel to the substrate surface (chip surface) is applied to the magnetic detection unit HP of the Hall element. If this is the case, the Hall voltage V _H corresponding to the magnetic field is generated between the terminal V1 and the terminal V2 due to the Hall effect described above. Therefore, by detecting the generated Hall voltage signal through these terminals V1 and V2, the magnetic field component to be detected based on the previous relational expression “V _H = (R _H IB / d) cos θ” shown in FIG. That is, a magnetic field component parallel to the surface (chip surface) of the substrate used for the Hall element is required. Incidentally, in this Hall element, the dimension d shown in FIG. 1 corresponds to the thickness (“d” in the above relational expression) of the magnetic detection part (Hall plate). In addition, the direction in which the drive current flows in the Hall element is arbitrary, and the magnetic field (magnetism) can be detected with the direction of the drive current being reversed.

  As described above, in the vertical Hall element according to this embodiment, the semiconductor region 12 is formed as a diffusion layer (well) by adding and diffusing an N-type conductivity impurity on the surface of the semiconductor substrate (semiconductor layer 11). I tried to do it. As seen in this embodiment, this makes it possible to adopt a substrate of a single conductivity type as a substrate (semiconductor substrate) of the Hall element. That is, the degree of freedom in selecting the substrate used for forming the Hall element is increased. In addition, in the vertical Hall element according to this embodiment, the buried layer as the lower electrode (for example, the buried layer BL in FIG. 43 or 44) is not formed. This does not cause misalignment (alignment misalignment) due to the mask alignment error and increase in offset voltage due to this. The buried layer made of the diffusion layer has a rate of change in resistance temperature (Ω / ° C.) correlated with the impurity concentration. The impurity concentration of the buried layer is affected by the manufacturing conditions when forming the buried layer. For this reason, for example, when mass production of Hall elements having the above-mentioned buried layer or when many such Hall elements are formed on the same substrate, the impurity concentration of the buried layer varies among these elements. This is inevitable, that is, the temperature characteristics (temperature coefficient) of the magnetic detection sensitivity vary among the elements. Further, in a Hall element including a temperature compensation circuit that compensates for such variations in temperature characteristics, an increase in the circuit scale is inevitable. In this respect, the vertical Hall element according to this embodiment is excellent in terms of temperature characteristics because the buried layer formed of the diffusion layer is not formed.

  Next, the structure of the Hall element, that is, the concentration distribution (concentration profile) of the semiconductor region 12 and each separation wall will be described in more detail with reference to FIG. 2 is a perspective view when the vertical Hall element shown in FIG. 1 is cut out so as to expose a cross section along line L2-L2 in FIG. In FIG. 2, the same elements as those shown in FIG. 1 are denoted by the same reference numerals.

  By the way, when a diffusion layer is formed by adding impurities from the surface of the semiconductor substrate and diffusing it, the width of the formed diffusion layer becomes narrower as it becomes deeper from the surface of the substrate. For this reason, in the vertical Hall element in which the magnetic detection unit (hole plate) is partitioned by such a diffusion layer, for example, in the vertical Hall element illustrated in FIG. 43, the current flowing through the magnetic detection unit HP is deeper. There is a problem in that the sensitivity increases as the magnetic detection element spreads as the distance increases. In this regard, in the vertical Hall element according to this embodiment, the semiconductor region 12 having the magnetic detection part HP inside, as well as the magnetic field, as shown in FIG. The diffusion layers 14a and 14b that partition and form the detection unit HP have a concentration distribution that gradually decreases (thinner) to the substrate surface with the maximum concentration and gradually decreasing from the surface. For this reason, the width of the depletion layer depending on the concentration of these p · n regions and the width of the diffusion layers 14a and 14b that become narrower from the surface of the substrate complement each other, and the magnetic detection unit HP is placed on the surface of the substrate. It will be partitioned along a substantially vertical direction. Thereby, the spread of the current in the magnetic detection unit HP is suppressed, and the current component flowing through the magnetic detection unit HP in the direction perpendicular to the substrate surface can be relatively increased. As a result, the sensitivity ( The so-called product sensitivity can be improved.

  FIG. 3 is a cross-sectional view showing the concentration distribution of the semiconductor region 12 in more detail by further enlarging a part of the Hall element. In FIG. 3 as well, the level of impurity concentration is indicated by the density of hatching (point hatching) (higher density means higher density). Moreover, the arrow in a figure has shown the direction through which an electric current flows.

  As described above and as shown in FIG. 3, the semiconductor region 12 is formed in such a manner that it has the highest concentration on the surface of the semiconductor substrate and decreases in concentration from the front surface to the back surface side. Here, for example, if a current is supplied from the contact region 13a to the contact region 13c, the current flows through a portion having a lower resistance (a lower portion), that is, a portion having a high impurity concentration. That is, as shown by the arrow in FIG. 3, this current passes directly under the diffusion layer 14b and flows in a direction oblique to the substrate surface in the magnetic detection unit HP.

  Incidentally, in the vertical Hall element exemplified in FIG. 43, the semiconductor region 32 is formed as an epitaxial layer. That is, the concentration distribution in the semiconductor region 32 is substantially constant, and the change in the width of the depletion layer in the depth direction cannot be sufficiently obtained, and the above-described sensitivity reduction due to the spread of current is inevitable. ing. On the other hand, in the vertical Hall element illustrated in FIG. 44, the spread of the current is somewhat suppressed by reducing the width of the buried layer BL. However, since the layout of the buried layer BL is changed, there is a concern that the offset voltage (unbalanced voltage) may be increased. According to the vertical Hall element according to this embodiment, the sensitivity as the magnetic detection element can be improved without increasing the offset voltage.

  2 indicates the width of the current path formed in the vicinity of the bottom surface of the semiconductor region 12 by the diffusion layers 14a and 14b, more specifically the width in the depth direction. In order to increase the sensitivity of the Hall element, it is effective to form the diffusion layers 14a and 14b deeply, that is, to narrow the width dimension a of the current path. This has been confirmed by the inventors' experiments and simulations.

  FIG. 4 shows one of the simulation results by the inventor as a graph. In the graph of FIG. 4, the vertical axis indicates the Hall voltage, and the horizontal axis indicates the diffusion depth (Xj) of the diffusion layers (P wells) 14a and 14b.

  As shown in FIG. 4, when the diffusion depth of the diffusion layers 14a and 14b is “2 μm” or more, the output voltage (Hall voltage) increases. Furthermore, the ratio of the increase is clearly increased at the point where “3 μm” or more is reached. Therefore, in the vertical Hall element according to this embodiment, the diffusion layers 14a and 14b are formed with a diffusion depth of at least “2 μm” or more. As is apparent from the graph of FIG. 4, by doing this, the spread of the current flowing in the magnetic detection unit HP in the lateral direction (direction parallel to the substrate surface) is effectively suppressed, and the sensitivity as the magnetic detection element. Improvement will be achieved. More preferably, it is desirable that the diffusion depth of the diffusion layers 14a and 14b be “3 μm” or more.

  In this embodiment, a signal processing circuit that performs predetermined signal processing on the Hall voltage signal output from the Hall element, a correction circuit that performs calculation correction of the offset voltage, a temperature compensation circuit, and the like are provided. A magnetic sensor provided as a peripheral circuit of the Hall element is assumed. FIG. 5 is a plan view schematically showing a schematic structure of the Hall element including such peripheral circuits. 5A is a plan view of the Hall element, and FIG. 5B is a cross-sectional view taken along line L1-L1 in FIG. 5A. Also in FIG. 5, the same elements as those shown in FIG. 1 are denoted by the same reference numerals.

As shown in FIG. 5, in this embodiment, a circuit (circuit unit) C <b> 10 including a complementary metal oxide semiconductor (CMOS) circuit or the like is employed as a peripheral circuit of the Hall element 10. The circuit C10 includes a semiconductor layer 11, an N-type semiconductor region (N-well) C12, a P-type diffusion layer (P-well) C13, and FETs (Field Effect Transistors) each having a channel. ing. These FETs are configured to have N-type diffusion layers (N ⁺ diffusion layers) C13a to C13d and P-type diffusion layers (P ⁺ diffusion layers) C13e and C13f as sources and drains. Further, in order to control the amount of current between the source and the drain by applying a voltage to the channel, gate insulating films I1a to I1c made of, for example, silicon oxide, and gate electrodes G1a to G1c made of, for example, polycrystalline silicon are further provided. . These FETs are isolated from each other by a field oxide film (LOCOS oxide film) CL1 having a LOCOS (Local Oxidation Of Silicon) structure. Further thereon, an insulating film 15 made of, for example, PSG (Phospho Silicate Glass) or the like is formed. The diffusion layers C13a to C13f are electrically connected to wirings (electrodes) C16a to C16f made of, for example, aluminum through contact holes formed in the insulating film 15, respectively.

Thus, the vertical Hall element according to this embodiment has a CMOS circuit as its peripheral circuit. As a result, the following effects can be expected.
Since miniaturization, that is, high integration is possible, for example, when used as a correction circuit, it is possible to perform high-precision correction for the Hall element.
・ High-speed circuits can be incorporated. For example, when the Hall element is used for a rotation sensor or the like, it may be required to detect high-speed rotation or the like with high accuracy. Even in such a case, if a CMOS circuit is used as the peripheral circuit, the response speed can be increased by incorporating a high-speed circuit, and high-speed rotation or the like can be accurately detected.
・ Low power consumption. That is, by using a CMOS circuit as a peripheral circuit, power consumption including standby power can be suppressed, and energy saving can be achieved. In addition, the battery and the like can be prolonged.
Furthermore, since high integration is possible, the cost per chip can be suppressed by making the peripheral circuit into one chip together with the Hall element. That is, the cost can be reduced.

  Further, in the vertical Hall element according to this embodiment, the Hall voltage signal output from the contact regions 13d and 13e (FIG. 1) corresponding to the voltage output pair is output via the wiring whose resistance value is variable. It has become so. 6 and 7 schematically show the arrangement of such wiring. FIG. 6 is a circuit diagram showing this as a mode common to all the Hall elements, and FIG. 7 is a more specific example when actually applied to the vertical Hall element according to this embodiment. It is a circuit diagram which shows this. The resistors R in these drawings all have the same resistance value.

  As shown in FIGS. 6 and 7, in this embodiment, the vertical Hall element 10 and the voltage output terminals V1 and V2 (voltage output pair) are electrically connected in parallel to each other. A plurality of wires having different resistance values are inserted. The plurality of wirings connected in parallel can be disconnected temporarily and permanently by the switching elements SW11 to SW14 and SW21 to SW24, respectively. That is, by controlling on / off of these switching elements SW11 to SW14 and SW21 to SW24, any of the plurality of wirings connected in parallel or a combination thereof can be arbitrarily selected. Therefore, when some output voltage, that is, an offset voltage is generated when no magnetic field is applied, the voltage output terminals V1 and V2 (voltage output pair) are interposed through the selection. With the wiring to be inserted as a desired resistance value, the offset voltage can be corrected so as to approach “0V”. Thus, the vertical Hall element according to this embodiment can correct and reduce the offset voltage (unbalanced voltage).

  Next, with reference to FIG. 8 and FIG. 9, the manufacturing method of the vertical Hall element according to this embodiment will be described in detail. Each of these figures is a cross-sectional view corresponding to the cross-sectional view of FIG. 5 (b), and the same elements as those shown in FIG. 5 (b) are denoted by the same reference numerals. Show. That is, a manufacturing method in the case where the circuit (circuit part) C10 as a peripheral circuit and the Hall element (Hall element part) 10 are simultaneously formed will be described.

  In this manufacturing, first, as shown in FIG. 8A, for example, a substrate (semiconductor layer 11) made of P-type silicon having a (100) plane as a cut surface is prepared. Then, as shown in FIG. 8B, after performing ion implantation of N-type impurities such as phosphorus on the surface of the semiconductor layer 11 using an appropriate mask patterned by, for example, photolithography, This is subjected to appropriate heat treatment to form N-type semiconductor regions 12 and C12 as diffusion layers (N wells).

  Thereafter, as shown in FIG. 8C, ion implantation of a P-type impurity made of, for example, boron (boron) or the like is performed at a desired location using an appropriate mask patterned by, for example, photolithography. Appropriate heat treatment is performed to form P type diffusion layers (P wells) 14 and 14a and 14b and a diffusion layer (P well) C13.

  At this time, the impurity concentrations of the semiconductor region 12 and the diffusion layers 14a and 14b are adjusted so that a current path is secured in the vicinity of the bottom surface of the semiconductor region 12 even after the depletion layer is formed therebetween. As a result, the width of the depletion layer formed between them is set to an appropriate width so that the current path is not blocked, and the above-described buried layer (see FIG. 43 or FIG. 44) is not provided. Even in this case, the function as the vertical Hall element is properly maintained. According to this manufacturing method, the current path can be easily secured simply by adjusting the impurity concentration.

  Next, in order to obtain the structure shown in FIG. 9A, a field oxide film (LOCOS oxide film) CL1 having a LOCOS structure is selectively formed at a desired location by, for example, a well-known selective oxidation method. Specifically, a silicon oxide film (pad oxide film) and a silicon nitride film are sequentially formed, and the silicon nitride film is selectively removed by, for example, photolithography to form an opening at a desired location. Then, only the opening that is not covered with the silicon nitride film is locally thermally oxidized to form the LOCOS oxide film CL1, and the silicon oxide film (pad oxide film) and the silicon nitride film thus formed are formed. Remove.

  Subsequently, after forming gate insulating films I1a to I1c made of silicon oxide or the like by, for example, thermal oxidation, gate electrodes G1a to G1c made of, for example, polycrystalline silicon are formed on the gate insulating films I1a to I1c, respectively. . Specifically, for example, a polycrystalline silicon film is formed by LP-CVD (low pressure chemical vapor deposition), and a conductive impurity such as phosphorus (P) is formed on the formed polycrystalline silicon film by thermal diffusion, for example. Added. Thereafter, the polycrystalline silicon film is selectively etched to form the gate electrodes G1a to G1c at desired locations.

  Next, after performing ion implantation of an N-type impurity made of, for example, arsenic or the like and a P-type impurity made of, for example, boron (boron) or the like in a desired portion using an appropriate mask patterned by, for example, photolithography. Is subjected to an appropriate heat treatment. Thus, as shown in FIG. 9B, contact regions 13a to 13e (here, only the contact regions 13a to 13c are shown for convenience) and diffusion layers (source / drain) C13a to C13f are formed. The diffusion layers C13a to C13f can also be formed in a self-aligned manner using the LOCOS oxide film CL1 or the gate electrodes G1a to G1c as a mask. At this time, sidewalls, silicide, and the like are also formed as necessary.

  Furthermore, an insulating film 15 made of PSG (Phospho Silicate Glass) or the like is formed thereon by, for example, thermal CVD, and the insulating film 15 is appropriately patterned to form a contact hole at a desired location. Then, a wiring material made of, for example, aluminum or the like is formed into a film so as to fill the contact holes, and the formed wiring material is appropriately patterned. Thus, as shown in FIG. 9C, wirings (electrodes) 16a to 16c and C16a to C16f that form good ohmic contacts with the contact region and the diffusion layer (source / drain) are formed. It will be. As a result, the vertical Hall element and its peripheral circuit shown in FIG. 5 are completed.

  As described above, in the manufacturing method of the vertical Hall element according to this embodiment, the Hall element 10 is manufactured in the form of sharing the manufacturing process of the CMOS circuit (circuit C10) as the peripheral circuit. As a result, the number of manufacturing steps of the Hall element can be greatly reduced.

As described above, according to the vertical Hall element and the manufacturing method thereof according to this embodiment, many excellent effects as described below can be obtained.
(1) The semiconductor region 12 is made of a diffusion layer (N well) formed by adding and diffusing conductive impurities to a semiconductor substrate. As a result, even a substrate of a single conductivity type can be employed as the Hall element substrate (semiconductor substrate). That is, it is possible to greatly increase the degree of freedom in selecting a substrate used for the Hall element.

  (2) A semiconductor substrate of a single conductivity type is used as the Hall element substrate. A semiconductor substrate having a single conductivity type is usually available at a lower price (lower cost) than the above-described epitaxial substrate. That is, according to the above structure, the cost can be reduced.

  (3) The semiconductor region 12 is formed in such a manner that the highest concentration is formed on the surface of the semiconductor substrate, and the concentration becomes lower as the surface proceeds from the front surface to the back surface side. Thus, as described in this embodiment, the semiconductor region 12 can be easily formed by a known semiconductor process, for example, by diffusing conductive impurities introduced into the substrate surface by ion implantation or the like by heat treatment. become.

  (4) The N-type semiconductor region 12 is formed so as to be surrounded by the P-type semiconductor substrate (semiconductor layer 11). As a result, a pn junction is formed between the semiconductor region 12 and the semiconductor substrate, and the semiconductor region 12 having the magnetic detection part HP inside becomes a region electrically separated from the surrounding region. That is, the Hall element is preferably separated from the peripheral circuit and the like.

  (5) P-type diffusion layers (diffusion separation walls) 14a and 14b that selectively narrow the vicinity of the bottom surface of the semiconductor region 12 to form a current path are formed in the N-type semiconductor region 12. The diffusion layers The magnetic detection unit HP is electrically partitioned by 14a and 14b. Thereby, the magnetic detection part HP is partitioned and formed in the semiconductor region 12 by the diffusion layers 14 a and 14 b, and a current path is reliably ensured near the bottom surface of the semiconductor region 12. And the original function as a vertical Hall element of detecting a magnetic field component parallel to the substrate surface (chip surface) is maintained high. Moreover, since the diffusion layers 14a and 14b can be easily formed by a normal CMOS process, the semiconductor region 12, the diffusion layers 14a and 14b, and the Hall element itself are easily manufactured by a normal CMOS process. It becomes possible.

  (6) P-type diffusion layers 14a and 14b are formed in the N-type semiconductor region 12 with a diffusion depth shallower than that of the semiconductor region 12, and the magnetic detection unit HP is electrically connected by the diffusion layers 14a and 14b. The structure was divided into two. Also by this, the effect similar to the effect of said (5) is acquired.

  (7) The diffusion layers 14a and 14b are formed with a diffusion depth of at least “2 μm” or more. By doing so, the spread of the current flowing through the magnetic detection unit HP in the lateral direction (direction parallel to the substrate surface) is effectively suppressed, and the sensitivity as a magnetic detection element is improved (FIG. 4). See the graph). More preferably, the diffusion depth of the diffusion layers 14a and 14b is set to “3 μm” or more.

  (8) The diffusion layers 14a and 14b are formed in such a manner that the maximum concentration is formed on the surface of the semiconductor substrate, and the concentration becomes lower as it proceeds from the front surface to the back surface side. Thereby, the spread of current in the magnetic detection unit HP is suppressed, and the current component flowing in the magnetic detection unit HP in the direction perpendicular to the substrate surface can be relatively increased. As a result, the sensitivity (so-called magnetic detection element) (Product sensitivity) is improved.

  (9) Further, as a manufacturing method for realizing these structures, the impurity concentration of the semiconductor region 12 and the diffusion layers 14a and 14b is set close to the bottom surface of the semiconductor region 12 even after the depletion layer is formed therebetween. Adjustments were made to ensure a current path. As a result, a current path is easily secured in the vicinity of the bottom surface of the semiconductor region 12. Moreover, in this method, the current path can be secured only by adjusting the impurity concentration.

  (10) A current supply pair and a voltage output pair are provided on the surface of the semiconductor region 12 with respect to a current including a component perpendicular to the substrate surface that is supplied from one end of the current supply pair and flows to the magnetic detector HP When a magnetic field component parallel to the substrate surface is applied, a Hall voltage signal corresponding to the magnetic field component is output to both ends of the voltage output pair. By adopting such a structure, a vertical Hall element can be realized in a form suitable for practical use in manufacturing the element and also in terms of performance as a magnetic detection element.

  (11) The contact region 13a corresponding to one end of the current supply pair is arranged between the contact regions 13d and 13e corresponding to the voltage output pair. As a result, the Hall voltage generated for the current flowing through the magnetic detection unit HP can be reliably captured through the voltage output pair.

  (12) The contact region 13a corresponding to one end of the current supply pair is sandwiched between the contact regions 13d and 13e corresponding to the voltage output pair, and the contact regions 13b and 13c corresponding to the other end of the current supply pair are The voltage output pair was arranged symmetrically. As a result, the magnetic field component to be detected can be accurately detected.

  (13) The current supply pair and the voltage output pair are arranged (layout) so as to be orthogonal to each other. According to such a layout, good element characteristics can be obtained with a simple element design.

(14) The ends of the current supply pair and the voltage output pair are formed as contact regions (N ⁺ diffusion layers) 13a to 13e, that is, as portions where the impurity concentration is selectively increased on the surface of the semiconductor region 12. I did it. As a result, a good ohmic contact is formed between the electrodes (wirings) disposed in these regions in order to supply or take out current or to detect the Hall voltage.

  (15) The Hall voltage signal output from the contact regions 13d and 13e corresponding to the voltage output pair is output via a wiring whose resistance value is variable. At this time, as a part of the lead wiring to the voltage output terminals V1 and V2 (voltage output pair), different resistors electrically connected in parallel with each other in a manner that can be temporarily and permanently disconnected. A plurality of wirings having values are provided. As a result, the offset voltage (unbalanced voltage) can be corrected and reduced.

  (16) A structure in which a current including a component perpendicular to the substrate surface (chip surface) is guided to flow in an oblique direction with respect to the substrate surface at least in the magnetic detection unit HP. According to such a structure, a current including a component perpendicular to the substrate surface (current in an oblique direction) is supplied to the magnetic detection unit HP, so that the original function as a vertical Hall element is maintained and This also greatly increases the degree of freedom of design related to elements that have been constrained up to now due to the flow of a vertical current.

  (17) A silicon substrate having a (100) plane as a cut surface is employed as the semiconductor substrate. As a result, for example, the offset voltage generated due to the application of stress during packaging or the like is suitably reduced.

  (18) Si (silicon) is adopted as a material for the semiconductor substrate used for the Hall element. As is well known, silicon is a widely used material in the semiconductor field. It is a material suitable for a semiconductor device in various aspects such as electrical characteristics and cost, and the Hall element is no exception.

  (19) The structure has no buried layer (see FIGS. 43 and 44). As a result, the occurrence of the offset voltage is suppressed, and variations in temperature characteristics (temperature coefficient) relating to the magnetic detection sensitivity are reduced, and thus the temperature compensation circuit can be reduced in size and size.

  (20) A magnet that integrates the Hall element on one chip together with a signal processing circuit that performs predetermined signal processing on the Hall voltage signal output from the Hall element, and detects a magnetic field applied from a predetermined direction. The sensor was configured. As a result, a magnetic sensor suitable for use in the aforementioned angle detection sensor or the like can be realized as a so-called Hall IC with a simple structure.

  (21) The peripheral circuit includes a circuit C10 made of a CMOS circuit. As a result, it is possible to manufacture the Hall element by sharing the manufacturing process of the CMOS circuit as the peripheral circuit.

(22) According to such a manufacturing method, the number of manufacturing steps can be greatly reduced.
(23) The semiconductor region 12 is formed by adding and diffusing conductive impurities to the semiconductor substrate. According to such a manufacturing method, a vertical Hall element can be formed (manufactured) on an epitaxial substrate, an SOI (Silicon On Insulator) substrate, etc. as well as a substrate having a single conductivity type. The degree of freedom of selection of the substrate used for manufacturing the Hall element can be greatly increased.

  (24) At this time, after ion implantation is performed on the surface of the semiconductor substrate to add an N-type impurity, the semiconductor region 12 is formed by performing heat treatment on the surface to diffuse the N-type impurity. did. According to such a method, it is possible to easily form the semiconductor region 12 having a concentration distribution such that the concentration on the surface of the substrate becomes lower as it progresses from the front surface to the back surface by a known semiconductor process. become able to. Since this structure can be realized by a very simple and inexpensive manufacturing process, it is particularly suitable for use in mass production of the Hall element.

  In the first embodiment, the impurity concentration of the semiconductor region 12 and the diffusion layers 14a and 14b is set so that a current path is secured in the vicinity of the bottom surface of the semiconductor region 12 even after the depletion layer is formed therebetween. The manufacturing method of adjusting as described is exemplified. However, this is not an essential process. For example, when the diffusion layers 14a and 14b are formed by a well-known ion implantation method, the energy at the time of implantation is adjusted to be near the bottom surface of the semiconductor region 12. A current path can be secured.

  Moreover, in the said 1st Embodiment, the manufacturing method which manufactures the said Hall element by sharing the manufacturing process of the CMOS circuit as a peripheral circuit was illustrated. However, this is not an essential process, and both can be formed separately.

  In the first embodiment, the voltage output terminals V1 and V2 (voltage output pair) are temporarily switched by the switching elements SW11 to SW14 and SW21 to SW24, respectively, as part of the lead-out wiring to both terminals. A plurality of wirings having different resistance values that are electrically and permanently connected to each other are provided. However, the present invention is not limited to this, and instead of the switching element, for example, a fuse that is disconnected by an overcurrent or a thin film resistor that can be disconnected by trimming can be used. Furthermore, it is not necessary that the wiring at both ends of the voltage output pair be such wiring, and it is sufficient if at least one wiring is such wiring. The point is that the Hall voltage signal is output at least at one end of the voltage output pair through a wiring whose resistance value is variable, that is, even when a variable resistance element or the like is used as appropriate, for example. An effect similar to or equivalent to the effect of (15) can be obtained.

  In the first embodiment, the diffusion layers 14a and 14b have a diffusion depth of at least “2 μm” in order to improve the sensitivity as the magnetic detection element. And the diffusion depth of 14b is basically arbitrary.

  In the vertical Hall element according to the first embodiment, the concentration distribution of the semiconductor region 12 is the concentration distribution as shown in FIG. 3, that is, the highest concentration on the substrate surface from the same surface to the back surface side. The concentration distribution was such that the concentration became lower as it proceeded. However, the present invention is not limited to this. For example, as shown in FIG. 10, the concentration distribution of the semiconductor region 12 may be a concentration distribution in which the concentration increases toward the back side from the same surface with the lowest concentration on the substrate surface. . A modification of the vertical Hall element according to the first embodiment will be described below with reference to FIG. In FIG. 10, the level of impurity concentration is indicated by the density of hatching (dot hatching) (higher density means higher density).

  In such a structure, for example, if a current is supplied from the contact region 13a to the contact region 13c, a current mainly containing a component perpendicular to the substrate surface flows in the magnetic detection unit HP as indicated by an arrow in FIG. It becomes like this. Further, here, a diffusion stopper film ST is provided in the semiconductor region 12, and the semiconductor region 12 is moved away from the diffusion stopper film ST with the highest concentration in a portion facing the diffusion stopper film ST (proceeding to the substrate surface side). It is assumed that it is formed in such a manner that the concentration becomes lower as the temperature increases.

According to such a structure, the following effects are produced.
(25) The semiconductor region 12 is formed on the surface of the semiconductor substrate with the lowest concentration and increasing in concentration from the front surface to the back surface. According to such a structure, the current component flowing in the direction perpendicular to the substrate surface in the magnetic detection unit HP can be relatively increased, and as a result, the sensitivity (so-called product sensitivity) as the magnetic detection element can be improved. It becomes like this.

  (26) The semiconductor region 12 is provided with a diffusion stopper film ST, and the semiconductor region 12 is formed in such a manner that the concentration decreases toward the portion facing the diffusion stopper film ST with the highest concentration as the distance from the diffusion stopper film ST increases. It was supposed to be. According to such a structure, the concentration change in the depth direction of the semiconductor region 12 can be easily formed with a high degree of freedom in designing the concentration distribution.

  11 and 12 are cross-sectional views showing an example of a manufacturing process for the vertical Hall element exemplified in FIG. First, an example of the manufacturing process will be described with reference to FIG.

  As shown in FIG. 11A, in this manufacturing, first, a substrate made of, for example, P-type silicon (semiconductor layer 11) is prepared, and, for example, ion implantation is performed on the surface side of the substrate from the same substrate. Also, a diffusion layer (diffusion stopper film ST) made of a high concentration P type and a semiconductor region H12 made of an N type diffusion layer are sequentially stacked. Then, as shown in FIG. 11B, a semiconductor region L12 made of an N-type epitaxial film having a lower concentration than the semiconductor region H12 is formed on the surface of the substrate. Furthermore, an appropriate heat treatment is performed on this to diffuse the conductive impurities contained in the semiconductor region H12 into the semiconductor region L12. Thus, that is, with this diffusion, the semiconductor region 12 is formed. Here, although the diffusion stopper film ST and the semiconductor region H12 are formed as diffusion layers (wells), they can also be formed as epitaxial films. Further, the structure is such that two layers of the diffusion stopper film ST and the semiconductor region H12 are laminated on the substrate surface side, but the number of semiconductor layers (diffusion stopper film ST and semiconductor region H12) to be laminated is arbitrary. For example, a structure in which three or more layers having different conductivity types are alternately stacked may be employed.

According to such a manufacturing method, the following effects are produced.
(27) Here, when the semiconductor region 12 is manufactured, a substrate in which high-concentration regions (diffusion stopper film ST and semiconductor region H12) with relatively high impurity concentration are alternately stacked on the surface side with different conductivity types is formed. In addition, an epitaxial film (semiconductor region L12) having a lower concentration than the semiconductor region H12 is further formed on the surface of the substrate. Then, this is subjected to heat treatment to diffuse the conductive impurities contained in the semiconductor region H12 into the semiconductor region L12. Thereby, the diffusion stopper film ST can suppress the diffusion of the conductive impurities, and the semiconductor region 12 can be easily formed by a known semiconductor process.

Next, another example of the manufacturing process will be described with reference to FIG.
As shown in FIG. 12A, at the time of manufacturing, first, a first substrate composed of a semiconductor region L12 and a semiconductor region H12 having a higher concentration than this, and a diffusion made of, for example, silicon oxide or the like. A second substrate provided with the stopper film ST is prepared. Then, as shown in FIG. 12B, the semiconductor region H12 is on the back surface side and the diffusion stopper film ST is on the front surface side, and both are bonded by a well-known bonding method. After the first and second substrates are bonded to each other, an appropriate heat treatment is applied to diffuse the conductive impurities contained in the semiconductor region H12 into the semiconductor region L12. As a result, the semiconductor region 12 is formed.

According to such a manufacturing method, the following effects are produced.
(28) Here, when the semiconductor region 12 is manufactured, a first substrate having a high concentration region (semiconductor region H12) having a relatively high impurity concentration on the back surface side and a second having a diffusion stopper film ST on the front surface side. These substrates are bonded to each other on their back and front surfaces. Then, this is subjected to heat treatment to diffuse the conductive impurities contained in the semiconductor region H12 into the semiconductor region L12. Thereby, the diffusion stopper film ST can suppress the diffusion of the conductive impurities, and the semiconductor region 12 can be easily formed by a known semiconductor process.

  Further, as shown in FIG. 13, for example, the concentration distribution of the semiconductor region 12 has a maximum concentration at a predetermined depth of the semiconductor substrate, and decreases from the substrate surface side to the substrate rear surface side. It may be. A modification of the vertical Hall element according to the first embodiment will be described below with reference to FIG. In FIG. 13 as well, the level of the impurity concentration is indicated by the density of hatching (dot hatching) (the higher the concentration, the higher the density).

  In such a structure, if a current is supplied from the contact region 13a to the contact region 13c, for example, the current flows through a portion having a lower resistance (ie, a portion having a high impurity concentration). Specifically, as indicated by an arrow in FIG. 13, this current first flows from the contact region 13a in a direction perpendicular to the substrate surface and passes through the semiconductor region having the highest concentration provided at a predetermined depth of the semiconductor substrate. After flowing below the diffusion layer 14b to the contact region 13c side, it flows toward the contact region 13c along a direction perpendicular to the substrate surface. That is, a current mainly including a component perpendicular to the substrate surface flows through the magnetic detection unit HP.

According to such a structure, the following effects are produced.
(29) The semiconductor region 12 is formed in such a manner that it has a maximum concentration at a predetermined depth of the semiconductor substrate, and decreases in concentration as it proceeds from there to the substrate surface side and substrate back side. Thereby, the current component flowing in the direction perpendicular to the substrate surface in the magnetic detection unit HP can be relatively increased, and as a result, the sensitivity (so-called product sensitivity) as the magnetic detection element can be improved. .

  14 and 15 are cross-sectional views showing an example of a manufacturing process for the vertical Hall element exemplified in FIG. First, an example of the manufacturing process will be described with reference to FIG.

  As shown in FIG. 14A, in this manufacturing process, first, a substrate (semiconductor layer 11) made of, for example, P-type silicon is prepared. Then, as shown in FIG. 14B, a semiconductor region H12 made of an N-type diffusion layer having a higher concentration than that of the substrate is formed in the substrate by, for example, high-acceleration ion implantation. Further, this is subjected to an appropriate heat treatment to diffuse the conductive impurities contained in the semiconductor region H12 to the substrate front side and the substrate back side, respectively. Thus, that is, with this diffusion, the semiconductor region 12 is formed.

According to such a manufacturing method, the following effects are produced.
(30) Here, when the semiconductor region 12 is manufactured, high-acceleration ion implantation is performed on the semiconductor substrate to form a high concentration region (semiconductor region H12) having a relatively high impurity concentration inside the substrate. And this was heat-processed and the conductive type impurity contained in the semiconductor region H12 was diffused to the surface side and back surface side of a board | substrate, respectively. According to such a method, the semiconductor region 12 can be easily formed by a well-known high-acceleration ion implantation method in manufacturing an SOI substrate.

Next, another example of the manufacturing process will be described with reference to FIG.
As shown in FIG. 15A, in this manufacture, first, a substrate made of, for example, P-type silicon (semiconductor layer 11) is prepared. A semiconductor region H12 made of a high concentration N-type diffusion layer is formed. Then, as shown in FIG. 15B, a semiconductor region L12 made of an N-type epitaxial film having a lower concentration than the semiconductor region H12 is formed on the surface of the substrate. Furthermore, an appropriate heat treatment is applied to diffuse the conductive impurities contained in the semiconductor region H12 into the semiconductor layer 11 and the semiconductor region L12, respectively. That is, the semiconductor region 12 is thereby formed. Here, the semiconductor region H12 is formed as a diffusion layer (well), but it can also be formed as an epitaxial film.

According to such a manufacturing method, the following effects are produced.
(31) Here, when the semiconductor region 12 is manufactured, a high concentration region (semiconductor region H12) having a relatively high impurity concentration is formed on the surface of the semiconductor substrate (semiconductor layer 11). Then, an epitaxial film (semiconductor region L12) having a concentration lower than that of the semiconductor region H12 is formed on the surface. Further, this was subjected to heat treatment to diffuse the conductive impurities contained in the semiconductor region H12 to the front surface side (semiconductor region L12 side) and back surface side (semiconductor layer 11 side) of the substrate. Also by such a method, the semiconductor region 12 can be easily formed by a known semiconductor process.

(Second Embodiment)
FIG. 16 shows a second embodiment of the vertical Hall element according to the present invention.
Hereinafter, with reference to FIG. 16, the structure of the vertical Hall element according to this embodiment will be described focusing on the differences from the first embodiment. 16A to 16C correspond to the previous FIGS. 1A to 1C. In FIG. 16, the same elements as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description of these elements is omitted here.

  As shown in FIGS. 16A to 16C, this vertical Hall element basically has the same structure as the vertical Hall element of the first embodiment illustrated in FIG. The operation mode and the manufacturing method thereof are as described above. However, in this embodiment, the structure is such that the diffusion layer 14 (FIG. 1) provided to isolate the Hall element from other elements is omitted. Thereby, simplification of the structure as a Hall element and miniaturization (area reduction) can be achieved. In this vertical Hall element, the semiconductor layer 11 surrounding the semiconductor region 12 plays the role of element isolation instead of the omitted diffusion layer 14.

  FIG. 17 is a perspective view showing the concentration distribution of this vertical Hall element, specifically the concentration distribution (concentration profile) of the semiconductor region 12 and the diffusion layers 14a and 14b. This is a perspective view corresponding to FIG. 2 described above, and here, the impurity concentration is indicated by the density of hatching (point hatching) (higher density means higher density).

As shown in FIG. 17, the concentration distribution of the vertical Hall element is basically the same as that of the vertical Hall element of the first embodiment, and the description thereof is omitted here.
As described above, according to the vertical Hall element according to this embodiment, in addition to the same effects as the effects (1) to (24) of the previous first embodiment or effects equivalent thereto. Further, the following effects can be obtained.

  (32) A structure in which the diffusion layer 14 provided to isolate the Hall element from other elements is omitted. Thereby, simplification of the structure as a Hall element and miniaturization (area reduction) can be achieved.

(Third embodiment)
FIG. 18 shows a third embodiment of the vertical Hall element according to the present invention.
Hereinafter, with reference to FIG. 18, the structure of the vertical Hall element according to this embodiment will be described focusing on the differences from the first embodiment. 18A to 18C also correspond to FIGS. 1A to 1C. Also in FIG. 18, the same elements as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description of these elements is omitted here.

  As shown in FIGS. 18A to 18C, this vertical Hall element basically has the same structure as the vertical Hall element of the first embodiment illustrated in FIG. The operation mode and the manufacturing method thereof are as described above. However, in this embodiment, instead of the diffusion layers 14, 14a, 14b (FIG. 1), trenches (grooves) T1, T2a embedded with insulating films IL1, IL2a, IL2b made of, for example, silicon oxide, etc. Insulating isolation walls having a so-called STI (Shallow Trench Isolation) structure are used as the isolation walls for T2b. That is, this Hall element is isolated from other elements by the insulating isolation wall formed by the insulating film IL1. In addition, the insulating isolation walls formed by the insulating films IL2a and IL2b have a depth dimension shallower than that of the semiconductor region 12, and electrically partition the magnetic detection part (hole plate) HP in the semiconductor region 12, and also the bottom surface of the semiconductor region 12 The neighborhood is selectively narrowed to form a current path there.

Below, an example of the manufacturing method of this vertical Hall element is demonstrated easily.
In this Hall element, the insulating separation walls made of the insulating films IL1, IL2a, and IL2b are formed using, for example, a well-known STI technique. That is, after a silicon oxide film (pad oxide film) and a silicon nitride film are sequentially formed on the substrate, selective etching is performed using, for example, a photolithography technique, and trenches T1, T2a, T2b is formed. Next, insulating films IL1, IL2a, and IL2b are embedded in these trenches T1, T2a, and T2b by, for example, CVD (chemical vapor deposition). At this time, the insulating film deposited outside the trench is appropriately removed by, for example, CMP (Chemical Mechanical Polishing). Thereafter, the silicon oxide film (pad oxide film) and the silicon nitride film remaining on the substrate are removed to form insulating isolation walls by the insulating films IL1, IL2a, and IL2b.

  The STI technique is used for element isolation and the like in a normal CMOS process. For this reason, as described above, an insulating isolation wall having an STI structure is adopted as the isolation wall, which can be easily formed by a normal CMOS process. In addition, since the STI technique is a technique that assumes element isolation, an insulating isolation wall having a shallower depth than the semiconductor region 12 can be easily formed.

  In addition, since the insulating isolation wall having the STI structure uses a trench, it can be easily formed (extended) perpendicular to the substrate surface. That is, the spread of current in the magnetic detection unit HP, which is a concern when the aforementioned diffusion layer is used as a separation wall, is suppressed, and the current component flowing in the magnetic detection unit HP in the direction perpendicular to the substrate surface is relatively increased. Will be able to. Thus, the sensitivity (so-called product sensitivity) as the magnetic detection element is improved.

  Also, variations in temperature characteristics (temperature coefficient) related to magnetic detection sensitivity, which are a concern when the diffusion layer is used as a separation wall, or an increase in the size of the temperature compensation circuit are reduced or suppressed.

  As described above, the vertical Hall element according to this embodiment can provide the same effects as the effects (1) to (24) according to the first embodiment described above or effects equivalent thereto. It becomes like this.

  Further, as shown in FIG. 19, if the insulating isolation wall for element isolation by the insulating film IL1 is omitted, an effect similar to or equivalent to the effect of the above (32) can be obtained. .

(Fourth embodiment)
FIG. 20 shows a fourth embodiment of the vertical Hall element according to the present invention.
Hereinafter, with reference to FIG. 20, the structure of the vertical Hall element according to this embodiment will be described focusing on the differences from the third embodiment. 20A to 20C correspond to the previous FIGS. 18A to 18C. In FIG. 20, the same elements as those shown in FIG. 18 are denoted by the same reference numerals, and redundant description of these elements is omitted here.

  As shown in FIGS. 20A to 20C, this vertical Hall element basically has the same structure as the vertical Hall element of the third embodiment illustrated in FIG. The operation mode and the manufacturing method thereof are as described above. However, in this embodiment, a P-type impurity layer D1 is provided on the inner walls of the trenches T1, T2a, T2b by introducing a P-type impurity such as boron.

  By the way, when a trench is formed in a semiconductor substrate, a damaged layer is usually formed on the inner wall of the trench, where carrier recombination is likely to occur. In this regard, according to the structure provided with the impurity layer D1, recombination of such carriers is suppressed by the impurity layer D1, and the carrier mobility of the semiconductor region 12 is maintained high. Further, since the depletion layer of the pn junction formed between the impurity layer D1 and the semiconductor region 12 enters the inside of the element, the thickness d (shown in FIG. 41) of the magnetic detection part (hole plate) HP The dimension corresponding to “d”) in the relational expression is also substantially narrowed. That is, according to such a structure, high sensitivity as a magnetic detection element can be achieved.

  As described above, according to the vertical Hall element according to this embodiment, in addition to the same effects as the effects (1) to (24) of the previous first embodiment or effects equivalent thereto. Further, the following effects can be obtained.

  (33) An impurity layer D1 having a conductivity type (P-type) different from that of the N-type semiconductor region 12 is formed on the inner walls of the trenches T1, T2a, and T2b of the insulating separation walls having the STI structure. Thereby, the high sensitivity as a magnetic detection element comes to be achieved.

  Further, as shown in FIG. 21, if the insulating isolation wall for element isolation by the insulating film IL1 is omitted, an effect similar to or equivalent to the effect of the above (32) can be obtained. .

(Fifth embodiment)
FIG. 22 shows a fifth embodiment of the vertical Hall element according to the present invention.
Hereinafter, with reference to FIG. 22, the structure of the vertical Hall element according to this embodiment will be described focusing on the differences from the first embodiment. FIGS. 22A and 22B correspond to FIGS. 5A and 5B. In FIG. 22, the same elements as those shown in FIG. 5 are denoted by the same reference numerals, and redundant description of these elements is omitted here.

  As shown in FIGS. 22A and 22B, this vertical Hall element basically has the same structure as the vertical Hall element of the first embodiment illustrated in FIG. The operation mode and the manufacturing method thereof are as described above. However, in this embodiment, the LOCOS oxide film HL1 is provided so as to cover substantially the entire surface excluding the contact regions 13a to 13e on the element surface.

  Incidentally, movable ions such as sodium (Na) exist in an interlayer insulating film (for example, the insulating film 15) formed on the element surface in this type of Hall element. For this reason, when the movable ions move as the Hall element is energized or changes in temperature, the potential near the voltage output end on the substrate surface becomes unstable, and a very small hole is output from the Hall element. The voltage signal may be staggered. This is called time-dependent fluctuation or drift, and causes an error in the detection of a magnetic field based on the same voltage. Especially when the Hall element is used as an angle detection sensor, deterioration of the sensor characteristics is unavoidable and serious. .

  In this regard, according to the vertical Hall element according to this embodiment, the element surface (semiconductor region 12 and the like) is protected by the LOCOS oxide film HL1, and the influence of the movable ions, that is, the detection accuracy is improved. The decrease is suppressed. Moreover, the LOCOS oxide film HL1 can be formed (simultaneously) together with the LOCOS oxide film CL1 used for element isolation in the circuit C10 which is a peripheral circuit. Then, after forming the Hall element, even if, for example, an ion implantation process or a plasma process is performed on the entire surface of the substrate as a manufacturing process of the peripheral circuit, the element surface is protected by the LOCOS oxide film HL1, and the Hall element is thereby formed. Damage to can be reduced.

  As described above, according to the vertical Hall element according to this embodiment, in addition to the same effects as the effects (1) to (24) of the previous first embodiment or effects equivalent thereto. Further, the following effects can be obtained.

  (34) The LOCOS oxide film HL1 is provided so as to cover the element surface (semiconductor region 12 and the like). Thereby, the influence by a movable ion, ie, the fall of a detection accuracy, comes to be suppressed suitably. Furthermore, damage to the element surface in the manufacturing process or the like is also suitably reduced.

  In the vertical Hall element according to the fifth embodiment, the LOCOS oxide film HL1 is provided so as to cover substantially the entire surface except for the contact regions 13a to 13e on the element surface. However, the present invention is not limited to this. As long as at least the semiconductor region 12 is covered with this, an effect similar to the effect of the above (34) or an effect equivalent thereto can be obtained.

(Sixth embodiment)
FIG. 23 shows a sixth embodiment of the vertical Hall element according to the present invention.
Hereinafter, with reference to FIG. 23, the structure of the vertical Hall element according to this embodiment will be described focusing on the differences from the first embodiment. FIGS. 23A to 23C correspond to FIGS. 1A to 1C. In FIG. 23, the same elements as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description of these elements is omitted here.

  As shown in FIGS. 23A to 23C, this vertical Hall element basically has the same structure as that of the vertical Hall element of the first embodiment illustrated in FIG. The operation mode and the manufacturing method thereof are as described above. However, in this embodiment, a P-type impurity layer D2 is formed so as to cover substantially the entire surface except for the contact regions 13a to 13e on the element surface by introducing a P-type impurity such as boron. I am doing so.

  By the way, as described above, the behavior of mobile ions contained in the interlayer insulating film on the element surface influences the detection accuracy of the Hall element. In this regard, according to the vertical Hall element according to this embodiment, for example, when the element is placed in a state where a reverse bias voltage is applied between the impurity layer D2 and the semiconductor region 12, The element surface is protected by a depletion layer near the pn junction formed by application. Thus, the influence of the movable ions, that is, a decrease in detection accuracy is suppressed.

  As described above, according to the vertical Hall element according to this embodiment, the same effects as the effects (1) to (24) and (34) according to the first or fifth embodiment. Or the effect according to it comes to be acquired.

(Seventh embodiment)
FIG. 24 shows a seventh embodiment of the vertical Hall element according to the present invention.
Hereinafter, with reference to FIG. 24, the structure of the vertical Hall element according to this embodiment will be described focusing on the differences from the first embodiment. 24A to 24C correspond to FIGS. 1A to 1C. In FIG. 24, the same elements as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description of these elements is omitted here.

  As shown in FIGS. 24A to 24C, this vertical Hall element basically has the same structure as the vertical Hall element of the first embodiment illustrated in FIG. The operation mode and the manufacturing method thereof are as described above. However, in this embodiment, a plate-like electrode material GP made of, for example, aluminum or polycrystalline silicon is included on the substrate via the insulating film 15 made of, for example, PSG or silicon oxide, including the magnetic detection unit HP. It is provided to cover the surface of the element. The electrode material GP is fixed to a predetermined potential (for example, a ground (GND) potential) through an appropriate wiring together with the diffusion layers 14, 14a, and 14b.

  By the way, as described above, the behavior of mobile ions contained in an interlayer insulating film (for example, the insulating film 15) on the surface of the element affects the detection accuracy of the Hall element. In this regard, in the vertical Hall element according to this embodiment, the electrode material GP is provided and fixed to a predetermined potential together with the diffusion layers 14, 14a, and 14b. It is fixed and its surroundings are also in a stable potential environment. As a result, the movement of the movable ions is suppressed, and the variation with time due to the movable ions is reduced, so that the detection accuracy as the magnetic detection element is maintained high. Furthermore, since the electrode material GP also functions as a shield against noise from above the element, the noise resistance of the Hall element is also increased.

  As described above, according to the vertical Hall element according to this embodiment, in addition to the same effects as the effects (1) to (24) of the previous first embodiment or effects equivalent thereto. Further, the following effects can be obtained.

  (35) The electrode material GP fixed at a predetermined potential (here, the ground potential) is provided so as to cover the element surface. As a result, the detection accuracy as the magnetic detection element is maintained high, and the noise resistance of the element is greatly increased.

  In the vertical Hall element according to the seventh embodiment, the electrode material GP is fixed to the ground potential. However, the present invention is not limited to this, and for example, it can be fixed to the power supply potential.

  In the seventh embodiment, the diffusion layers 14, 14a and 14b are also fixed at a predetermined potential in order to make the potential fixation stronger. This is also essential. If only the electrode material GP is fixed to a predetermined potential instead of the above configuration, an effect similar to the effect of the above (35) or an effect equivalent thereto can be obtained.

  In the seventh embodiment, the electrode material GP is provided so as to cover the surface of the element and is fixed at a predetermined potential. However, the electrode material GP is fixed to a part or a plurality of portions of the element surface. The resistance distribution of the magnetic detection unit HP may be made variable by applying a voltage thereto. In such a configuration, by arranging the electrode material GP at an appropriate position, the resistance distribution of a desired portion can be made variable, and the potential distribution inside the element is changed to cause an offset voltage (unbalance). Can be adjusted and balanced. That is, the offset voltage can be adjusted and reduced without using a simple circuit configuration or a correction circuit, and the circuit scale of the configuration including a correction circuit for calculating and correcting the offset voltage can be reduced. Reduction will be achieved.

(Eighth embodiment)
FIG. 25 shows an eighth embodiment of a vertical Hall element according to the present invention.
Hereinafter, with reference to FIG. 25, the structure of the vertical Hall element according to this embodiment, more precisely, the configuration of the magnetic sensor using this vertical Hall element will be described. In the plan view of FIG. 25, the same elements as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description of these elements is omitted here.

  As shown in FIG. 25, in this embodiment, n (an integer greater than or equal to 2) vertical Hall elements 101 to 10n electrically connected in series are integrated on one chip to form a magnetic sensor. It is composed. Each of the vertical Hall elements 101 to 10n has the structure illustrated in FIG.

  Specifically, the terminals G1 and G2 of the vertical Hall element 101 are electrically connected to the terminal S of the vertical Hall element 102 adjacent thereto via an appropriate wiring, and the terminal G1 of the vertical Hall element 102 is further connected. , G2 are electrically connected to terminals S of adjacent vertical Hall elements (not shown) through appropriate wirings, and so on, and so on up to the vertical Hall element 10n. The terminals of the vertical Hall element located at both ends, that is, the terminal S of the vertical Hall element 101 and the terminals G1 and G2 of the vertical Hall element 10n are electrically connected to the terminals S0 and G0, respectively. Yes. That is, in the magnetic sensor, a drive current is supplied to each Hall element through these terminals S0 and G0.

  By connecting a plurality of Hall elements in series in this way, the output voltage (Hall voltage signal) of the entire sensor is increased, and the magnetic detection sensitivity (so-called product sensitivity) of the magnetic sensor is greatly increased. .

  As described above, according to the vertical Hall element according to this embodiment, in addition to the same effects as the effects (1) to (24) of the previous first embodiment or effects equivalent thereto. Further, the following effects can be obtained.

  (36) The magnetic sensor is configured by integrating n (an integer of 2 or more) vertical Hall elements 101 to 10n electrically connected in series on one chip. As a result, the output voltage (Hall voltage signal) of the entire sensor is increased, and the magnetic detection sensitivity (so-called product sensitivity) of the magnetic sensor is greatly increased.

(Ninth embodiment)
FIG. 26 shows a ninth embodiment of the vertical Hall element according to the present invention.
Hereinafter, with reference to FIG. 26, the structure of the vertical Hall element according to this embodiment, more precisely, the configuration of the magnetic sensor using this vertical Hall element will be described. In the plan view of FIG. 26, the same elements as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description of these elements is omitted here.

  As shown in FIG. 26, in this embodiment, n (an integer of 2 or more) vertical Hall elements 101 to 10n that are electrically connected in parallel are integrated on one chip to form a magnetic sensor. It is composed. Each of the vertical Hall elements 101 to 10n has the structure illustrated in FIG.

  Specifically, the vertical Hall element 101 and the vertical Hall element 102 adjacent thereto are electrically connected to each other via appropriate wirings at the terminals S and G1, G2, and the vertical Hall element 102 and the adjacent vertical Hall element 102 are also connected. A mold Hall element (not shown) is electrically connected to the terminal S and the terminals G1 and G2 through appropriate wirings, and so on, and so on up to the vertical Hall element 10n. Thus, the terminals S and the terminals G1 and G2 of the vertical Hall elements 101 to 10n are combined into terminals S0 and G0, respectively. That is, in the magnetic sensor, a drive current is supplied to each Hall element through these terminals S0 and G0.

  By the way, if a large number of Hall elements are produced or many such Hall elements are formed on the same substrate, output voltage (Hall voltage) and offset between these elements due to variations in manufacturing conditions. Variations occur in the voltage (unbalanced voltage). In this respect, in this embodiment, since a magnetic sensor is formed by connecting a plurality of Hall elements in parallel, an output voltage (Hall voltage signal) as a whole sensor, and further an offset voltage (unbalanced voltage). Are averaged, and the magnetic detection accuracy as the magnetic sensor is maintained high.

  As described above, according to the vertical Hall element according to this embodiment, in addition to the same effects as the effects (1) to (24) of the previous first embodiment or effects equivalent thereto. Further, the following effects can be obtained.

  (37) The magnetic sensor is configured by integrating n (an integer of 2 or more) vertical Hall elements 101 to 10n electrically connected in parallel on one chip. As a result, the output voltage (Hall voltage signal) as a whole of the sensor and further the offset voltage (unbalanced voltage) are averaged, and the magnetic detection accuracy as the magnetic sensor is maintained high.

(Tenth embodiment)
27 and 28 show a tenth embodiment of a vertical Hall element according to the present invention.
First, with reference to FIG. 27, the structure of the vertical Hall element according to this embodiment, more precisely, the configuration of the magnetic sensor using this vertical Hall element will be described. In the plan view of FIG. 27, the same elements as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description of these elements is omitted here.

  As shown in FIG. 27, in this embodiment, the magnetic field applied from two mutually perpendicular directions (for example, magnetic fields indicated by arrows Bx and By in FIG. 27) is arranged in a manner to detect. A vertical Hall element, that is, two vertical Hall elements 10 arranged orthogonal to each other are integrated on one chip to constitute a magnetic sensor. Each of these vertical Hall elements 10 has the structure illustrated in FIG.

  FIG. 28 is a graph showing output waveforms Vx and Vy of Hall voltage signals respectively output from the two vertical Hall elements 10 arranged orthogonal to each other. The angle on the horizontal axis represents the angle of the magnetic field applied to these Hall elements.

  As can be seen from the graph of FIG. 28, the Hall voltage signal can be used to perform appropriate signal processing (arithmetic processing) on these Hall voltage signals, more accurately through, for example, a peripheral circuit or a signal processing circuit provided separately. By performing the above, it is possible to detect a magnetic field from all directions on one plane, that is, to detect a magnetic field having a wide angle of 360 °.

  Note that the two vertical Hall elements integrated on one chip in this way are likely to deteriorate the pairing properties of the elements due to variations in various conditions in the manufacturing process. For example, it is desirable to arrange within “100 μm”. By adopting such an arrangement, variations between the two due to the manufacturing process and the like are suppressed, and better pairing can be obtained. In addition, variations in use conditions including temperature environment are suppressed, and in this sense, good pairing can be obtained.

  As described above, according to the vertical Hall element according to this embodiment, in addition to the same effects as the effects (1) to (24) of the previous first embodiment or effects equivalent thereto. Further, the following effects can be obtained.

  (38) Two vertical Hall elements 10 are integrated on one chip so as to detect a magnetic field applied from two orthogonal directions perpendicular to each other, thereby constituting a magnetic sensor. As a result, a high-performance magnetic sensor capable of detecting a magnetic field with a wide angle of 360 ° can be realized.

  In the tenth embodiment, two vertical Hall elements 10 are integrated on one chip to form a magnetic sensor in such a manner that magnetic fields applied from two mutually perpendicular directions are detected. However, it is not limited to this structure. In short, it is sufficient to form a magnetic sensor by integrating two elements on one chip in a manner to detect magnetic fields applied from different angles, that is, for example, two longitudinally arranged in a manner that intersects each other at an acute angle. The effect according to the effect of the above (38) can be obtained also by the mold Hall element.

(Eleventh embodiment)
FIG. 29 shows an eleventh embodiment of a vertical Hall element according to the present invention.
Hereinafter, with reference to FIG. 29, the structure of the vertical Hall element according to this embodiment, more precisely, the configuration of the magnetic sensor using this vertical Hall element will be described. In the plan view of FIG. 29, the same elements as those shown in FIGS. 1 and 42 are denoted by the same reference numerals, and redundant description of these elements is omitted here.

  As shown in FIG. 29, in this embodiment, two vertical Hall elements 10 arranged orthogonally together with a horizontal Hall element 20 that detects a magnetic field component perpendicular to the substrate surface (chip surface) are provided as one chip. Are integrated into a three-dimensional magnetic sensor that detects magnetic fields (for example, magnetic fields indicated by arrows Bx, By, and Bz in FIG. 29) from three axial directions orthogonal to each other. Each of the vertical Hall elements 10 has the structure illustrated in FIG. Also, the horizontal Hall element 20 basically has the structure illustrated in FIG. However, here, the semiconductor region 22 is formed not as an epitaxial film but as a diffusion layer (well).

  In the magnetic sensor having such a configuration, for example, by performing appropriate signal processing (arithmetic processing) on the Hall voltage signal output from each Hall element by a signal processing circuit or the like provided in a peripheral circuit or separately, 1 In addition to all directions (two-dimensional directions) on one plane, it is also possible to detect a magnetic field (arrow Bz) from an axial direction orthogonal to this. That is, so-called three-dimensional magnetic field detection is realized.

  As described above, according to the vertical Hall element according to this embodiment, in addition to the same effects as the effects (1) to (24) of the previous first embodiment or effects equivalent thereto. Further, the following effects can be obtained.

  (39) Two vertical Hall elements 10 arranged orthogonally together with the horizontal Hall element 20 for detecting a magnetic field component perpendicular to the substrate surface (chip surface) are integrated on one chip, and from three axial directions orthogonal to each other. A three-dimensional magnetic sensor for detecting the magnetic field is configured. As a result, three-dimensional magnetic field detection is possible.

  The horizontal Hall element only needs to detect a magnetic field component perpendicular to the substrate surface (chip surface), and is not limited to the horizontal Hall element 20 having the structure illustrated in FIG. Can be adopted.

(Twelfth embodiment)
30 and 31 show a twelfth embodiment of a vertical Hall element according to the present invention.
Hereinafter, with reference to FIGS. 30 and 31, focusing on the differences from the previous tenth embodiment, the structure of the vertical Hall element according to this embodiment, more precisely, this vertical Hall element. The configuration of the magnetic sensor will be described. In the plan views of FIGS. 30 and 31, the same elements as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description of these elements is omitted here.

  As shown in FIG. 30, also in this embodiment, the vertical Hall elements are arranged in such a manner that magnetic fields applied from two mutually perpendicular directions are detected, that is, arranged in a form orthogonal to each other. Two vertical Hall elements 10 (both vertical Hall elements having the structure illustrated in FIG. 1) are integrated on one chip to constitute a magnetic sensor. However, here, the two vertical Hall elements 10 are arranged in a manner opposite to each other in the same direction, and another vertical Hall element 10a (which is also a vertical Hall element having the structure illustrated in FIG. 1). It is supposed to make a pair. By adopting such a configuration, the magnetic sensor can average the output voltages (Hall voltages) of two vertical Hall elements that are arranged opposite to each other and make a pair, or switch the outputs of the vertical Hall elements. As a result, the detection accuracy can be improved.

  In addition, as shown in FIG. 31, both the vertical Hall element 10 and the vertical Hall element 10a paired therewith are disposed by being inclined by 45 ° with respect to the side surface of the substrate cut out as a chip. It becomes difficult to be affected by various mechanical stresses applied from the outside. That is, the offset voltage of each Hall element is suitably reduced, and the detection accuracy as a magnetic sensor is further enhanced.

  As described above, according to the vertical Hall element according to this embodiment, the same effects as the effects (1) to (24) and (38) according to the first or tenth embodiment. Or, in addition to the effects equivalent to the above, the following effects can be obtained.

  (40) A pair of two vertical Hall elements 10 that are integrated on one chip in a form orthogonal to each other to form a magnetic sensor and another vertical Hall element 10a that are arranged in the same direction. It was supposed to make. Thereby, the detection accuracy as a magnetic sensor can be improved.

  (41) Further, both of the pairs formed by the two vertical Hall elements 10 are arranged so as to be inclined by 45 ° with respect to the side surface of the substrate cut out as a chip. This will further improve the detection accuracy.

(Thirteenth embodiment)
FIG. 32 shows a thirteenth embodiment of a vertical Hall element according to the present invention.
Hereinafter, with reference to FIG. 32, the structure of the vertical Hall element according to this embodiment, more precisely, the configuration of the magnetic sensor using this vertical Hall element will be described. In the plan view of FIG. 32, the same elements as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description of these elements is omitted here.

  As shown in FIG. 32, also in this embodiment, the vertical Hall elements are arranged in such a manner as to detect magnetic fields applied from two orthogonal directions perpendicular to each other, that is, arranged in a form perpendicular to each other. Two vertical Hall elements 10 (both vertical Hall elements having the structure illustrated in FIG. 1) are integrated on one chip (the same substrate) to constitute a magnetic sensor. However, here, these two vertical Hall elements 10 are placed in a crystal orientation that makes the atomic arrangement of the semiconductor substrate (here, silicon substrate) equal, that is, crystal orientation (001) (or (00-1)) and crystal orientation ( 010) (or (0-10)).

  Usually, the output voltage (Hall voltage) of the Hall element is proportional to the carrier mobility of the magnetic detection unit HP. This carrier mobility tends to depend on the crystal structure (more specifically, the atomic arrangement). Also, the influence of the piezoresistive effect accompanying various mechanical stresses applied from the outside of the element also tends to depend on the crystal structure. For this reason, when a plurality of Hall elements are integrated on one chip (the same substrate), it is important to arrange the Hall elements in which crystal orientation (plane orientation) of the substrate. In this regard, like the vertical Hall element according to this embodiment, if the vertical Hall element 10 is arranged in a crystal orientation that makes the atomic arrangement of the semiconductor substrate equal, the vertical Hall element 10 is good. A good pair property will be obtained. That is, the Hall voltage (output voltage) generated in these vertical Hall elements 10 and the resistance change caused by the application of stress due to the piezoresistive effect are also suppressed from variation among these Hall elements, and thus the magnetic sensor. As a result, high detection accuracy can be obtained.

  As described above, according to the vertical Hall element according to this embodiment, the same effects as the effects (1) to (24) and (38) according to the first or tenth embodiment. Or, in addition to the effects equivalent to the above, the following effects can be obtained.

  (42) Two vertical Hall elements 10 integrated on one chip (the same substrate) are arranged in a crystal orientation that makes the atomic arrangement of the substrates equal. Thereby, high detection accuracy as a magnetic sensor comes to be obtained.

Note that the crystal orientation for equalizing the atomic arrangement in the silicon substrate is not limited to that illustrated in FIG. As is well known, since single crystal silicon is a material having a tiremond structure (tetrahedral structure), a similar atomic arrangement is provided in crystal orientations (001), (00-1), (010), and (0-10). Have. That is, for example, as shown in FIG.
A structure in which the two vertical Hall elements 10 are arranged in the crystal orientation (011) or (0-1-1), the crystal orientation (0-11) or (01-1),
Or as shown in FIG.
A structure in which the two vertical Hall elements 10 are arranged in the crystal orientation (1-11) or (-11-1), the crystal orientation (11-1) or (-1-11),
Or as shown in FIG.
A structure in which the two vertical Hall elements 10 are arranged in the crystal orientation (1-10) or (−110), the crystal orientation (10-1) or (−101),
Or as shown in FIG.
A structure in which the two vertical Hall elements 10 are arranged in the crystal orientation (10-1) or (−101), the crystal orientation (0-11) or (01-1),
Or as shown in FIG.
A structure in which the two vertical Hall elements 10 are arranged in the crystal orientation (0-11) or (01-1), the crystal orientation (1-10) or (−110),
Even with such a structure, the same effect as the effect (42) or an effect equivalent thereto can be obtained.

Furthermore, the number of vertical Hall elements is not limited to two and is arbitrary. For example, when three vertical Hall elements are integrated on one chip, as illustrated in FIG.
The three vertical Hall elements 10 are divided into crystal orientation (1-10) or (−110), crystal orientation (0-11) or (01-1), crystal orientation (10-1) or (−101). The structure of each
Thus, the same effect as the effect (42) or an effect equivalent thereto can be obtained.

  Even when a substrate other than a silicon substrate is used, by arranging a plurality of elements integrated on one chip in a crystal orientation that makes the atomic arrangement of the substrate equal, the same effect as the effect of (42) above or An effect equivalent to that will be obtained.

(Fourteenth embodiment)
FIG. 37 shows a fourteenth embodiment of a vertical Hall element according to the present invention.
In the following, with reference to FIG. 37, focusing on the differences from the thirteenth embodiment, the structure of the vertical Hall element according to this embodiment, more precisely, the magnetic sensor using this vertical Hall element. The configuration of will be described. Note that the plan view of FIG. 37 corresponds to FIG. In FIG. 37, the same elements as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description of these elements is omitted here.

  As shown in FIG. 37, also in this embodiment, the vertical Hall elements are arranged in such a manner as to detect magnetic fields applied from two orthogonal directions perpendicular to each other, that is, arranged in a form orthogonal to each other. Two vertical Hall elements 10 (both vertical Hall elements having the structure illustrated in FIG. 1) are integrated on one chip (the same substrate) to constitute a magnetic sensor. The two vertical Hall elements 10 are formed adjacent to each other in the form of being adjacent to each other, and are arranged in crystal orientations that equalize the atomic arrangement of the semiconductor substrate. However, here, in such a manner as to surround the periphery of the two vertical Hall elements 10, the trench isolation, that is, the trench TN in which the insulating film IL is embedded is provided. As a result, the influence of various mechanical stresses applied from the outside of the element is alleviated, and better pairing can be obtained. Note that a shallow trench (STI) or the like may be used as the trench TN.

  As described above, according to the vertical Hall element according to this embodiment, the above (1) to (24), (38) and (42) according to the first, tenth or thirteenth embodiment. In addition to the same effect as or a similar effect, the following effects can be obtained.

  (43) Two vertical Hall elements 10 are integrated in one chip close to each other, and a trench isolation is provided in such a manner as to surround the vertical Hall elements 10. Thereby, the influence of the various mechanical stresses applied from the outside of the element described above is alleviated, and better pairing can be obtained.

  Here, an example is shown in which trench isolation is applied to the vertical Hall element illustrated in FIG. 32. However, the present invention is not limited to this, and a plurality of chips integrated in one chip in close proximity to each other are shown. In the case of an element, by applying such trench isolation, an effect similar to or equivalent to the effect of (43) can be obtained. That is, for example, as shown in FIG. 38, the present invention may be applied to the vertical Hall element exemplified in FIG. Further, the number of elements is not limited to two, and is arbitrary, and can be applied to, for example, the three vertical Hall elements illustrated in FIG.

(Other embodiments)
In addition, each said embodiment can also be implemented with the following aspects.
In the eighth to fourteenth embodiments, the magnetic sensor is formed using the vertical Hall element of the first embodiment. However, the present invention is not limited to this. A similar magnetic sensor may be realized by using any one of the vertical Hall elements according to the seventh embodiment or by combining them.

  In each of the above embodiments, the Hall element is integrated on one chip together with a signal processing circuit that performs predetermined signal processing on the Hall voltage signal output from the Hall element, and is applied from a predetermined direction. A magnetic sensor for detecting a magnetic field generated is configured. However, this is not an essential configuration, and for example, a signal processing circuit or the like can be provided as a separate chip.

In each of the above embodiments, a vertical Hall element having one voltage output pair is assumed. However, the present invention is not limited to this, and the vertical Hall element having two or more voltage output pairs is also applicable. The present invention can be similarly applied. For example, as shown in FIG. 39, in the vertical Hall element according to the first embodiment, a contact region (N ⁺ diffusion layer) corresponding to a voltage output pair with respect to contact regions 13b and 13c corresponding to a current supply end. 13f and 13g and contact regions (N ⁺ diffusion layers) 13h and 13i may be provided. In such a structure, the characteristics of the voltage signals (V _out ) output to the terminals V11 and V12 for voltage output and the terminals V21 and V22, respectively, are the terminals V1 and V1 of the vertical Hall element exemplified in FIG. The characteristics are opposite to those of the voltage signal output to V2 (the polarity is opposite).

  Further, the number of current supply pairs is not limited to two pairs, but is arbitrary. For example, the present invention can be similarly applied to a vertical Hall element including a pair of current supply pairs. For example, as shown in FIG. 40, the present invention can be similarly applied to the vertical Hall element according to the first embodiment even if the region 12c, that is, the contact region 13c on the terminal G2 side is omitted. it can. That is, one end of the current supply pair of the vertical Hall element is sandwiched between the voltage output pair, and the other end is disposed only on one side with the voltage output pair as a boundary. According to such a structure, the area of about “1/3” is reduced as compared with the vertical Hall element illustrated in FIG. 1, and the size can be greatly reduced. The operation mode of such a Hall element is also basically the same as that of the previous vertical Hall element exemplified in FIG.

  In each of the above embodiments, the current supply pair and the voltage output pair are arranged (layout) so as to be orthogonal to each other. However, the present invention is not limited to this. For example, the voltage output pair and the current supply pair may be arranged in a line (layout).

  In addition, in each of the above embodiments, the separation walls that electrically partition the region 12a (FIG. 1A), such as the diffusion layers 14a and 14b, are not essential components. That is, for example, a vertical Hall element provided with wirings (electrodes) for flowing current to the magnetic detection unit HP facing the front and back of the substrate, or each end of the voltage output pair and the current supply pair are arranged in a row. In a vertical Hall element or the like, a current containing a component perpendicular to the substrate surface (chip surface) can be supplied to the magnetic detection unit HP without providing such a separation wall.

In each of the above embodiments, each end of the voltage output pair and the current supply pair is provided as a contact region (N ⁺ diffusion layer) in which the concentration of the conductive impurity on the substrate surface is selectively increased. I made it. However, this is not an essential configuration. For example, a wiring (electrode) may be provided directly on the semiconductor region 12 without providing such a contact region.

  In the above-described embodiment, the circuit C10 (FIG. 5) configured with a CMOS circuit is illustrated as an example of the peripheral circuit of the Hall element. However, the configuration of the peripheral circuit is arbitrary. For example, a circuit including a bipolar circuit can be used as the peripheral circuit.

  In the above embodiment, constant current driving has been described as an example of a vertical Hall element driving method. However, the vertical Hall element driving method is arbitrary, and may be driven by constant voltage driving, for example. it can.

  In each of the above embodiments, the present invention can be similarly applied to a structure in which the conductivity type of each element constituting the Hall element is switched, that is, a structure in which the P type and the N type are switched.

  In each of the above embodiments, silicon is used as the material for the substrate, but other materials may be appropriately employed depending on the manufacturing process, structural conditions, and the like. For example, compound semiconductor materials such as GaAs, InSb, InAs, and SiC, and other semiconductor materials such as Ge (germanium) can also be used. In particular, GaAs and InAs are materials having excellent temperature characteristics, and are effective in increasing the sensitivity of the Hall element.

  ・ Even if any of these semiconductor materials is adopted, the semiconductor substrate has a cut surface in a plane orientation that makes resistance change accompanying stress application due to the piezoresistance effect smaller than other plane orientations. As a result, an effect similar to or equivalent to the effect of (17) can be obtained.

  In each of the above embodiments, a substrate having a single conductivity type is adopted. However, the present invention is not limited to this. For example, an epitaxial substrate, an SOI (Silicon On Insulator) substrate, or a different conductive material is used. A semiconductor substrate having a structure in which type semiconductor layers are alternately stacked (for example, a structure such as PNP... Or NPN...) Can also be used as the substrate of the Hall element. Further, the cut surface of the substrate is not limited to the (100) surface and is arbitrary.

  After all, the semiconductor region 12 is made of a diffusion layer (well) formed by adding and diffusing conductive impurities to the semiconductor substrate, thereby increasing the degree of freedom in selecting the substrate to be used. The intended purpose will be achieved.

  On the other hand, if the vertical Hall element is manufactured by adding a conductive impurity to a semiconductor substrate and diffusing the same, the intended purpose can be achieved. become.

In the first embodiment of the vertical Hall element according to the present invention, (a) is a plan view schematically showing the schematic structure of the Hall element, and (b) is taken along line L1-L1 in (a). Sectional drawing, (c) is a sectional view along line L2-L2 in (a). FIG. 6 is a perspective view showing a concentration distribution (concentration profile) of the vertical Hall element according to the first embodiment. Sectional drawing which shows density | concentration distribution (concentration profile) of a semiconductor region about the vertical Hall element which concerns on the same 1st Embodiment. The graph which illustrates the simulation result by an inventor about the relationship between the output voltage (Hall voltage) of the vertical Hall element which concerns on the said 1st Embodiment, and the diffusion depth of a separation wall. FIG. 5A is a plan view schematically showing a schematic structure of a vertical Hall element according to the first embodiment including a peripheral circuit, and FIG. 5B is along a line L1-L1 in FIG. Sectional drawing. The circuit diagram which shows the arrangement | positioning aspect of the wiring of the vertical Hall element based on the said 1st Embodiment. The circuit diagram which shows the arrangement | positioning aspect of the wiring of the vertical Hall element based on the said 1st Embodiment. (A)-(c) is sectional drawing which shows typically the manufacturing process about an example of the manufacturing method of the vertical Hall element based on the 1st Embodiment. (A)-(c) is sectional drawing which shows typically the manufacturing process about an example of the manufacturing method of the vertical Hall element based on the 1st Embodiment. Sectional drawing which shows the modification of the vertical Hall element based on the said 1st Embodiment. FIGS. 11A and 11B are cross-sectional views schematically showing a manufacturing process of an example of a method for manufacturing the vertical Hall element illustrated in FIG. 10. FIGS. 11A and 11B are cross-sectional views schematically showing a manufacturing process of another example of the method for manufacturing the vertical Hall element illustrated in FIG. 10. Sectional drawing which shows another modification of the vertical Hall element based on the said 1st Embodiment. FIGS. 14A and 14B are cross-sectional views schematically showing a manufacturing process of an example of a method for manufacturing the vertical Hall element illustrated in FIG. FIGS. 14A and 14B are cross-sectional views schematically showing the manufacturing process of another example of the method for manufacturing the vertical Hall element illustrated in FIG. Regarding the second embodiment of the vertical Hall element according to the present invention, (a) is a plan view schematically showing the schematic structure of the Hall element, and (b) is taken along line L1-L1 in (a). Sectional drawing, (c) is a sectional view along line L2-L2 in (a). The perspective view which shows the density | concentration distribution (density profile) of the vertical Hall element based on the said 2nd Embodiment. Regarding the third embodiment of the vertical Hall element according to the present invention, (a) is a plan view schematically showing the schematic structure of the Hall element, and (b) is taken along line L1-L1 in (a). Sectional drawing, (c) is a sectional view along line L2-L2 in (a). About the modification of the vertical Hall element which concerns on the said 3rd Embodiment, (a) is a top view which shows the schematic structure of the Hall element typically, (b) is along the L1-L1 line | wire of (a). (C) is sectional drawing which followed the L2-L2 line of (a). Regarding the fourth embodiment of the vertical Hall element according to the present invention, (a) is a plan view schematically showing the schematic structure of the Hall element, and (b) is taken along line L1-L1 in (a). Sectional drawing, (c) is a sectional view along line L2-L2 in (a). About the modification of the vertical Hall element which concerns on the said 4th Embodiment, (a) is a top view which shows the schematic structure of the Hall element typically, (b) is along the L1-L1 line of (a). (C) is sectional drawing which followed the L2-L2 line of (a). In the fifth embodiment of the vertical Hall element according to the present invention, (a) is a plan view schematically showing a schematic structure of the Hall element including peripheral circuits, and (b) is an L1- Sectional drawing along a L1 line. Regarding the sixth embodiment of the vertical Hall element according to the present invention, (a) is a plan view schematically showing the schematic structure of the Hall element, and (b) is taken along line L1-L1 in (a). Sectional drawing. Regarding the seventh embodiment of the vertical Hall element according to the present invention, (a) is a plan view schematically showing the schematic structure of the Hall element, and (b) is taken along line L1-L1 in (a). Sectional drawing, (c) is a sectional view along line L2-L2 in (a). The top view which shows schematic structure of the magnetic sensor by the vertical Hall element about 8th Embodiment of the vertical Hall element which concerns on this invention. The top view which shows schematic structure of the magnetic sensor by the vertical Hall element about 9th Embodiment of the vertical Hall element which concerns on this invention. The top view which shows schematic structure of the magnetic sensor by the vertical Hall element about 10th Embodiment of the vertical Hall element which concerns on this invention. The graph which shows the example of a waveform of the output voltage (Hall voltage) of the vertical Hall element which concerns on the 10th Embodiment. The top view which shows schematic structure of the magnetic sensor by the vertical Hall element about 11th Embodiment of the vertical Hall element which concerns on this invention. The top view which shows schematic structure of the magnetic sensor by the vertical Hall element about 12th Embodiment of the vertical Hall element which concerns on this invention. The top view which shows the modification of the vertical Hall element based on the 12th embodiment. The top view which shows schematic structure of the magnetic sensor by the vertical Hall element about 13th Embodiment of the vertical Hall element which concerns on this invention. The top view which shows the modification of the vertical Hall element based on the 13th Embodiment. The top view which shows another modification of the vertical Hall element based on the 13th Embodiment. (A)-(c) is a top view which shows another modification of the vertical Hall element based on the 13th Embodiment. The top view which shows another modification of the vertical Hall element based on the 13th Embodiment. The top view which shows schematic structure of the magnetic sensor by the vertical Hall element about 14th Embodiment of the vertical Hall element which concerns on this invention. The top view which shows the modification of the vertical Hall element based on the 14th Embodiment. The top view which shows another embodiment of the vertical Hall element concerning this invention. The top view which shows another embodiment of the vertical Hall element concerning this invention. The perspective view which shows the magnetic detection principle of a Hall element. (A) is a top view which shows typically the planar structure of the Hall element about an example of the conventional Hall element (horizontal type Hall element), (b) is sectional drawing along the L1-L1 line of (a). As for an example of a conventional Hall element (vertical Hall element), (a) is a plan view schematically showing a planar structure of the Hall element, (b) is a sectional view taken along line L1-L1 in (a), (C) is sectional drawing along the L2-L2 line of (a). Regarding another example of a conventional Hall element (vertical Hall element), (a) is a plan view schematically showing a planar structure of the Hall element, and (b) is a cross section taken along line L1-L1 of (a). The figure, (c) is sectional drawing which followed the L2-L2 line of (a).

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 10a, 101-10n ... Vertical Hall element, 11 ... Semiconductor layer (semiconductor substrate), 12, H12, L12 ... Semiconductor region, 12a-12c ... Region, 13a-13i, 23a-23d ... Contact region (N ⁺ Diffusion layer), 14, 14a, 14b, 24 ... diffusion layer, 15 ... insulating film (interlayer insulating film), 16a-16c, C16a-C16f ... wiring (electrode), 20 ... horizontal Hall element, BL ... buried layer, C10: Circuit (peripheral circuit), C12: Semiconductor region, C13: Diffusion layer, C13a to C13f: Diffusion layer (source / drain layer), CL1, HL1 ... LOCOS oxide film (field oxide film), D1, D2 ... Impurity layer , G1a to G1c... Gate electrode, GP... Electrode material, HP... Magnetic detection part (Hall plate), I1a to I1c ... gate insulating film, IL, IL1, IL2a, I. 2b ... insulating film, R ... resistance, ST ... diffusion stopper layer, SW11~SW14, SW21~SW24 ... switching device, T1, T2a, T2b, TN ... trench.

Claims (40)

A semiconductor region having a predetermined conductivity type is formed in a semiconductor substrate, and has a current supply pair and a voltage output pair on the surface of the semiconductor region, and includes a component perpendicular to the surface of the substrate. When a magnetic field component parallel to the surface of the substrate is applied to the magnetic detection unit in a state where is supplied to one end of the current supply pair to the magnetic detection unit in the semiconductor region, a hole corresponding to the magnetic field component In a vertical Hall element that outputs a voltage signal to both ends of the voltage output pair ,
The semiconductor region is composed of a diffusion layer formed in such a manner that a conductive impurity is added and diffused to the semiconductor substrate,
Semiconductor region consisting of the diffusion layer, Ri Na is formed with a concentration change in the depth direction,
The semiconductor region comprises a diffusion layer of a conductivity type different from that of the semiconductor region, and is between the voltage output pair and one end of the current supply pair sandwiched between the voltage output pair and the other end of the current supply pair. And a diffusion separation wall that selectively narrows the vicinity of the bottom surface of the semiconductor region to form a current path, and the magnetic detection unit is electrically partitioned by the diffusion separation wall. Vertical Hall element characterized by A semiconductor region having a predetermined conductivity type is formed in a semiconductor substrate, and has a current supply pair and a voltage output pair on the surface of the semiconductor region, and includes a component perpendicular to the surface of the substrate. When a magnetic field component parallel to the surface of the substrate is applied to the magnetic detection unit in a state where is supplied to one end of the current supply pair to the magnetic detection unit in the semiconductor region, a hole corresponding to the magnetic field component In a vertical Hall element that outputs a voltage signal to both ends of the voltage output pair ,
The semiconductor region is composed of a diffusion layer formed in such a manner that a conductive impurity is added and diffused to the semiconductor substrate,
Semiconductor region consisting of the diffusion layer, Ri Na is formed with a concentration change in the depth direction,
The semiconductor region is disposed between the voltage output pair and one end of the current supply pair sandwiched between the voltage output pair and the other end of the current supply pair, and has a diffusion depth shallower than the semiconductor region. The vertical Hall element is characterized in that a diffusion separation wall composed of a diffusion layer of a different conductivity type from the semiconductor region is formed, and the magnetic detection portion is electrically partitioned by the diffusion separation wall. . The semiconductor region and the different conductivity type diffusion separation wall comprising a diffusion layer of the vertical Hall element according to claim 1 or 2 formed by formed with at least "2μm" than the diffusion depth. The semiconductor region and the different conductivity type diffusion separation wall comprising a diffusion layer of the with the highest concentration on the semiconductor substrate surface, according to claim 1 to 3 comprising formed in a manner to become a low concentration as one proceeds from the surface to the back surface side The vertical Hall element according to any one of the above. A semiconductor region having a predetermined conductivity type is formed in a semiconductor substrate, and has a current supply pair and a voltage output pair on the surface of the semiconductor region, and includes a component perpendicular to the surface of the substrate. When a magnetic field component parallel to the surface of the substrate is applied to the magnetic detection unit in a state where is supplied to one end of the current supply pair to the magnetic detection unit in the semiconductor region, a hole corresponding to the magnetic field component In a vertical Hall element that outputs a voltage signal to both ends of the voltage output pair ,
The semiconductor region is composed of a diffusion layer formed in such a manner that a conductive impurity is added and diffused to the semiconductor substrate,
Semiconductor region consisting of the diffusion layer, Ri Na is formed with a concentration change in the depth direction,
The semiconductor region has an STI structure and is arranged between the voltage output pair and one end of the current supply pair sandwiched between the voltage output pair and the other end of the current supply pair. A vertical Hall element characterized in that an insulating separation wall that selectively narrows the vicinity of the bottom surface of the region to form a current path is formed, and the magnetic detection portion is electrically partitioned by the insulating separation wall. . A semiconductor region having a predetermined conductivity type is formed in a semiconductor substrate, and has a current supply pair and a voltage output pair on the surface of the semiconductor region, and includes a component perpendicular to the surface of the substrate. When a magnetic field component parallel to the surface of the substrate is applied to the magnetic detection unit in a state where is supplied to one end of the current supply pair to the magnetic detection unit in the semiconductor region, a hole corresponding to the magnetic field component In a vertical Hall element that outputs a voltage signal to both ends of the voltage output pair ,
The semiconductor region is composed of a diffusion layer formed in such a manner that a conductive impurity is added and diffused to the semiconductor substrate,
Semiconductor region consisting of the diffusion layer, Ri Na is formed with a concentration change in the depth direction,
The semiconductor region is disposed between the voltage output pair and one end of the current supply pair sandwiched between the voltage output pair and the other end of the current supply pair, and has a shallower depth than the semiconductor region. A vertical Hall element characterized in that an insulating separation wall having an STI structure is formed with a size, and the magnetic detection part is electrically partitioned by the insulating separation wall . The vertical Hall element according to claim 5 or 6 ,
An impurity layer having a conductivity type different from that of the semiconductor region is formed on a trench inner wall of the insulating isolation wall having the STI structure. The vertical Hall element according to any one of claims 1 to 7, wherein one end of the current supply pair is sandwiched between the voltage output pair and the other end is arranged line-symmetrically with respect to the voltage output pair. 8. The vertical type according to claim 1, wherein one end of the current supply pair is sandwiched between the voltage output pair, and the other end is disposed only on one side with the voltage output pair as a boundary. Hall element. The vertical Hall element according to any one of claims 1 to 9 , wherein the current supply pair and the voltage output pair are arranged so as to be orthogonal to each other. Each end of the current supply pair and the voltage output pair, according to any one of claims 1 to 10 comprising arranged as a selective elevated portion of the impurity concentration at the surface of said semiconductor substrate Vertical Hall element. The vertical Hall element according to any one of claims 1 to 11 , wherein at least one end of the voltage output pair, the Hall voltage signal is output via a wiring whose resistance value is variable. The vertical wiring according to claim 12 , wherein the wiring having the variable resistance value is formed by electrically connecting a plurality of wirings having different resistance values in parallel with each other in a manner in which the wirings can be temporarily or permanently disconnected. Hall element. The semiconductor region composed of the diffusion layer is formed in such a manner that it has the highest concentration on the surface of the semiconductor substrate and becomes a lower concentration as it advances from the front surface to the back surface side, and is supplied to the magnetic detection unit by this concentration gradient. 14. The vertical type according to claim 1, wherein a current including a component perpendicular to the surface of the substrate is guided to flow in an oblique direction with respect to the surface of the substrate at least in the magnetic detection unit. Hall element. Semiconductor region consisting of the diffusion layer, the have the lowest concentration on the surface of the semiconductor substrate, according to any one of claims 1 to 13 comprising formed in a manner to become a high concentration as one proceeds from the surface to the back surface side Vertical Hall element. Semiconductor region consisting of the diffusion layer, the have semiconductor highest concentration at a predetermined depth of the substrate, from which the claims 1 to 13, respectively formed in a manner to become a low concentration as the substrate surface side and proceeds to the rear surface side of the substrate The vertical Hall element according to any one of the above. A diffusion stopper film is provided in the semiconductor region composed of the diffusion layer, and the semiconductor region is formed in such a manner that the highest concentration is in a portion facing the diffusion stopper film, and the concentration decreases as the distance from the diffusion stopper film increases. The vertical Hall element according to any one of claims 1 to 13 . The semiconductor region, the made from the semiconductor substrate with a conductivity type different from the vertical Hall element according to any one of claims 1 to 17 comprising formed in a manner to be surrounded by the semiconductor substrate. In the vertical Hall element according to any one of claims 1 to 18 ,
A vertical Hall element, wherein a planar electrode material is provided on the surface of the semiconductor substrate via an insulating film. The vertical Hall element according to claim 19 , wherein the electrode material is provided so as to cover at least the magnetic detection unit, and is fixed to a predetermined potential via an appropriate wiring. The vertical Hall element according to claim 19 , wherein the electrode material has a variable resistance distribution of the magnetic detection unit according to an applied voltage. In the vertical Hall element according to any one of claims 1 to 18 ,
A vertical Hall element characterized in that a field oxide film having a LOCOS structure is provided on the surface of the semiconductor substrate so as to cover at least the semiconductor region. In the vertical Hall element according to any one of claims 1 to 18 ,
The vertical Hall element, wherein an impurity layer having a conductivity type different from that of the semiconductor region is formed on the surface of the semiconductor substrate so as to cover at least the semiconductor region. The vertical Hall element according to any one of claims 1 to 23 , wherein the semiconductor substrate is made of an N type, and the semiconductor region is made of a P type. Said semiconductor substrate is a P-type, the semiconductor region is vertical Hall element according to any one of claims 1 to 23 consisting of N-type. The vertical Hall element according to any one of claims 1 to 25 , wherein the semiconductor substrate has a cut surface in a plane orientation that makes resistance change due to stress application caused by a piezoresistance effect smaller than other plane orientations. . 27. The vertical Hall element according to claim 26 , wherein the semiconductor substrate is made of silicon and has a (100) plane as a cut surface. The vertical Hall element according to any one of claims 1 to 26 , wherein the semiconductor substrate is made of one of silicon and germanium. The vertical Hall element according to any one of claims 1 to 26 , wherein the semiconductor substrate is made of a compound semiconductor. The vertical Hall element according to claim 29 , wherein the semiconductor substrate is made of any one of GaAs, InSb, and InAs. The vertical Hall element according to claim 1 , wherein a plurality of elements electrically connected in series are integrated on one chip to constitute a magnetic sensor. The vertical Hall element according to any one of claims 1 to 30 , wherein a plurality of elements electrically connected in parallel are integrated on one chip to constitute a magnetic sensor. The vertical Hall element according to any one of claims 1 to 32 , wherein a magnetic sensor is configured by being integrated on one chip in a pair with another element arranged in an opposing manner. 34. The vertical Hall element according to claim 33 , wherein the two elements forming the pair are disposed so as to be inclined by 45 ° with respect to the side surface of the substrate cut out as a chip. The vertical Hall element according to any one of claims 1 to 34 , wherein a plurality of elements are integrated on one chip and arranged in a crystal orientation that makes the atomic arrangement of the semiconductor substrate equal. The vertical isolation according to any one of claims 1 to 35 , wherein a plurality of elements are integrated on one chip close to each other, and trench isolation is provided in a manner surrounding the plurality of adjacent elements. Type Hall element. The vertical Hall element according to any one of claims 1 to 36 , wherein a magnetic sensor is configured by integrating a plurality of elements on one chip in a manner of detecting magnetic fields applied from different angles. A three-dimensional magnetic sensor for detecting magnetic fields from three orthogonal directions in which two orthogonally arranged elements are integrated on one chip together with a horizontal Hall element that detects a magnetic field component perpendicular to the surface of the semiconductor substrate. The vertical Hall element according to any one of claims 1 to 36 . Claim is together 1 chip integrated with the signal processing circuit for performing predetermined signal processing on the Hall voltage signal output from the Hall element to form a magnetic sensor for detecting a magnetic field applied from a predetermined direction 1 The vertical Hall element as described in any one of -38 . The vertical Hall element according to any one of claims 1 to 39 , further comprising a CMOS circuit as a peripheral circuit.

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