JP4353055B2 - Vertical Hall element - Google Patents

Description

  The present invention is based on the fact that a current containing a component perpendicular to the surface of a semiconductor substrate (wafer) is supplied to a magnetic detection unit in the semiconductor substrate, and is horizontal to the surface of the semiconductor substrate through a Hall voltage generated for the current. The present invention relates to a vertical Hall element that detects a simple magnetic field component.

  As is well known, since the Hall element can detect the angle without contact, it is used as an angle detection sensor such as a throttle valve opening sensor of an in-vehicle internal combustion engine as a magnetic sensor. First, the magnetic detection principle of the Hall element will be described with reference to FIG.

  In general, when a magnetic field (magnetism) perpendicular to a current flowing in a material is applied, an electric field perpendicular to both the current and the magnetic field is generated. The carrier moving by this electric field receives the Lorentz force and is bent in a direction perpendicular to both the movement (movement) direction of the carrier and the direction of the magnetic field. Thus, carriers accumulate on one side of the substance, and an electric field (voltage) is generated in the bent direction of the carriers. This phenomenon is called the Hall effect, and the voltage generated here is called the Hall voltage.

For example, when a Hall element 100 as shown in FIG. 8 is considered, the magnetic detection width (Hall element width) of the element is w, the length is L, the thickness is t, and the angle formed by the element and the magnetic field. Is the Hall voltage (terminals V1-V2) where θ is the magnetic flux density, B is the supply (drive) current (current supplied between the terminals S-G) is I, and the width of the electrodes forming the voltage terminals V1, V2 is s. The voltage generated between) V _H is
V _H = R _H (IB / t) cos θ (1)
R _H = 1 / (qn) (2)
It can be expressed as Here, R _H is the Hall coefficient, q is the charge, and n is the carrier concentration. Further, since the Hall voltage V _H also changes depending on the shape of the current path, Equation 1 can be expressed as V _H = (R _H / t) G (L / w, s / w) IB cos θ (3)
It can also be expressed as Here, G is a shape effect coefficient.

As can be seen from Equations 1 to 3, the Hall voltage V _H changes in accordance with the angle θ formed by the Hall element and the magnetic field. Therefore, by using this, the angle can be detected. Thus, the above-described angle detection sensor can be realized by using the Hall element.

  By the way, as a general Hall element, a horizontal Hall element that detects a magnetic field component perpendicular to the substrate (wafer) surface is known. Recently, however, in addition to this, a magnetic field that is horizontal to the substrate (wafer) surface is known. Vertical Hall elements that detect components have also been studied. Since this vertical Hall element has a feature that two elements having different phase differences can be integrated on one chip, the two vertical Hall elements are arranged at an angle of 90 °, so that 0 ° to A rotation sensor capable of obtaining a linear output in an angle range of 360 ° can also be realized. And as such a vertical Hall element, what is described, for example in patent documents 1 is known. Hereinafter, an example of the vertical Hall element will be described with reference to FIG.

  9A shows a planar structure of the vertical Hall element, FIG. 9B shows a cross-sectional structure taken along line C1-C1 of FIG. 9A, and FIG. The cross-sectional structures along the line C2-C2 in FIG. 9A are respectively shown.

  As shown in FIGS. 9A to 9C, the Hall element 90 is formed on a semiconductor substrate having an epitaxial film, that is, a so-called epitaxial substrate. Specifically, for example, it has a semiconductor layer (P-sub) 91 made of, for example, P-type silicon, and is formed by introducing N-type impurities into this surface to form a buried layer BL. On top of this, an N-type semiconductor region 92 is formed by epitaxial growth. The buried layer BL functions as a lower electrode, and its impurity concentration is set higher than that of the semiconductor region 92.

Further, N ⁺ diffusion layers 93a to 93e are formed on the surface of the semiconductor region 92 so that the impurity concentration (N-type) on the surface is selectively increased. As a result, an ohmic contact is formed between the N ⁺ diffusion layers 93a to 93e and the electrodes (wirings) disposed therein. These N ⁺ diffusion layers 93a to 93e are electrically connected to terminals S, G1, G2, V1, and V2, respectively, through electrodes (wirings) formed there. N ⁺ diffusion layer 93a is formed in such a manner as to be narrowed by both N ⁺ diffusion layers 93b and 93c and N ⁺ diffusion layers 93d and 93e formed in a mode orthogonal to these N ⁺ diffusion layers.

In the semiconductor region 92, a P-type diffusion layer 94 is formed so as to be connected to the semiconductor layer 91 so as to surround the entire periphery of the N ⁺ diffusion layers 93a to 93e. As a result, the Hall element 90 is separated from other elements. Further, P-type diffusion layers 94a and 94b are formed inside the N ⁺ diffusion layers 93a, 93d and 93e so as to surround the diffusion layers 94. And the part divided in the said semiconductor region 92 by these diffusion layers 94 and 94a and 94b becomes what is called a hole plate (magnetic detection part) HP9. That is, the Hall element 90 detects the magnetism (magnetic field) incident on this portion (Hall plate HP9).

Here, for example, when a constant current flows between the terminal S and the terminal G1 and between the terminal S and the terminal G2, the current flows from the N ⁺ diffusion layer 93a through the buried layer BL. It flows to the N ⁺ diffusion layer 93b or the N ⁺ diffusion layer 93c, respectively. As a result, a current including a current component perpendicular to the substrate surface flows in the hall plate HP9. At this time, if a magnetic field including a horizontal component is incident on the Hall plate 90, more precisely, the Hall plate HP9, the terminal V1 and the terminal V2 are caused by the Hall effect described above. Hall voltage is generated during the period. That is, by detecting the Hall voltage through these terminals V1 and V2, a magnetic field component horizontal to the substrate surface can be obtained from the equation shown in FIG. In this Hall element 90, the dimension d shown in FIG. 9 corresponds to the thickness t of the Hall element in the equation shown in FIG. In addition, a vertical Hall element having a structure described in Non-Patent Document 1 is also known, and an example thereof will be described with reference to FIG. 10A shows the planar structure of the vertical Hall element, FIG. 10B shows the cross-sectional structure along the line D1-D1 in FIG. 10A, and FIG. The cross-sectional structures along line D2-D2 in FIG. 10 (a) are respectively shown. In FIGS. 10A to 10C, the same elements as those shown in FIGS. 9A to 9C are denoted by the same reference numerals. As shown in FIGS. 10A to 10C, in the Hall element 90a, the width w9a of the buried layer BL is the same as that of the Hall element 90 shown in FIGS. 9A to 9C. The buried layer BL is formed narrower than the width w9. As a result, the width of the effective current path from the electrode (wiring) on the substrate surface to the buried layer BL is narrowed, and the spread of such current in the width direction is suppressed. Can also be raised.
Japanese Patent Laid-Open No. 1-251763 Ichisuke Maenaka, 3 others, "Integrated 3D magnetic sensor", IEEJ Transaction C, 1989, Vol. 109, No. 7, p483-490

  As described above, the vertical Hall element illustrated in FIG. 9 or 10 can detect a magnetic field component applied to the Hall plate HP9, that is, a magnetic field component horizontal to the substrate (wafer) surface. In particular, these vertical Hall elements are provided with the buried layer BL, so that a current path is ensured in the vicinity of the bottom surface of the semiconductor region 92, and further described in Non-Patent Document 1. As described above, by reducing the width of the buried layer BL, the magnetic detection sensitivity as a Hall element can be improved. However, in such a vertical Hall element, since an epitaxial substrate must be used as a semiconductor substrate, the degree of freedom in selecting the substrate is greatly limited, and the buried layer BL caused by the heat treatment step is also limited. From the viewpoint of improving sensitivity, there is still room for improvement.

  The present invention has been made in view of such circumstances, and provides a vertical Hall element capable of detecting a magnetic field component horizontal to the substrate surface with higher sensitivity while increasing the degree of freedom in selecting the substrate. The purpose is to do.

In order to achieve such an object, according to the first aspect of the present invention, a semiconductor region having a predetermined conductivity type is formed in a semiconductor substrate, and a current containing a current component perpendicular to the surface of the semiconductor substrate is supplied to the semiconductor substrate. As a vertical Hall element that detects a magnetic field component horizontal to the surface of the semiconductor substrate through a Hall voltage generated based on being supplied to a magnetic detection unit in the region, two Hall voltage output terminals for detecting the Hall voltage are provided. The semiconductor regions arranged side by side so as to sandwich the current supply end for supplying the current are of the same conductivity type and are sandwiched by the semiconductor regions serving as the output regions of the supplied current. while it is partitioned by the surface of the semiconductor substrate by diffusion layer serving as a magnetic detector compartment layer made of electrically semiconductor region serving as an output region of their current within the semiconductor substrate Are connected, also by widening the diffusion layer serving as the element isolation layer formed of another conductive type, width in the direction perpendicular to the path of the current of each semiconductor region serving as the output region of the current, the surface of the semiconductor substrate In this case, the width of the semiconductor region to which the current is supplied is narrower than the width in the direction perpendicular to the current path .

According to such a structure as a vertical Hall element, the current is supplied in the semiconductor region partitioned on the surface of the semiconductor substrate by the diffusion layer (magnetic detection unit partition layer) having the other conductivity type. The semiconductor region becomes a magnetic detection unit. In the vicinity of the bottom surface of each semiconductor region, a current path is secured in such a manner that it is selectively narrowed by the diffusion layer (element isolation layer) made of the other conductivity type. Accordingly, a current including a current component perpendicular to the surface of the semiconductor substrate supplied from the surface of the magnetic detection unit is induced to the outside of the magnetic detection unit through such a current path, and the current output region It flows into each semiconductor region. However, due to the widening of the diffusion layer (element isolation layer) made of the other conductivity type , the width in the direction perpendicular to the current path of each semiconductor region serving as the current output region is only at the surface of the semiconductor substrate. Since the width of the semiconductor region to which the current is supplied ( magnetic detection unit ) is narrower than the width in the direction perpendicular to the current path , the effective current path flowing in the semiconductor region is narrowed. Be able to. As a result, the magnetic detection sensitivity as a vertical Hall element that detects a magnetic field component horizontal to the surface of the semiconductor substrate can be increased. The same structure as a vertical Hall element can be realized in any semiconductor substrate, not limited to the above-described epitaxial substrate, and the degree of freedom in selecting the substrate is naturally increased. Further, as in the same structure, if the width in the direction perpendicular to the current path of each semiconductor region serving as the current output region is formed narrow only on the surface of the semiconductor substrate, it is relatively easy. Since the current path width in the current output region can be reduced, the effective current path width flowing in the semiconductor region can be reduced in such a range .

Alternatively, in order to achieve such an object, a semiconductor region having a predetermined conductivity type is formed in the semiconductor substrate, and includes a current component perpendicular to the surface of the semiconductor substrate. Two holes that detect the Hall voltage as vertical Hall elements that detect a magnetic field component that is horizontal to the surface of the semiconductor substrate through a Hall voltage that is generated when current is supplied to the magnetic detection unit in the semiconductor region. The semiconductor regions arranged side by side so that the voltage output end sandwiches the current supply end for supplying the current are sandwiched between the semiconductor regions that are of the same conductivity type and become the output region of the supplied current, It is partitioned on the surface of the semiconductor substrate by a magnetic detecting portion partition layer which is a diffusion layer of another conductivity type, and becomes an output region of these currents inside the semiconductor substrate. It is connected to conductive area electrically, also by widening the diffusion layer serving as the element isolation layer formed of another conductive type, the width in the direction perpendicular to the path of the current of each semiconductor region serving as the output region of the current the over the semiconductor substrate, and a structure in which the current is smaller than the width perpendicular to the path of the current of the semiconductor regions to be supplied.

Incidentally, as in the structure according to the invention described in claim 2, the width in the direction perpendicular to the path of the current of each semiconductor region serving as the output region of said current, narrowing is formed over the semiconductor substrate If so, the width of the current path can be narrowed over a wider range in the current output region, and therefore, the width of the effective current path flowing in the semiconductor region in a wider range can be reduced. Ri Na to allow, resulting exert the invention described in claim 1
It is possible to obtain the same operational effects as the operational effects .

Further, in the vertical Hall element according to claim 1 or 2 , according to the invention of claim 3 , the surface of the semiconductor region to which the current is supplied and each semiconductor region to be the output region of the current on the surface of, provided the current supply terminal and said current output terminal to which the impurity concentration are selectively formed as elevated diffusion layer electrode and the ohmic contact made of those semiconductor regions the same conductivity type and each Further, the surface of the semiconductor region to which the current is supplied is further formed as a diffusion layer which is also of the same conductivity type as the semiconductor region and has a selectively increased impurity concentration, and is in ohmic contact with the electrode. it is particularly effective that the two Hall voltage output terminal which is a structure provided in a direction perpendicular to the path of the current, according to this structure, this Luo current supply terminal, current output, with good ohmic contact between the two Hall voltage output terminal electrodes disposed on each of those parts are formed, it corresponds to the horizontal magnetic field component to the surface of the semiconductor substrate As a result, the Hall voltage output as a voltage can be extracted efficiently.

Further, in the vertical Hall element according to any one of claims 1 to 3 , according to the invention according to claim 4 , the semiconductor region to which the current is supplied and each semiconductor region to be the output region of the current are Both have a structure in which the semiconductor substrate is formed as a diffusion layer in which the impurity of the predetermined conductivity type is added, as well as a substrate of a single conductivity type, an epitaxial substrate, and an SOI (Silicon On Insulator) substrate. For example, the semiconductor region described above can be easily formed in any shape. In this case, since the formation of the buried layer as the current path of the Hall element can be omitted, the complicated alignment process for forming the buried layer can be omitted. It is also possible to increase the degree of freedom in manufacturing. Further, since it becomes possible to suppress the generation of the offset voltage due to the complicated manufacturing process for forming the buried layer, the magnetic detection accuracy can be improved in this sense.

Further in this case, such as by the invention described in claim 5, wherein the semiconductor substrate and the semiconductor regions defining respective the surface of the semiconductor substrate diffusion layer serving as the element isolation layer and the magnetic detection unit compartment layer P It is particularly effective that the diffusion layer forming the semiconductor region of the type conductivity type and forming the semiconductor region to which the current is supplied and the semiconductor region to be the current output region have an N type conductivity type. In general, a semiconductor material composed of an N-type conductivity has a higher carrier mobility than a semiconductor material composed of a P-type conductivity. By adopting such a structure, the magnetic detection sensitivity as a vertical Hall element is further increased. Can be raised. Note that the semiconductor region is not limited to being formed as a diffusion layer doped with impurities,
In order to increase the magnetic detection sensitivity as a Hall element, it is effective to employ a semiconductor material of N type conductivity for the semiconductor region.

Further, regarding the vertical Hall element according to claim 4 or 5 , as in the invention according to claim 6 , if the Hall element is formed integrally with a CMOS circuit as a peripheral circuit thereof, The Hall element can be manufactured together with the CMOS circuit by a normal CMOS process. That is, the Hall element can be manufactured by sharing the manufacturing process of the CMOS circuit as such a peripheral circuit, and as a result, the Hall element can be manufactured more easily and efficiently.

With respect to the vertical Hall element according to any one of claims 1 to 6 , according to the invention according to claim 7 , the semiconductor region to which the current is supplied and each semiconductor region to be the output region of the current If a field oxide film having a LOCOS (Local Oxidation Of Silicon) structure is formed on the surface of the semiconductor layer so as to cover these semiconductor regions, these semiconductor regions are covered with a field oxide film having a LOCOS structure. After manufacturing the Hall element, for example, when an ion implantation process or a plasma process is performed as a manufacturing process of the peripheral circuit or the like, damage to the Hall element that is a concern is reduced. . In addition, since the field oxide film having such a LOCOS structure is also used for element isolation in a normal CMOS process, when a CMOS circuit is adopted as a peripheral circuit, the manufacturing process is shared with the CMOS circuit. Therefore, such a field oxide film can be easily formed.

(First embodiment)
A first embodiment of a vertical Hall element according to the present invention will be described below with reference to FIGS. The vertical Hall element according to this embodiment also detects a magnetic field component horizontal on the substrate (wafer) surface, similarly to the vertical Hall element exemplified in FIGS.

  First, FIG. 1A shows a planar structure of the vertical Hall element, FIG. 1B shows a cross-sectional structure taken along line A1-A1 of FIG. 1A, and FIG. 1 (a) schematically shows a cross-sectional structure taken along line A2-A2, and FIG. 1 (d) schematically shows a cross-sectional structure taken along line A3-A3 in FIG. 1 (a).

  As shown in FIGS. 1A to 1D, the Hall element 10 is formed on a semiconductor substrate (P-sub) 11 made of, for example, P-type silicon. A semiconductor region (N well) 12 as a diffusion layer is formed on the surface of the semiconductor substrate 11 by adding, for example, an N-type impurity. In general, a semiconductor material such as silicon has a larger carrier mobility in an N-type semiconductor than in a P-type semiconductor. Even in the vertical Hall element according to this embodiment, the semiconductor region has 12 By adopting N type, the sensitivity of the Hall element is increased. Incidentally, as the impurity concentration of the semiconductor region 12 is lower, the carrier mobility in the same region is increased, and the sensitivity as the Hall element can be increased. By forming the semiconductor region 12 as a diffusion layer in this manner, the Hall element substrate may be a single conductive type substrate such as the semiconductor substrate 11, an epitaxial substrate, or SOI (Silicon On Insulator). ) A substrate or the like can also be adopted.

Further, above the surface of the semiconductor region 12, the impurity concentration of the surface (N-type) is N ⁺ diffusion layer 13a~13e in the form that is selectively enhanced are formed, each of these respective N ⁺ diffusion layer 13a~13e is Are in ohmic contact with electrodes (wirings) disposed on the substrate. Specifically, the N ⁺ diffusion layer 13a is provided with a current supply terminal electrically connected to the terminal S, and the N ⁺ diffusion layers 13b and 13c are electrically connected to the terminals G1 and G2, respectively. A current output terminal is provided. Further, as the N ⁺ diffusion layers 13d and 13e, Hall voltage output terminals electrically connected to the terminals V1 and V2 are provided in a direction orthogonal to a current path described later.

Further, a P-type diffusion layer (P well) 14 is formed in the semiconductor region 12 so as to surround the entire periphery of the N ⁺ diffusion layers 13a to 13e, and the Hall element 10 is connected to other elements. And the elements are separated. The semiconductor region 12 includes a semiconductor region 12a in which the N ⁺ diffusion layers 13a, 13d and 13e are formed on the surface of the semiconductor substrate 11, and each semiconductor region in which the N ⁺ diffusion layers 13b and 13c are formed. It is partitioned by P-type diffusion layers (P wells) 14a and 14b so as to be sandwiched between 12b and 12c. The semiconductor region 12a is a region to which the current is supplied, and the semiconductor regions 12b and 12c are output regions for the current. The semiconductor region 12a to which this current is supplied becomes the Hall plate (magnetic detection unit) HP1 of the Hall element 10. Specifically, the hall plate HP1 is formed such that the length between the diffusion layers 14a and 14b is a dimension d, and the width in the direction orthogonal to the current path is a dimension w1a. The semiconductor region 12a to which these currents are supplied is electrically connected to the semiconductor regions 12b and 12c serving as the current output regions in the vicinity of the bottom surface. In other words, the semiconductor region 12 is selectively narrowed by the diffusion layers 13 b and 13 c, and a current path is formed near the bottom surface of the semiconductor region 12.

  As described above, in the Hall element 10 according to this embodiment, unlike the Hall element illustrated in FIGS. 9 and 10, the buried layer BL (see FIGS. 9 and 10) is formed on the surface of the semiconductor substrate 11. A current path is secured without being formed. Each of the semiconductor regions 12b and 12c serving as the current output region has a width in a direction orthogonal to the current path as dimensions w1b and w1c due to the widening of the P-type diffusion layers (P wells) 14a and 14b. Is formed. These are all formed narrower than the width (dimension w1a) of the hole plate HP1, so that the effective width of the current path is reduced.

  FIG. 2 shows an impurity concentration distribution (concentration profile) of the Hall element 10 according to this embodiment, and shows a perspective view when the cross-sectional structure shown in FIG. It is a thing. The dimension a shown in FIG. 2 indicates the width of a current path formed in the vicinity of the bottom surface of the semiconductor region 12 by the diffusion layers 14a and 14b. Normally, when such a diffusion layer is formed by adding an impurity to a semiconductor substrate, the width of the diffusion layer becomes narrower as it gets deeper from the surface of the substrate. The flowing current tends to spread as it goes deeper, and there is a concern that the sensitivity of the Hall element will decrease. In this regard, in the vertical Hall element 10 according to this embodiment, the impurity concentration distribution (concentration profile) of the semiconductor region 12 and the diffusion layers 14a and 14b is as shown in FIG. As it gets deeper from the surface of the substrate 11, it gradually becomes lower (thinner). Since the width of the depletion layer formed becomes larger as the impurity concentration becomes lower in this way, the spread of the current flowing through the hole plate HP1 is suppressed by taking such an impurity concentration distribution, and as a result, high sensitivity as a Hall element. Can be achieved. In addition, in the Hall element 10 according to this embodiment, since a buried layer or the like as a current path is not formed, misalignment (alignment misalignment) due to a mask alignment error at the time of element fabrication and an offset voltage resulting therefrom. In this sense, the spread of current is suppressed without causing an increase in current.

Here, with reference to these FIG. 1 and FIG. 2, an outline of the magnetic detection principle in the Hall element 10 will be described. In the Hall element 10, for example, when a constant current (drive current) is allowed to flow between the terminal S and the terminal G1 and between the terminal S and the terminal G2, the current flows through the Hall plate HP1. The inside flows from the N ⁺ diffusion layer 13 a to the bottom surface of the semiconductor region 12. Then, it is guided to the outside of the Hall plate HP1 through a current path formed in the vicinity of the bottom surface in the semiconductor region 12, and flows toward the N ⁺ diffusion layer 13b or the N ⁺ diffusion layer 13c. If a magnetic field including a horizontal component is incident on the surface of the substrate in the Hall plate HP1, a Hall voltage V _H is generated between the terminal V1 and the terminal V2 due to the Hall effect described above. That is, by detecting the Hall voltage V _H through the terminals V1 and V2, a magnetic field component horizontal to the substrate surface can be obtained using the equation shown in FIG. In this Hall element 10, the dimension d corresponds to the thickness t of the Hall element of the formula shown in FIG. 8, and the dimensions w1a and w1b are the Hall elements of the formula shown in FIG. Is equivalent to the width w. Incidentally, when the direction of the drive current in the opposite, that is, even when the N ⁺ diffusion layer 13b, or N ⁺ diffusion layer 13c to flow a drive current to the N ⁺ diffusion layer 13a, the magnetic field in the same principle ( Magnetism) can be detected.

  Further, the impurity concentration of the semiconductor region 12 and the diffusion layers 14a and 14b is such that the current path is surely ensured near the bottom surface in the semiconductor region 12 even after the depletion layer is formed therebetween. Range. However, in order to increase the sensitivity of the Hall element 10, it is effective to form the diffusion layers 14a and 14b deep to reduce the width (dimension a) of the current path. More preferably, the impurity concentrations of the diffusion layers 14a and 14b are set in consideration of the influence on the magnetic detection sensitivity.

  FIG. 3 shows the Hall element 10 according to this embodiment together with its peripheral circuit for reference. The Hall element 10 according to this embodiment is formed as a region in which the semiconductor region 12 is electrically isolated from other regions by a pn bond formed between the semiconductor substrate 11 and the hole. The element 10 is preferably separated from the peripheral circuit and the like. 3A schematically shows a planar structure of the Hall element 10 and peripheral circuits, and FIG. 3B schematically shows a cross-sectional structure taken along line A4-A4 of FIG. 3A. .

  As shown in FIGS. 3A and 3B, the Hall element 10 is integrated with a CMOS circuit C10 as a peripheral circuit including a drive circuit, a power supply circuit, and the like of the Hall element 10, for example. Is formed. More specifically, the CMOS circuit C10 includes, for example, a P-channel FET (using a semiconductor substrate 11 itself as a channel and a gate insulating film I1a, a gate electrode G1a, and N-type source / drain layers C13a and C13b). Field Effect Transistor). Further, for example, a semiconductor region (N well) C12 formed by adding an N-type impurity in the semiconductor substrate 11 is used as a channel, a gate insulating film I1c and a gate electrode G1c, and a P-type source / drain layer C13e and An N-channel FET constituted by C13f is also included in the circuit. Further, in the CMOS circuit C10, a semiconductor region (P well) C13 formed by adding a P-type impurity in the semiconductor region C12 is used as a channel, and a gate insulating film I1b, a gate electrode G1b, and an N-type are formed. Also included is a P-channel FET formed by the source / drain layers C13c and C13d. These FETs are isolated from each other by a field oxide film CL1 having a LOCOS (Local Oxidative Of Silicon) structure. The source / drain layers C13a to C13f are electrically connected to wirings (electrodes) C16a to C16f through contact holes formed in the insulating film 15, respectively. The material of the gate electrodes G1a to G1c is, for example, polycrystalline silicon, and the material of the insulating film 15 is, for example, PSG (Phosphorus Silicate Glass). Moreover, aluminum etc. are used for the material of wiring (electrode), for example.

  Next, an example of a method for manufacturing such a Hall element 10 will be described with reference to FIGS. 4 and 5 show the cross-sectional structure corresponding to the cross-sectional view shown in FIG. 3B, and FIG. 6 shows A5 in FIG. 3A. This shows a cross-sectional structure along the line -A5. It should be noted that the same elements as those shown in FIG. 3 are denoted by the same reference numerals, and redundant description of these elements is omitted.

  When manufacturing the Hall element 10, first, as shown in FIGS. 4A and 6A, a (100) semiconductor substrate 11 made of, for example, P-type silicon is prepared. Next, for example, an N-type impurity such as phosphorus (P) is selectively ion-implanted into the semiconductor substrate 11 using, for example, a resist (not shown) as a mask, and then an appropriate heat treatment is performed to diffuse the implanted impurity. . As a result, as shown in FIGS. 4B and 6B, the semiconductor region (N well) 12 and the semiconductor region (N well) C12 are formed.

  Next, for example, using a resist or the like (not shown) as a mask, a P-type impurity such as boron (B) is selectively ion-implanted into the semiconductor substrate 11 and then subjected to an appropriate heat treatment to diffuse the implanted impurity. Let As a result, as shown in FIGS. 4C and 6C, the diffusion layers (P wells) 14 and 14a and 14b and the semiconductor region (P well) C13 are formed. The impurity concentration of the semiconductor region 12 and the diffusion layers 14a and 14b is such that a current path is ensured in the vicinity of the bottom surface in the semiconductor region 12 even after a depletion layer is formed between them. Set to range.

  Next, as shown in FIG. 5A, a field oxide film CL1 having a LOCOS structure is selectively formed at a desired location by, for example, a well-known selective oxidation method. Although details of this formation method are not shown, specifically, a silicon oxide film (pad oxide film) and a silicon nitride film are sequentially formed, and the silicon nitride film is selectively removed by, for example, a photolithography technique. Then, an opening is formed at a desired location. Then, only the opening not covered with the silicon nitride film is locally thermally oxidized to form the field oxide film CL1, and the formed silicon oxide film (pad oxide film) and silicon nitride film are removed. Formed by. Then, after forming the gate insulating films I1a to I1c made of silicon oxide, for example, by thermal oxidation, the gate electrodes G1a to G1c are formed on the gate insulating films I1a to I1c, respectively. Although details of this forming method are not shown, specifically, a polycrystalline silicon film is formed by, for example, LP-CVD (low pressure chemical vapor deposition), and, for example, a conductive type such as phosphorus (P) is formed by thermal diffusion. Impurities are added to the formed polycrystalline silicon film. Thereafter, the polycrystalline silicon film is selectively etched to form the gate electrodes G1a to G1c at desired locations.

Next, for example, an N-type impurity such as arsenic (As) or a P-type impurity such as boron (B) is selectively ion-implanted into the semiconductor substrate 11 using a resist or the like (not shown) as a mask. The implanted impurities are diffused by performing the heat treatment. As a result, as shown in FIGS. 5B and 6D, the N ⁺ diffusion layers 13a to 13c and the source / drain layers C13a to C13d are formed. Although not shown here, C13a to C13f may be formed in a self-aligned manner using the field oxide film CL1 and the gate electrodes G1a to G1c as masks. Further, if necessary, for example, a sidewall, silicide, or the like may be formed thereafter.

  Further, as shown in FIGS. 5C and 6E, the insulating film 15 is formed on the semiconductor substrate 11 by, for example, a thermal CVD method, and the insulating film 15 is appropriately patterned to be desired. A contact hole is formed at the location. Then, a wiring material such as aluminum is formed in a manner to fill the contact holes, and the formed wiring material is patterned to thereby form the wirings (electrodes) 16a to 16c and the wirings (electrodes) C16a to C16f. Form. Thus, as shown in FIGS. 3A and 3B, the Hall element 10 is integrally formed with the peripheral circuit (CMOS circuit C10).

Thus, the manufacture of the Hall element 10 according to this embodiment can be efficiently realized by sharing the manufacturing process of the CMOS circuit C10.
As described above, according to the vertical Hall element according to this embodiment, the effects listed below can be obtained.

  (1) In the vicinity of the bottom surface of the semiconductor region (N well) 12, a current path is secured in such a manner that it is selectively narrowed by the diffusion layer (P well) 14. Further, in each of the semiconductor regions 12b and 12c that are N-type conductivity and serve as the current output region, the widths w1b and w1c in the direction orthogonal to the current path are P-type conductivity and the diffusion layer The width of the semiconductor region 12a supplied with the current is narrower than the width w1a of the semiconductor region 12a due to the widening of 14a and 14b. Thereby, the width of the effective current path flowing in the semiconductor region 12 is narrowed, and the magnetic detection sensitivity as the vertical Hall element 10 for detecting the magnetic field component horizontal to the surface of the semiconductor substrate 11 is increased. Will be able to. Further, the same structure as the vertical Hall element can further increase the magnetic detection sensitivity as the Hall element 10 when the semiconductor region 12 is made of an N-type conductivity type having a large carrier mobility. become able to. Further, these semiconductor regions 12 are formed as diffusion layers to which an impurity of N-type conductivity is added. As a result, the above-described semiconductor region can be easily formed in an arbitrary shape on a substrate having a single conductivity type, an epitaxial substrate, an SOI (Silicon On Insulator) substrate, or the like. In this case, since the formation of the buried layer as the current path of the Hall element can be omitted, the complicated alignment process for forming the buried layer can be omitted. It is also possible to increase the degree of freedom in manufacturing. Further, since it becomes possible to suppress the generation of the offset voltage due to the complicated manufacturing process for forming the buried layer, the magnetic detection accuracy can be improved in this sense.

  (2) The widths of the semiconductor regions 12b and 12c serving as the current output regions are narrowed only on the surface of the semiconductor substrate 11. For this reason, since the width of the current path in each of the semiconductor regions 12b and 12c, which are the current output regions, can be reduced relatively easily, the effective current flowing in the semiconductor region 12 in such a range can be reduced. The width of the path can be reduced.

(3) The impurity concentration is selectively increased on the surface of the semiconductor region (N well) 12 to which the current is supplied and on the surface of each semiconductor region (N well) 12 serving as a current output region. ^{The +} diffusion layer 13a, the N ⁺ diffusion layers 13b and 13c, and the N ⁺ diffusion layers 13d and 13e are formed. Thus, as these N ⁺ diffusion layer, a current supply terminal, an output terminal of the current output terminal and the Hall voltage is provided, good ohmic contact is formed between the electrodes disposed on the N ⁺ diffusion layer At the same time, a Hall voltage output as a voltage corresponding to a magnetic field component horizontal to the surface of the semiconductor substrate can be efficiently extracted.

  (4) The Hall element 10 is formed integrally with a CMOS circuit C10 as a peripheral circuit thereof. This makes it possible to produce the Hall element 10 together with the CMOS circuit C10 by a normal CMOS process. That is, the Hall element 10 can be manufactured by sharing the manufacturing process of the CMOS circuit C10 as such a peripheral circuit, and as a result, the Hall element 10 can be manufactured more easily and efficiently. become.

  (5) The field oxide film CL1 having the LOCOS structure on the surface of the semiconductor region 12a to which the current is supplied and the surfaces of the semiconductor regions 12b and 12c serving as the current output region so as to cover the semiconductor regions 12a to 12c. Was decided to be formed. As a result, the semiconductor regions 12a to 12c are covered with the field oxide film CL1 having a LOCOS structure. Therefore, after the Hall element 10 is manufactured, for example, an ion implantation process or a plasma process is performed as a manufacturing process of the peripheral circuit or the like. Even in such a case, the damage to the vertical Hall element, which is a concern due to them, can be reduced. The field oxide film CL1 having such a LOCOS structure is also used for element isolation in a normal CMOS process. Therefore, when a CMOS circuit is employed as a peripheral circuit, the CMOS circuit and the manufacturing process are shared. As a result, such a field oxide film can be easily formed.

(Second Embodiment)
Next, a second embodiment of the vertical Hall element according to the present invention will be described with reference to FIG. The basic operation mode and configuration of the vertical Hall element according to this embodiment is the same as that of the first embodiment, and the formation of the semiconductor region (N well) formed in the semiconductor substrate is performed. Only the aspects are different.

  FIG. 7A shows a planar structure of the vertical Hall element, FIG. 7B shows a cross-sectional structure taken along line B1-B1 of FIG. 7A, and FIG. 7C shows FIG. ) Schematically shows a cross-sectional structure taken along line B2-B2, and FIG. 7D schematically shows a cross-sectional structure taken along line B3-B3 in FIG. 7A.

  As shown in FIGS. 7A to 7D, the Hall element 20 includes a semiconductor substrate (P-sub) 21 and a semiconductor region (as a diffusion layer) as in the first embodiment. N well) 22. As in the first embodiment, the semiconductor region (N well) 22 is selectively formed with respect to the semiconductor substrate 21 using, for example, a resist (not shown) as an N-type impurity such as phosphorus (P). Is formed by ion implantation. Therefore, a region where such a semiconductor region 22 is formed can be set according to the shape of the mask. Specifically, in this embodiment, the semiconductor region 22 is formed in a substantially cross shape on the surface of the substrate 21.

Further, N ⁺ diffusion layers 23a to 23e are formed on the surface of the semiconductor region 22 in the same manner as in the first embodiment in such a manner that the impurity concentration (N type) on the surface is selectively increased. These N ⁺ diffusion layers 23a to 23e are in ohmic contact with the electrodes (wirings) disposed therein. Specifically, the N ⁺ diffusion layer 23a terminal S and the current supply terminal which is electrically connected is provided as, the N ⁺ diffusion layer 23b and the respective terminals as 23c G1 and G2 electrically connected to the current An output end is provided. Further, Hall voltage output terminals electrically connected to terminals V1 and V2 are provided as N ⁺ diffusion layers 23d and 23e, respectively.

Further, a P-type diffusion layer (P well) 24 is formed in the semiconductor region 22 so as to surround all the periphery of the N ⁺ diffusion layers 23a to 23e, and the Hall element 20 is connected to other elements. And the elements are separated. Furthermore, the semiconductor region 22, the semiconductor region 22a in which the current which the N ⁺ diffusion layer 23a~23c is formed in the surface thereof is supplied, the current which the N ⁺ diffusion layers 23b and 23c are formed In such a manner as to be sandwiched between the respective semiconductor regions 22b and 22c serving as output regions, the P regions are partitioned by P type diffusion layers (P wells) 24a and 24b. The semiconductor region 22a to which this current is supplied becomes the Hall plate (magnetic detection unit) HP2 of the Hall element 20. Specifically, the hole plate HP2 is formed such that the length between the diffusion layers 24a and 24b is a dimension d, and the width in the direction orthogonal to the current path is a dimension w2a. Then, the semiconductor region 22a to which these currents are supplied and the semiconductor regions 22b and 22c serving as the current output regions are electrically connected in the vicinity of the bottom surface. In other words, the semiconductor region 22 is selectively narrowed by the diffusion layers 23 a and 23 b, and a current path is formed near the bottom surface of the semiconductor region 22.

  Each of the semiconductor regions 22b and 22c serving as the current output region has a width in a direction orthogonal to the current path as dimensions w2b and w2c, both of which are the width of the hall plate HP2 (dimension w2a). As a result, the effective width of the current path is narrowed. In addition, in the Hall element 20 according to this embodiment, the semiconductor regions 22b and 22c serving as the current output regions are formed to have a narrow width across the semiconductor substrate 21, and the semiconductor regions 22 and 22c The effective width of the current path is narrowed over a wider range. For this reason, the magnetic detection sensitivity as the Hall element 10 can be more effectively enhanced by the same detection principle as in the first embodiment.

  As described above, the vertical Hall element according to the second embodiment also has an effect equivalent to or equivalent to the effects (1) to (5) of the first embodiment. The following effects can be obtained as well.

  (6) The semiconductor regions 22b and 22c serving as the current output regions are formed so as to have a width narrower than the width of the semiconductor region 22a to which the current is supplied over the semiconductor substrate 21. As a result, the width of the current path in the current output region can be narrowed, so that the width of the effective current path flowing in the semiconductor region can be narrowed in a wider range.

(Other embodiments)
Note that the vertical Hall element according to the present invention is not limited to the structure exemplified as the first and second embodiments, but can be implemented in the modes exemplified below by appropriately changing these embodiments. .

  In each of the above embodiments, the surface of the semiconductor regions (N wells) 12 and 22 is divided into a semiconductor region to which current is supplied by a diffusion layer (P well) and a current output region. However, the method of forming each of the semiconductor regions that are formed in these sections is arbitrary. That is, after the semiconductor regions (N wells) 12 and 22 are integrally formed, the diffusion layer (P well) may be formed to partition the semiconductor regions (P wells). You may make it form in a process.

  In each of the above embodiments, the vertical Hall element 10 includes the terminal S as a current supply terminal, the terminals G1 and G2 as current output terminals, and the terminals V1 and V2 as terminals that output Hall voltage. However, the number and arrangement of these terminals, or the direction of current flow are not limited to these.

  In each of the above embodiments, the CMOS circuits C10 and C20 are used as the peripheral circuits of the Hall elements 10 and 20. However, the present invention is not limited thereto, and for example, a bipolar circuit or the like can be used as the peripheral circuit of the Hall elements. .

  In each of the above embodiments, the substrates 11 and 21 made of P-type conductivity are used as the substrates (semiconductor substrates) on which the vertical Hall elements 10 and 20 are formed. The semiconductor regions 12 and 22 having the conductivity type are formed. However, such a substrate is not limited to this, and for example, an epitaxial substrate, an SOI substrate, or the like can be adopted, and a substrate having a multiple diffusion structure such as PNP or NPN can also be adopted. it can. In addition, a P-type semiconductor region can be formed using a substrate made of N-type conductivity.

  Further, when the above epitaxial substrate is used, for example, the vertical Hall element illustrated in FIG. 9 or FIG. 10 has a structure according to the present invention, that is, “the width of each semiconductor region serving as a current output region is other conductive A structure in which the width of the semiconductor region to which current is supplied is narrowed by expanding the diffusion layer made of a mold can also be applied.

  In each of the embodiments described above, silicon is used as the material of the semiconductor substrate 11, but other materials may be used depending on the manufacturing process, the structural conditions of the Hall element, and the like. For example, a compound semiconductor such as GaAs (gallium arsenide), InSb (indium antimony), InAs (indium arsenic), SiC (silicon carbide), Ge (germanium), or the like may be employed. In particular, since GaAs (gallium arsenide) and InSb (indium antimony) are materials having excellent temperature characteristics, they are particularly effective for achieving high sensitivity as a vertical Hall element.

Regarding the first embodiment of the vertical Hall element according to the present invention, (a) is a plan view schematically showing the schematic structure, (b) is a cross-sectional view taken along line A1-A1 of (a), (C) is sectional drawing along the A2-A2 line of (a), (d) is sectional drawing along the A3-A3 line of (a). The perspective view which shows the density | concentration profile about the vertical Hall element concerning the said 1st Embodiment. About the vertical Hall element and its peripheral circuit according to the first embodiment, (a) is a plan view schematically showing a schematic structure of the vertical Hall element and the peripheral circuit, and (b) is a plan view of (a). Sectional drawing along the A4-A4 line. (A)-(c) is sectional drawing which shows the manufacturing process about the manufacturing method of the vertical Hall element concerning the same 1st Embodiment, and its peripheral circuit. (A)-(c) is sectional drawing which shows the manufacturing process about the manufacturing method of the vertical Hall element concerning the same 1st Embodiment, and its peripheral circuit. (A)-(e) is sectional drawing which shows the manufacturing process about the manufacturing method of the vertical Hall element concerning the same 1st Embodiment, and its peripheral circuit. Regarding the second embodiment of the vertical Hall element according to the present invention, (a) is a plan view schematically showing the schematic structure, (b) is a cross-sectional view taken along line B1-B1 of (a), (C) is sectional drawing along the B2-B2 line of (a), (d) is sectional drawing along the B3-B3 line of (a). The perspective view which shows the magnetic detection principle of a Hall element. As for an example of a conventional vertical Hall element, (a) is a plan view schematically showing the schematic structure of the Hall element, (b) is a cross-sectional view taken along line C1-C1 in (a), and (c) is Sectional drawing along the C2-C2 line of (a). As for an example of a conventional vertical Hall element, (a) is a plan view schematically showing a schematic structure of the Hall element, (b) is a cross-sectional view taken along line D1-D1 of (a), and (c) is Sectional drawing along the D2-D2 line of (a).

Explanation of symbols

  10, 20, 90 ... Hall element, 11, 21, 91 ... Semiconductor substrate, 12, 12a, 12b, 12c, 22, 22a, 22b, 22c, 92, C12, C13, C22 ... Semiconductor region, 13a-13e, 23a ˜23e ... N + diffusion layer, 14, 14a, 14b, 24, 24a, 24b ... diffusion layer, 15, 25 ... insulating film, 16a-16c, C16a-C16f ... wiring (electrode), G1, G2, V1, V2, S ... terminal, BL ... buried layer, C10, C20 ... CMOS circuit, C13a-C13f ... source / drain layer, G1a-G1c ... gate electrode, HL2, CL1, CL2 ... field oxide film, HP1, HP2, HP9 ... hole Plate (magnetic detection unit), I1a to I1c... Gate insulating film.

Claims (7)

A semiconductor region having a predetermined conductivity type is formed in a semiconductor substrate, and a hole is generated when a current including a current component perpendicular to the surface of the semiconductor substrate is supplied to a magnetic detection unit in the semiconductor region. A vertical Hall element that detects a magnetic field component horizontal to the surface of the semiconductor substrate through a voltage,
The semiconductor regions arranged in parallel so that the two Hall voltage output ends for detecting the Hall voltage sandwich the current supply end for supplying the current are made of the same conductivity type and the output region of the supplied current In a mode sandwiched between the semiconductor regions, the magnetic detection unit partitioning layer, which is a diffusion layer of another conductivity type, is partitioned on the surface of the semiconductor substrate, and the semiconductor region serving as an output region of the current is electrically connected to the semiconductor substrate. The width of the semiconductor substrate, which is a diffusion layer of another conductivity type, is widened in a direction perpendicular to the current path of each semiconductor region serving as the current output region, A vertical Hall element characterized in that it is formed only on the surface of the semiconductor region so as to be narrower than a width in a direction orthogonal to the current path of the semiconductor region to which the current is supplied. A semiconductor region having a predetermined conductivity type is formed in a semiconductor substrate, and a hole is generated when a current including a current component perpendicular to the surface of the semiconductor substrate is supplied to a magnetic detection unit in the semiconductor region. A vertical Hall element that detects a magnetic field component horizontal to the surface of the semiconductor substrate through a voltage,
The semiconductor regions arranged in parallel so that the two Hall voltage output ends for detecting the Hall voltage sandwich the current supply end for supplying the current are made of the same conductivity type and the output region of the supplied current In a mode sandwiched between the semiconductor regions, the magnetic detection unit partitioning layer, which is a diffusion layer of another conductivity type, is partitioned on the surface of the semiconductor substrate, and the semiconductor region serving as an output region of the current is electrically connected to the semiconductor substrate. The width of the semiconductor substrate, which is a diffusion layer of another conductivity type, is widened in a direction perpendicular to the current path of each semiconductor region serving as the current output region, The semiconductor region to which the current is supplied is formed to be narrower than the width in the direction perpendicular to the current path.
A vertical Hall element characterized by that . The surface of the semiconductor region to which the current is supplied, and each semiconductor region to be the current output region
The current supply end and the current output end, which are formed as diffusion layers having the same conductivity type as those semiconductor regions and whose impurity concentration is selectively increased and are in ohmic contact with the electrodes, are respectively provided on the surface of In addition, the surface of the semiconductor region to which the current is supplied is further formed as a diffusion layer having the same conductivity type as that of the semiconductor region, and the impurity concentration thereof being selectively increased, and is in ohmic contact with the electrode. vertical Hall element according to claim 1 or 2 provided we are formed by a direction in which the two Hall voltage output terminal perpendicular to the path of the current to be. Each semiconductor region serving as the output region of the semiconductor region, and the current the current is supplied together claim 1 in which impurities consisting of the predetermined conductivity type in the semiconductor substrate is formed as a diffusion layer that is added vertical Hall element according to any one of 3. The element isolation layer, which is a diffusion layer that partitions the semiconductor substrate and the semiconductor region on the surface of the semiconductor substrate , and the magnetic detection unit partition layer are of a P-type conductivity type, and the semiconductor region to which the current is supplied and The vertical Hall element according to claim 4 , wherein the diffusion layer forming each semiconductor region serving as a current output region is of N-type conductivity . The vertical Hall element according to claim 4 or 5 , wherein the Hall element is formed integrally with a CMOS circuit as a peripheral circuit thereof . Semiconductor region wherein the current is supplied, and the surface of each semiconductor region serving as the output region of said current, according to claim 1-6 in which the field oxide film to take LOCOS structure in the form them which covers the semiconductor regions is formed The vertical Hall element according to any one of the above.

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