JP4781159B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a wireless chip that performs wireless communication via electromagnetic waves.

  In recent years, development of automatic recognition technology consisting of a wireless chip that stores information in an electronic circuit, a reader / writer that reads and writes information stored in the wireless chip, and a host system that processes the read information and controls the reader / writer And introduction has been carried out (see FIG. 2). The wireless chip 201 is called by various names such as an RFID tag, an IC tag, and a wireless tag, but since there is no specific name, it is described as a wireless chip in this specification. The wireless chip 201 is basically a battery-free system, performs a dielectric operation by electromagnetic waves emitted from the reader / writer 202, and performs wireless communication with the reader / writer 202. A computer 203 is generally used as a host system, and communicates with a reader via a serial port, a USB (Universal Serial Bus) port 204, or the like. This automatic recognition technology is expected to be able to comprehensively manage everything from the manufacture of goods to physical distribution and retailing. For this reason, the development of inexpensive, high-communication, and even smaller wireless chips is underway. It has been.

As an example, Patent Document 1 considers a multilayer electronic component having a small size and excellent electrical characteristics by using a plurality of two or more types of resin substrates having different dielectric constants and magnetic permeability.
JP 2004-6897 A

  In addition to the electronic components exemplified in the above-mentioned patent document, development of a small and inexpensive wireless chip is underway, and automatic recognition technology using the wireless chip is introduced in the market. As these technologies are used throughout the manufacturing, distribution and retailing of goods, the wireless chip will eventually reach the consumer. The end consumer is an unspecified number of people, some of whom have no knowledge of wireless chips and automatic recognition technology, resulting in unforeseen accidents such as skin injuries or accidental swallowing The danger of doing will arise. Furthermore, the fact that it is used for retailing means that a large amount of wireless chips are used, resulting in a disposal method and a problem related to recycling.

  In order to solve the above problems, the present invention provides a wireless chip capable of ensuring the safety of the end consumer while being a small, highly communicable and inexpensive wireless chip, and a method of using the wireless chip. Is an issue. It is another object of the present invention to provide a wireless chip that can be recycled even after being used for manufacturing, physical distribution, and retail management.

  In order to solve the above problems, the present invention takes the following measures.

  The wireless chip of the present invention includes an antenna and a layer including a semiconductor element electrically connected to the antenna. The antenna includes a first conductive layer, a second conductive layer, and the first conductive layer. A dielectric layer sandwiched between the layer and the second conductive layer, and the dielectric layer is spherical, oval, meteorite-like ellipsoidal sphere, rugby ball-like ellipsoidal sphere, disk, or cylindrical or polygonal column And the outer shape end part has the shape which has a curved surface, It is characterized by the above-mentioned.

  In the wireless chip, the layer including the antenna and the semiconductor element is electrically connected through a resin layer including conductive particles.

The wireless chip of the present invention includes a layer having a semiconductor element, a layer having a passive element electrically connected to the layer having the semiconductor element, and an antenna electrically connected to the layer having the passive element. The antenna includes a first conductive layer, a second conductive layer, and a dielectric layer sandwiched between the first conductive layer and the second conductive layer. It has a shape, a meteorite-like ellipsoidal sphere, a rugby ball-like ellipsoidal sphere, a disc shape, a columnar shape or a polygonal column shape, and its outer end has a curved surface.

  In the wireless chip, the layer including the passive element includes a passive element including at least one of an inductor, a capacitor, and a resistor. The layer including the passive element and the layer including the semiconductor element include conductive particles. It is electrically connected through a resin layer.

  The antenna included in the wireless chip of the present invention includes a first conductive layer that functions as a radiation electrode, a second conductive layer that functions as a grounding body, and the first conductive layer and the second conductive layer. It has a sandwiched dielectric layer.

  In addition, the layer including the semiconductor element included in the wireless chip of the present invention is formed over a semiconductor substrate or an insulating substrate. As the insulating substrate, a flexible substrate can be used. Further, the semiconductor element manufactured over the insulating substrate has an inorganic semiconductor layer or an organic semiconductor layer. And it is preferable that the film thickness of the layer which has the said semiconductor element is 1 micrometer or more and 5 micrometers or less.

  The wireless chip of the present invention includes a high-frequency circuit.

  In the wireless chip of the present invention, the dielectric layer constituting the antenna includes alumina, glass, forsterite, barium titanate, lead titanate, strontium titanate, lead zirconate, lithium diobate, and zircon titanate. It is formed of one or more selected from lead. Further, the dielectric layer can be formed of one or more selected from epoxy resin, phenol resin, polybutadiene resin, BT resin, vinyl benzyl, and polyfumarate.

  The wireless chip of the present invention is coated with resin or DLC so that it has a spherical shape, an oval shape, a meteorite-like elliptical sphere, a rugby ball-like elliptical sphere, a disc shape, or a cylindrical shape or a polygonal column shape, and its outer edge. The part has a shape having a curved surface.

  In the present invention, an antenna is manufactured using a dielectric or magnetic material having a high dielectric constant, whereby a small, high-communication, and inexpensive wireless chip can be provided.

  In addition, the present invention can provide a highly safe wireless chip in which the outer shape of the dielectric layer that forms the outer shape of the wireless chip has only a flat surface and a curved surface, thereby eliminating corners and causing no injury or the like even when touched.

  The wireless chip of the present invention is coated with resin, DLC (diamond-like carbon), etc. on the outermost surface, and shaped into a shape having a curved surface, so that even if accidental ingestion occurs, the human body is not adversely affected. A wireless chip with high safety can be provided. Further, by coating the outermost surface of the wireless chip, the physical strength is increased, and a recyclable wireless chip that can be used repeatedly can be provided.

  Furthermore, when attaching a wireless tag to a product, wrap it with paper, plastic, cloth, etc., or incorporate it in a bag, box, mascot, etc. to make the outermost surface a highly safe material and shape and consume it. By making the wireless tag easy to recognize the wireless tag, the wireless chip can be used safely.

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description. It will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments and examples. Note that in describing the structure of the present invention with reference to the drawings, the same portions are denoted by the same reference numerals in different drawings.

(Embodiment 1)
As shown in FIG. 2A, the wireless chip 201 of the present invention performs wireless communication with the reader / writer 202. The wireless chip 201 generally operates by receiving power supply from the reader / writer 202 via electromagnetic waves for communication. Then, the data transmitted from the reader / writer 202 is received, whether the data is correct or not is determined, and if the data is correct, the stored data is returned to the reader / writer 202. Further, in response to an instruction from the reader / writer 202, data is stored and erased.

  1A and 1B show a wireless chip of the present invention having the above structure. FIG. 1A is a perspective view illustrating an example of an appearance of a wireless chip, and FIG. 1B is a cross-sectional view of the wireless chip.

  As shown in FIG. 1A as an example, the wireless chip of the present invention has a cylindrical shape, and its outer end has a curved surface. More specifically, chamfering is performed by polishing the cylindrical upper surface and the angle at which the bottom surface and the side surface intersect to form a shape having only a flat surface and a curved surface. In addition, as shown in FIGS. 23 (A) to (C), it is formed in a polygonal column shape such as a quadrangular column, and by chamfering the corner where the top surface, the bottom surface and the side surface intersect, and the corner where the side surface and the side surface intersect. A shape without corners may be formed. Furthermore, spherical shape, oval shape (FIG. 23 (D)), meteorite-like elliptical sphere (FIG. 23 (E)), rugby ball-like elliptical sphere (FIG. 23 (F)) or disk shape (FIG. 23 (G)), You may shape | mold to.

  In addition, as illustrated in FIG. 1B, the wireless chip of the present invention includes an antenna 101 and a layer 102 having a semiconductor element. The antenna 101 is a planar antenna formed by two parallel conductive layers (a first conductive layer 103 and a second conductive layer 104) with a dielectric layer 106 interposed therebetween. The wireless chip transmits and receives electromagnetic waves in order to perform wireless communication with the reader / writer. The layer having a semiconductor element includes a plurality of circuits including transistors, capacitors, diodes, and the like. Then, information processing such as processing and storage of data received from the reader / writer is performed.

  FIG. 2B shows a circuit configuration example of a wireless chip of the present invention having the above function.

  A wireless chip 201 of the present invention includes an antenna 211, a layer 212 having semiconductor elements, a communication circuit portion 213, an arithmetic processing circuit portion 214, a power supply circuit portion 215, a memory portion 216, a demodulation circuit 217, and a modulation circuit 218. The antenna 211 and the layer 212 including a semiconductor element are the same as the layer 101 including the antenna 101 and the semiconductor element described with reference to FIG.

  The antenna receives electromagnetic waves radiated from the reader / writer, and generates an alternating induced voltage. The induced voltage includes data from the reader / writer 202 as well as driving power for the wireless chip 201.

  The frequency band of electromagnetic waves used for wireless communication by the reader / writer and the wireless chip is a long wave band of 30 kHz to 135 kHz, a short wave band of 6 to 60 MHz (typically 13.56 MHz), an ultra short wave band of 400 to 950 MHz, There is a microwave band of 2 to 25 GHz. The antenna can be appropriately designed according to the frequency of the electromagnetic wave used for communication. Further, the antenna can be provided separately from an antenna for communicating with the reader / writer and an antenna for supplying driving power.

  The layer 212 including a semiconductor element includes, for example, an arithmetic processing circuit portion, a memory, a communication circuit portion, a power supply circuit portion, and the like.

  The communication circuit unit includes a demodulation circuit and a modulation circuit. The demodulation circuit demodulates the data from the reader / writer received by the antenna and outputs it to the arithmetic processing circuit unit. The modulation circuit modulates data stored in the memory and transmits the data to the reader / writer. The arithmetic processing circuit unit performs an operation such as determining whether the demodulated data from the reader / writer is correct or reading the data from the memory and outputting the data to the modulation circuit.

  The memory has information specific to the wireless chip. Therefore, a write-once (write-once) nonvolatile memory, a rewritable nonvolatile memory, a volatile memory, or the like is included. The power supply circuit unit generates a constant voltage from the induced voltage generated in the antenna, and supplies the constant voltage to each circuit as a drive voltage. The power supply circuit portion can also include a clock generation circuit for generating a clock signal having a frequency required by another circuit.

  Next, a method for manufacturing a wireless chip of the present invention will be described in the order of a method for forming an antenna, a method for forming a layer having a semiconductor element, and a method for connecting the antenna and a layer having a semiconductor element.

  As shown in FIG. 1B, the antenna 101 included in the wireless chip is larger and thicker than the layer 102 having a semiconductor element, and the shape of the wireless chip of the present invention is almost determined by the antenna 101. The antenna 101 has a structure in which a first conductive layer 103 and a second conductive layer 104 sandwich a dielectric layer 106, and the dielectric layer 106 substantially determines the shape of the antenna 101. Therefore, the shape of the wireless chip of the present invention can be determined by forming the dielectric layer 106 into a shape having a columnar shape as described above and having a curved end at the outer end. it can.

  In addition, the antenna 101 includes a first conductive layer 103 that functions as a radiation electrode and a second conductive layer 104 that functions as a grounding body with a dielectric layer 106 interposed therebetween. Power can be supplied from the first conductive layer 103 to the layer including a semiconductor element by providing a power supply layer 105. Furthermore, it is possible to provide a power supply by providing a power supply point. In this embodiment, an antenna 101 having a structure in which the power feeding layer 105 is provided is described.

  In the antenna 101, a dielectric layer 106 is formed using a dielectric material or a magnetic material, and conductive layers 103 and 104 are formed on the surface of the dielectric layer using a conductive material.

  As an example of a method for forming the dielectric layer 106, a cylindrical dielectric layer 301 is formed as shown in FIG. (The present invention is not limited to a cylindrical shape, and can be formed in a polygonal column shape.) And, as shown in FIG. 3 (B), the corners where the top surface, the bottom surface and the side surface intersect are chamfered by polishing or the like. By performing this process, a dielectric layer 302 having a columnar shape and a curved end surface is produced.

  However, the dielectric layer of the antenna that constitutes the wireless chip of the present invention is not limited to the above-described manufacturing method, and has a cylindrical shape using a mold or the like, and its outer end is formed into a shape having a curved surface. You can also Further, it may be formed in a spherical shape, an oval shape, a meteorite-like elliptical sphere, a rugby ball-like elliptical sphere, or a disc shape.

  The dielectric layer 106 is manufactured using ceramic, organic resin, a mixture thereof, or the like with a high dielectric constant. Typical examples of the ceramic include silica, alumina, zirconia, glass, forsterite and the like. Furthermore, titanium barium neodymium ceramics, titanium barium tin ceramics, lead calcium ceramics, titanium dioxide ceramics, barium titanate ceramics, lead titanate ceramics, strontium titanate ceramics, calcium titanate ceramics, titanium Examples thereof include bismuth acid ceramics and magnesium titanate ceramics. These may be used singly or in combination of two or more. Here, the titanium dioxide-based ceramics refers to those containing the titanium dioxide crystal structure, including those containing only titanium dioxide and those containing a small amount of other additives. The same applies to other ceramics.

  Further, as the organic resin, a thermosetting resin or a thermoplastic resin can be used. Typical examples of thermosetting resins include epoxy resins, phenol resins, unsaturated polyester resins, vinyl ester resins, polyimide resins, polyphenylene ether resins, bismaleimide triazine resins, polyfumarate resins, polybutadiene resins, polyvinyl benzyl ether compound resins, and the like. Can be mentioned. As a representative example of the thermoplastic resin, a resin material such as a liquid crystal polymer, an aromatic polyester resin, a polyphenylene sulfide resin, a polyethylene terephthalate resin, a polybutylene terephthalate resin, a BT resin, a vinylbenzyl resin, or a fluororesin can be used. Furthermore, a plurality of organic resin materials may be mixed and used.

  In the case where the dielectric layer 106 is formed of a mixture of ceramic and organic resin, it is preferable to form by dispersing particulate ceramic particles in the organic resin. At this time, the content of the particulate ceramic with respect to the dielectric layer is preferably 20% by volume or more and 60% by volume or less. The ceramic particle size is preferably 1 to 50 μm. The dielectric constant of the dielectric layer 106 is 2.6 to 150, preferably 2.6 to 40. By using a ferroelectric material having a high dielectric constant, the volume of the antenna can be reduced.

  The dielectric layer 106 constituting the antenna is not limited to the ceramics and organic resins mentioned in the above example, and is selected from materials according to the purpose in consideration of formability, workability, adhesiveness, and the like. Can be used.

  Next, as shown in FIG. 3C, two conductive layers 103 and 104 and a power supply layer are formed on the surface of the dielectric layer 302 having a columnar shape and an outer end portion having a curved surface. 105 is formed.

  The two conductive layers 103 and 104 and the power feeding layer 105 can be formed on the surface of the dielectric layer 302 by a printing method, a plating method, or the like using a conductive material.

  In addition, a conductive layer is formed on the entire surface of the dielectric layer 302 by using an evaporation method, a sputtering method, or the like, and the conductive layer is processed into a desired shape by etching. The layers 103 and 104 and the power feeding layer 105 can also be formed.

  As an example of a conductive substance that is a material of the two conductive layers 103 and 104 and the power supply layer 105, a metal such as gold, silver, copper, palladium, platinum, or aluminum, an alloy, or the like can be used.

  The second conductive layer 104 and the power feeding layer 105 manufactured as described above are electrically connected to the layer 102 having a semiconductor element. Specifically, the second conductive layer 104 is connected to a portion that provides the ground potential of the layer including the semiconductor element, and the power feeding layer 105 is connected to the power supply circuit portion and the communication circuit portion described with reference to FIG. Connected. Therefore, it is preferable that the antenna be shaped to be easily connected to the layer 102 having a semiconductor element.

    The size of the antenna is preferably within a range of several mm × several mm to several tens mm × several tens mm. Typically, it is about 7 mm × 7 mm to 12 mm × 12 mm. The thickness of the antenna is about 1 mm to 15 mm, typically 1.5 mm to 5 mm. The size of this antenna determines the size of the wireless chip.

  Next, a method for manufacturing a layer having a semiconductor element is described.

  The layer including a semiconductor element included in the wireless chip of the present invention includes a plurality of circuits including a semiconductor element and a memory including a semiconductor element and a memory element. Therefore, in this embodiment, a method for manufacturing a semiconductor element and a memory element will be described.

  Further, here, a semiconductor element manufactured using a thin film of a semiconductor on an insulating substrate such as glass in order to form a layer having a semiconductor element that is thin and small and can be attached to the antenna manufactured above, and A method for manufacturing an organic memory having a memory element using an organic compound will be described.

  An organic memory refers to a memory including a memory element having a structure in which a layer having an organic compound or a mixed layer of an organic compound and an inorganic compound is interposed between a pair of conductive layers. A known technique may be used for the decoder constituting the memory. In addition, a memory cell included in the memory can be formed using only the memory element, or can be formed using a transistor and the memory element. In this specification, the layer having the organic compound or the mixed layer of the organic compound and the inorganic compound is collectively referred to as an organic compound layer.

  The organic compound layer included in the memory element is manufactured using a substance whose crystal state, conductivity, and the like change by applying light, heat, or electrical action. The memory element having the above configuration stores a binary state depending on a state in which the organic compound layer is changed by applying the light, heat, and electric action, and a state in which the organic compound layer is not changed without applying the action. This memory element has a simple structure and can be easily made thin.

  First, the separation layer 402 is formed over the insulating substrate 401 (see FIG. 4A). As the insulating substrate 401, a substrate such as glass, quartz, silicon, or metal can be used. The peeling layer 402 is formed by partially or partially forming an element or a compound such as metal or silicon over the entire surface of the substrate. Note that in this embodiment mode, the separation layer 402 is formed in order to separate the layer including the semiconductor element formed over the insulating substrate 401 and attach it to the antenna. However, in the case where the layer including a semiconductor element manufactured over the insulating substrate 401 is attached to the antenna together with the insulating substrate 401, the separation layer 402 is not necessarily formed. Next, an insulating layer 403 is formed so as to cover the separation layer 402. The insulating layer 403 is formed using silicon oxide, silicon nitride, or the like. Next, a semiconductor layer 404 is formed over the insulating layer 403, and the semiconductor layer is crystallized by laser crystallization, thermal crystallization using a metal catalyst, or the like, and then processed into a desired shape. Next, a gate insulating layer 405 is formed so as to cover the semiconductor layer. The gate insulating layer 405 is formed using silicon oxide, silicon nitride, or the like. The gate insulating layer 405 can be formed with a high-density plasma CVD apparatus so that an insulating layer with a small thickness and high insulating properties can be formed.

  Next, the gate electrode layer 406 is formed. The gate electrode layer 406 is formed into a desired shape by forming a conductive layer using a conductive element or compound. In the case where processing is performed by a photolithography method, when the resist mask is etched with plasma or the like, the gate electrode width can be shortened and the performance of the transistor can be improved. FIG. 4A shows the case where the gate electrode layer is formed in a stacked structure. Next, an impurity element is added to the semiconductor layer 404 to form an n-type impurity region 407 and a p-type impurity region 408. The impurity region is formed by forming a resist mask by photolithography and adding an impurity element such as phosphorus, arsenic, or boron. Next, an insulating layer is formed using a nitrogen compound or the like, and the insulating layer is subjected to anisotropic etching in the vertical direction, whereby an insulating layer 409 (side wall) in contact with the side surface of the gate electrode is formed (FIG. 4B). reference). Next, an impurity is added to the semiconductor layer having the n-type impurity region, and the first n-type impurity region 410 immediately below the sidewall 409 and the second impurity concentration higher than that of the first n-type impurity region 410 are added. An n-type impurity region 411 is formed. Through the above steps, an n-type transistor 412 and a p-type transistor 413 are formed.

  Next, an insulating layer 414 is formed so as to cover the transistors 412 and 413 (see FIG. 4C). The insulating layer 414 is formed using an insulating inorganic compound, an organic compound, or the like. FIG. 4C illustrates the insulating layer 414 formed with a stacked structure. Next, a contact hole exposing the second n-type impurity region 411 and the p-type impurity region 408 is formed, a conductive layer 415 is formed so as to fill the contact hole, and the conductive layer 415 is formed as desired. To the shape of The conductive layer 415 is formed using a conductive metal element, compound, or the like. Next, an insulating layer 416 is formed so as to cover the conductive layer 415. The insulating layer 416 is formed using an insulating inorganic compound, an organic compound, or the like.

  Next, the formation of the memory element is shown in FIG. First, a contact hole that exposes the conductive layer 415 is formed, and a first conductive layer 417 is formed so as to fill the contact hole. The first conductive layer 417 is formed of a conductive metal element, compound, or the like, and serves as a first conductive layer that forms a memory element. Next, an insulating layer 418 is formed so as to cover the first conductive layer 417. The insulating layer 418 is formed using an inorganic compound, an organic compound, or the like having high insulating properties in order to electrically isolate adjacent memory elements. Next, a contact hole that exposes the first conductive layer 417 is formed. Then, a wiring 419 for connecting an antenna is formed over the first conductive layer 417. Next, the organic compound layer 420 is formed so as to be in contact with the first conductive layer 417, and then the conductive layer 421 is formed. The organic compound layer 420 is formed using an organic compound whose electrical characteristics change by applying an electrical action. The conductive layer 421 is formed using a conductive metal element, a compound, or the like, and serves as a second conductive layer included in the memory element. Next, the protective layer 422 is formed. The protective layer 422 is formed using an insulating compound, resin, or the like.

  FIG. 5B illustrates a memory element having a structure different from the above. In the memory element, the conductive layer 415 formed for connecting the transistor and the memory element in FIG. 5A is used as the first conductive layer of the memory element. First, a contact hole that exposes the second n-type impurity region 411 and the p-type impurity region 408 is formed, a conductive layer 415 is formed so as to fill the contact hole, and the conductive layer 415 is formed in a desired shape. Process into shape. The conductive layer 415 serves as a first conductive layer included in the memory element. Next, the organic compound layer 420 is formed so as to be in contact with the conductive layer 415, and then the conductive layer 421 is formed. The organic compound layer 420 is formed using an organic compound whose electrical characteristics change by applying an electrical action. The conductive layer 421 is formed using a conductive metal element, a compound, or the like, and serves as a second conductive layer included in the memory element. Next, the protective layer 422 is formed. The protective layer 422 is formed using an insulating compound, resin, or the like. By forming the memory element in the contact hole in this manner, the semiconductor device can be reduced in size and thickness. In addition, since the first conductive layer 417 and the insulating layer 418 are not necessary, a manufacturing process can be reduced and a memory with reduced cost can be provided.

  Each layer forming the insulating layer, the conductive layer, and the element can be formed using a single-layer structure of a single material or a stacked structure of a plurality of materials.

Any semiconductor such as an amorphous semiconductor, a microcrystalline semiconductor, a microcrystalline semiconductor, a polycrystalline semiconductor, an organic semiconductor, or the like may be used for a semiconductor layer included in the semiconductor element manufactured through the above steps. In order to obtain a semiconductor element having good characteristics, a crystalline semiconductor layer (low-temperature polysilicon layer) crystallized at a temperature of 200 to 600 degrees (preferably 350 to 500 degrees), or a temperature of 600 degrees or more. A crystalline semiconductor layer (high-temperature polysilicon layer) crystallized in (1) can be used. In order to obtain a semiconductor element with better characteristics, a semiconductor layer crystallized using a metal element as a catalyst or a semiconductor layer crystallized by a laser irradiation method may be used. Alternatively, a semiconductor layer formed by a plasma CVD method using a mixed gas of SiH ₄ and F _2, a mixed gas of SiH ₄ and H ₂ , or the like, or a semiconductor layer that is irradiated with laser light may be used. The semiconductor layer of the semiconductor element in the circuit is preferably formed so as to have a crystal grain boundary extending in parallel with the carrier flow direction (channel length direction). Such an active layer can be formed using a continuous wave laser (which can be abbreviated as CWLC) or a pulse laser operating at 10 MHz or higher, preferably 60 to 100 MHz. The thickness of the semiconductor layer is 20 nm to 200 nm, preferably 50 nm to 150 nm. The semiconductor layer (particularly the channel formation region) has a concentration of 1 × 10 ¹⁹ atoms / cm ³ to 1 × 10 ²² atoms / cm ³ , preferably 1 × 10 ¹⁹ atoms / cm ^{3 to} 5 × 10 ²⁰ atoms. By adding hydrogen or a halogen element at a concentration of / cm ³ , it is possible to obtain an active layer with fewer defects and less cracking.

The transistor manufactured as described above has an S value (subthreshold value) of 0.35 V / dec or less, preferably 0.09 to 0.25 V / dec. Further, the mobility may have a characteristic of 10 cm ² / Vs or higher. Further, the transistor is a ring oscillator that operates at a power supply voltage of 3 to 5 V, and desirably has a characteristic of 1 MHz or more, preferably 10 MHz or more. In addition, the transistor described in this embodiment has a structure in which a semiconductor layer, a gate insulating layer, and a gate electrode layer are sequentially stacked over a substrate. However, the present invention is not limited to this example. For example, the gate electrode layer, It is also possible to adopt a structure in which an insulating film and a semiconductor layer are sequentially stacked. In this embodiment mode, an n-type transistor includes a first n-type impurity region and a second n-type impurity region. However, the present invention is not limited to this example, and the impurity concentration in the impurity region is uniform. May be.

  As the material of the organic compound layer, a material whose property or state is changed by an electric action, an optical action, a thermal action, or the like is used. For example, a material that changes the property or state of the organic compound by applying a voltage and short-circuits the first conductive layer and the second conductive layer included in the memory element is used. Therefore, the thickness of the organic compound layer is 5 nm to 100 nm, preferably 10 nm to 60 nm. Such an organic compound layer can use an inorganic material or an organic compound material described below, and can be formed by an evaporation method, a spin coating method, a droplet discharge method, or the like.

As a material for the organic compound layer, for example, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD) or 4,4′-bis [N— (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD), 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) and 4,4′-bis (N- (4- (N , N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond), polyvinylcarbazole (abbreviation: PVK) ) Or phthalo Cyanine _{(abbreviation:} H 2 Pc), copper phthalocyanine (abbreviation: CuPc), or vanadyl phthalocyanine (abbreviation: VOPc), and can be used phthalocyanine compounds such as. These materials are substances having a high hole transporting property.

As other materials for the organic compound layer, for example, tris (8-quinolinolato) aluminum (abbreviation: Alq3), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq3), bis (10-hydroxybenzo [ h] -quinolinato) beryllium (abbreviation: BeBq2), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc., a material comprising a metal complex having a quinoline skeleton or benzoquinoline skeleton And bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) 2), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) 2) Materials such as metal complexes with oxazole and thiazole ligands such as Can. These materials are substances having a high electron transporting property.

  In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, Compounds such as 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can be used.

The organic compound layer may have a single layer structure or a laminated structure. In the case of a laminated structure, a laminated structure can be selected from the above materials. Further, the organic compound material and the light emitting material may be stacked. As a light-emitting material, 4-dicyanomethylene-2-methyl-6- [2- (1,1,7,7-tetramethyljulolidyl-9-yl) ethenyl] -4H-pyran (abbreviation: DCJT), 4 -Dicyanomethylene-2-t-butyl-6- [2- (1,1,7,7-tetramethyljulolidyl-9-yl) ethenyl] -4H-pyran, perifuranthene, 2,5-dicyano-1 , 4-bis [(10-methoxy-1,1,7,7-tetramethyljulolidyl-9-yl) ethenyl] benzene, N, N′-dimethylquinacridone (abbreviation: DMQd), coumarin 6, coumarin 545T , Tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), 9,9′-bianthryl, 9,10-diphenylanthracene (abbreviation: DPA) and 9,10-bis (2-naphthyl) a Intracene (abbreviation: DNA), 2,5,8,11-tetra-t-butylperylene (abbreviation: TBP), and the like.

Alternatively, a layer in which the light emitting material is dispersed may be used. In the layer in which the light emitting material is dispersed, the base material includes an anthracene derivative such as 9,10-di (2-naphthyl) -2-tert-butylanthracene (abbreviation: t-BuDNA), 4,4′- Carbazole derivatives such as di (N-carbazolyl) biphenyl (abbreviation: CBP), bis [2- (2′-hydroxyphenyl) pyridinato] zinc (abbreviation: Znpp2), bis [2- (2′-hydroxyphenyl) benzoxa Zolato] metal complexes such as zinc (abbreviation: ZnBOX) can be used. In addition, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), 9,10-bis (2-naphthyl) anthracene (abbreviation: DNA), bis (2-methyl-8-quinolinolato) -4-phenylphenolato- Aluminum (abbreviation: BAlq) or the like can be used.

  Such an organic compound material has a glass transition temperature (Tg) of 50 ° C. to 300 ° C., preferably 80 ° C. to 120 ° C., in order to change its properties by thermal action or the like.

  Alternatively, a material in which a metal oxide is mixed in an organic compound material or a light emitting material may be used. Note that the material in which the metal oxide is mixed includes a state in which the organic compound material or the light-emitting material and the metal oxide are mixed or stacked. Specifically, it refers to a state formed by a co-evaporation method using a plurality of evaporation sources. Such a material can be called an organic-inorganic composite material.

  For example, when a metal oxide is mixed with a substance having a high hole transporting property, the metal oxide includes vanadium oxide, molybdenum oxide, niobium oxide, rhenium oxide, tungsten oxide, ruthenium oxide, titanium oxide. It is preferable to use an oxide, chromium oxide, zirconium oxide, hafnium oxide, or tantalum oxide.

  In the case where a substance having a high electron transporting property and a metal oxide are mixed, it is preferable to use lithium oxide, calcium oxide, sodium oxide, potassium oxide, or magnesium oxide as the metal oxide.

  For the organic compound layer, a material whose properties are changed by an electric action, an optical action, or a thermal action may be used. For example, a compound that generates an acid by absorbing light (photo acid generator) is used. Doped conjugated polymers can also be used. As the conjugated polymer, polyacetylenes, polyphenylene vinylenes, polythiophenes, polyanilines, polyphenylene ethynylenes, and the like can be used. As the photoacid generator, arylsulfonium salts, aryliodonium salts, o-nitrobenzyl tosylate, arylsulfonic acid p-nitrobenzyl esters, sulfonylacetophenones, Fe-allene complex PF6 salts and the like can be used.

  In addition, the first conductive layer and the second conductive layer included in the memory element can be formed from a conductive material. For example, it can be formed of a film made of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), or silicon (Si), or an alloy film using these elements. Alternatively, a light-transmitting material such as indium tin oxide (ITO), indium tin oxide containing silicon oxide, or indium oxide containing zinc oxide can be used. Further, as the material for the protective layer 422, silicon oxide or silicon nitride can be used as the inorganic material. As the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or polysilazane can be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Polysilazane is formed using a polymer material having a bond of silicon (Si) and nitrogen (N) as a starting material. By forming a protective layer using these materials, planarity can be improved and intrusion of impurity elements can be prevented.

  Further, the semiconductor element and the memory element may be provided over a plurality of layers. In the case of manufacturing with a multilayer structure, a low dielectric constant material is preferably used as a material for the interlayer insulating film in order to reduce parasitic capacitance between layers. Examples thereof include resin materials such as epoxy resins and acrylic resins, and compound materials made by polymerization of siloxane polymers. If parasitic capacitance is reduced in a multi-layer structure, it is possible to reduce the area, increase the operation speed, and reduce power consumption. In addition, reliability can be improved by providing a protective layer for preventing alkali metal contamination. The protective layer may be provided with an inorganic material such as aluminum nitride or a silicon nitride film so as to wrap the semiconductor element in the circuit or to wrap the entire circuit.

  Next, a method of peeling the semiconductor element and the memory element configured as described above from the insulating substrate 401 and attaching them to the antenna will be described.

  First, an opening 427 is formed so that the peeling layer 402 is exposed, an etchant is introduced into the opening 427, and the peeling layer 402 is partially removed (see FIG. 6A). Next, a first flexible substrate 429 (eg, a plastic film) is bonded from the upper surface direction of the insulating substrate 401. Then, the layer 428 including a semiconductor element and a memory element is separated from the insulating substrate 401 with the separation layer 402 as a boundary. In this manner, the layer 428 including a semiconductor element and a memory element can be transferred to the first flexible substrate 429 side. At this time, the material of the separation layer may remain in the layer including the semiconductor element and the memory element. Next, the second flexible substrate 430 (eg, a thin plastic film) is bonded to the side where the layer 428 including the semiconductor element and the memory element is in contact with the insulating substrate 401 (see FIG. 6B). . Then, the wiring 419 for connecting the antenna is exposed by removing the first flexible substrate 429 (see FIG. 6C).

  At this time, the thickness of the layer 428 including a semiconductor element and a memory element is 5 μm or less, preferably 1 μm to 3 μm. In addition, when a layer having a semiconductor element is attached to an antenna having a curved surface, the carrier flow direction (channel length direction) of the semiconductor element is parallel to the tangential line that makes the angle formed by the curved surface at the attachment position minimum. Then, the influence on the semiconductor element can be reduced.

  A layer having a semiconductor element formed over the second flexible substrate 430 thus manufactured is the layer 102 having a semiconductor element shown in FIG.

  Next, as illustrated in FIG. 3D, the antenna 101 and the layer 102 having a semiconductor element which are manufactured through the above steps are attached to be electrically connected. It is preferable to use an anisotropic conductive adhesive for bonding. Specifically, the second conductive layer 104 of the antenna is connected to a portion that provides the ground potential of the layer including the semiconductor element, and the power supply layer 105 includes the power supply circuit portion described with reference to FIG. Adhesive so as to be connected to a communication circuit unit or the like.

  The present invention can provide a wireless chip that is small in size, has high communication properties, and is inexpensive. Furthermore, the wireless chip of the present invention has a cylindrical shape, and its outer end has a curved surface. More specifically, chamfering is performed by polishing the cylindrical upper surface and the angle at which the bottom surface and the side surface intersect to form a shape having only a flat surface and a curved surface. In addition, it may be formed in a polygonal column shape such as a quadrangular column, and a cornerless shape may be formed by chamfering a corner where the top surface, the bottom surface and the side surface intersect, or a corner where the side surface and the side surface intersect. Furthermore, a highly safe wireless chip is provided which is formed into a spherical shape, an oval shape, a meteorite-like ellipsoidal sphere, a rugby ball-like ellipsoidal sphere or a disc shape, etc., so that corners are eliminated and no injuries or the like occur even when contacted. be able to.

(Embodiment 2)
In this embodiment mode, different manufacturing methods are described for the wireless chip of the present invention having the functions described in Embodiment Mode 1.

  As shown in FIG. 7A, the wireless chip of this embodiment includes a layer 701 including a semiconductor element and an antenna 703. The layer having a semiconductor element has a semiconductor element such as a field effect transistor on a semiconductor substrate such as silicon. The antenna may be the same as the antenna described in Embodiment 1.

  In the wireless chip in this embodiment, the antenna 703 and the layer 701 including a semiconductor element are connected to each other by conductive layers 702a and 702b. Specifically, the connection terminal 704a formed on the surface of the layer 701 having a semiconductor element and the feeder layer 713 of the antenna are connected by the conductive layer 702a. Then, the connection terminal 704b formed on the surface of the layer 701 including the semiconductor element and the conductive layer 712 functioning as an antenna grounding body are connected by the conductive layer 702b. Further, a connection portion between the antenna 703 and the layer 701 having a semiconductor element may be filled with an underfill 704.

  The antenna 703 forms a dielectric layer 710, two conductive layers (a first conductive layer 711 and a second conductive layer 712), and a power feeding layer 713. The dielectric layer 710 has a columnar shape as in the first embodiment, and its outer end has a curved surface. More specifically, chamfering is performed by polishing the cylindrical upper surface and the angle at which the bottom surface and the side surface intersect to form a shape having only a flat surface and a curved surface. In addition, it may be formed in a polygonal column shape such as a quadrangular column, and a cornerless shape may be formed by chamfering a corner where the top surface, the bottom surface and the side surface intersect, or a corner where the side surface and the side surface intersect. Furthermore, it may be formed into a spherical shape, an oval shape, a meteorite-like elliptical sphere, a rugby ball-like elliptical sphere, or a disc shape.

  A first conductive layer 711 formed on one surface of the dielectric layer and a second conductive layer 711 facing the first conductive layer 711 through the dielectric layer and formed on the other surface of the dielectric layer A conductive layer 712 and a power feeding layer 713 are included. The first conductive layer 711 functions as a radiation electrode. Further, the second conductive layer 712 functions as a grounding body. The power feeding layer 713 is provided so as not to contact the first conductive layer 711 and the second conductive layer 712. In addition, power is supplied from the antenna to the antenna or the layer having the semiconductor element to the antenna through the power feeding layer 713. Note that power may be supplied using a power supply point instead of the power supply layer.

Here, the structure of the antenna 703 will be described. The dielectric layer 710 of the antenna can be formed of ceramic, organic resin, a mixture of ceramic and organic resin, or the like. Representative examples of ceramics include alumina, glass, forsterite and the like. Furthermore, a plurality of ceramics may be mixed and used. In order to obtain a high dielectric constant, the dielectric layer 710 is preferably formed of a ferroelectric material. Representative examples of the ferroelectric material include barium titanate (BaTiO ₃ ), lead titanate (PbTiO ₃ ), strontium titanate (SrTiO ₃ ), lead zirconate (PbZrO ₃ ), lithium diobate (LiNbO ₃ ). And lead zirconate titanate (PZT). Further, a plurality of ferroelectric materials may be mixed and used.

  As the organic resin, a thermosetting resin or a thermoplastic resin is used as appropriate. As a typical example of the organic resin, a resin material such as an epoxy resin, a phenol resin, a polybutadiene resin, a BT resin, vinyl benzyl, polyfumarate, and a fluorine resin can be used. Furthermore, a plurality of organic resin materials may be mixed and used.

  In the case where the dielectric layer 710 is formed of a mixture of a ceramic and an organic resin, it is preferable to form by dispersing particulate ceramic particles in the organic resin. At this time, the content of the particulate ceramic with respect to the dielectric layer 710 is preferably 20% by volume or more and 60% by volume or less. The ceramic particle size is preferably 1 to 50 μm.

  The dielectric constant of the dielectric layer 710 is 2.6 to 150, preferably 2.6 to 40. By using a ferroelectric material having a high non-dielectric constant, the volume of the antenna can be reduced.

  For the first conductive layer 711, the second conductive layer 712, and the power feeding layer 713 of the antenna, a metal selected from gold, silver, copper, palladium, platinum, aluminum, an alloy, or the like can be used. The first conductive layer 711, the second conductive layer 712, and the power feeding layer 713 of the antenna can be formed by a printing method or a plating method. In addition, after forming a conductive film on the dielectric layer by vapor deposition or sputtering, a part of the conductive layer can be etched to form each conductive layer.

  Next, the layer 701 including a semiconductor element is described with reference to FIGS.

  FIG. 8 is a cross-sectional view of a part of a layer 701 having a semiconductor element. Element isolation regions 801a to 801e are formed on a substrate 800, and a semiconductor element 802 such as a field effect transistor is provided between the element isolation regions 801a to 801e. It is formed.

  The semiconductor element 802 is formed over a gate insulating film 803 formed over a single crystal semiconductor substrate, a gate electrode 804 formed over the gate insulating film, source and drain regions 805a and 805b in the single crystal semiconductor substrate, and over the gate electrode. An interlayer insulating layer 811, and source and drain wirings 809a and 809b connected to the source and drain regions 805a and 805b. Note that sidewalls 807a and 807b formed on the sidewalls of the gate electrode 804 and the gate insulating film 803, or low-concentration impurity regions 806a and 806b covered with the sidewalls 807a and 807b in the single crystal semiconductor substrate may be provided.

  The substrate 800 is a single crystal semiconductor substrate or a compound semiconductor substrate, and is typically an n-type or p-type single crystal silicon substrate, a GaAs substrate, an InP substrate, a GaN substrate, a SiC substrate, a sapphire substrate, a ZnSe substrate, or the like. Is mentioned. An SOI substrate (Silicon On Insulator) can also be used. In this embodiment, an n-type single crystal silicon substrate is used as the substrate 800.

  The element isolation regions 801a to 801e can be formed by appropriately using a known selective oxidation method (LOCOS (Local Oxidation of Silicon) method) or a trench isolation method. Here, as the element isolation regions 801a to 801e, silicon oxide layers are formed by a trench isolation method.

  The gate insulating film 803 is formed by thermally oxidizing a single crystal semiconductor substrate. The gate electrode 804 can have a stacked structure in which a polycrystalline silicon layer with a thickness of 100 to 300 nm or a silicide layer such as a tungsten silicide layer, a molybdenum silicide layer, or a cobalt silicide layer is provided over the polycrystalline silicon layer. Further, a tungsten nitride layer and a tungsten layer may be stacked over the polycrystalline silicon layer.

  As the source and drain regions 805a and 805b, an n + region in which phosphorus is added to the p well region and a p + region in which boron is added to the n well region can be used. As the low-concentration impurity regions 806a and 806b, an n− region in which phosphorus is added to the p well region or a p− region in which boron is added to the well region can be used. Here, since an n-type single crystal silicon substrate is used, boron is added to the substrate to form a source region and a drain region made of a p + region, and a low concentration impurity region made of a p− region. Note that the source and drain regions 805a and 805b may include silicide such as manganese silicide, tungsten silicide, titanium silicide, cobalt silicide, or nickel silicide. By having silicide on the surface of the source region and the drain region, it is possible to reduce the connection resistance between the source wiring and the drain wiring and the source region and the drain region.

  The sidewalls 807a and 807b are formed by forming an insulating layer made of silicon oxide on a substrate by a CVD method and anisotropically etching the insulating layer by a RIE (Reactive Ion Etching) method. it can.

  The interlayer insulating layer 808 is formed using an inorganic insulating material such as silicon oxide or silicon oxynitride, or an organic insulating material such as an acrylic resin or a polyimide resin. When a coating method such as spin coating or roll coater is used, silicon oxide in which an insulating layer is formed by heat treatment after coating an insulating film material dissolved in an organic solvent can also be used. Here, the interlayer insulating layer 808 is formed using silicon oxide.

  The source and drain wirings 809a and 809b are formed of a low resistance material such as aluminum (Al) such as a laminated structure of titanium (Ti) and aluminum (Al), a laminated structure of molybdenum (Mo) and aluminum (Al), and the like. It is preferably formed by a combination with a barrier metal using a refractory metal material such as titanium (Ti) or molybdenum (Mo).

  Note that the layer 701 including a semiconductor element includes a semiconductor element such as a resistor or a capacitor in addition to the field effect transistor.

  Further, an interlayer insulating layer 811 is formed over the interlayer insulating layer 808 and the source and drain wirings 809a and 809b. The interlayer insulating layer 811 is formed in the same manner as the interlayer insulating layer 808. Further, connection terminals 812 and 813 connected to the semiconductor element 802 are provided over the interlayer insulating layer 808.

  Further, an insulating layer 814 that covers part of the connection terminals 812 and 813 and the interlayer insulating layer 811 may be formed. The interlayer insulating layer 811 functions as a protective layer, and is preferably formed using silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, DLC (diamond-like carbon), or the like.

  The conductive layers 702a and 702b that connect the antenna 703 and the layer 701 having a semiconductor element are formed using a bump, a conductive paste, an anisotropic conductive adhesive, an anisotropic conductive film, or the like. Further, a pump and a conductive paste may be used. Furthermore, bumps and anisotropic conductive adhesives, bumps and anisotropic conductive films may be used. In these cases, the conductive layer and the connection terminal are connected by the bump and the conductive particles.

  An anisotropic conductive film and an anisotropic conductive adhesive are adhesive organic resins in which conductive particles having a particle size of several nm to several μm are dispersed, and examples of the organic resins include epoxy resins and phenol resins. . The conductive particles are formed of one element or a plurality of elements selected from gold, silver, copper, palladium, or platinum. Moreover, the particle | grains which have the multilayer structure of these elements may be sufficient. Furthermore, even if it uses the electroconductive particle by which the surface of the particle | grains formed with resin was coated with the thin film formed with one metal selected from gold | metal | money, silver, copper, palladium, or platinum, or several metals. Good.

  The underfill 704 functions to reinforce the connection between the layer 701 having a semiconductor element and the antenna 703 and to prevent moisture from entering, and is formed using an epoxy resin, an acrylic resin, a polyimide resin, or the like. The

  In addition, the wireless chip of the present invention can have a structure as shown in FIG.

  In the antenna included in the wireless chip illustrated in FIG. 7B, after the dielectric layer 710 is formed, a hole for inserting the layer 701 including a semiconductor element is formed. Next, a first conductive layer 711 is formed on the surface of the dielectric layer 710. Then, a layer 701 including a semiconductor element is inserted, and a second conductive layer 712 and a power feeding layer 713 are formed.

  Here, the connection terminal 704a formed on the surface of the layer 701 having a semiconductor element and the feeder layer 713 of the antenna are connected by the conductive layer 702a. Then, the connection terminal 704b formed on the surface of the layer 701 including the semiconductor element and the conductive layer 712 functioning as an antenna grounding body are connected by the conductive layer 702b. Further, a connection portion between the antenna 703 and the layer 701 having a semiconductor element may be filled with an underfill 704.

  The wireless chip of the present invention is not limited to the above manufacturing method. However, as described above, by forming the dielectric layer 710 included in the antenna so that the layer 701 including the semiconductor element is placed, the outer shape is not uneven, and the surface has only a flat surface and a curved surface. Can be improved.

  The present invention can provide a wireless chip that is small, has high communication performance, and is inexpensive. Furthermore, the wireless chip of the present invention has a cylindrical shape, and its outer end has a curved surface. More specifically, chamfering is performed by polishing the cylindrical upper surface and the angle at which the bottom surface and the side surface intersect to form a shape having only a flat surface and a curved surface. In addition, it may be formed in a polygonal column shape such as a quadrangular column, and a cornerless shape may be formed by chamfering a corner where the top surface, the bottom surface and the side surface intersect, or a corner where the side surface and the side surface intersect. Furthermore, a highly safe wireless chip is provided which is formed into a spherical shape, an oval shape, a meteorite-like ellipsoidal sphere, a rugby ball-like ellipsoidal sphere or a disc shape, etc., so that corners are eliminated and no injuries or the like occur even when contacted. be able to.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 3)
In this embodiment mode, a process for manufacturing a semiconductor element included in the layer including the semiconductor element described in Embodiment Modes 1 and 2 using a different material will be described. In this embodiment mode, an example of forming a layer having a semiconductor element by forming a semiconductor element having an organic semiconductor layer over an insulating substrate will be described.

  For example, a flexible substrate has a lower heat resistant temperature than an inflexible substrate such as a glass substrate. For this reason, when a semiconductor element is formed over a flexible substrate, it is preferably formed using an organic semiconductor. In the layer having a semiconductor element formed using an organic semiconductor, the semiconductor element is formed over a flexible substrate, and an insulating layer covering the semiconductor element is formed. In addition, a connection terminal connected to the wiring of the semiconductor element is formed on the surface of the layer having the semiconductor element.

  Here, a structure of a semiconductor element using an organic semiconductor will be described with reference to FIG. FIG. 9A illustrates an example of applying a staggered transistor. A semiconductor element 900 is provided over a flexible substrate 901. The semiconductor element 900 includes a gate electrode 902, an insulating layer 903 that functions as a gate insulating film, a semiconductor layer 904 that overlaps with the insulating layer that functions as a gate electrode and a gate insulating film, and wirings 905 and 906 that are connected to the semiconductor layer 904. Is formed. Note that the semiconductor layer is in contact with the insulating layer 903 functioning as a gate insulating film and the wirings 905 and 906.

  The gate electrode 902 is formed by, for example, using a method of forming a pattern with a predetermined shape by discharging a droplet of a composition containing fine particles from a minute hole (hereinafter referred to as a droplet discharge method in this specification). The gate electrode 902 can be formed by baking. Alternatively, the gate electrode 902 can be formed by printing a paste containing fine particles over a flexible substrate by a printing method, drying, and baking. As typical examples of the fine particles, fine particles mainly containing any of gold, copper, an alloy of gold and silver, an alloy of gold and copper, an alloy of silver and copper, and an alloy of gold, silver, and copper may be used. Further, fine particles mainly containing a conductive oxide such as indium tin oxide (ITO) may be used.

  The insulating layer 903 functioning as a gate insulating film can be formed using a material and a method similar to those of the gate insulating layer 405 described with reference to FIGS. However, when an insulating layer is formed by heat treatment after applying an insulating film material dissolved in an organic solvent by a spin coating method or a roll coater method, the heat treatment temperature is lower than the heat resistance temperature of the flexible substrate. Do at temperature.

  Examples of the semiconductor layer 904 include polycyclic aromatic compounds, conjugated double bond compounds, phthalocyanines, and charge transfer complexes. For example, anthracene, tetracene, pentacene, 6T (hexathiophene), TCNQ (tetracyanoquinodimethane), PTCDA (perylene carboxylic acid anhydride), NTCDA (naphthalene carboxylic acid anhydride) and the like can be used. Specific organic polymer compound materials include π-conjugated polymers, carbon nanotubes, polyvinyl pyridine, phthalocyanine metal complexes, and the like. In particular, when a polyacetylene, polyaniline, polypyrrole, polythienylene, polythiophene derivative, poly (3 alkylthiophene), polyparaphenylene derivative or polyparaphenylene vinylene derivative is used, which is a π-conjugated polymer whose skeleton is composed of conjugated double bonds preferable.

  As a method for forming the organic semiconductor film, a method that can form a film with a uniform thickness on the substrate may be used. The film thickness is 1 nm to 1000 nm, preferably 10 nm to 100 nm. As a specific method, an evaporation method, a spin coating method, a bar coating method, a solution casting method, a dip method, a screen printing method, a roll coater method, or a droplet discharge method can be used.

  The wirings 905 and 906 can be formed using a material and a method similar to those of the gate electrode 902.

  FIG. 9B illustrates an example in which a coplanar transistor is used. A semiconductor element 900 is provided over a flexible substrate 901. In the semiconductor element 900, a gate electrode 902, an insulating layer 903 that functions as a gate insulating film, wirings 905 and 906, and a semiconductor layer 904 that overlaps with the insulating layer that functions as a gate electrode and a gate insulating layer are formed. The wirings 905 and 906 are in contact with an insulating layer and a semiconductor layer that function as gate insulating layers.

  As described above, by forming a semiconductor element using an organic semiconductor layer over a flexible substrate, a layer having a very thin semiconductor element can be formed. Then, the antenna described in any of Embodiments 1 and 2 is manufactured, and as illustrated in FIG. 2D, the antenna and the layer including the semiconductor element are electrically connected (for example, anisotropic) By attaching (using a conductive conductive film or the like), it is possible to form a wireless chip with no irregularities in the outer shape.

  The present invention can provide a wireless chip that is small, has high communication performance, and is inexpensive. Furthermore, the wireless chip of the present invention has a cylindrical shape, and its outer end has a curved surface. More specifically, chamfering is performed by polishing the cylindrical upper surface and the angle at which the bottom surface and the side surface intersect to form a shape having only a flat surface and a curved surface. In addition, it may be formed in a polygonal column shape such as a quadrangular column, and a cornerless shape may be formed by chamfering a corner where the top surface, the bottom surface and the side surface intersect, or a corner where the side surface and the side surface intersect. Furthermore, providing a highly safe wireless chip that eliminates corners by causing a spherical shape, oval shape, meteorite-like elliptical sphere, rugby ball-like elliptical sphere, or disk shape, etc., and does not cause injury even if touched. Can do.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 4)
In this embodiment mode, a wireless chip coated with a resin or the like will be described with reference to FIGS. 10A and 10B unlike Embodiment Modes 1 to 3 described above.

  For example, if a wireless chip having a flat surface and / or a curved surface cannot be manufactured in consideration of workability and manufacturing cost of the dielectric layer, the wireless chip manufactured in an unspecified shape is protected with a resin or the like. Can be coated with layers. FIG. 10A illustrates a wireless chip 1001 coated with a protective layer 1002 such as a resin.

  By coating the wireless chip 1001 with a protective layer 1002 such as a resin, an oval shape, a spherical shape, a meteorite-like oval sphere, a rugby ball-like oval sphere, or a disc shape can be formed. Alternatively, it is possible to form a columnar shape (or a polygonal column shape) using a method such as forming with a mold or chamfering by polishing, and having a curved end at the outer end.

  Since the wireless chip of the present invention communicates with a reader / writer wirelessly via electromagnetic waves, the wireless tag can be coated with a protective layer made of a substance that does not inhibit communication.

  10B and 10C are cross-sectional views of wireless chips coated with a protective layer such as a resin. As shown in FIG. 10B, the wireless chip 1001 can be directly coated with a protective layer 1003 such as a resin. Further, as shown in FIG. 10C, a protective layer 1004 can be formed in a capsule shape to incorporate a wireless chip 1001, and a filler 1005 can be placed between the protective layer 1004 and the wireless chip 1001. .

  Examples of the protective layer for coating the wireless chip include organic resins, inorganic resins, diamond-like carbon (DLC), and the like. In addition, when the protective layer includes silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, carbon nitride, or the like, the layer including the semiconductor element can be protected from an alkali metal that degrades the function of the semiconductor element. .

  The method for forming the outer shape by coating the wireless tag as described above has a thickness because a layer having a semiconductor element is formed using a silicon wafer as shown in Embodiment Mode 2, and the shape of the wireless tag is that of an antenna. It can be used when it is not determined only by the dielectric layer, or when the wireless tag can be manufactured at a lower cost than when the shape of the dielectric layer is formed.

  In addition, as in the present invention, the outermost surface of the wireless chip is coated with resin, DLC (diamond-like carbon), etc., and shaped into a curved surface, which may adversely affect the human body even if accidental ingestion occurs. A highly secure wireless chip can be provided.

  Further, by coating the outermost surface of the wireless chip, it is possible to provide a recyclable wireless chip that has high physical strength and can be used over and over again.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 5)
In this embodiment, a method for using a wireless chip is described with reference to FIGS.

  A wireless chip such as the wireless chip of the present invention that is small and can be manufactured at low cost can be attached to an article and managed for retail sale. As described above, when a large amount of wireless chips are used for retailing, the wireless chips finally reach the consumer. The end consumer is an unspecified number, some of whom have no knowledge of wireless chips and automatic recognition technology, creating the risk of unpredictable accidents such as injury or accidental ingestion It will be. In addition, there are problems related to the disposal method of the used wireless chip and recycling.

  In order to solve these problems, the present invention provides a wireless chip in a box, bag, wrapping paper, mascot, etc. that has a safe appearance and size that can be recognized by users and consumers and that does not get in the way. A method is provided in which a product is packaged or built in and then attached to an article, and the article is managed using the wireless chip.

  For example, as shown in FIG. 11A, a wireless chip can be put in a bag 1101 and attached to an article 1102 such as a plastic bottle. If a wireless chip is put in a bag having a structure that is hooked on a product as shown in the figure, the retailer can easily attach the wireless chip to the product. In addition, since the bag has a size that can be recognized at a glance, it is possible to confirm at a glance an article that is not worn, and a consumer can also recognize that a wireless chip is contained. .

  In addition, as illustrated in FIG. 11B, the wireless chip can be mounted on an article 1104 such as a vegetable after being wrapped with wrapping paper 1103. As shown in the figure, by wrapping the wireless chip, it is easy to attach the wireless chip when bundling products such as vegetables. In addition, the consumer can use the wireless chip after reliably removing the wireless chip when cooking.

  Further, as shown in FIG. 11C, for example, when selling a high-quality bag or the like, the wireless chip can be mounted in the article 1106 after being built in the mascot 1105 or the like. As shown in the figure, incorporating a wireless chip in a cute mascot or the like may lead to a product image enhancement. Furthermore, since it is built in the mascot, it can be handled with care and the wireless chip can be recycled.

  By using the wireless chip as described above, the user of the wireless chip that performs retail sales and the consumer who purchases the goods can be aware of the wireless chip. Moreover, an unexpected accident can be avoided by using a safe material for the outermost surface of the packaged or built-in object. In addition, separate collection as waste becomes possible.

  Furthermore, it becomes easy to collect packaging, bags, and the like containing the tag in the retail store, and the wireless chip can be recycled. It is possible to prevent the wireless chip from being deteriorated by packaging or incorporating it. Further, the wireless chip can be recycled by replacing the package and the built-in one.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 6)
In this embodiment, types of antennas included in the wireless chip of the present invention are described with reference to FIGS.

  First, dielectric layers 1201, 1211, 1221, and 1241 of the antenna shown in FIGS. 12A to 12D are formed. The dielectric layer has a columnar shape, and the outer end thereof has a curved surface. More specifically, chamfering is performed by polishing the cylindrical upper surface and the angle at which the bottom surface and the side surface intersect to form a shape having only a flat surface and a curved surface. In addition, it may be formed in a polygonal column shape such as a quadrangular column, and a cornerless shape may be formed by chamfering a corner where the top surface, the bottom surface and the side surface intersect, or a corner where the side surface and the side surface intersect. Furthermore, it may be formed into a spherical shape, an oval shape, a meteorite-like elliptical sphere, a rugby ball-like elliptical sphere, or a disc shape. In FIG. 12, a dielectric layer formed in a cylindrical shape and then chamfered to eliminate corners is illustrated as an example. However, the present invention is not limited to this.

  First, the antenna illustrated in FIG. 12A includes a first conductive layer 1202 that functions as a radiation electrode, a dielectric layer 1201, a second conductive layer 1203 that functions as a grounding body, a feeding point 1204, The power supply body is formed in a through hole provided in the first conductive layer, the dielectric layer, and the second conductive layer, and connected to the power supply point. Note that the power supply body is connected to the first conductive layer at the power supply point, but is not connected to the second conductive layer. The first conductive layer 1202 functioning as a radiation electrode is circular and chamfers two regions 1205 that are point-symmetric so that an electromagnetic wave that is circularly polarized can be received. In the case where the first conductive layer 1202 is circular, the antenna is a linearly polarized antenna.

  Next, an antenna illustrated in FIG. 12B includes a first conductive layer 1212 that functions as a radiation electrode, a dielectric layer 1211, a second conductive layer 1213 that functions as a grounding body, a feeding point 1214, A power supply body is formed in a through hole provided in the first conductive layer, the dielectric layer, and the second conductive layer, and connected to a power supply point. Note that the power supply body is connected to the first conductive layer at the power supply point, but is not connected to the second conductive layer. The first conductive layer 1212 that functions as a radiation electrode is rectangular and becomes a circularly polarized antenna by chamfering two corners 1215 that are point-symmetric. In addition, when the first conductive layer 1212 is rectangular, the antenna is a direct-polarized antenna.

  In addition, the antenna illustrated in FIG. 12C includes a first conductive layer 1222 that functions as a radiation electrode, a dielectric layer 1221, a second conductive layer 1223 that functions as a grounding body, and a power feeding layer 1224. Have. The first conductive layer 1222 functioning as a radiation electrode is rectangular and can be used as a circularly polarized antenna by chamfering two corners 1225 that are point-symmetric. The first conductive layer 1222 functioning as a radiation electrode and the power feeder layer 1224 are capacitively coupled through a gap. In addition, the power feeding layer 1224 can be formed on the side surface of the dielectric layer and can be surface-mounted.

  In the antenna shown in FIGS. 12A to 12C, since the second conductive layer functioning as a grounding body is provided on one surface of the dielectric layer, directivity is provided on the first conductive layer side. And radiates radio waves to the first conductive layer side.

  12D includes a first conductive layer 1242 functioning as a radiation electrode, a dielectric layer 1241, a second conductive layer 1243 functioning as a grounding body, and a power feeding layer 1244. Have. In the first conductive layer 1242, orthogonal slits 1245 are formed on the diagonal lines. That is, a cross notch is provided. Therefore, the dielectric layer 1241 is exposed in a cross shape. The first conductive layer 1242 functioning as a radiation electrode and the power feeding layer 1244 are capacitively coupled through a gap.

  In particular, by using a circularly polarized antenna, satellite transmission / reception such as GPS (Global Positioning System (1.5 GHz)) and satellite digital broadcasting (2.6 GHz), wireless LAN (Local Area Network) (2.4 GHz, 5 GHz) .2 GHz), wireless communication for portable information devices (2.4 GHz), transmission / reception of PAN (Personal Area Network) such as UWB (Ultra Wide Band) (3-10 GHz), third generation data communication, Packet communication can be transmitted and received.

  Further, the wireless chip of the present invention can be configured using a known antenna other than the antenna shown in FIG.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 7)
In this embodiment, an example of a circuit configuration of the wireless chip of the present invention will be described with reference to FIGS.

  The wireless chip 20 of the present invention performs wireless communication with a reader / writer. As shown in FIG. 13A, the wireless chip 20 includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, a control circuit 14 for controlling other circuits, an interface circuit 15, a storage circuit 16, A bus 17 and an antenna 18 are provided.

  As shown in FIG. 13B, the wireless chip 20 of the present invention includes a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, a control circuit 14 for controlling other circuits, an interface circuit 15, In addition to the memory circuit 16, the bus 17, and the antenna 18, a central processing unit 21 may be included.

  Further, as shown in FIG. 13C, a power supply circuit 11, a clock generation circuit 12, a data demodulation / modulation circuit 13, a control circuit 14 for controlling other circuits, an interface circuit 15, a storage circuit 16, a bus 17, an antenna 18. In addition to the central processing unit 21, a detection unit 30 including a detection element 31 and a detection circuit 32 may be included. Here, the central processing unit 21 includes a CPU, an arithmetic processing circuit, and the like. The detection element 31 includes a sensor for measuring a physical quantity, a substance concentration, and the like.

  The wireless chip of this embodiment controls the power supply circuit 11, the clock generation circuit 12, the data demodulation / modulation circuit 13, and other circuits in the layer having the semiconductor elements described in the first to third embodiments. The wireless chip having a small size and multiple functions is configured by configuring the control circuit 14, the interface circuit 15, the memory circuit 16, the bus 17, the central processing unit 21, and the detection unit 30 including the detection element 31 and the detection circuit 32. Can be formed.

  The power supply circuit 11 is a circuit that generates various power supplies to be supplied to each circuit inside the wireless chip 20 based on the AC signal input from the antenna 18. The clock generation circuit 12 is a circuit that generates various clock signals to be supplied to each circuit inside the wireless chip 20 based on the AC signal input from the antenna 18. The data demodulation / modulation circuit 13 has a function of demodulating / modulating data communicated with the reader / writer 19. The control circuit 14 that controls other circuits has a function of controlling the memory circuit 16. The antenna 18 has a function of transmitting and receiving electromagnetic waves. The reader / writer 19 controls communication with the wireless chip, control, and processing related to the data. Note that the wireless chip is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and cryptographic processing dedicated hardware are added.

  The memory circuit 16 has one or more selected from DRAM, SRAM, FeRAM, mask ROM, PROM, EPROM, EEPROM, flash memory, and organic memory.

  Note that an organic memory is a memory in which a layer having an organic compound is interposed between a pair of electrodes. An organic memory is a memory in which a mixed layer of an organic compound and an inorganic compound is provided between a pair of electrodes. As a typical example of an organic compound, a substance whose crystal state, conductivity, and shape change when irradiated with an electric action or light is used. Typically, a conjugated polymer doped with a compound that generates acid by absorbing light (a photoacid generator), an organic compound with a high hole-transport property, or an organic compound with a high electron-transport property is used. it can.

  In the case where a mixed layer of an organic compound and an inorganic compound is provided between a pair of electrodes, it is preferable to mix an organic compound having a high hole-transport property and an inorganic compound that easily receives electrons. In addition, it is preferable to mix an organic compound having a high electron transporting property and an inorganic compound that easily gives electrons. By adopting such a configuration, many hole carriers and electron carriers are generated in organic compounds that have essentially no inherent carriers, and extremely excellent hole injection properties / transport properties and electron injection properties / transport properties are achieved. Show.

  Since the organic memory can simultaneously achieve downsizing, thinning, and large capacity, the wireless chip can be reduced in size and weight by providing the memory circuit 16 as an organic memory.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

(Embodiment 8)
One embodiment of the wireless chip of the present invention is shown in FIG. FIG. 14 is a cross-sectional view of the wireless chip. In this embodiment, a structure of a wireless chip in which a layer including a semiconductor element, a passive element, and an antenna are fixed with an anisotropic conductive adhesive, a conductive layer, or the like will be described.

  As shown in Embodiment Modes 1 to 3, a layer 1401 including a semiconductor element is formed. A layer 1401 having a semiconductor element and a passive element 1420 are fixed with an anisotropic conductive adhesive 1410. Here, the passive element 1420 is indicated by a first passive element 1430 and a second passive element 1440. In addition, the wiring 1402 exposed on the surface of the layer 1401 having a semiconductor element and the first wiring 1421 of the passive element 1420 are electrically connected by conductive particles in the anisotropic conductive adhesive.

  In addition, the passive element 1420 and the antenna 1460 are fixed to each other with conductive layers 1450 and 1451. The power supply layer 1463 of the antenna 1460 and the second wiring 1422 of the passive element 1420, the second conductive layer 1462 functioning as the antenna grounding body, and the third wiring 1423 of the passive element are electrically connected by conductive layers 1450 and 1451, respectively. Connected. The conductive layers 1450 and 1451 are formed by curing a conductive paste. Typical examples of the conductive layer obtained by curing the conductive paste include tin (Sn), silver (Ag), bismuth (Bi), copper (Cu), indium (In), nickel (Ni), antimony (Sb), and zinc. An alloy containing a plurality of (Zn) is mentioned. An anisotropic conductive adhesive can be used instead of the conductive layers 1450 and 1451.

  In addition, the first passive element 1430 includes insulating layers 1431 to 1434 and conductive layers 1441 to 1443 provided therebetween, and any one or more of a capacitor, an inductor, and a resistor is formed. Similarly, in the second passive element 1440, the insulating layers 1434 to 1437 and the conductive layers 1444 to 1446 provided therebetween constitute at least one of a capacitor, an inductor, and a resistor.

  The dielectric constant of the insulating layers 1431 to 1437 of the first passive element 1430 or the second passive element 1440 is preferably 2.6 to 40. For the conductive layers 1441 to 1446, a metal having high conductivity such as gold, silver, copper, or aluminum, or an alloy formed of any one of these metals is used.

  A method for forming the first passive element 1430 and the second passive element 1440 is described below. It is formed of a ceramic having aluminum oxide and silicon oxide in a sheet form with a film thickness of 10 to 150 μm (so-called green sheet), a metal having high conductivity such as gold, silver, copper, aluminum, or any one of these. The alloy is printed by a printing method to form a conductive layer. If necessary, a through hole may be formed in the green sheet, and a conductive paste may be filled in the through hole to form a plug. The green sheet may be formed by appropriately mixing ceramic, organic resin, or the like that forms the dielectric layer 1461 of the antenna 1460 described in Embodiment 1 or 2. A plurality of green sheets printed with such a conductive layer are stacked and thermocompression bonded, processed to a predetermined size, heated at 800 to 1300 degrees to fire the insulating layer and the conductive layer, and the first passive element 1430, a second passive element 1440 can be formed.

  By combining multiple passive elements such as capacitors, inductors, resistors, wiring, etc., an antenna front-end module including a diplexer and a low-pass filter constituting a high-frequency circuit, and an isolator power amplifier including an isolator, a coupler, an attenuator, and a power amplifier A module, a VCO (voltage controlled oscillator), a band-pass filter (BPF), a multilayer filter, a balun transformer, a dielectric filter, a coupler, a resonator, and the like can be configured. Here, the high-frequency circuit is a circuit that operates at a frequency of several hundred MHz to several tens GHz.

  In addition, the control circuit, interface circuit, storage circuit, central processing unit, and detection circuit that control the power supply circuit, clock generation circuit, data demodulation / modulation circuit and other circuits that are high frequency circuits by the layer having the semiconductor element and the passive element An element, a detection control circuit, and the like are configured.

  Similarly to Embodiment Mode 1, the layer 1401 including a semiconductor element may be fixed to a flexible substrate with an organic resin layer interposed therebetween.

  The wireless chip of this embodiment includes an integrated circuit formed using a passive element and a semiconductor element which are formed by stacking an insulating layer and a conductive film. Therefore, each circuit is highly integrated with an element having a suitable function. By mounting the wireless chip of the present invention on a wiring board, the number of mounted components can be reduced, so that the wiring board area can be reduced and an electronic device having the wiring board can be downsized.

  Note that this embodiment mode can be freely combined with the above embodiment modes.

  In this embodiment, a method for forming a semiconductor element will be described with an example.

  An example of a layer having a semiconductor element which forms the wireless chip of the present invention is shown in FIG. 15B corresponds to a cross-sectional view taken along line ab in FIG. 15A, and FIG. 15C corresponds to a cross-sectional view taken along line cd in FIG. 15A. To do.

  15 includes semiconductor films 1503a and 1503b provided over a substrate 1501 with an insulating film 1502 interposed therebetween, and a gate provided over the semiconductor films 1503a and 1503b with a gate insulating film 1504 interposed therebetween. An electrode 1505, insulating films 1506 and 1507 provided so as to cover the gate electrode, and a conductive film 1508 which is electrically connected to the source region or the drain region of the semiconductor films 1503a and 1503b and is provided over the insulating film 1507 Have. Note that FIG. 15 illustrates the case where an n-type thin film transistor 1510a using part of the semiconductor film 1503a as a channel region and a p-type thin film transistor 1510b using part of the semiconductor film 1503b as a channel region are shown. However, it is not limited to this configuration. For example, in FIG. 15, an n-type thin film transistor 1510 a is provided with an LDD region and a p-type thin film transistor 1510 b is not provided with an LDD region, but may be provided in both or may not be provided in both. Is possible.

  As the substrate 1501, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a quartz substrate, a ceramic substrate, a metal substrate including stainless steel, or the like can be used. In addition, it is also possible to use a substrate made of a plastic such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES), or a flexible synthetic resin such as acrylic. is there. By using a flexible substrate, a layer having a semiconductor element that can be bent can be manufactured. In addition, since there is no significant limitation on the area and shape of such a substrate, if the substrate 1501 is, for example, a rectangular shape having a side of 1 meter or more and a rectangular shape, the productivity is remarkably increased. Can be improved. Such an advantage is a great advantage compared to the case of using a circular silicon substrate.

  The insulating film 1502 functions as a base film and is provided to prevent alkali metal such as Na or alkaline earth metal from the substrate 1501 from diffusing into the semiconductor films 1503a and 1503b and adversely affecting the characteristics of the semiconductor element. As the insulating film 1502, an insulating film containing oxygen or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) (x> y), or the like It is possible to provide a single layer structure or a stacked structure of these. For example, in the case where the insulating film 1502 is provided with a two-layer structure, a silicon nitride oxide film may be provided as a first insulating film and a silicon oxynitride film may be provided as a second insulating film. In the case where the insulating film 1502 is provided with a three-layer structure, a silicon oxynitride film is provided as a first insulating film, a silicon nitride oxide film is provided as a second insulating film, and an oxynitriding film is used as a third insulating film. A silicon film may be provided.

The semiconductor films 1503a and 1503b can be formed using an amorphous semiconductor or a semi-amorphous semiconductor (SAS). A polycrystalline semiconductor film may also be used. SAS is a semiconductor having an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal) and having a third state that is stable in terms of free energy and has a short-range order and a lattice. It includes a crystalline region with strain. A crystal region of 0.5 to 20 nm can be observed in at least a part of the film, and when silicon is a main component, the Raman spectrum is shifted to a lower wave number side than 520 cm ^−1. Yes. In X-ray diffraction, diffraction peaks of (111) and (220) that are derived from the silicon crystal lattice are observed. In order to terminate dangling bonds (dangling bonds), hydrogen or halogen is contained at least 1 atomic% or more. SAS is formed by glow discharge decomposition (plasma CVD) of a gas containing silicon. As a gas containing silicon, SiH ₄ , Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF _{4, and the} like can be used. Further, GeF ₄ may be mixed. This silicon-containing gas may be diluted with H ₂ , or H ₂ and one or more kinds of rare gas elements selected from He, Ar, Kr, and Ne. The dilution rate is in the range of 2 to 1000 times. The pressure is in the range of 0.1 Pa to 133 Pa, and the power supply frequency is 1 MHz to 120 MHz, preferably 13 MHz to 60 MHz. The substrate heating temperature may be 300 ° C. or less. As an impurity element in the film, impurities of atmospheric components such as oxygen, nitrogen, and carbon are desirably 1 × 10 ²⁰ cm ⁻¹ or less, and in particular, the oxygen concentration is 5 × 10 ¹⁹ / cm ³ or less, preferably 1 × 10 ¹⁹ / cm ³ or less. Here, an amorphous semiconductor film is formed from a material (eg, Si _x Ge _1-x ) containing silicon (Si) as a main component using a known means (sputtering method, LPCVD method, plasma CVD method, or the like). The amorphous semiconductor film is crystallized by a known crystallization method such as a laser crystallization method, a thermal crystallization method using an RTA or furnace annealing furnace, or a thermal crystallization method using a metal element that promotes crystallization.

  The gate insulating film 1504 is an insulating film containing oxygen or nitrogen such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) (x> y). It is possible to provide a single layer structure or a stacked structure of these.

  The insulating film 1506 is formed by a known means (a sputtering method, a plasma CVD method, or the like) using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), silicon nitride oxide (SiNxOy) ( It can be provided with a single layer structure of an insulating film containing oxygen or nitrogen such as x> y) or a film containing carbon such as DLC (diamond-like carbon), or a laminated structure thereof.

  The insulating film 1507 is an insulating film containing oxygen or nitrogen, such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), or silicon nitride oxide (SiNxOy) (x> y). In addition to a film containing carbon such as DLC (diamond-like carbon), it may be provided in a single layer or laminated structure made of an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or siloxane resin. it can. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Note that in the layer having a semiconductor element in FIG. 15, the insulating film 1507 can be provided directly so as to cover the gate electrode 1505 without providing the insulating film 1506.

  As the conductive film 1508, a single layer or a stacked structure including one kind of element selected from Al, Ni, C, W, Mo, Ti, Pt, Cu, Ta, Au, and Mn or an alloy containing a plurality of such elements is used. be able to. For example, as a conductive film made of an alloy containing a plurality of the elements, for example, an Al alloy containing C and Ti, an Al alloy containing Ni, an Al alloy containing C and Ni, an Al alloy containing C and Mn, etc. Can be used. Moreover, when providing with a laminated structure, it can provide by laminating | stacking Al and Ti.

  In FIG. 15, an n-type thin film transistor 1510a has a sidewall in contact with the sidewall of the gate electrode 1505, and a source region and a drain in which an impurity imparting n-type conductivity is selectively added to the semiconductor film 1503a. An LDD region provided below the region and the sidewall is formed. The p-type thin film transistor 1510b has a sidewall in contact with the sidewall of the gate electrode 1505, and a source region and a drain region to which an impurity imparting p-type conductivity is selectively added are formed in the semiconductor film 1503b. ing.

  Note that the layer having a semiconductor element included in the wireless chip of the present invention includes at least one of the substrate 1501, the insulating film 1502, the semiconductor films 1503a and 1503b, the gate insulating film 1504, the insulating film 1506, and the insulating film 1507. Then, the semiconductor film or the insulating film is oxidized or nitrided by performing oxidation or nitridation using plasma treatment. In this manner, the surface of the semiconductor film or the insulating film is modified by oxidizing or nitriding the semiconductor film or the insulating film using plasma treatment, and compared with an insulating film formed by a CVD method or a sputtering method. Since a dense insulating film can be formed, defects such as pinholes can be suppressed and characteristics of a layer including a semiconductor element can be improved.

  A method for manufacturing a layer having a semiconductor element by using plasma treatment will be described below with reference to the drawings. Specifically, a layer having a semiconductor element is manufactured by oxidizing or nitriding the substrate 1501, the insulating film 1502, the semiconductor films 1503a and 1503b, the gate insulating film 1504, the insulating film 1506, or the insulating film 1507 using plasma treatment. The case will be described.

  Here, a method of manufacturing a layer having a semiconductor element by performing plasma treatment on the semiconductor films 1503a and 1503b or the gate insulating film 1504 in FIG. 15 and oxidizing or nitriding the semiconductor films 1503a and 1503b or the gate insulating film 1504 is performed. Will be described with reference to the drawings.

  First, the case where an island-shaped semiconductor film provided over a substrate is provided with an end portion of the island-shaped semiconductor film having a shape close to a right angle is described.

First, island-shaped semiconductor films 1503a and 1503b are formed over the substrate 1501 (FIGS. 16A-1 and 16A-2). The island-shaped semiconductor films 1503a and 1503b are mainly composed of silicon (Si) by using a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) over an insulating film 1502 formed in advance on the substrate 1501. An amorphous semiconductor film can be formed using a material (eg, Si _x Ge _1-x or the like), the amorphous semiconductor film can be crystallized, and the semiconductor film can be selectively etched. The crystallization of the amorphous semiconductor film may be performed by laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, or a combination of these methods. It can carry out by the well-known crystallization method. Note that in FIG. 16, the end portions of the island-shaped semiconductor films 1503a and 1503b are provided in a shape close to a right angle (θ = 85 to 100 °).

Next, plasma treatment is performed to oxidize or nitride the semiconductor films 1503a and 1503b, whereby oxide or nitride films 1521a and 1521b (hereinafter also referred to as insulating films 1521a and 1521b) are formed on the surfaces of the semiconductor films 1503a and 1503b, respectively. ) (FIGS. 16B-1 and 16B-2). For example, when Si is used for the semiconductor films 1503a and 1503b, silicon oxide (SiOx) or silicon nitride (SiNx) is formed as the insulating films 1521a and 1521b. Alternatively, the semiconductor films 1503a and 1503b may be oxidized by plasma treatment and then nitrided by performing plasma treatment again. In this case, silicon oxide (SiOx) is formed in contact with the semiconductor films 1503a and 1503b, and silicon nitride oxide (SiNxOy) (x> y) is formed on the surface of the silicon oxide. Note that in the case where the semiconductor film is oxidized by plasma treatment, an oxygen atmosphere (eg, oxygen (O ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere or oxygen is used. Plasma treatment is performed under an atmosphere of hydrogen (H ₂ ) and a rare gas or dinitrogen monoxide and a rare gas. On the other hand, in the case of nitriding a semiconductor film by plasma treatment, in a nitrogen atmosphere (for example, nitrogen (N ₂ ) and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) atmosphere or nitrogen Plasma treatment is performed under a hydrogen and rare gas atmosphere or a NH ₃ and rare gas atmosphere. As the rare gas, for example, Ar can be used. A gas in which Ar and Kr are mixed may be used. Therefore, the insulating films 1521a and 1521b include a rare gas (including at least one of He, Ne, Ar, Kr, and Xe) used for plasma treatment. When Ar is used, the insulating films 1521a and 1521b are used. Contains Ar.

In addition, the plasma treatment is performed in the above gas atmosphere at an electron density of 1 × 10 ¹¹ cm ⁻³ or more and 1 × 10 ¹³ cm ⁻³ or less and an electron temperature of plasma of 0.5 eV or more and 1.5 eV or less. . Since the electron density of plasma is high and the electron temperature in the vicinity of the object to be processed (here, the semiconductor films 1503a and 1503b) formed on the substrate 1501 is low, damage to the object to be processed is prevented. Can do. In addition, since the electron density of plasma is as high as 1 × 10 ¹¹ cm ⁻³ or more, an oxide or a nitride film formed by oxidizing or nitriding an irradiation object using plasma treatment is a CVD method. Compared with a film formed by sputtering or the like, a film having excellent uniformity in film thickness and the like and a dense film can be formed. In addition, since the electron temperature of plasma is as low as 1 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma treatment or thermal oxidation. For example, even if the plasma treatment is performed at a temperature that is 100 degrees or more lower than the strain point temperature of the glass substrate, the oxidation or nitridation treatment can be sufficiently performed. Note that a high frequency such as a microwave (2.45 GHz) can be used as a frequency for forming plasma. Note that the plasma treatment is performed using the above conditions unless otherwise specified.

  Next, a gate insulating film 1504 is formed so as to cover the insulating films 1521a and 1521b (FIGS. 16C-1 and 16C-2). The gate insulating film 1504 is formed using known means (sputtering method, LPCVD method, plasma CVD method, or the like) using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), or nitride. A single-layer structure of an insulating film containing oxygen or nitrogen such as silicon oxide (SiNxOy) (x> y) or a stacked structure thereof can be used. For example, in the case where Si is used as the semiconductor films 1503a and 1503b and silicon is oxidized by plasma treatment to form silicon oxide as the insulating films 1521a and 1521b on the surfaces of the semiconductor films 1503a and 1503b, over the insulating films 1521a and 1521b Then, silicon oxide (SiOx) is formed as a gate insulating film. In FIGS. 16B-1 and 16B-2, the insulating films 1521a and 1521b formed by oxidizing or nitriding the semiconductor films 1503a and 1503b by plasma treatment are sufficient. The insulating films 1521a and 1521b can also be used as gate insulating films.

  Next, by forming a gate electrode 1505 or the like over the gate insulating film 1504, a semiconductor element including an n-type thin film transistor 1510a and a p-type thin film transistor 1510b using the island-shaped semiconductor films 1503a and 1503b as channel regions is provided. A layer can be manufactured (FIGS. 16D-1 and 16D-2).

  As described above, before the gate insulating film 1504 is provided over the semiconductor films 1503a and 1503b, the surface of the semiconductor films 1503a and 1503b is oxidized or nitrided by plasma treatment, so that the gate insulation in the end portions 1551a and 1551b of the channel region is obtained. A short-circuit between the gate electrode and the semiconductor film due to the coating failure of the film 1504 can be prevented. That is, when the end portion of the island-shaped semiconductor film has a shape close to a right angle (θ = 85 to 100 °), the gate insulating film is formed so as to cover the semiconductor film by a CVD method, a sputtering method, or the like. However, there is a possibility that the problem of poor coating due to step breakage of the gate insulating film may occur at the end of the semiconductor film. However, by oxidizing or nitriding the surface of the semiconductor film in advance using plasma treatment, the end of the semiconductor film It is possible to prevent a defective coating of the gate insulating film at the portion.

  In FIG. 16, the gate insulating film 1504 may be oxidized or nitrided by performing plasma treatment after the gate insulating film 1504 is formed. In this case, plasma treatment is performed on the gate insulating film 1504 (FIGS. 17A-1 and 17A-2) formed so as to cover the semiconductor films 1503a and 1503b, and the gate insulating film 1504 is oxidized or nitrided. Thus, an oxide film or a nitride film 1523 (hereinafter also referred to as an insulating film 1523) is formed on the surface of the gate insulating film 1504 (FIGS. 17B-1 and 17B-2). The conditions for the plasma treatment can be the same as those in FIGS. 16B-1 and 16B-2. The insulating film 1523 contains a rare gas used for the plasma treatment. For example, when Ar is used, the insulating film 1523 contains Ar.

  In FIGS. 17B-1 and 17B-2, the gate insulating film 1504 is once oxidized by performing plasma treatment in an oxygen atmosphere, and then nitrided by performing plasma treatment again in a nitrogen atmosphere. You may let them. In this case, silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) is formed on the semiconductor films 1503a and 1503b, and silicon nitride oxide (SiNxOy) (x> y) is formed in contact with the gate electrode 1505. Is done. After that, by forming a gate electrode 1505 and the like over the insulating film 1523, a layer having a semiconductor element including an n-type thin film transistor 1510a and a p-type thin film transistor 1510b using the island-shaped semiconductor films 1503a and 1503b as channel regions is formed. It can produce (FIG. 17 (C-1) and (C-2)).

  In this manner, by performing plasma treatment on the gate insulating film, the surface of the gate insulating film is oxidized or nitrided, whereby the surface of the gate insulating film can be modified and a dense film can be formed. An insulating film obtained by performing plasma treatment is denser and has fewer defects such as pinholes than an insulating film formed by a CVD method or a sputtering method, so that characteristics of the thin film transistor can be improved.

  Note that FIG. 17 illustrates the case where the surfaces of the semiconductor films 1503a and 1503b are oxidized or nitrided by performing plasma treatment on the semiconductor films 1503a and 1503b in advance, but the semiconductor films 1503a and 1503b are subjected to plasma treatment. Alternatively, a method of performing plasma treatment after the gate insulating film 1504 is formed may be used. As described above, by performing the plasma treatment before forming the gate electrode, even if a coating failure occurs due to a step breakage of the gate insulating film at the end of the semiconductor film, the semiconductor film exposed due to the coating failure Therefore, short-circuit between the gate electrode and the semiconductor film due to poor coverage of the gate insulating film at the end of the semiconductor film can be prevented.

  In this manner, even when the end portion of the island-shaped semiconductor film is provided in a shape that is nearly perpendicular, plasma treatment is performed on the semiconductor film or the gate insulating film to oxidize or nitride the semiconductor film or the gate insulating film. As a result, a short circuit between the gate electrode and the semiconductor film due to poor coverage of the gate insulating film at the end of the semiconductor film can be prevented.

  Next, in the island-shaped semiconductor film provided over the substrate, the case where the end portion of the island-shaped semiconductor film is provided in a tapered shape (θ = 30 to 85 °) is described.

First, island-shaped semiconductor films 1503a and 1503b are formed over the substrate 1501 (FIGS. 18A-1 and 18A-2). The island-shaped semiconductor films 1503a and 1503b are mainly composed of silicon (Si) by using a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) over an insulating film 1502 formed in advance on the substrate 1501. An amorphous semiconductor film is formed using a material (for example, Si _x Ge _1-x ) and the like, and the amorphous semiconductor film is subjected to laser crystallization, thermal crystallization using RTA or a furnace annealing furnace, crystallization The semiconductor film can be provided by being crystallized by a known crystallization method such as a thermal crystallization method using a metal element that promotes and selectively removing the semiconductor film by etching. Note that in FIG. 18, the end portion of the island-shaped semiconductor film is provided in a tapered shape (θ = 30 to 85 °).

  Next, a gate insulating film 1504 is formed so as to cover the semiconductor films 1503a and 1503b (FIGS. 18B-1 and 18B-2). The gate insulating film 1504 is formed using known means (sputtering method, LPCVD method, plasma CVD method, or the like) using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), or nitride. A single-layer structure of an insulating film containing oxygen or nitrogen such as silicon oxide (SiNxOy) (x> y) or a stacked structure thereof can be used.

  Next, plasma treatment is performed to oxidize or nitride the gate insulating film 1504, thereby forming an oxide film or a nitride film 1524 (hereinafter also referred to as an insulating film 1524) on the surface of the gate insulating film 1504 (FIG. C-1) and (C-2)). The plasma treatment conditions can be the same as described above. For example, when silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) is used as the gate insulating film 1504, the gate insulating film 1504 is oxidized by performing plasma treatment in an oxygen atmosphere, whereby the gate insulating film A dense film with few defects such as pinholes can be formed on the surface of this film as compared with a gate insulating film formed by CVD or sputtering. On the other hand, by performing plasma treatment in a nitrogen atmosphere and nitriding the gate insulating film 1504, silicon nitride oxide (SiNxOy) (x> y) can be provided as the insulating film 1524 on the surface of the gate insulating film 1504. Alternatively, the gate insulating film 1504 may be oxidized by once performing plasma treatment in an oxygen atmosphere, and then nitrided by performing plasma treatment again in a nitrogen atmosphere. The insulating film 1524 contains a rare gas used for plasma treatment. For example, when Ar is used, the insulating film 1524 contains Ar.

  Next, by forming a gate electrode 1505 or the like over the gate insulating film 1504, a semiconductor element including an n-type thin film transistor 1510a and a p-type thin film transistor 1510b using the island-shaped semiconductor films 1503a and 1503b as channel regions is provided. A layer can be formed (FIGS. 18D-1 and 18D-2).

  In this manner, by performing plasma treatment on the gate insulating film, an insulating film made of an oxide film or a nitride film can be provided on the surface of the gate insulating film, and the surface of the gate insulating film can be modified. An insulating film oxidized or nitrided by plasma treatment is denser and has fewer defects such as pinholes than a gate insulating film formed by a CVD method or a sputtering method, so that the characteristics of the thin film transistor can be improved. it can. In addition, by forming the end portion of the semiconductor film in a tapered shape, a short circuit between the gate electrode and the semiconductor film due to poor coverage of the gate insulating film at the end portion of the semiconductor film can be suppressed. By performing plasma treatment after the formation, a short circuit between the gate electrode and the semiconductor film can be further prevented.

  Next, a method for manufacturing a layer having a semiconductor element different from that in FIG. 18 is described with reference to drawings. Specifically, a case where plasma treatment is selectively performed on an end portion of a semiconductor film having a tapered shape is described.

First, island-shaped semiconductor films 1503a and 1503b are formed over the substrate 1501 (FIGS. 19A-1 and 19A-2). The island-shaped semiconductor films 1503a and 1503b are mainly composed of silicon (Si) by using a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) over an insulating film 1502 formed in advance on the substrate 1501. An amorphous semiconductor film is formed using a material (eg, Si _x Ge _1-x or the like), the amorphous semiconductor film is crystallized, and the semiconductor film is selectively etched using the resists 1525a and 1525b as masks. Can be provided. The crystallization of the amorphous semiconductor film may be performed by laser crystallization, thermal crystallization using an RTA or furnace annealing furnace, thermal crystallization using a metal element that promotes crystallization, or a combination of these methods. It can carry out by the well-known crystallization method.

  Next, before removing the resists 1525a and 1525b used for etching the semiconductor film, plasma treatment is performed to selectively oxidize or nitride the end portions of the island-shaped semiconductor films 1503a and 1503b. An oxide film or a nitride film 1526 (hereinafter also referred to as an insulating film 1526) is formed on end portions of the films 1503a and 1503b (FIGS. 19B-1 and 19B-2). The plasma treatment is performed under the conditions described above. The insulating film 1526 contains a rare gas used for plasma treatment.

  Next, a gate insulating film 1504 is formed so as to cover the semiconductor films 1503a and 1503b (FIGS. 19C-1 and 19C-2). The gate insulating film 1504 can be provided in a manner similar to the above.

  Next, by forming a gate electrode 1505 or the like over the gate insulating film 1504, a semiconductor element including an n-type thin film transistor 1510a and a p-type thin film transistor 1510b using the island-shaped semiconductor films 1503a and 1503b as channel regions is provided. A layer can be formed (FIGS. 19D-1 and 19D-2).

  In the case where the end portions of the semiconductor films 1503a and 1503b are provided in a tapered shape, the end portions 1552a and 1552b of the channel regions formed in part of the semiconductor films 1503a and 1503b are also tapered and the thickness of the semiconductor film or the gate insulating film Since the film thickness changes as compared with the central portion, the characteristics of the thin film transistor may be affected. Therefore, here, a thin film transistor caused by an end portion of the channel region is formed by selectively oxidizing or nitriding the end portion of the channel region by plasma treatment and forming an insulating film in the semiconductor film which becomes the end portion of the channel region. The influence on can be reduced.

  Note that FIG. 19 shows an example in which oxidation or nitridation is performed by plasma treatment only on the end portions of the semiconductor films 1503a and 1503b. However, as shown in FIG. 18, the gate insulating film 1504 is also subjected to plasma treatment. It is also possible to perform oxidation or nitridation (FIGS. 21A-1 and 21A-2).

  Next, a method for manufacturing a layer having a semiconductor element different from the above is described with reference to drawings. Specifically, a case where plasma treatment is performed on a semiconductor film having a tapered shape is described.

  First, island-shaped semiconductor films 1503a and 1503b are formed over the substrate 1501 as described above (FIGS. 20A-1 and 20A-2).

  Next, plasma treatment is performed to oxidize or nitride the semiconductor films 1503a and 1503b, whereby oxide or nitride films 1527a and 1527b (hereinafter also referred to as insulating films 1527a and 1527b) are formed on the surfaces of the semiconductor films 1503a and 1503b, respectively. (FIGS. 20B-1 and 20B-2). The plasma treatment can be similarly performed under the above-described conditions. For example, when Si is used for the semiconductor films 1503a and 1503b, silicon oxide (SiOx) or silicon nitride (SiNx) is formed as the insulating films 1527a and 1527b. Alternatively, the semiconductor films 1503a and 1503b may be oxidized by plasma treatment and then nitrided by performing plasma treatment again. In this case, silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) is formed in contact with the semiconductor films 1503a and 1503b, and silicon nitride oxide (SiNxOy) (x> y) is formed on the surface of the silicon oxide. It is formed. Therefore, the insulating films 1527a and 1527b contain a rare gas used for plasma treatment. Note that the end portions of the semiconductor films 1503a and 1503b are simultaneously oxidized or nitrided by performing the plasma treatment.

  Next, a gate insulating film 1504 is formed so as to cover the insulating films 1527a and 1527b (FIGS. 20C-1 and 20C-2). The gate insulating film 1504 is formed using known means (sputtering method, LPCVD method, plasma CVD method, or the like) using silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x> y), or nitride. A single-layer structure of an insulating film containing oxygen or nitrogen such as silicon oxide (SiNxOy) (x> y) or a stacked structure thereof can be used. For example, when silicon oxide is formed as the insulating films 1527a and 1527b on the surfaces of the semiconductor films 1503a and 1503b by oxidizing the semiconductor films 1503a and 1503b by plasma treatment using Si, a gate is formed over the insulating films 1527a and 1527b. Silicon oxide (SiOx) is formed as an insulating film.

  Next, by forming a gate electrode 1505 or the like over the gate insulating film 1504, a semiconductor element including an n-type thin film transistor 1510a and a p-type thin film transistor 1510b using the island-shaped semiconductor films 1503a and 1503b as channel regions is provided. A layer can be formed (FIGS. 20D-1 and 20D-2).

  In the case where the end portion of the semiconductor film is provided in a tapered shape, the end portions 1553a and 1553b of the channel region formed in part of the semiconductor film are also tapered, which may affect the characteristics of the semiconductor element. Therefore, by oxidizing or nitriding the semiconductor film by plasma treatment, as a result, the end portion of the channel region is also oxidized or nitrided, so that the influence on the semiconductor element can be reduced.

  Note that although FIG. 20 illustrates an example in which oxidation or nitridation is performed by plasma treatment only on the semiconductor films 1503a and 1503b, it goes without saying that the gate insulating film 1504 is oxidized or oxidized by plasma treatment as shown in FIG. Nitridation is also possible (FIGS. 21B-1 and 21B-2). In this case, the gate insulating film 1504 may be oxidized by once performing plasma treatment in an oxygen atmosphere and then nitrided by performing plasma treatment again in a nitrogen atmosphere. In this case, silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x> y) is formed in the semiconductor films 1503a and 1503b, and silicon nitride oxide (SiNxOy) (x> y) is formed in contact with the gate electrode 1505. Is done.

  Further, by performing plasma treatment as described above, impurities such as dust attached to the semiconductor film and the insulating film can be easily removed. In general, dust (also referred to as particles) may be attached to a film formed by a CVD method, a sputtering method, or the like. For example, as illustrated in FIG. 22A, dust 1573 may be formed over an insulating film 1572 formed by a CVD method, a sputtering method, or the like over a film 1571 such as an insulating film, a conductive film, or a semiconductor film. . Even in such a case, an oxide film or a nitride film 1574 (hereinafter also referred to as an insulating film 1574) is formed on the surface of the insulating film 1572 by performing plasma treatment to oxidize or nitride the insulating film 1572. The insulating film 1574 is oxidized or nitrided so as to go around not only the portion where the dust 1573 is not present but also the lower portion of the dust 1573, whereby the volume of the insulating film 1574 is increased. On the other hand, the surface of the dust 1573 is also oxidized or nitrided by plasma treatment to form an insulating film 1575. As a result, the volume of the dust 1573 increases (FIG. 22B).

  At this time, the dust 1573 is easily removed from the surface of the insulating film 1574 by simple cleaning such as brush cleaning. In this manner, by performing plasma treatment, removal of dust is facilitated even if the dust is attached to the insulating film or the semiconductor film. This is an effect obtained by performing the plasma treatment, and the same can be said not only in this embodiment but also in other embodiments.

  In this manner, by performing plasma treatment to oxidize or nitride the semiconductor film or the gate insulating film to modify the surface, a dense insulating film with good film quality can be formed. In addition, dust or the like attached to the surface of the insulating film can be easily removed by cleaning. As a result, even when the insulating film is formed thin, defects such as pinholes can be prevented, and miniaturization and high performance of semiconductor elements such as thin film transistors can be achieved.

  Note that this embodiment can be freely combined with the above embodiment mode.

FIG. 6 is a perspective view and a cross-sectional view of a wireless chip of the present invention. FIG. 6 is a block diagram illustrating a circuit configuration of a wireless chip of the present invention. 8A and 8B illustrate a manufacturing process of an antenna included in a wireless chip of the present invention. Sectional drawing of the semiconductor element which comprises a wireless chip. 8A and 8B illustrate a manufacturing process of a semiconductor element and a memory element included in a wireless chip. 8A and 8B illustrate a manufacturing process of a semiconductor element and a memory element included in a wireless chip. 1 is a cross-sectional view of a wireless chip of the present invention. FIG. 14 is a cross-sectional view of a semiconductor element included in a wireless chip of the present invention. FIG. 14 is a cross-sectional view of a semiconductor element included in a wireless chip of the present invention. 6A and 6B illustrate a wireless chip of the present invention. 4A and 4B illustrate a method for using a wireless chip of the present invention. 6A and 6B illustrate an antenna included in a wireless chip of the present invention. FIG. 6 is a block diagram illustrating a circuit configuration of a wireless chip of the present invention. 1 is a cross-sectional view of a wireless chip of the present invention. 2A and 2B are a top view and a cross-sectional view of a semiconductor element included in a wireless chip. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor element included in a wireless chip. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor element included in a wireless chip. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor element included in a wireless chip. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor element included in a wireless chip. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor element included in a wireless chip. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor element included in a wireless chip. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor element included in a wireless chip. FIG. 9 shows a shape of an antenna included in a wireless chip.

Explanation of symbols

11 power supply circuit 12 clock generation circuit 13 data demodulation / modulation circuit 14 control circuit 15 for controlling other circuits 15 interface circuit 16 storage circuit 17 bus 18 antenna 19 reader / writer 20 wireless chip 21 central processing unit 30 detection unit 31 detection element 32 detection Circuit 101 Antenna 102 Layer 103 with Semiconductor Element First Conductive Layer 104 Second Conductive Layer 105 Feeder Layer 106 Dielectric Layer 201 Wireless Chip 202 Reader / Writer 203 Computer 204 USB (Universal Serial Bus) Port 211 Antenna 212 Semiconductor Element Layer 213 Communication circuit portion 214 Arithmetic processing circuit portion 215 Power supply circuit portion 216 Memory portion 217 Demodulation circuit 218 Modulation circuit 301 Dielectric layer 302 Dielectric layer 401 Insulating substrate 402 Release layer 403 Insulating layer 04 Semiconductor layer 405 Gate insulating layer 406 Gate electrode layer 407 n-type impurity region 408 p-type impurity region 409 insulating layer 410 first n-type impurity region 411 second n-type impurity region 412 n-type transistor 413 p-type transistor 414 insulating Layer 415 conductive layer 416 insulating layer 417 first conductive layer 418 insulating layer 419 wiring 420 organic compound layer 421 conductive layer 422 protective layer 427 opening 428 layer having semiconductor element and memory element 429 first flexible substrate 430 Second flexible substrate 701 Semiconductor element layer 702a Conductive layer 702b Conductive layer 703 Antenna 704 Underfill 704a Connection terminal 704b Connection terminal 710 Dielectric layer 711 First conductive layer 712 Second conductive layer 713 Feeder layer 800 Substrate 801a Element isolation region 01b element isolation region 801c element isolation region 801d element isolation region 801e element isolation region 802 semiconductor element 803 gate insulating film 804 gate electrode 805a drain region 806a low concentration impurity region 807a sidewall 808 interlayer insulating layer 809a drain wiring 811 interlayer insulating layer 812 connection Terminal 813 Connection terminal 814 Insulating layer 900 Semiconductor element 901 Substrate 902 Gate electrode 903 Insulating layer 904 Semiconductor layer 905 Wiring 1001 Wireless chip 1002 Protective layer 1003 Protective layer 1004 Protective layer 1005 Filler 1101 Bag 1102 Article 1103 Wrapping paper 1104 Article 1105 Mascot 1106 Article 1201 Dielectric layer 1202 First conductive layer 1203 Second conductive layer 1204 Feed point 1205 Region 1211 Dielectric layer 1212 First conductive layer 12 3 Second conductive layer 1214 Feed point 1215 Corner portion 1221 Dielectric layer 1222 First conductive layer 1223 Second conductive layer 1224 Feeder layer 1225 Corner portion 1241 Dielectric layer 1242 First conductive layer 1243 Second conductivity Layer 1244 Feeder layer 1245 Orthogonal slit 1401 Layer 1402 having semiconductor elements Wiring 1410 Anisotropic conductive adhesive 1420 Passive element 1421 First wiring 1422 Second wiring 1423 Third wiring 1430 First passive element 1431 Insulating layer 1432 Insulating layer 1433 Insulating layer 1434 Insulating layer 1440 Second passive element 1441 Conductive layer 1442 Conductive layer 1443 Conductive layer 1444 Conductive layer 1445 Conductive layer 1446 Conductive layer 1450 Conductive layer 1451 Conductive layer 1460 Antenna 1461 Dielectric layer 1462 Second conductive Layer 1463 Power supply layer 1501 Plate 1502 insulating film 1503a semiconductor film 1503b semiconductor film 1504 gate insulating film 1505 gate electrode 1506 insulating film 1507 insulating film 1508 conductive film 1510a n-type thin film transistor 1510b p-type thin film transistor 1521a insulating film 1521b insulating film 1523 insulating film 1524 insulating film 1525a resist 1525b Resist 1526 Insulating film 1527a Insulating film 1527b Insulating film 1551a End of channel region 1551b End of channel region 1552a End of channel region 1552b End of channel region 1553a End of channel region 1553b End of channel region 1571 Film 1572 Insulating film 1573 Dust 1574 Insulating film 1575 Insulating film

Claims (7)

A layer having a semiconductor element, a layer having a passive element electrically connected to the layer having the semiconductor element, and an antenna electrically connected to the layer having the passive element,
The antenna has a first conductive layer, a second conductive layer, and a dielectric layer sandwiched between the first conductive layer and the second conductive layer,
The layer having the passive element and the layer having the semiconductor element are electrically connected via a resin layer having conductive particles,
The dielectric layer, go stone shaped oval sphere, rugby ball-shaped oval sphere, or a disk shape, One or, wherein a the outer edge portion has a shape having a curved surface. In claim 1,
The layer having a passive element includes a passive element including at least one of an inductor, a capacitor, and a resistor. In claim 1 or claim 2,
The semiconductor device formed in the layer having the semiconductor element has an organic semiconductor layer. In any one of Claims 1 thru | or 3,
The layer including the semiconductor element includes a transistor, an insulating layer covering the transistor, and a memory element including a third conductive layer, an organic compound layer, and a fourth conductive layer.
In the insulating layer, a contact hole exposing the source region and the drain region of the transistor is formed,
The third conductive layer is provided in contact with one of a source region or a drain region of the transistor through the contact hole,
The organic compound layer is provided in contact with the third conductive layer in the contact hole,
The semiconductor device, wherein the fourth conductive layer is provided in contact with the organic compound layer in the contact hole. In any one of Claims 1 thru | or 4,
The dielectric layer is formed of one or more selected from alumina, glass, forsterite, barium titanate, lead titanate, strontium titanate, lead zirconate, lithium diobate, and lead zirconate titanate. A semiconductor device. In any one of Claims 1 thru | or 5,
It said dielectric layer is an epoxy resin, phenol resin, polybutadiene resin, and wherein a is formed at one or more selected from the vinylbenzyl, and polyfumarate. In any one of Claims 1 thru | or 6,
The semiconductor device is coated with a protective layer made of resin or diamond-like carbon, and a filler is filled between the semiconductor device and the protective layer.

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