JPH10303640A - Antenna system - Google Patents
Antenna systemInfo
- Publication number
- JPH10303640A JPH10303640A JP9108741A JP10874197A JPH10303640A JP H10303640 A JPH10303640 A JP H10303640A JP 9108741 A JP9108741 A JP 9108741A JP 10874197 A JP10874197 A JP 10874197A JP H10303640 A JPH10303640 A JP H10303640A
- Authority
- JP
- Japan
- Prior art keywords
- antenna
- circuit
- substrate
- band
- microwave integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
Landscapes
- Control Of Motors That Do Not Use Commutators (AREA)
- Variable-Direction Aerials And Aerial Arrays (AREA)
- Transceivers (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は素子アンテナと半導
体デバイスを一体化して構成したアクティブアンテナに
関し、特に、通信用アンテナとして用いるとき送信時に
おける他システムへの影響が少なく、受信時における他
からの干渉の影響の少ない、アクティブアンテナの構造
に係る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active antenna in which an element antenna and a semiconductor device are integrated with each other. The present invention relates to a structure of an active antenna which is less affected by interference.
【０００２】[0002]
【従来の技術】図３は従来のアクティブアンテナ構成の
第一の例を示す図であり、（ａ）はアンテナ素子付近を
模式的に表した斜視図、（ｂ）はアンテナ装置の断面を
示す図である。同図において、数字符号３はマイクロ波
用集積回路、７はビアホール、８は地板、２０は励振用
スタブ、２１はスロット、２２はスロット給電マイクロ
ストリップアンテナ、２３はポリイミド基板、２４はア
ルミナ−セラミック基板であり、２５はストリップ線路
を示している。2. Description of the Related Art FIGS. 3A and 3B show a first example of a conventional active antenna configuration. FIG. 3A is a perspective view schematically showing the vicinity of an antenna element, and FIG. 3B is a cross-sectional view of the antenna device. FIG. In the figure, numeral 3 is a microwave integrated circuit, 7 is a via hole, 8 is a ground plane, 20 is an excitation stub, 21 is a slot, 22 is a slot feed microstrip antenna, 23 is a polyimide substrate, and 24 is alumina-ceramic. A substrate 25 is a strip line.
【０００３】〔文献：K.Kamogawa,T.Tokumitsu and M.A
kikawa：“A Novel MicrostripAntenna Using Alumina-
ceramic/Polyimide Multilayer Dielectric Substrat
e,”in IEEE MTT-S Int. Microwave Symp. Dig.,1996,p
p.71-74.参照〕[Literature: K. Kamogawa, T. Tokumitsu and MA
kikawa: “A Novel MicrostripAntenna Using Alumina-
ceramic / Polyimide Multilayer Dielectric Substrat
e, ”in IEEE MTT-S Int. Microwave Symp. Dig., 1996, p
(See p.71-74.)
【０００４】図３のアンテナ装置は、ポリイミド・セラ
ミック多層基板を用いた平面アンテナの構成例を示した
ものである。本アンテナはセラミック・ポリイミド基板
の使用レイヤを組み合わせることにより、異なる周波数
の素子アンテナを同一基板に構成した場合でも、ほぼ同
一の比帯域を実現可能とする。FIG. 3 shows an example of the configuration of a planar antenna using a polyimide ceramic multilayer substrate. By combining the use layers of the ceramic / polyimide substrate, the present antenna can realize substantially the same fractional bandwidth even when element antennas of different frequencies are configured on the same substrate.
【０００５】しかし、本アンテナ構成は、マイクロ波用
集積回路３とスロット給電マイクロストリップアンテナ
２２を直結しており、マイクロ波用集積回路３内に送受
信用増幅器を具備した場合、送信時に増幅器の非線形歪
みにより生じる高調波により他の通信システムに影響を
与える恐れがあり、また、受信時におけるイメージ混信
などの干渉を受けるなどの不都合を生じ易かった。However, in this antenna configuration, the microwave integrated circuit 3 is directly connected to the slot-fed microstrip antenna 22. When the microwave integrated circuit 3 includes a transmitting / receiving amplifier, the nonlinearity of the amplifier during transmission is increased. Harmonics generated by the distortion may affect other communication systems, and are likely to cause inconveniences such as interference due to image interference during reception.
【０００６】図４は、従来の半導体デバイスと平面アン
テナを一体化したアンテナの構成例を示したものであ
る。同図において、数字符号１はマイクロストリップ線
路入出力端、５はローパスフィルタ、６はマイクロスト
リップ線路、１９はバンドパスフィルタ、２６はアンテ
ナパッチ、２７はラットレース回路であり、２８はダイ
オードを示している。FIG. 4 shows a configuration example of an antenna in which a conventional semiconductor device and a planar antenna are integrated. In the figure, numeral 1 denotes a microstrip line input / output terminal, 5 denotes a low-pass filter, 6 denotes a microstrip line, 19 denotes a band-pass filter, 26 denotes an antenna patch, 27 denotes a rat race circuit, and 28 denotes a diode. ing.
【０００７】〔文献：C.W.Pobanz and T.Itoh:“A Conf
ormal Retrodirective Array forRadar Applications U
sing a Heterodyne Phased Scattering Element,” inI
EEE MTT-S Int.Microwave Symp.Dig.,1995,pp.905-908.
参照〕[Reference: CWPobanz and T. Itoh: “A Conf
ormal Retrodirective Array for Radar Applications U
sing a Heterodyne Phased Scattering Element, ”inI
EEE MTT-S Int.Microwave Symp.Dig., 1995, pp. 905-908.
reference〕
【０００８】図４のアンテナ装置はミキサ用ダイオード
２８を用いて周波数変換すると同時に変換された信号を
ローパスフィルタ５により選択し、アンテナパッチ２６
を給電するものである。また構造的には１枚の誘電体基
板上に構成され、同一面にアンテナパッチ２６、ローパ
スフィルタ５及びバンドパスフィルタ１９を含む帯域制
限用フィルタ回路、ミキサ用ダイオード２８を配置して
構成したものである。The antenna device shown in FIG. 4 performs frequency conversion by using a mixer diode 28 and simultaneously selects a converted signal by a low-pass filter 5 and an antenna patch 26.
Power. Further, it is structurally configured on a single dielectric substrate, and has a configuration in which an antenna patch 26, a band-limiting filter circuit including the low-pass filter 5 and the band-pass filter 19, and a mixer diode 28 are arranged on the same surface. It is.
【０００９】本アンテナはミキサ回路及びフィルタ回路
と平面アンテナを組み合わせたアンテナ装置であるが、
アンテナパッチ２６からマイクロストリップ線路入出力
端１までに挿入された回路損失が比較的大きく、特に準
ミリ波・ミリ波帯においては無視できないという事情が
あった。The present antenna is an antenna device combining a mixer circuit, a filter circuit, and a planar antenna.
The circuit loss inserted from the antenna patch 26 to the microstrip line input / output terminal 1 is relatively large, and cannot be ignored especially in the quasi-millimeter wave / millimeter wave band.
【００１０】[0010]
【発明が解決使用とする課題】上述したように、従来の
アクティブアンテナは一体化するマイクロ波用集積回路
内に送受信用増幅器を具備している場合、送信時におけ
る電力飽和による他の通信システムへの影響や、受信時
におけるイメージ混信などの干渉の防止ができないとい
う問題があった。また準ミリ波・ミリ波帯においてアン
テナ装置自体にパッシブ回路のみで機能を実現すること
は回路損失の観点から不利であるという問題があった。As described above, when a conventional active antenna includes a transmission / reception amplifier in an integrated microwave integrated circuit, the conventional active antenna is connected to another communication system due to power saturation during transmission. There is a problem that it is not possible to prevent interference such as image interference at the time of reception. Also, in the quasi-millimeter-wave / millimeter-wave band, realizing the function of the antenna device itself with only the passive circuit is disadvantageous from the viewpoint of circuit loss.
【００１１】本発明は、このような従来の課題を解決す
るために成されたもので、アンテナ装置に実装されたマ
イクロ波用集積回路内に送受信用増幅器を設けても、送
信時に増幅器の非線形歪みによって生ずる高調波が他の
通信システムに影響を与えたり、受信時にイメージ混信
などの干渉を生ずることがなく、また、入出力端からア
ンテナ素子までの回路損失を低減させることのできるア
ンテナ装置の実現を目的としている。The present invention has been made to solve such a conventional problem. Even when a transmitting / receiving amplifier is provided in a microwave integrated circuit mounted on an antenna device, the nonlinearity of the amplifier during transmission is increased. An antenna device that does not cause harmonics caused by distortion to affect other communication systems, does not cause interference such as image interference at the time of reception, and can reduce circuit loss from an input / output end to an antenna element. It is aimed at realization.
【００１２】[0012]
【課題を解決するための手段】本発明によれば、上述の
目的は前記特許請求の範囲に記載した手段により解決さ
れる。According to the present invention, the above objects are solved by the means as set forth in the appended claims.
【００１３】すなわち、請求項１の発明は、誘電体基板
上に、平面構造のアンテナ又はアンテナアレーを形成せ
しめると共に、マイクロ波用集積回路を実装したアクテ
ィブアンテナにおいて、誘電体基板の面に、帯域制限用
フィルタ回路を形成せしめ、前記マイクロ波用集積回路
に、増幅器と移相器の内の少なくとも一方からなる回路
を、送信用と受信用の２系統設けると共に、That is, according to the first aspect of the present invention, an antenna or an antenna array having a planar structure is formed on a dielectric substrate, and an active antenna on which a microwave integrated circuit is mounted is provided with a band on a surface of the dielectric substrate. A limiting filter circuit is formed, and the microwave integrated circuit is provided with a circuit including at least one of an amplifier and a phase shifter, two systems for transmission and reception,
【００１４】該２系統の内のいずれの系統に接続するか
を切り替える切替回路を設け、前記アンテナ又はアンテ
ナアレーが、前記帯域制限用フィルタ回路を介して前記
マイクロ波用集積回路の切替回路に接続されるよう、電
気的又は電磁的結合によって、接続したアンテナ装置で
ある。A switching circuit for switching to which of the two systems a connection is provided, wherein the antenna or the antenna array is connected to the switching circuit of the microwave integrated circuit via the band-limiting filter circuit; Antenna devices connected by electrical or electromagnetic coupling as shown in FIG.
【００１５】請求項２の発明は、上記請求項１記載のア
ンテナ装置において、誘電体基板を、複数の誘電体板を
積層して多層誘電体基板として構成したものである。According to a second aspect of the present invention, in the antenna device according to the first aspect, the dielectric substrate is configured as a multilayer dielectric substrate by laminating a plurality of dielectric plates.
【００１６】請求項３の発明は、請求項１記載のアンテ
ナ装置において、帯域制限用フィルタ回路を、多層誘電
体基板を用いて構成したものである。According to a third aspect of the present invention, in the antenna device of the first aspect, the band-limiting filter circuit is configured using a multilayer dielectric substrate.
【００１７】請求項４の発明は、上記請求項１〜請求項
３のいずれか１項に記載のアンテナ装置において、帯域
制限用フィルタ回路を、マイクロストリップ線路又はコ
プレーナ線路又はストリップ線路で構成したものであ
る。According to a fourth aspect of the present invention, in the antenna device according to any one of the first to third aspects, the band-limiting filter circuit is constituted by a microstrip line, a coplanar line, or a strip line. It is.
【００１８】請求項５の発明は、前記請求項２〜請求項
４のいずれか１項に記載のアンテナ装置において、帯域
制限用フィルタ回路を、複数の誘電体板の層間を接続す
るビアホール又はスルーホールと少なくとも一つの上記
誘電体板に設けられた導体面との間に生じるキャパシタ
を用いて構成したものである。According to a fifth aspect of the present invention, in the antenna device according to any one of the second to fourth aspects, the band-limiting filter circuit includes a via hole or a through hole for connecting between a plurality of dielectric plates. It is configured using a capacitor generated between the hole and a conductor surface provided on at least one of the dielectric plates.
【００１９】請求項６の発明は、前記請求項２〜請求項
５のいずれか１項に記載のアンテナ装置において、誘電
体基板として、アルミナ−セラミック等の比誘電率がほ
ぼ６から９の第１の基板と、ポリイミド等の比誘電率が
前記第１の基板よりも小さくほぼ１から３の第２の基板
とを組み合わせた多層誘電体基板を用いたものである。According to a sixth aspect of the present invention, in the antenna device according to any one of the second to fifth aspects, the dielectric substrate has a relative dielectric constant of approximately 6 to 9 such as alumina-ceramic. A multi-layer dielectric substrate is used in which one substrate is combined with a second substrate having a relative permittivity of about 1 to 3 which is smaller than that of the first substrate, such as polyimide.
【００２０】本発明は上述のような構成の内、アンテナ
回路に帯域制限用フィルタ回路を挿入するという構成及
びアンテナ装置に実装するマイクロ波用集積回路内に送
受両系の増幅器（移相器）とそれらを切り替える切替回
路を設けるという構成によって、送信に際する高調波の
アンテナ回路等への漏洩及び受信に際してのアンテナ系
を経由する干渉波などによる影響を大幅に低減させるこ
とが可能となる。According to the present invention, there is provided a configuration in which a band-limiting filter circuit is inserted into an antenna circuit in the above-described configuration, and a transmission / reception amplifier (phase shifter) in a microwave integrated circuit mounted on an antenna device. And a switching circuit for switching between them, it is possible to greatly reduce the leakage of harmonics to an antenna circuit or the like at the time of transmission and the influence of interference waves passing through an antenna system at the time of reception.
【００２１】また、その構造上アンテナ又はアンテナア
レーと、帯域制限用フィルタ回路と、マイクロ波用集積
回路とが密接して配設されているので、その間を非常に
短い経路で電気的あるいは電磁的結合によって接続する
ことが可能である。そのため、入出力端からアンテナ素
子までの損失を非常に少なくすることができると共に、
同時に、これらの回路からの高調波の漏洩や、これらの
回路自身が受ける干渉波の影響を低減することができ
る。Further, since the antenna or the antenna array, the band-limiting filter circuit, and the microwave integrated circuit are closely arranged due to their structure, they can be electrically or electromagnetically routed through a very short path therebetween. It is possible to connect by coupling. Therefore, while the loss from the input / output end to the antenna element can be extremely reduced,
At the same time, it is possible to reduce the leakage of harmonics from these circuits and the effect of interference waves on these circuits.
【００２２】[0022]
【発明の実施の形態】図１は本発明の実施の形態の第一
の例を示す図であって、数字符号１はマイクロストリッ
プ線路入出力端、２はワイヤーボンディング、３はマイ
クロ波用集積回路、４は線路給電マイクロストリップア
ンテナ、５はローパスフィルタ回路、６はマイクロスト
リップ線路、７はビアホール、８は地板、９は高周波回
路用誘電体基板、１０はアンテナ用誘電体基板、１１は
入出力端子、１２はマイクロ波用集積回路ブロック、１
３はアンテナ装置、１４はＴＤＤスイッチ、１５は送信
用増幅器、１６は受信用増幅器、１７は帯域制限用フィ
ルタ、１８は素子アンテナを示している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a first embodiment of the present invention, in which numeral 1 denotes a microstrip line input / output terminal, 2 denotes wire bonding, and 3 denotes an integrated microwave. Circuit, 4 is a line-fed microstrip antenna, 5 is a low-pass filter circuit, 6 is a microstrip line, 7 is a via hole, 8 is a ground plane, 9 is a high-frequency circuit dielectric substrate, 10 is an antenna dielectric substrate, and 11 is an input. Output terminal, 12 is a microwave integrated circuit block, 1
Reference numeral 3 denotes an antenna device, 14 denotes a TDD switch, 15 denotes a transmission amplifier, 16 denotes a reception amplifier, 17 denotes a band limiting filter, and 18 denotes an element antenna.
【００２３】同図（ａ）はアンテナ装置を上面から見た
図を示したものであり、同図（ｂ）は図（ａ）中に記し
たＡ−Ａの線に沿った断面図を示している。また、同図
（ｃ）は本アンテナ装置の機能ブロック図を示してい
る。本アンテナは、それぞれ４層の多層基板からなる異
なる２種の、例えばポリイミド基板とアルミナ−セラミ
ック基板を組み合わせた全８層からなる多層基板上に構
成した場合を示したものである。FIG. 2A is a view of the antenna device as viewed from above, and FIG. 2B is a cross-sectional view taken along the line AA shown in FIG. ing. FIG. 1C shows a functional block diagram of the present antenna device. This antenna shows a case where the antenna is formed on a multilayer substrate composed of a total of eight layers obtained by combining a polyimide substrate and an alumina-ceramic substrate.
【００２４】本構成は送受２系統の増幅器と移相器の内
のいずれか一方又は、その両方、及び送受２系統を切り
替える切替回路とを具備したマイクロ波用集積回路３と
平面構造アンテナとを２種の誘電体のそれぞれ背向かい
に構成し、またそれらの中間層にストリップ線路により
ローパスフィルタ回路５を構成した例を示している。In this configuration, a microwave integrated circuit 3 having one or both of an amplifier and a phase shifter of two transmission / reception systems and a switching circuit for switching the two transmission / reception systems and a planar structure antenna are used. An example is shown in which two types of dielectrics are configured to face each other, and a low-pass filter circuit 5 is configured by a strip line in an intermediate layer between them.
【００２５】また、本実施例では、マイクロ波用集積回
路３と高周波回路用誘電体基板９上の線路との接続にワ
イヤーボンディング２を用いた例を示したものである
が、その他の方法としてバンプを用いることも考えられ
る。In this embodiment, an example is shown in which the wire bonding 2 is used to connect the microwave integrated circuit 3 and the line on the high-frequency circuit dielectric substrate 9. It is also conceivable to use bumps.
【００２６】本構成のアンテナ装置はマイクロ波用集積
回路３と線路給電マイクロストリップアンテナ４間にロ
ーパスフィルタ回路５を内蔵しているため、マイクロ波
用集積回路３に内蔵された送信用増幅器１５の非直線歪
みなどにより放出される高調波を減衰することができ
る。Since the antenna device of this configuration incorporates the low-pass filter circuit 5 between the microwave integrated circuit 3 and the line feed microstrip antenna 4, the transmission amplifier 15 incorporated in the microwave integrated circuit 3 Harmonics emitted due to non-linear distortion or the like can be attenuated.
【００２７】従って、用いる増幅器の直線性に対する要
求性能を低くすることが可能となる。また、故障等によ
り増幅器が誤動作した場合においても、他の通信システ
ムに対する影響を最小限に留めることができる。Therefore, it is possible to lower the required performance for the linearity of the amplifier used. Further, even when the amplifier malfunctions due to a failure or the like, the influence on other communication systems can be minimized.
【００２８】また、本構造のアンテナ装置は多層基板中
に素子アンテナ及び高周波回路を構成しているため、図
４に示したような同一平面に構成したアンテナ装置に比
べ、小型化が実現できる。従って、線路長も短くて済む
ため線路による損失を抑えることができる。Further, since the antenna device having the present structure includes the element antenna and the high-frequency circuit in the multilayer substrate, the antenna device can be downsized compared to the antenna device configured on the same plane as shown in FIG. Accordingly, since the line length can be reduced, the loss due to the line can be suppressed.
【００２９】図２は本発明の実施の形態の第二の例を示
す図である。この例はアンテナ素子と帯域制限用フィル
タ回路とを電磁的に接続している。同図において、数字
符号１はマイクロストリップ線路入出力端、２はワイヤ
ーボンディング、３はマイクロ波用集積回路、６はマイ
クロストリップ線路、７はビアホール、８は地板、９は
高周波回路用誘電体基板、１０はアンテナ用誘電体基
板、１１は入出力端子、１２はマイクロ波用集積回路ブ
ロック、１３はアンテナ装置、１４はＴＤＤスイッチ、
１５は送信用増幅器、１６は受信用増幅器、１７は帯域
制限用フィルタ回路、１８は素子アンテナ、１９はバン
ドパスフィルタ回路、２０は励振用スタブ、２１はスロ
ットであり、２２はスロット給電マイクロストリップア
ンテナを示している。FIG. 2 is a diagram showing a second example of the embodiment of the present invention. In this example, an antenna element and a band limiting filter circuit are electromagnetically connected. In the figure, numeral 1 denotes a microstrip line input / output terminal, 2 denotes wire bonding, 3 denotes a microwave integrated circuit, 6 denotes a microstrip line, 7 denotes a via hole, 8 denotes a ground plane, and 9 denotes a high-frequency circuit dielectric substrate. 10, a dielectric substrate for an antenna, 11 an input / output terminal, 12 an integrated circuit block for microwaves, 13 an antenna device, 14 a TDD switch,
15 is a transmitting amplifier, 16 is a receiving amplifier, 17 is a band limiting filter circuit, 18 is an element antenna, 19 is a band pass filter circuit, 20 is an excitation stub, 21 is a slot, and 22 is a slot-fed microstrip. Shows the antenna.
【００３０】同図（ａ）はアンテナ装置を上面から見た
図を示したものであり、同図（ｂ）は図（ａ）中に記し
たＡ−Ａの線に沿った断面図を示したものである。ま
た、同図（ｃ）は本アンテナ装置の機能ブロック図を示
したものである。本アンテナ構成はそれぞれ４層の多層
基板からなる異なる２種の、例えば、ポリイミド基板と
アルミナ−セラミック基板を組み合わせた全８層からな
る多層基板上に構成した場合を示している。FIG. 3A is a diagram showing the antenna device as viewed from above, and FIG. 3B is a cross-sectional view taken along the line AA shown in FIG. It is a thing. FIG. 1C shows a functional block diagram of the present antenna device. The present antenna configuration shows a case where the antenna is formed on two different types of multilayer substrates each having four layers, for example, a multilayer substrate having a total of eight layers obtained by combining a polyimide substrate and an alumina-ceramic substrate.
【００３１】本構成は送受２系統の増幅器と移相器の内
のいずれか一方、又はその両方、及び送受２系統を切り
替える切替回路とを具備したマイクロ波用集積回路３と
平面構造アンテナとを２種の誘電体の背向かいに構成
し、また、マイクロ波用集積回路３と同一基板面にマイ
クロストリップ線路による構成したオープンスタブを用
いたカップラー回路を組み合わせたバンドパスフィルタ
回路１９を配置した例を示している。In this configuration, the microwave integrated circuit 3 having one or both of an amplifier and a phase shifter of two transmission / reception systems and a switching circuit for switching the two transmission / reception systems and a planar structure antenna are used. An example in which a band-pass filter circuit 19 configured opposite to two types of dielectrics, and a coupler circuit using an open stub configured by a microstrip line is arranged on the same substrate surface as the microwave integrated circuit 3. Is shown.
【００３２】この例では、マイクロ波用集積回路３と高
周波回路用誘電体基板９上の線路との接続にワイヤーボ
ンディング２を用いた例を示しているが、その他の方法
としてバンプを用いることも考えられる。In this example, the wire bonding 2 is used to connect the microwave integrated circuit 3 and the line on the high frequency circuit dielectric substrate 9, but bumps may be used as another method. Conceivable.
【００３３】本構成のアンテナ装置はマイクロ波用集積
回路３とスロット給電マイクロストリップアンテナ２２
間にバンドパスフィルタ回路１９を内蔵しているため、
マイクロ波用集積回路３に内蔵された送信用増幅器１５
の非直線歪みなどにより放出される高調波を減衰するこ
とができるため、用いる増幅器の直線性に対する要求性
能を低くすることが可能となる。The antenna device of this configuration comprises a microwave integrated circuit 3 and a slot-fed microstrip antenna 22.
Since the band-pass filter circuit 19 is built in between,
Transmission amplifier 15 built in microwave integrated circuit 3
Since harmonics emitted due to non-linear distortion can be attenuated, it is possible to reduce the required performance of the amplifier used for linearity.
【００３４】また受信時には近接周波数を用いた通信シ
ステムの電磁波による電力飽和を防止することができ
る。さらに故障等により送信用増幅器１５が誤動作した
場合においても、他の通信システムに対する影響を最小
限に留めることができる。Further, at the time of reception, it is possible to prevent power saturation due to electromagnetic waves of a communication system using a close frequency. Furthermore, even when the transmission amplifier 15 malfunctions due to a failure or the like, the influence on other communication systems can be minimized.
【００３５】また、本構造のアンテナ装置は多層基板中
に素子アンテナ及び高周波回路を構成しているため、図
４に示したような同一平面に構成したアンテナ装置に比
べ、小型化が実現できる。従って、線路長も短くて済む
ため線路による損失を抑えることができる。Further, since the antenna device of the present structure includes the element antenna and the high-frequency circuit in the multilayer substrate, it is possible to realize a smaller size than the antenna device configured on the same plane as shown in FIG. Accordingly, since the line length can be reduced, the loss due to the line can be suppressed.
【００３６】上記実施の形態の例では、いずれも誘電体
基板は、複層のポリイミド基板と複層のアルミナ−セラ
ミック基板などからなる多層誘電体基板を用いる例を示
しているが、本発明は、これに限るものではなく、一枚
の誘電体基板あるいは、一種類の材質の誘電体板を積層
した誘電体基板を用いても、本発明のアンテナ装置を実
現できるものであることはいうまでもない。In each of the above embodiments, the dielectric substrate is a multilayer dielectric substrate comprising a multilayer polyimide substrate and a multilayer alumina-ceramic substrate. However, the present invention is not limited to this, and it goes without saying that the antenna device of the present invention can be realized even by using a single dielectric substrate or a dielectric substrate obtained by laminating dielectric plates of one type of material. Nor.
【００３７】[0037]
【発明の効果】以上説明したように、本発明のアンテナ
装置は、帯域制限用フィルタ回路を内蔵しているので、
送信用増幅器の非直線歪みによる影響を低減することが
できる。また、送信用増幅器自体の非直線歪み特性を追
求する必要がないため、電力効率の良い増幅器を使用で
きる。As described above, since the antenna device of the present invention has a built-in band-limiting filter circuit,
The effect of the nonlinear distortion of the transmission amplifier can be reduced. Further, since it is not necessary to pursue the nonlinear distortion characteristic of the transmission amplifier itself, an amplifier with high power efficiency can be used.
【００３８】更に、同一基板内にフィルタ回路を構成し
ているから素子アンテナと能動素子を最短の経路で接続
することができる。これにより、接続経路の損失を最小
限に抑えることができる。これによって、送信時におい
ては増幅器の線形性に対する要求が軽減され、また、受
信時においては低雑音特性を実現することが可能とな
る。Further, since the filter circuit is formed on the same substrate, the element antenna and the active element can be connected by the shortest path. Thereby, the loss of the connection path can be minimized. Thereby, the requirement for the linearity of the amplifier is reduced during transmission, and low noise characteristics can be realized during reception.
【００３９】前記帯域制限用フィルタ回路を、マイクロ
ストリップ線路又はコプレーナ線路又はストリップ線路
で構成した場合には、フィルタ回路を多層基板の内の一
部の層に配置が可能となる。これにより、アンテナ装置
サイズを増加させるなく、フィルタ回路を内蔵すること
ができる。When the band-limiting filter circuit is constituted by a microstrip line, a coplanar line, or a strip line, the filter circuit can be arranged on a part of the layers of the multilayer substrate. Thus, the filter circuit can be built in without increasing the size of the antenna device.
【００４０】前記帯域制限用フィルタ回路を複数の層間
を接続するビアホール又はスルーホールと複数の層間で
構成したキャパシタを用いて構成し場合には、帯域制限
用フィルタ回路を構成するために特別な層を用意するこ
となく、素子アンテナと高周波回路間を最短で配置する
ことができる。これにより、低損失なフィルタ回路一体
型アンテナが構成できる。When the band-limiting filter circuit is formed by using a via hole or a through-hole connecting a plurality of layers and a capacitor formed between the plurality of layers, a special layer is formed to constitute the band-limiting filter circuit. , The element antenna and the high-frequency circuit can be arranged in the shortest distance. Thus, a low-loss antenna integrated with a filter circuit can be configured.
【００４１】前記誘電体基板にアルナミ−セラミック等
の比誘電率が、ほぼ、６から９の第１の基板と、ポリイ
ミド等の比誘電率が前記第１の基板よりも小さく、ほ
ぼ、１から３の第２の基板を組み合わせた多層誘電体基
板を用いる構成とした場合には、高周波回路を３次元構
造高周波回路を、構成しやすいポリイミド基板等の側に
構成し、誘電率の高いアルミナ−セラミック基板等にア
ンテナを構成することで、アンテナ形状を小さくでき
る。これにより、設計の自由度を落とすことなく、特性
の良い高周波回路とアンテナを設計することができる。The dielectric substrate has a relative dielectric constant of Alnami-ceramic or the like of about 6 to 9, and a first substrate of polyimide or the like having a relative dielectric constant smaller than that of the first substrate. In the case of using a multi-layer dielectric substrate in which the second substrate is combined with the third substrate, a high-frequency circuit is formed by forming a three-dimensional high-frequency circuit on a polyimide substrate or the like, which is easy to configure, and by using an alumina having a high dielectric constant. By forming the antenna on a ceramic substrate or the like, the antenna shape can be reduced. As a result, a high-frequency circuit and an antenna having good characteristics can be designed without lowering the design flexibility.
【図１】本発明の実施の形態の第一の例を示す図であ
る。FIG. 1 is a diagram showing a first example of an embodiment of the present invention.
【図２】本発明の実施の形態の第二の例を示す図であ
る。FIG. 2 is a diagram showing a second example of the embodiment of the present invention.
【図３】従来の能動素子一体化アンテナの構成の例を示
す図である。FIG. 3 is a diagram illustrating an example of a configuration of a conventional active element integrated antenna.
【図４】従来の半導体デバイスと平面アンテナの一体化
構成の例を示す図である。FIG. 4 is a diagram showing an example of a conventional integrated configuration of a semiconductor device and a planar antenna.
１ マイクロストリップ線路入出力端 ２ ワイヤーボンディング ３ マイクロ波用集積回路 ４ 線路給電マイクロストリップアンテナ ５ ローパスフィルタ回路 ６ マイクロストリップ線路 ７ ビアホール ８ 地板 ９ 高周波回路用誘電体基板 １０ アンテナ用誘電体基板 １１ 入出力端子 １２ マイクロ波用誘電体基板 １３ アンテナ装置 １４ ＴＤＤスイッチ １５ 送信用増幅器 １６ 受信用増幅器 １７ 帯域制限用フィルタ回路 １８ 素子アンテナ １９ バンドパスフィルタ回路 ２０ 励振用スタブ ２１ スロット ２２ スロット給電マイクロストリップアンテナ ２３ ポリイミド基板 ２４ アルミナ−セラミック基板 ２５ ストリップ線路 ２６ アンテナパッチ ２７ ラットレース回路 ２８ ダイオード DESCRIPTION OF SYMBOLS 1 Microstrip line input / output end 2 Wire bonding 3 Microwave integrated circuit 4 Line feeding microstrip antenna 5 Low pass filter circuit 6 Microstrip line 7 Via hole 8 Ground plane 9 High frequency circuit dielectric substrate 10 Antenna dielectric substrate 11 Input / output Terminal 12 Dielectric substrate for microwave 13 Antenna device 14 TDD switch 15 Transmitting amplifier 16 Receiving amplifier 17 Band limiting filter circuit 18 Element antenna 19 Band pass filter circuit 20 Exciting stub 21 Slot 22 Slot feeding microstrip antenna 23 Polyimide Substrate 24 Alumina-ceramic substrate 25 Strip line 26 Antenna patch 27 Rat race circuit 28 Diode
───────────────────────────────────────────────────── フロントページの続き (72)発明者 中津川 征士 東京都新宿区西新宿三丁目19番２号 日本 電信電話株式会社内 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Seiji Nakatsugawa Nippon Telegraph and Telephone Corporation, 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo
Claims (6)
はアンテナアレーを形成せしめると共に、マイクロ波用
集積回路を実装したアクティブアンテナにおいて、 誘電体基板の面に、帯域制限用フィルタ回路を形成せし
め、 前記マイクロ波用集積回路に、増幅器と移相器の内の少
なくとも一方からなる回路を、送信用と受信用の２系統
設けると共に、該２系統の内のいずれの系統に接続する
かを切り替える切替回路を設け、 前記アンテナ又はアンテナアレーが、前記帯域制限用フ
ィルタ回路を介して前記マイクロ波用集積回路の切替回
路に接続されるよう、電気的又は電磁的結合によって、
接続したことを特徴とするアンテナ装置。An antenna or antenna array having a planar structure is formed on a dielectric substrate, and a band limiting filter circuit is formed on a surface of the dielectric substrate in an active antenna having a microwave integrated circuit mounted thereon. In the microwave integrated circuit, two circuits for transmitting and receiving are provided with at least one of an amplifier and a phase shifter, and the connection to which of the two systems is switched. Provide a switching circuit, such that the antenna or antenna array is connected to the switching circuit of the microwave integrated circuit through the band-limiting filter circuit, by electrical or electromagnetic coupling,
An antenna device which is connected.
て多層誘電体基板として構成したものである請求項１記
載のアンテナ装置。2. The antenna device according to claim 1, wherein the dielectric substrate is configured as a multilayer dielectric substrate by laminating a plurality of dielectric plates.
基板を用いて構成したものである請求項１記載のアンテ
ナ装置。3. The antenna device according to claim 1, wherein the band-limiting filter circuit is configured using a multilayer dielectric substrate.
トリップ線路又はコプレーナ線路又はストリップ線路で
構成した請求項１〜請求項３のいずれか１項に記載のア
ンテナ装置。4. The antenna device according to claim 1, wherein the band-limiting filter circuit comprises a microstrip line, a coplanar line, or a strip line.
体板の層間を接続するビアホール又はスルーホールと少
なくとも一つの上記誘電体板に設けられた導体膜との間
に生じるキャパシタを用いて構成した請求項２〜請求項
４のいずれか１項に記載のアンテナ装置。5. A band limiting filter circuit comprising a capacitor formed between a via hole or a through hole connecting between layers of a plurality of dielectric plates and a conductor film provided on at least one of the dielectric plates. The antenna device according to any one of claims 2 to 4, wherein:
ク等の比誘電率がほぼ６から９の第１の基板と、ポリイ
ミド等の比誘電率が前記第１の基板よりも小さくほぼ１
から３の第２の基板とを組み合わせた多層誘電体基板を
用いた請求項２〜請求項５のいずれかに１項に記載のア
ンテナ装置。6. A dielectric substrate comprising a first substrate such as alumina-ceramic having a relative dielectric constant of approximately 6 to 9, and a polyimide having a relative dielectric constant of approximately 1 to 9 which is smaller than that of the first substrate.
The antenna device according to any one of claims 2 to 5, wherein a multilayer dielectric substrate obtained by combining the second and third substrates is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9108741A JPH10303640A (en) | 1997-04-25 | 1997-04-25 | Antenna system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9108741A JPH10303640A (en) | 1997-04-25 | 1997-04-25 | Antenna system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10303640A true JPH10303640A (en) | 1998-11-13 |
Family
ID=14492350
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9108741A Pending JPH10303640A (en) | 1997-04-25 | 1997-04-25 | Antenna system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10303640A (en) |
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