JP2007012035A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stop operation of an RFID chip after a product is purchased, and prevent the change of data of the RFID chip at that time point because there is a possibility that what is purchased is read by a RFID reader/writer when finishing shopping and leaving a shop when an RFID is used for product management, and under such a condition, it is preferable that the RFID does not execute a request even when a writing request or reading request is sent from the RFID reader/writer. <P>SOLUTION: When an operation-stop instruction is received from the RFID reader/writer, the RFID chip decodes the instruction by a control circuit and executes the operation-stop instruction. In addition, the RFID chip uses a register which has a write-once function such as an organic memory and does not return to an original state physically if a value is written once as a register which maintains a setting whether to conduct operation-stop or not. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a semiconductor device using RFID (Radio Frequency Identification) technology having an operation stop function.

In recent years, RFID has become widespread and is used for merchandise management, transportation tickets, cash cards, and the like.

When used for merchandise management, it becomes possible to manage the inventory status of merchandise more easily, or to store detailed information on merchandise in RFID and view it on a terminal in the store. This makes it possible to provide high quality services. It is also used to prevent shoplifting.

In the case where RFID is used for the cash card function, it has been necessary to carry the cash and carry out the complicated work of paying the cash at the cash register, but it is possible to carry the cash register just by carrying one card. As described above, the RFID brings convenience to life, but also has a demerit due to the characteristic of wireless communication.

For example, in the case where RFID is used for merchandise management, there is a possibility that what has been bought is read by the RFID reader / writer after finishing shopping and leaving the store. Since it is wireless in this way, there is a possibility that other people can read their information without noticing it.

Further, when an RFID holding important personal information such as a credit card is lost, there is a possibility that information held inside the credit card can be seen by others. Under such conditions, it is desirable that the RFID does not execute the request even if a write request or read request is sent from the RFID reader / writer.

As in the above example, the possibility of RFID being abused by a malicious person needs to be avoided as a whole system of RFID.

From such a background, it has been proposed to stop the operation of the RFID chip after purchasing a product (see Non-Patent Document 1).
"Challenges for IC tag leap", Nikkei Byte magazine (published by Nikkei BP), May 2003, 78 pages

As described above, when the RFID chip receives a command to stop the operation, it is necessary to keep the information to stop the operation from that point.

The RFID chip used for the distribution of merchandise is basically a passive chip that does not have a power supply itself and generates power from a magnetic field generated by the RFID reader / writer. For this reason, it is necessary to maintain information even when there is no power source.

For this reason, a method of maintaining the state with an EEPROM or the like is conceivable. However, a high voltage is required to write a value to the EEPROM, and a large booster circuit is required only to stop the operation.

Since the EEPROM is basically rewritable, there is a physical possibility that the operation stop state is released.

Therefore, an object of the present invention is to efficiently mount a register holding an operation stop setting on an RFID chip, which does not physically cause the possibility of canceling the operation stop function.

The present invention has been made in view of the above problems. When it is determined that an RFID does not need to accept a request from a reader / writer as a system in consideration of the existence of an attacker to the RFID system, It is characterized by having a safety mechanism that can put the RFID into an operation stop state.

The RFID system using the RFID chip of the present invention has an operation stop command in the command set.

The RFID chip of the present invention has a memory circuit, and a register for holding a setting for stopping operation in the memory circuit.

When the RFID chip of the present invention receives an operation stop command from the RFID reader / writer, the control circuit decodes the command and executes the operation stop command. At this time, the control circuit writes the operation stop value in a register holding the operation stop setting.

The RFID chip of the present invention has a write-once function such as an organic memory in a register that holds the setting of whether or not to stop the operation, and uses a register that does not physically return to the original state once a value is written. .

For this reason, the operation can be stopped more reliably as compared with the case where a rewritable memory such as an EEPROM is used without the possibility of returning to a physically operable state.

The specific configuration of the present invention is shown below.

The semiconductor device of the present invention includes an antenna, a memory cell, and a control circuit. The memory cell includes a memory material layer between electrodes provided to face each other, and the control circuit receives from the antenna. The instruction is stored as data in the memory cell by changing the physical characteristics of the memory cell, and the physical characteristics of the memory cell do not change reversibly.

The semiconductor device of the present invention includes an antenna, a memory circuit including a memory cell array having a plurality of memory cells, and a control circuit, and the memory cell array includes a plurality of bit lines extending in a first direction. A plurality of word lines extending in a direction perpendicular to the first direction, and memory cells are respectively formed at intersections between the bit lines and the word lines, and a memory cell is formed between the bit lines and the word lines of the memory cells. Having a material layer, the control circuit has means for storing the command received from the antenna as data by changing the physical characteristics of the memory cell, and the physical characteristics of the memory cell do not change reversibly.

In the semiconductor device of the present invention having the above structure, the command stops the operation of the semiconductor device.

In addition, a semiconductor device of the present invention includes a circuit having an antenna, a memory circuit having a ROM and a RAM, a receiving circuit for storing a command received from the antenna as data in the RAM, and an antenna for data taken from the RAM A ROM having a memory cell, a memory cell having a memory material layer between opposing electrodes, and the control circuit having an antenna The memory cell has means for reading the data from the RAM in which the operation stop command received from the memory is stored as data and storing the data in the memory cell by changing the physical characteristics of the memory cell. The memory cell has reversible physical characteristics. Does not change.

In addition, a semiconductor device of the present invention includes a circuit having an antenna, a memory circuit having a ROM and a RAM, a receiving circuit for storing a command received from the antenna as data in the RAM, and an antenna for data taken from the RAM A ROM including a memory cell array having a plurality of memory cells, the memory cell array including a plurality of bit lines extending in a first direction; A plurality of word lines extending in a direction perpendicular to the direction, memory cells are formed at the intersections between the bit lines and the word lines, and a memory material layer is provided between the bit lines and the word lines of the memory cells. The control circuit reads the data from the RAM in which the operation stop command received from the antenna is stored as data, and changes the physical characteristics of the memory cell. And means for storing the data in the memory cell by Rukoto, memory cells are physical properties do not change reversibly.

In the semiconductor device of the present invention having the above structure, the operation stop command stops the operation of the control circuit.

In the semiconductor device of the present invention having the above structure, the physical characteristics of the memory cell change due to an electrical action, an optical action, or a thermal action on the memory material layer.

In the semiconductor device of the present invention having the above structure, the physical characteristic is a resistance characteristic.

In the semiconductor device of the present invention having the above structure, an inorganic material is used for the memory material layer.

In the semiconductor device of the present invention having the above structure, an organic material is used for the memory material layer.

In the semiconductor device of the present invention having the above structure, a light emitting material is used for the memory material layer.

In the semiconductor device of the present invention having the above structure, the memory material layer includes a metal oxide.

The communication distance of RFID tends to become larger due to recent technological innovation, and it is easily imagined that it will become even larger in the future. As a result, new usage appears and life becomes more and more convenient. On the other hand, as the communication distance increases, it becomes necessary to take into account the negative side as well as the positive side.

According to the present invention, it is possible to design a system in consideration of the presence of an attacker with respect to an RFID system, and it is possible to provide a safer and more secure RFID system with a simpler and more reliable method.

Embodiments of the present invention will be described below with reference to the drawings.
However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.
Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, a structure of an RFID chip is described. A device using a semiconductor element such as an RFID chip of the present invention can also be called a semiconductor device.

As shown in FIG. 1, the RFID chip 101 of the present invention includes a control circuit 102, a memory circuit 103, a receiving circuit 104, a transmitting circuit 105, and an RF circuit 106. The memory circuit 103 includes a RAM (Random Access Memory) 110 and a ROM (Read Only Memory) 111. The RAM 110 includes a data register 120 configured by SRAM or the like, and a standby register 121. The ROM 111 has an operation stop register 122 composed of a memory element such as a write-once memory, RFID-specific information, a program used in a control circuit, and the like. The RF circuit 106 includes a resonance circuit 113, a power supply circuit 114, a clock generation circuit 115, a demodulation circuit 116, and a modulation circuit 117. The RFID chip 101 is not limited to the above configuration, and may have a congestion control circuit or the like. The resonant circuit 113 has an antenna. Further, a capacitor may be provided in the resonance circuit 113 so as to resonate with the antenna and the capacitor.

In the RFID chip 101 of the present invention, when the resonance circuit 113 receives a radio wave emitted from the antenna 131 of the RFID reader / writer 130, a power supply potential is generated by the power supply circuit 114. Further, the demodulation circuit 116 demodulates information from the received radio wave. Information is transmitted by the modulation circuit 117. In this manner, information can be transmitted / received to / from the RFID reader / writer 130 by wireless communication.

The antenna 131 of the RFID reader / writer is connected to the information processing device 132 via the communication line 133, and can transmit / receive information to / from the RFID chip 101 under the control of the information processing device 132. Note that the antenna 131 and the information processing apparatus 132 may exchange information through wireless communication such as infrared communication.

The resonance circuit 113 receives radio waves emitted from the antenna 131 of the RFID reader / writer, and generates an AC signal at both ends of the antenna of the resonance circuit 113. The generated AC signal becomes the power of the RFID chip 101 and includes information such as a command transmitted from the antenna 131 of the RFID reader / writer. The power supply circuit 114 rectifies the AC signal generated in the resonance circuit 113 with a diode and smoothes it using a capacitor, thereby generating a power supply potential and supplying it to each circuit. The clock generation circuit 115 generates clock signals having various frequencies based on the AC signal generated in the resonance circuit 113. The demodulating circuit 116 demodulates information included in the AC signal generated in the resonant circuit.

The reception circuit 104 receives the data demodulated by the demodulation circuit 116 and writes the data in the data register 120. When the writing is completed, 1 is written to the standby register 121. The control circuit 102 starts operation when the receiving circuit 104 writes 1 to the standby register. The control circuit 102 analyzes the instruction from the data received from the data register and executes a series of operations according to the instruction. Further, a circuit for checking whether the demodulated signal has an error may be provided. Next, a write command is sent to the data register 120, data of the operation result based on the command is stored in the data register 120, and then 1 is written to the standby register 121. The control circuit 102 can send a read command to the memory circuit 103 to read data. The transmission circuit 105 receives data from the data register and outputs it to the modulation circuit 117 when the control circuit 102 writes 1 to the standby register 121.

The operation stop register 122 is provided with a write-once memory. When the control circuit 102 starts operation, the control circuit 102 always checks the value of the operation stop register 122. When the value of the operation stop register 122 is 0, the control circuit 102 starts processing. When the value of the operation stop register 122 is 1, the control circuit 102 stops processing.

The data register 120 and the standby register 121 are provided with rewritable memories such as SRAM. A rewritable nonvolatile memory may be provided as necessary.

Although this embodiment mode shows an example in which the RFID chip 101 receives power supply from the antenna 131 of the RFID reader / writer 130, the present invention is not limited to this mode. For example, the RFID chip 101 can supply power with a battery or the like inside, and can also only transmit and receive information wirelessly with the antenna 131 of the RFID reader / writer 130.

(Embodiment 2)
In this embodiment, a normal operation of the RFID chip 101 will be described.

The RFID chip 101 receives the instruction by the RF circuit 106, demodulates it, and sends it to the receiving circuit 104. The receiving circuit 104 writes the demodulated data to the data register 120 in the memory circuit 103, and then writes 1 to the standby register 121 to indicate that the data writing has been completed. The control circuit 102 confirms the value of the operation stop register 122 when the reception circuit 104 confirms that writing to the standby register 121 is completed.

The control circuit 102 confirms that the value of the operation stop register 122 is 0, and starts reading from the data register 120. At this time, the control circuit 102 analyzes the instruction from the read data and executes the instruction. Then, the result is written into the data register 120, and when all the values have been written, the value is written into the standby register 121. The transmission circuit 105 confirms that the control circuit 102 has written a value to the standby register 121, fetches data from the data register, and transmits it to the RF circuit 106. The RF circuit 106 modulates the data received from the transmission circuit 105, places the data on the antenna of the RF circuit, and transmits the data to the RFID reader / writer.

(Embodiment 3)
For example, when RFID is used for merchandise management, the information held in the RFID chip 101 may not be necessary when the customer purchases the merchandise. In this embodiment, when a product is purchased, an operation stop command is sent from the RFID reader / writer 130 to the RFID chip 101, and after that, even if any command is received from the RFID reader / writer, no response is made. explain.

The RFID chip 101 receives the operation stop command by the RF circuit 106, demodulates it, and sends it to the receiving circuit 104. The receiving circuit 104 writes the demodulated data to the data register 120 in the memory circuit 103, and then writes 1 to the standby register 121 to indicate that the data writing has been completed. The control circuit 102 confirms the value of the operation stop register 122 when the reception circuit 104 confirms that writing to the standby register 121 is completed.

The control circuit 102 confirms that the value of the operation stop register 122 is 0, and starts reading from the data register 120. At this time, the control circuit 102 analyzes from the read data that it is an operation stop command, and writes the value 1 to the operation stop register 122 in the memory circuit. As a result, the RFID chip 101 will not respond even if it receives a command from the RFID reader / writer 130 thereafter. In this embodiment, the case where the operation stop register is 1 bit has been described. However, the operation stop register does not have to be 1 bit, and the number of bits may be changed as necessary.

(Embodiment 4)
In this embodiment, an operation in the case where the value of the operation stop register 122 in the RFID chip 101 is set to 1 and no response is received even when a command is received from the RFID reader / writer will be described.

The RFID chip 101 receives the instruction by the RF circuit 106, demodulates it, and sends it to the receiving circuit 104. The receiving circuit 104 writes the demodulated data to the data register 120 in the memory circuit 103, and then writes 1 to the standby register 121 to indicate that the data writing has been completed. The control circuit 102 confirms the value of the operation stop register 122 when the reception circuit 104 confirms that writing to the standby register 121 is completed.

The control circuit 102 confirms that the value of the operation stop register 122 is 1, and stops the processing at this point.

(Embodiment 5)
FIG. 2 is a flowchart showing a processing procedure of the RFID chip 101 in the present embodiment.
When the RFID chip 101 receives a command from the RFID reader / writer 130 at step ST11, the power is generated by the power supply circuit 114 and the clock generation circuit 115 is generated at step ST12, and the information from the radio wave received by the demodulation circuit 116 is converted into digital data. Demodulate.

Next, when the receiving circuit 104 receives data from the demodulation circuit 116 at step ST13, the received data is first written to the data register 120 at step ST14. When the data writing is completed, 1 is written to the standby register 121 at ST15.

Next, in step ST16, the control circuit 102 reads the value of the operation stop register 122 after the value is written to the standby register 121. When the value of the operation stop register is 1, the process is stopped at that time, and when the value of the operation stop register is 0, the process is started.

Next, in ST17, the control circuit 102 reads data from the data register 120 and analyzes an instruction from the data.

If the instruction is an operation stop instruction in step ST18 (yes), the control circuit 102 writes 1 to the operation stop register 122 in step ST20, and even if the RFID chip 101 subsequently receives an instruction from the RFID reader / writer 130, it responds. The process ends without doing so.

If the instruction is not an operation stop instruction in step ST18 (no), the control circuit 102 executes processing according to the instruction, and writes the processing result in the data register 120 in step ST19.

In step ST21, the control circuit 102 writes 1 to the standby register 121 when the data writing to the data register 120 is completed, and notifies the transmission circuit 105 that the processing has been completed.

In step ST22, the transmission circuit 105 captures data from the data register 120 and transmits it to the modulation circuit 117 when the control circuit 102 writes a value in the standby register 121.

In step ST23, the modulation circuit 117 modulates the received data and transmits the modulated signal to the resonance circuit 113. The resonance circuit 113 resonates the modulated data and transmits the processing result from the antenna to the reader / writer. Thus, a series of processing of the RFID chip 101 is completed.

(Embodiment 6)
In this embodiment, a ROM 111 included in the RFID chip 101 and an operation method thereof will be described.

The configuration of the ROM 111 in FIG. 1 will be described using the ROM 707 in FIG. The ROM 707 includes a memory cell array 756 in which memory elements are formed and a driving circuit. The drive circuit includes a column decoder 751, a row decoder 752, a read circuit 754, a write circuit 755, and a selector 753.

The memory cell array 756 includes a memory cell 757 at each intersection of the bit line Bm (m = 1 to x), the word line Wn (n = 1 to y), and the bit line and the word line. Note that the memory cell 757 may be an active type to which a transistor is connected or a passive type including only passive elements. The bit line Bm is controlled by the selector 753, and the word line Wn is controlled by the row decoder 752.

The column decoder 751 receives an address signal designating an arbitrary bit line and gives a signal to the selector 753. The selector 753 receives a signal from the column decoder 751 and selects a designated bit line. The row decoder 752 receives an address signal designating an arbitrary word line and selects a designated word line. Through the above operation, one memory cell 757 corresponding to the address signal is selected. The reading circuit 754 reads and outputs information included in the selected memory cell. The writing circuit 755 generates a voltage necessary for writing, and writes information by applying a voltage to the selected memory cell.

Next, the circuit configuration of the memory cell 757 will be described. In this embodiment, a memory cell including a memory element 783 having a lower electrode and an upper electrode and a memory material layer interposed between the pair of electrodes will be described.

A memory cell 757 illustrated in FIG. 4A is an active memory cell including a transistor 781 and a memory element 783. A thin film transistor can be used as the transistor 781. A gate electrode of the transistor 781 is connected to the word line Wy. One of a source electrode and a drain electrode of the transistor 781 is connected to the bit line Bx, and the other is connected to the memory element 783. A lower electrode of the memory element 783 is electrically connected to one of a source electrode and a drain electrode of the transistor 781. The upper electrode (corresponding to 782) of the memory element 783 can be shared by the memory elements as a common electrode.

As shown in FIG. 4B, a structure in which the memory element 783 is connected to the diode 784 may be used. The diode 784 can employ a so-called diode connection structure in which one of a source electrode and a drain electrode of a transistor and a gate electrode are connected. As the diode 784, a Schottky diode by contact between the memory material layer and the lower electrode, or a diode formed by stacking memory materials can be used.

As the memory material layer, a material whose property or state is changed by an electric action, an optical action, a thermal action, or the like can be used. For example, a material that can change its properties or state due to melting due to Joule heat, dielectric breakdown, or the like and can short-circuit the lower electrode and the upper electrode may be used. Therefore, the thickness of the memory material layer is 5 nm to 100 nm, preferably 10 nm to 60 nm. Such a memory material layer can be formed using an inorganic material or an organic material, and can be formed by an evaporation method, a spin coating method, a droplet discharge method, or the like.

Examples of the inorganic material include silicon oxide, silicon nitride, and silicon oxynitride. Even with such an inorganic material, by controlling the film thickness, dielectric breakdown can be caused and the lower electrode and the upper electrode can be short-circuited.

Examples of the organic material include 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD) and 4,4′-bis [N- (3- Methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD), 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA), 4,4 ', 4''-tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) and 4,4'-bis (N- (4- (N, N- Di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond), polyvinylcarbazole (abbreviation: PVK), and phthalocyanine ( _Referred: H 2 Pc), copper phthalocyanine (abbreviation: CuPc), or vanadyl phthalocyanine (abbreviation: VOPc), and can be used phthalocyanine compounds such as. These materials are substances having a high hole transporting property.

As other organic materials, for example, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [h ] -Quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc. And bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) ₂ ) It is also possible to use materials such as metal complexes having oxazole and thiazole ligands such as it can. These materials are substances having a high electron transporting property.

In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, Compounds such as 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can be used.

The memory material layer may have a single layer structure or a stacked structure. In the case of a laminated structure, a laminated structure can be selected from the above materials. Alternatively, the organic material and the light-emitting material may be stacked. As a light-emitting material, 4-dicyanomethylene-2-methyl-6- (1,1,7,7-tetramethyljulolidyl-9-enyl) -4H-pyran (abbreviation: DCJT), 4-dicyanomethylene-2 -T-butyl-6- (1,1,7,7-tetramethyljulolidyl-9-enyl) -4H-pyran, periflanthene, 1,4-bis [2- (10-methoxy-1,1, 7,7-tetramethyljulolidin-9-yl) ethenyl] -2,5-dicyanobenzene, N, N′-dimethylquinacridone (abbreviation: DMQd), coumarin 6, coumarin 545T, tris (8-quinolinolato) aluminum ( Abbreviations: Alq ₃ ), 9,9′-bianthryl, 9,10-diphenylanthracene (abbreviation: DPA) and 9,10-bis (2-naphthyl) anthracene (abbreviation: DNA) ), 2,5,8,11-tetra-t-butylperylene (abbreviation: TBP).

Alternatively, a layer in which the light emitting material is dispersed may be used. In the layer in which the light emitting material is dispersed, the base material includes an anthracene derivative such as 9,10-di (2-naphthyl) -2-tert-butylanthracene (abbreviation: t-BuDNA), 4,4′- Carbazole derivatives such as bis (N-carbazolyl) biphenyl (abbreviation: CBP), bis [2- (2-hydroxyphenyl) pyridinato] zinc (abbreviation: Znpp ₂ ), bis [2- (2-hydroxyphenyl) benzoxazola G] A metal complex such as zinc (abbreviation: ZnBOX) can be used. In addition, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), 9,10-bis (2-naphthyl) anthracene (abbreviation: DNA), bis (2-methyl-8-quinolinolato) -4-phenylphenolato- Aluminum (abbreviation: BAlq) or the like can be used.

Such an organic material has a glass transition temperature (Tg) of 50 ° C. to 300 ° C., preferably 80 ° C. to 120 ° C., in order to change its properties by a thermal action or the like.

Alternatively, a material in which a metal oxide is mixed in an organic material or a light emitting material may be used. Note that the material in which the metal oxide is mixed includes a state where the organic material or the light-emitting material and the metal oxide are mixed or stacked. Specifically, it refers to a state formed by a co-evaporation method using a plurality of evaporation sources. Such a material can be called an organic-inorganic composite material.

For example, when a metal oxide is mixed with a substance having a high hole transporting property, the metal oxide includes vanadium oxide, molybdenum oxide, niobium oxide, rhenium oxide, tungsten oxide, ruthenium oxide, titanium oxide. It is preferable to use an oxide, chromium oxide, zirconium oxide, hafnium oxide, or tantalum oxide.

In the case where a substance having a high electron transporting property and a metal oxide are mixed, it is preferable to use lithium oxide, calcium oxide, sodium oxide, potassium oxide, or magnesium oxide as the metal oxide.

For the memory material layer, a material whose properties are changed by an electric action, an optical action, or a thermal action may be used. For example, a compound that generates an acid by absorbing light (photo acid generator) is used. Doped conjugated polymers can also be used. As the conjugated polymer, polyacetylenes, polyphenylene vinylenes, polythiophenes, polyanilines, polyphenylene ethynylenes, and the like can be used. As the photoacid generator, arylsulfonium salts, aryliodonium salts, o-nitrobenzyl tosylate, arylsulfonic acid p-nitrobenzyl esters, sulfonylacetophenones, Fe-allene complex PF6 salts and the like can be used.

Next, an operation when data is written to the active memory cell 757 as illustrated in FIG. 4A will be described. In the present embodiment, the value stored in the memory element in the initial state is “0”, and the value stored in the memory element whose characteristics are changed by an electrical action or the like is “1”. In addition, the memory element in the initial state has a high resistance value, and the memory element after the change has a low resistance value.

When writing, the column decoder 751, the row decoder 752, and the selector 753 select the bit line Bm in the m-th column and the word line Wn in the n-th row and are included in the memory cell 757 in the m-th column and the n-th row. The transistor 781 is turned on.

Subsequently, the write circuit 755 applies a predetermined voltage to the bit line Bm in the m-th column for a predetermined period. The application voltage and the application time are such that the memory element 783 changes from an initial state to a low resistance state. The voltage applied to the bit line Bm in the m-th column is transmitted to the lower electrode of the memory element 783, and a potential difference is generated with the upper electrode. Then, a current flows through the memory element 783, the state of the memory material layer changes, and the memory element characteristics change. Then, the value stored in the memory element 783 is changed from “0” to “1”.

Such a write operation is performed according to the control circuit 102.

Next, an operation for reading information will be described. As shown in FIG. 5, the reading circuit 754 includes a resistance element 790 and a sense amplifier 791. Information is read by applying a voltage between the lower electrode and the upper electrode to determine whether the memory element is in an initial state or a low state after change. Specifically, information can be read by a resistance division method.

For example, a case where information is read from the memory element 783 in the m-th column and the n-th row from the plurality of memory elements 783 included in the memory cell array 756 is described. First, the column decoder 751, the row decoder 752, and the selector 753 select the bit line Bm in the m-th column and the word line Wn in the n-th row. Then, the transistor 781 included in the memory cell 757 arranged in the m-th column and the n-th row is turned on, and the memory element 783 and the resistance element 790 are connected in series. As a result, the potential at the point P shown in FIG. 5 is determined according to the current characteristics of the memory element 783.

The potential at the point P when the memory element is in the initial state is V1, the potential at the point P when the memory element is in the low resistance state after the change is V2, and a reference potential Vref that satisfies V1> Vref> V2 is used. Thus, the information stored in the memory element can be read. Specifically, when the memory element is in the initial state, the output potential of the sense amplifier 791 is Lo, and when the memory element is in the low resistance state, the output potential of the sense amplifier 791 is Hi.

According to the above method, the voltage value is read by using the difference in resistance value of the memory element 783 and the resistance division. However, the information included in the memory element 783 may be read using a current value. Note that the reading circuit 754 of the present invention is not limited to the above structure, and may have any structure as long as information stored in the memory element can be read.

The memory element having such a configuration changes from “0” to “1”, and the change from “0” to “1” is irreversible, and thus becomes a write-once memory element.

The identification number of the RFID chip can be written into such a memory element 783. The written information can be read out by wireless communication from a sensor provided on the telephone terminal, that is, an antenna.

Note that this embodiment mode can be implemented freely combining with the above embodiment modes.

(Embodiment 7)
In this embodiment, a cross-sectional view of the memory circuit 103 is described.

FIG. 6A is a cross-sectional view of a memory element in which a memory cell portion 301 and a driver circuit portion 302 are integrally formed over an insulating substrate 310. As the insulating substrate 310, a glass substrate, a quartz substrate, a substrate made of silicon, a metal substrate, a plastic substrate, or the like can be used.

A base film 311 is provided over the insulating substrate 310. In the driver circuit portion 302, thin film transistors 320 and 321 are provided via a base film 311, and a transistor 781 is provided in the memory cell portion 301 via a base film 311. Each thin film transistor includes a semiconductor film 312 formed in an island shape, a gate electrode 314 provided via a gate insulating film, an insulator (so-called sidewall) 313 provided on a side surface of the gate electrode, and a gate electrode 314. Yes. The semiconductor film 312 is formed to have a thickness of 0.2 μm or less, typically 40 nm to 170 nm, preferably 50 nm to 150 nm. Further, the insulating film 316 covering the insulator 313 and the semiconductor film 312, and the electrode 315 connected to the impurity region formed in the semiconductor film 312 are provided. Note that since the electrode 315 is connected to the impurity region, a contact hole can be formed in the gate insulating film and the insulating film 316, a conductive film can be formed in the contact hole, and the conductive film can be patterned.

As the semiconductor film, amorphous silicon or polycrystalline silicon can be used. In the case of using polycrystalline silicon, amorphous silicon can be formed first, and heat treatment or laser irradiation can be performed to obtain polycrystalline silicon. At this time, the crystallization temperature can be reduced by performing heat treatment or laser irradiation using a metal element typified by nickel. For laser irradiation, a continuous wave or pulsed laser irradiation apparatus can be used. Alternatively, a crystallization method involving heat treatment may be combined with a crystallization method in which a continuous wave laser or a laser beam oscillated at a frequency of 10 MHz or higher is irradiated. By irradiation with a continuous wave laser or a laser beam oscillated at a frequency of 10 MHz or higher, the surface of the crystallized semiconductor film can be flattened. As a result, the gate insulating film can be made thinner and can contribute to improving the breakdown voltage of the gate insulating film.

In addition, a semiconductor film obtained by scanning and crystallizing in one direction while irradiating a semiconductor film with a continuous wave laser or a laser beam oscillating at a frequency of 10 MHz or more grows crystals in the scanning direction of the beam. There is a characteristic to do. Transistors are arranged with the scanning direction aligned with the channel length direction (the direction in which carriers flow when a channel formation region is formed), and by combining the following gate insulating films, there is little variation in characteristics and field effect transfer A high degree transistor (TFT) can be obtained.

In the thin film transistor included in the wireless chip of the present invention, an insulating film typified by a gate insulating film or the like can be manufactured by oxidizing or nitriding the surface of a formation surface using high-density plasma treatment. The high-density plasma treatment means that the plasma density is 1 × 10 ¹¹ cm ⁻³ or more, preferably 1 × 10 ¹¹ cm ⁻³ to 9 × 10 ¹⁵ cm ⁻³ , such as a microwave (for example, a frequency of 2.45 GHz). This is plasma processing using high frequency. When plasma is generated under such conditions, the low electron temperature is changed from 0.2 eV to 2 eV. As described above, high-density plasma characterized by low electron temperature has low kinetic energy of active species, and thus can form a film with less plasma damage and fewer defects. For example, in the case where an insulating film is formed over an object to be processed, a substrate on which a semiconductor film patterned as an object to be formed is placed in a film formation chamber that enables such plasma treatment. Then, a film forming process is performed with a distance between an electrode for plasma generation, a so-called antenna, and an object to be formed being 20 mm to 80 mm, preferably 20 mm to 60 mm. Such a high-density plasma treatment can realize a low-temperature process (substrate temperature of 400 ° C. or lower). Therefore, a plastic having low heat resistance can be used as the substrate.

Such an insulating film can be formed in a nitrogen atmosphere or an oxygen atmosphere. The nitrogen atmosphere is typically a mixed atmosphere of nitrogen and a rare gas, or a mixed atmosphere of nitrogen, hydrogen, and a rare gas. A gas having nitrogen and hydrogen can include ammonia.
As the rare gas, at least one of helium, neon, argon, krypton, and xenon can be used. The oxygen atmosphere is typically a mixed atmosphere of oxygen and a rare gas, a mixed atmosphere of oxygen, hydrogen, and a rare gas, or a mixed atmosphere of dinitrogen monoxide and a rare gas. As the rare gas, at least one of helium, neon, argon, krypton, and xenon can be used. Alternatively, a mixed atmosphere of hydrogen and a rare gas may be used.

The surface of the surface to be formed can be oxidized or nitrided by oxygen radicals (which may include OH radicals) or nitrogen radicals (which may include NH radicals) generated by this high-density plasma.

By such treatment using high-density plasma, an insulating film having a thickness of 1 to 20 nm, typically 5 to 10 nm, can be formed. Since the reaction in this case is a solid-phase reaction, the interface state density between the insulating film and the semiconductor film can be extremely low. For example, when an insulating film is formed on the surface of the semiconductor film by oxidizing or nitriding the surface of the semiconductor film (crystalline silicon or polycrystalline silicon) by high-density plasma treatment, the thickness of the insulating film formed on the surface of the semiconductor film The variation in thickness can be made extremely small. In addition, in the case of crystalline silicon, since it is not oxidized more than necessary at the crystal grain boundary, it becomes a very preferable state. That is, by subjecting the surface of the semiconductor film to solid phase oxidation by the high-density plasma treatment shown here, an insulating film having good uniformity and low interface state density can be obtained without causing an oxidation reaction more than necessary at the grain boundary. Can be formed.

The insulating film formed in this way has little damage to other films and becomes dense. In addition, an insulating film formed by high-density plasma treatment can improve an interface state in contact with the insulating film. For example, when the gate insulating film is formed using high-density plasma treatment, the interface state with the semiconductor film can be improved. As a result, the electrical characteristics of the thin film transistor can be improved.

Although the case where high-density plasma treatment is used for manufacturing the insulating film has been described, the semiconductor film may be subjected to high-density plasma treatment. The semiconductor film surface can be modified by high-density plasma treatment. As a result, the interface state can be improved, and the electrical characteristics of the thin film transistor can be improved.

In the present invention, as an insulating film such as a gate insulating film, only an insulating film formed by high-density plasma treatment may be used, or silicon oxide, silicon oxynitride, silicon nitride by a CVD method using plasma or thermal reaction. Alternatively, an insulating film such as may be deposited and laminated. In any case, a transistor formed by including an insulating film formed by high-density plasma in part or all of the gate insulating film can reduce variation in characteristics.

In order to improve flatness, insulating films 317 and 318 are preferably provided. At this time, the insulating film 317 is preferably formed from an organic material, and the insulating film 318 is preferably formed from an inorganic material. In the case where the insulating films 317 and 318 are provided, the electrode 315 can be formed to be connected to the impurity regions through the contact holes in the insulating films 317 and 318.

Further, an insulating film 325 is provided, and a lower electrode 327 is formed so as to be connected to the electrode 315. An insulating film 328 is formed which covers an end portion of the lower electrode 327 and has an opening provided so that the lower electrode 327 is exposed. A memory material layer 329 is formed in the opening, and an upper electrode 330 is formed. In this manner, a memory element 783 having the lower electrode 327, the memory material layer 329, and the upper electrode 330 is formed. The memory material layer 329 can be formed of an organic material or an inorganic material. The lower electrode 327 or the upper electrode 330 can be formed from a conductive material. For example, it can be formed of a film made of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), or silicon (Si), or an alloy film using these elements. Alternatively, a light-transmitting material such as indium tin oxide (ITO), indium tin oxide containing silicon oxide, or indium oxide containing 2 to 20 wt% zinc oxide can be used.

In addition, an insulating film 331 is preferably formed in order to further increase planarity and prevent an impurity element from entering.

For the insulating film described in this embodiment, an inorganic material or an organic material can be used. As the inorganic material, silicon oxide or silicon nitride can be used. As the organic material, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or polysilazane can be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Polysilazane is formed using a polymer material having a bond of silicon (Si) and nitrogen (N) as a starting material.

FIG. 6B is a cross-sectional view of a memory element in which a memory material layer is formed in the contact hole 351 of the electrode 315, unlike FIG. Similarly to FIG. 6A, the memory element 783 can be formed by using the electrode 315 as the lower electrode and forming the memory material layer 329 and the upper electrode 330 over the electrode 315. Thereafter, an insulating film 331 is formed. The other structures are the same as those in FIG.

When the memory element is formed in the contact hole 351 as described above, the memory device can be reduced in size. In addition, since the memory electrode is not necessary, the number of manufacturing steps can be reduced, and a memory device with reduced cost can be provided.

(Embodiment 8)
In this embodiment, a layout of a part of a thin film transistor in a circuit included in a wireless chip is described.

A semiconductor layer corresponding to the semiconductor film 312 described in the above embodiment has a base film or the like over the entire surface or a part of a substrate having an insulating surface (a region having a larger area than that determined as a semiconductor region of a transistor). Formed through. Then, a mask pattern is formed on the semiconductor layer by photolithography. By etching the semiconductor layer using the mask pattern, an island-shaped semiconductor pattern having a specific shape including a source region, a drain region, and a channel formation region of the thin film transistor can be formed. The shape of the patterned semiconductor layer is determined in consideration of the required circuit characteristics and appropriate layout based on the characteristics of the thin film transistor.

In the thin film transistor of the present invention, the photomask for forming the semiconductor layer has a pattern. This photomask pattern has corners, and one side of the (right triangle) is rounded by removing the corners to a size of 10 μm or less. The shape of this mask pattern can be transferred as the pattern shape of the semiconductor film 312 as shown in FIG. Further, when transferring to the semiconductor layer, the corner of the semiconductor film may be transferred so as to be more rounded than the corner of the photomask pattern. In other words, the corners of the semiconductor film pattern may be provided with roundness that is smoother than the photomask pattern. In FIG. 7, gate electrodes and wirings to be formed later are indicated by dotted lines.

Next, a gate insulating film is formed over the semiconductor layer formed so that the corners are rounded. Then, as shown in the above embodiment mode, the gate electrode 314 and the gate wiring are formed at the same time so as to partially overlap the semiconductor layer. The gate electrode or the gate wiring can be formed by a photolithography technique by forming a metal layer or a semiconductor layer.

The photomask for forming the gate electrode or the gate wiring has a pattern.
This photomask pattern has a corner that is bent in an L shape, and a right triangle in which one side is 10 μm or less or 1/2 or less of the line width of the wiring and 1/5 or more of the line width. Has been deleted. That is, the outer periphery of the gate electrode or the gate wiring at the corner as viewed from the upper surface forms a curve. Specifically, in order to round the outer peripheral edge of the corner portion, two first straight lines perpendicular to each other sandwiching the corner portion and one second straight line forming an angle of about 45 degrees with these two first straight lines. Then, a portion corresponding to a right isosceles triangle portion formed by is removed. When removed, two obtuse angle portions are newly formed. However, by appropriately setting the etching conditions, a gate electrode or a curve that touches both the first straight line and the second straight line is formed at each obtuse angle portion. It is preferable to etch the gate wiring. The length of two equal sides of the right-angled isosceles triangle is set to 1/5 or more and 1/2 or less of the wiring width. Also, the inner periphery of the corner portion is formed so that the inner periphery is rounded along the outer periphery of the corner portion. The shape of the mask pattern can be transferred as a pattern shape of a gate electrode or a gate wiring as shown in FIG. Further, when transferring to the gate electrode or the gate wiring, the corner of the gate electrode or the gate wiring may be further rounded. In other words, the corners of the gate electrode or the gate wiring may be provided with roundness with a smoother pattern shape than the photomask pattern. A corner portion of a gate electrode or a gate wiring formed using such a photomask can be rounded at a corner portion that is 1/2 or less of the line width and 1/5 or more. In FIG. 8, wirings to be formed later are indicated by dotted lines.

Such a gate electrode or gate wiring is bent into a rectangle due to layout restrictions. Therefore, a rounded corner portion of the gate electrode or gate wiring is provided with a convex portion (outer side) and a concave portion (inner side). The rounded convex portion can suppress generation of fine powder due to abnormal discharge during dry etching using plasma. Moreover, even if fine powder is generated during dry etching, the rounded recess can be easily flowed during cleaning. As a result, the yield can be greatly improved.

Next, an insulating layer or the like corresponding to the insulating films 316, 317, and 318 is formed over the gate electrode or the gate wiring as described in the above embodiment mode. Of course, in the present invention, the insulating film may be a single layer.

Over the insulating layer, an opening is formed in a predetermined position in the insulating film, and a wiring corresponding to the electrode 315 is formed in the opening. This opening is provided in order to establish electrical connection between the semiconductor layer or gate wiring layer located in the lower layer and the wiring layer. The wiring is formed with a mask pattern by a photolithography technique and formed into a predetermined pattern by etching.

A certain element can be connected by wiring. This wiring does not connect a specific element with a straight line, but bends into a rectangle (hereinafter referred to as a bent portion) due to layout restrictions. In addition, the wiring width of the wiring may change in the opening and other regions. For example, in the opening, when the opening is equal to or larger than the wiring width, the wiring width is changed so as to widen at that portion. Further, since the wiring also serves as one electrode of the capacitor portion in the circuit layout, the wiring width may be increased.

In this case, in the bent portion of the photomask pattern, one side of the right-angled triangle to be formed is 10 μm or less, or half or less of the line width of the wiring, and a corner portion having a size of 1/5 or more of the line width. Is deleted. Then, as shown in FIG. 9, the wiring pattern corresponding to the electrode 315 is also rounded similarly. The corner portion of the wiring is ½ or less of the line width, and the bent portion can be rounded to 1/5 or more. In such a rounded wiring, the convex part in the bent part can suppress the generation of fine powder due to abnormal discharge during dry etching by plasma. Further, even if fine powder is generated during dry etching, the recess is rounded and can be easily washed away during cleaning. As a result, the yield can be greatly improved. By rounding the corners of the wiring, it can be expected to be electrically conducted.

In the circuit having the layout shown in FIG. 9, the generation of fine powder due to abnormal discharge is suppressed during dry etching by plasma by smoothing and rounding the corners of the bent part and the part where the wiring width changes. Can do. Moreover, even if fine powder is generated during dry etching, the corners are rounded and can be easily washed away during cleaning. As a result, the yield can be greatly improved. That is, the problem of dust and fine powder in the manufacturing process can be solved. In addition, it can be expected that the wiring is electrically conductive by adopting a configuration in which the corners of the wiring are rounded. In particular, it is very advantageous to be able to wash away dust in wiring such as a drive circuit section provided with a large number of parallel wirings.

Note that in this embodiment mode, a mode in which corners or bent portions are rounded in three layouts of a semiconductor layer, a gate wiring, and a wiring is described; however, the present invention is not limited to this. That is, in any one layer, it is only necessary to round the corners or the bent portions to solve problems such as dust and fine powder in the manufacturing process.

(Embodiment 9)
The circuit of the RFID chip shown in Embodiment Mode 1 includes a transistor. In addition to a MOS transistor formed on a single crystal substrate, the transistor can be a thin film transistor (TFT). FIG. 10 is a diagram showing a cross-sectional structure of transistors constituting these circuits. FIG. 10 shows an n-channel transistor 1001, an n-channel transistor 1002, a capacitor element 1004, a resistor element 1005, and a p-channel transistor 1003. Each transistor includes a semiconductor layer 1015, a gate insulating layer 1018, and a gate electrode 1019. The gate electrode 1019 is formed with a stacked structure of a first conductive layer 1013 and a second conductive layer 1012. 11A to 11E are top views corresponding to the transistor, the capacitor, and the resistor shown in FIG. 10, and can be referred to together.

  In FIG. 10, an n-channel transistor 1001 is also called a low concentration drain (LDD) on both sides of a channel formation region in the channel length direction (carrier flow direction). An impurity region 1017 doped at a lower concentration than the impurity concentration of the impurity region 1016 to be formed is formed in the semiconductor layer 1015. In the case where the n-channel transistor 1001 is formed, phosphorus or the like is added to the impurity region 1016 and the impurity region 1017 as an impurity imparting n-type conductivity. LDD is formed as a means for suppressing hot electron degradation and short channel effect.

  As shown in FIG. 11A, in the gate electrode 1019 of the n-channel transistor 1001, the first conductive layer 1013 is formed so as to spread on both sides of the second conductive layer 1012. In this case, the first conductive layer 1013 is formed thinner than the second conductive layer. The thickness of the first conductive layer 1013 is formed so as to allow passage of ion species accelerated by an electric field of 10 to 100 kV. The impurity region 1017 is formed so as to overlap with the first conductive layer 1013 of the gate electrode 1019. That is, an LDD region overlapping with the gate electrode 1019 is formed. In this structure, an impurity region 1017 is formed in a self-aligned manner in the gate electrode 1019 by adding one conductivity type impurity through the first conductive layer 1013 using the second conductive layer 1012 as a mask. That is, the LDD overlapping with the gate electrode is formed in a self-aligning manner.

  Transistors having LDDs on both sides of the channel formation region are applied to transistors constituting a rectifying TFT of the power supply circuit 114 in FIG. 1 and a transmission gate (also referred to as an analog switch) used in a logic circuit. In these TFTs, since both positive and negative voltages are applied to the source electrode or the drain electrode, it is preferable to provide LDDs on both sides of the channel formation region.

  In FIG. 10, an n-channel transistor 1002 has an impurity region 1017 doped in a lower concentration than the impurity concentration of the impurity region 1016 in the semiconductor layer 1015 on one side of the channel formation region. As shown in FIG. 11B, in the gate electrode 1019 of the n-channel transistor 1002, the first conductive layer 1013 is formed so as to spread on one side of the second conductive layer 1012. In this case as well, an LDD can be formed in a self-aligned manner by adding an impurity of one conductivity type through the first conductive layer 1013 using the second conductive layer 1012 as a mask.

  A transistor having an LDD on one side of the channel formation region may be applied to a transistor to which only a positive voltage or only a negative voltage is applied between the source and drain electrodes. Specifically, it may be applied to a transistor constituting a logic gate such as an inverter circuit, a NAND circuit, a NOR circuit, or a latch circuit, or a transistor constituting an analog circuit such as a sense amplifier, a constant voltage generation circuit, or a VCO.

  In FIG. 10, the capacitor element 1004 is formed with a gate insulating layer 1018 sandwiched between a first conductive layer 1013 and a semiconductor layer 1015. The semiconductor layer 1015 forming the capacitor element 1004 includes an impurity region 1021 and an impurity region 1022. The impurity region 1022 is formed in the semiconductor layer 1015 so as to overlap with the first conductive layer 1013. Further, the impurity region 1021 forms a contact with the wiring 1014. Since the impurity region 1022 can be doped with one conductivity type impurity through the first conductive layer 1013, the impurity concentration in the impurity region 1021 and the impurity region 1022 can be the same or different. It is. In any case, since the semiconductor layer 1015 functions as an electrode in the capacitor 1004, it is preferable to reduce the resistance by adding an impurity of one conductivity type. In addition, as shown in FIG. 11C, the first conductive layer 1013 can sufficiently function as an electrode by using the second conductive layer 1012 as an auxiliary electrode. In this manner, by using a composite electrode structure in which the first conductive layer 1013 and the second conductive layer 1012 are combined, the capacitor element 1004 can be formed in a self-aligning manner.

  In FIG. 1, the capacitor element is used as a storage capacitor included in the power supply circuit 114 or a resonance capacitor included in the resonance circuit 113. In particular, since both positive and negative voltages are applied between the two terminals of the capacitive element, the resonant capacitor needs to function as a capacitor regardless of whether the voltage between the two terminals is positive or negative.

  In FIG. 10, the resistance element 1005 is formed by the first conductive layer 1013. Since the first conductive layer 1013 is formed to a thickness of about 30 to 150 nm, the resistance element can be configured by appropriately setting the width and length thereof.

  The resistance element is used as a resistance load included in the modulation circuit 117 in FIG. Also, it may be used as a load when current is controlled by a VCO or the like. The resistance element may be formed using a semiconductor layer containing an impurity element at a high concentration or a thin metal layer. In contrast to a semiconductor layer whose resistance value depends on the film thickness, film quality, impurity concentration, impurity activation rate, and the like, the metal layer is preferable because the resistance value is determined by the film thickness and film quality, so that variation is small.

  In FIG. 10, the p-channel transistor 1003 includes an impurity region 1020 in the semiconductor layer 1015. The impurity region 1020 forms source and drain regions that form a contact with the wiring 1014. The gate electrode 1019 has a structure in which the first conductive layer 1013 and the second conductive layer 1012 overlap each other. The p-channel transistor 1003 is a single drain transistor without an LDD. In the case of forming the p-channel transistor 1003, boron or the like is added to the impurity region 1020 as an impurity imparting p-type conductivity. On the other hand, if phosphorus is added to the impurity region 1020, an n-channel transistor having a single drain structure can be obtained.

One or both of the semiconductor layer 1015 and the gate insulating layer 1018 is excited by microwaves, has an electron temperature of 2 eV or less, an ion energy of 5 eV or less, and an electron density of about 10 ¹¹ to 10 ¹³ / cm ^3. Oxidation or nitridation may be performed by the treatment. At this time, the substrate temperature is set to 300 to 450 ° C., and the treatment is performed in an oxidizing atmosphere (O ₂ , N ₂ O, etc.) or a nitriding atmosphere (N ₂ , NH _3, etc.), thereby the interface between the semiconductor layer 1015 and the gate insulating layer 1018. The defect level of can be reduced. By performing this treatment on the gate insulating layer 1018, the insulating layer can be densified. That is, generation of charged defects can be suppressed and fluctuations in the threshold voltage of the transistor can be suppressed. In the case where the transistor is driven with a voltage of 3 V or lower, an insulating layer oxidized or nitrided by this plasma treatment can be used as the gate insulating layer 1018. When the driving voltage of the transistor is 3 V or more, the gate is formed by combining an insulating layer formed on the surface of the semiconductor layer 1015 by this plasma treatment and an insulating layer deposited by a CVD method (plasma CVD method or thermal CVD method). An insulating layer 1018 can be formed. Similarly, this insulating layer can also be used as a dielectric layer of the capacitor 1004. In this case, since the insulating layer formed by this plasma treatment is formed with a thickness of 1 to 10 nm and is a dense film, a capacitor having a large charge capacity can be formed.

  As described with reference to FIGS. 10 and 11, elements having various structures can be formed by combining conductive layers having different film thicknesses. The region where only the first conductive layer is formed and the region where the first conductive layer and the second conductive layer are laminated are a photo provided with an auxiliary pattern having a light intensity reducing function consisting of a diffraction grating pattern or a semi-transmissive film. It can be formed using a mask or a reticle. That is, in the photolithography process, when the photoresist is exposed, the amount of light transmitted through the photomask is adjusted to vary the thickness of the resist mask to be developed. In this case, a resist having a complicated shape may be formed by providing a slit having a resolution limit or less in a photomask or a reticle. Alternatively, the mask pattern formed of the photoresist material may be deformed by baking at about 200 ° C. after development.

  Further, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function consisting of a diffraction grating pattern or a semi-transmissive film, a region where only the first conductive layer is formed, the first conductive layer and the second conductive layer A region where the conductive layer is stacked can be formed continuously. As shown in FIG. 11A, a region where only the first conductive layer is formed can be selectively formed over the semiconductor layer. Such a region is effective on the semiconductor layer, but is not necessary in other regions (a wiring region continuous with the gate electrode). By using this photomask or reticle, it is not necessary to form a region of only the first conductive layer in the wiring portion, so that the wiring density can be substantially increased.

  10 and 11, the first conductive layer is a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or a refractory metal. An alloy or a compound mainly composed of is formed with a thickness of 30 to 50 nm. The second conductive layer is made of a refractory metal such as tungsten (W), chromium (Cr), tantalum (Ta), tantalum nitride (TaN), or molybdenum (Mo), or an alloy or compound containing a refractory metal as a main component. To a thickness of 300 to 600 nm. For example, different conductive materials are used for the first conductive layer and the second conductive layer, and a difference in etching rate is caused in an etching process performed later. As an example, TaN can be used for the first conductive layer, and a tungsten film can be used for the second conductive layer.

  In this embodiment mode, transistors, capacitors, and resistors having different electrode structures are formed in the same patterning process using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function including a diffraction grating pattern or a semi-transmissive film. It shows that it can be made separately. Thus, elements having different forms can be formed and integrated without increasing the number of steps in accordance with circuit characteristics.

(Embodiment 10)
In the present embodiment, an example of using the operation stop system of the present invention will be described.

  The semiconductor device of the present invention is characterized by being small, thin, and lightweight. With the above features, the semiconductor device of the present invention can be used as a wireless chip. The semiconductor device of the present invention can be safely used as a wireless chip by having an operation stop system.

For example, it can be used in packaging containers, books, recording media, personal items, foods, clothing, health supplies, daily necessities, medicines, electronic devices, and the like. These examples will be described with reference to FIG. Note that a wireless chip 1201 is provided in each of FIGS.

  Packaging containers refer to wrapping paper such as lunch boxes, plastic bottles, and the like (see FIG. 12A). Books refer to books, books, and the like (see FIG. 12B). The recording medium refers to DVD software, video tape, and the like (see FIG. 12C). Personal belongings refer to bags, glasses, and the like (see FIG. 12D). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Note that health supplies refer to medical instruments, health instruments, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

  In addition, the provision of wireless chips on electronic devices such as packaging containers, books, recording media, personal items, foods, daily necessities, health supplies, chemicals, etc. Forgery and theft can be prevented. Moreover, if it is chemicals, the mistake of taking a medicine can be prevented. As a method of providing the wireless chip, the wireless chip is provided on the surface of the article or embedded in the article. For example, a book may be embedded in paper, and a package made of an organic resin may be embedded in the organic resin. Further, when writing is performed by applying an optical action later, it is preferable to form the transparent element so that light can be applied to the portion of the memory element provided in the chip. Furthermore, problems such as privacy after the user purchases a product can also be solved by providing a system for stopping the wireless chip.

As a method for bringing the wireless chip into a stop state, for example, when purchasing a product, when a barcode reader is held over the barcode portion of the product at a cash register, an operation stop command is written into the wireless chip. That is, the memory material layer whose physical characteristics of the wireless chip do not change reversibly is physically changed, and the operation stop command is stored as data. At this time, a wireless chip may be provided in the vicinity of the barcode of the product, or the wireless chip may have a barcode function. In this way, when the operation stop command is written to the wireless chip, the wireless chip cannot be operated again, so that privacy after purchasing the product can be protected.

In addition, the usage form shown in this Embodiment is an illustration and is not limited to this. Further, this embodiment can be freely combined with the above embodiment.

It is the figure which showed the structure of the RFID chip | tip of this invention. It is the figure which showed the flow of operation | movement of the RFID chip | tip of this invention. It is the figure which showed the memory of this invention FIG. 4 is a diagram illustrating a memory device of the present invention. It is the figure which showed operation | movement of the memory of this invention. It is sectional drawing which showed the memory of this invention 6A and 6B illustrate a layout of a part of a thin film transistor in a circuit included in a wireless chip of the present invention. 6A and 6B illustrate a layout of a part of a thin film transistor in a circuit included in a wireless chip of the present invention. 6A and 6B illustrate a layout of a part of a thin film transistor in a circuit included in a wireless chip of the present invention. FIG. 9 illustrates a cross-sectional structure of a transistor. The top view corresponding to a transistor, a capacitive element, and a resistive element. 4A and 4B illustrate a usage mode of a semiconductor device of the invention.

Explanation of symbols

101 RFID chip 102 Control circuit 103 Memory circuit 104 Reception circuit 105 Transmission circuit 106 RF circuit 110 RAM
111 ROM
113 Resonant circuit 114 Power supply circuit 115 Clock generation circuit 116 Demodulation circuit 117 Modulation circuit 120 Data register 121 Standby register 122 Operation stop register 130 RFID reader / writer 131 Antenna 132 Information processing device 133 Communication line

Claims (12)

An antenna,
A memory cell;
A control circuit,
The memory cell has a memory material layer between opposing electrodes,
The control circuit has means for storing an instruction received from the antenna as data in the memory cell by changing a physical characteristic of the memory cell;
A semiconductor device characterized in that physical characteristics of the memory cell do not change reversibly. An antenna,
A memory circuit including a memory cell array having a plurality of memory cells;
A control circuit,
The memory cell array includes a plurality of bit lines extending in a first direction and a plurality of word lines extending in a direction perpendicular to the first direction,
Memory cells are formed at the intersections between the bit lines and the word lines,
A memory material layer between the bit line and the word line of the memory cell;
The control circuit has means for storing an instruction received from the antenna as data in the memory cell by changing a physical characteristic of the memory cell;
A semiconductor device characterized in that physical characteristics of the memory cell do not change reversibly. 3. The semiconductor device according to claim 1, wherein the command stops the operation of the semiconductor device. A circuit having an antenna;
A memory circuit having ROM and RAM;
A receiving circuit for storing instructions received from the antenna as data in the RAM;
A transmission circuit for transmitting data fetched from the RAM to a circuit having the antenna;
A control circuit,
The ROM has memory cells;
The memory cell has a memory material layer between opposing electrodes,
The control circuit has means for reading the data from the RAM in which an operation stop command received from the antenna is stored as data, and storing the data in the memory cell by changing physical characteristics of the memory cell. And
A semiconductor device characterized in that physical characteristics of the memory cell do not change reversibly. A circuit having an antenna;
A memory circuit having ROM and RAM;
A receiving circuit for storing instructions received from the antenna as data in the RAM;
A transmission circuit for transmitting data fetched from the RAM to a circuit having the antenna;
A control circuit,
The ROM includes a memory cell array having a plurality of memory cells,
The memory cell array includes a plurality of bit lines extending in a first direction and a plurality of word lines extending in a direction perpendicular to the first direction,
Memory cells are formed at the intersections between the bit lines and the word lines,
A memory material layer between the bit line and the word line of the memory cell;
The control circuit has means for reading the data from the RAM in which an operation stop command received from the antenna is stored as data, and storing the data in the memory cell by changing physical characteristics of the memory cell. And
A semiconductor device characterized in that physical characteristics of the memory cell do not change reversibly. 6. The semiconductor device according to claim 4, wherein the operation stop command stops the operation of the control circuit. 7. The semiconductor device according to claim 1, wherein physical characteristics of the memory cell change due to an electrical action, an optical action, or a thermal action on the memory material layer. 8. 8. The semiconductor device according to claim 1, wherein the physical characteristic is a resistance characteristic. 9. The semiconductor device according to claim 1, wherein an inorganic material is used for the memory material layer. 9. The semiconductor device according to claim 1, wherein an organic material is used for the memory material layer. The semiconductor device according to claim 1, wherein a light emitting material is used for the memory material layer. 12. The semiconductor device according to claim 10, wherein the memory material layer includes a metal oxide.

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