JP5297591B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a novel memory which allows process technologies to be relatively simple and which is capable of storing multivalued information with a fewer number of devices. <P>SOLUTION: A part of the shape of a first electrode in a first storage element is made different from the shape of the first electrode in a second storage element to cause a voltage value, at which electric resistance between the first electrode and the second electrode changes, to be made different, so that a single memory cell can store multivalued information in excess of one bit. Partial processing of the first electrode enables increase in a storage capacity per unit area. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device that stores multilevel data. The present invention relates to a semiconductor device having a circuit including a memory element and a thin film transistor (hereinafter referred to as TFT) and a manufacturing method thereof.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  In general, a storage device (also referred to as a memory device) includes a memory unit that stores data, and peripheral circuits (drivers, decoders, sense amplifiers, and the like) that write data into the memory unit and read data from the memory unit. I have. In a conventional memory device, the area required to store one bit is larger than the size of one switching element (typically a field effect transistor). Therefore, in the case of realizing a large-capacity storage device, an area necessary for storing one bit depends on a processing technique for manufacturing a transistor, which prevents the realization of a large-capacity storage device.

  In recent years, with the increasing complexity of application software, there has been a strong demand for large capacity memory, and the demand for higher integration has become stricter.

Patent Document 1 discloses a memory cell structure in which an impedance phase change film of an organic material is provided between electrodes. The memory has a structure in which the film thickness of the organic material is changed or the electrode contact area is changed in one memory cell, and the write voltage is stored in one memory cell by setting a plurality of impedance state transition points in the hysteresis characteristics as boundaries. Information that can be held can be multi-valued.
JP 2001-189431 A

  The present invention provides a novel memory capable of storing multilevel information with a relatively simple process technology and a small number of elements.

It is another object of the present invention to provide a storage device having a high degree of integration per bit, that is, a low cost per bit. It is another object of the present invention to provide a memory device with low power consumption by reducing the number of circuit elements and the number of wirings per bit.

In view of the above problems, in the present invention, when a memory element in which a material layer is disposed between a pair of electrodes is formed, a plurality of regions that are destroyed (or changed) at different voltages are formed in one memory cell. And a method for operating the same.

Note that the destruction of the material layer of the memory element means that the conductive layers (electrodes) provided above and below the material layer of the destroyed memory element are short-circuited. For example, the breakdown of the material layer of the memory element includes a dielectric breakdown. Further, when heated above the glass transition temperature, it softens or melts and changes the state of the material layer of the memory element, and as a result, the conductive layers provided above and below the material layer of the memory element may be short-circuited.

Note that the change in the material layer of the memory element means that the electrical characteristics of the material layer of the memory element are changed by application of a voltage. For example, a phase-change memory element in which the electrical characteristics of the material layer of the memory element change reversibly by application of a voltage can be given.

In the present invention, a corner (end) is formed by providing a step in the lower electrode, and the voltage at which the characteristics of the memory cell change due to electric field concentration at the corner or thinning of the organic layer near the corner. The value can be lowered. In addition, by changing the height of the step of the lower electrode and the cross-sectional shape of the lower electrode, the voltage value at which the characteristics of the memory cell change varies depending on the region, such as a region with a step or a region with a different cross-sectional shape. Can be made.

Using such characteristics, a plurality of regions having different voltage values in which the characteristics of the memory cells change can be formed in one memory cell. That is, one memory cell can be multi-valued (store multi-value information) exceeding 1 bit.

For example, the material layer of the memory element is divided into three regions of a first region, a second region, and a third region, and a first step is provided on the electrode in contact with the first region of the material layer of the memory element. A structure in which the second step is provided in the electrode in contact with the second region, and the step in the electrode in contact with the third region is not provided, that is, the first memory element in the first region and the second step in the second region. The memory element includes a third memory element in the third region. It is assumed that the first step is larger than the second step. The larger the level difference, the more the material layer of the memory element formed thereon is destroyed by a lower voltage value. The breakdown voltage value of the material layer of the memory element in each region becomes a first region, a second region, and a third region in ascending order.

Further, the present invention is not limited to the structure of a memory in which a step is provided on an electrode, and any structure may be employed as long as a plurality of regions having different voltage values in which the characteristics of memory cells change can be formed. For example, when a step is provided on the electrode, there is a method using a difference in taper angle of the step in addition to a method using the difference in height of the step. A breakdown voltage can be lowered at a step with a large taper angle, and a breakdown voltage can be increased at a step with a small taper angle. By forming steps with different taper angles on the side surfaces of the electrodes in the memory cell, the memory cell can be multi-valued. Further, a difference between a step having a side surface close to vertical and a step having a small taper angle can be used. In the present specification, the taper shape refers to an angle of 5 ° to less than 85 ° with respect to the horizontal plane. Moreover, the level | step difference which has a side surface near perpendicular | vertical refers to 85 degrees or more and 95 degrees or less with respect to a horizontal surface.

Alternatively, a plurality of regions having different voltage values for changing the characteristics of the memory cell may be formed by combining a structure in which a step is provided on the electrode and a structure having different taper angles.

  In addition, a memory cell in the present invention refers to one unit including a plurality of memory elements and wirings (or TFTs), and a plurality of memory cells are regularly arranged to constitute a memory portion of a semiconductor device. Yes.

In Structure 1 of the invention disclosed in this specification, one memory cell includes a first memory element and a second memory element, and the first memory element and the second memory element have a common first , A common second electrode, and a common material layer between the first electrode and the second electrode, and at least a part of the shape of the first electrode in the first memory element Is different from the shape of the first electrode in the second memory element. By making a part of the shape of the first electrode in the first memory element different from the shape of the first electrode in the second memory element, the electric resistance between the first electrode and the second electrode is reduced. Different voltage values are changed, and multi-value information exceeding 1 bit is stored in one memory cell. The memory capacity per unit area can be increased by partially processing the first electrode.

  In the conventional structure in which the film thickness of the organic material is changed in one memory cell, it is difficult to accurately adjust the film thickness of the organic material, and thus it is difficult to reduce the variation in the write voltage in a plurality of memory cells. is there. On the other hand, according to the present invention, it is only necessary to partially process the first electrode as compared with the conventional structure. Therefore, the higher the etching accuracy, the smaller the variation in the write voltage across the plurality of memory cells. it can.

In addition, when the conventional structure is used to change the electrode contact area in one memory cell, the area is greatly increased, and it is difficult to increase the storage capacity per unit area. On the other hand, since the present invention can suppress an increase in area as compared with the conventional structure, the storage capacity per unit area can be increased.

  In the present invention, a passive matrix memory portion can be formed by electrically connecting a first electrode to a word line and electrically connecting a second electrode to a bit line. In addition, an active matrix memory portion can be formed by connecting a switching element to the first electrode. Another structure 2 of the present invention is the first electrode on the insulating surface and the first electrode. A first memory element having a material layer, a second electrode on the material layer, and a second memory element at a position adjacent to the first memory element, and the first memory element And the second memory element have different voltage values at which electrical resistance changes, and the second electrode of the first memory element is common to the second memory element, The second memory element is a semiconductor device which is electrically connected to the same thin film transistor. In this manner, by electrically connecting a plurality of memory elements to the same thin film transistor, a driver circuit can be reduced as compared with a semiconductor device including a passive matrix memory portion, and the semiconductor device can be downsized.

  Further, in one memory cell, a partition may be provided between a plurality of memory elements. Another structure 3 of the present invention includes a first electrode on an insulating surface, and a partition on the first electrode. A first layer having a material layer on the partition and the first electrode, a second electrode on the material layer, and surrounded by the partition on the first electrode; A partition is provided between the second region surrounded by the partition on the end of the electrode, and the first region includes at least the first electrode, the material layer, and the second electrode. In the semiconductor device, the second region overlaps at least the material layer and the second electrode. By providing such a partition wall, it is possible to prevent defects such as a short circuit between adjacent memory cells even if the memory cell interval is narrowed, enabling high integration, and increasing the storage capacity per unit area. Become.

Further, in order to simplify the partial processing of the first electrode, the first electrode may be formed of two or more layers, and the configuration 4 of another invention includes the first electrode on the insulating surface, A partition on the first electrode, a material layer on the partition and the first electrode, and a second electrode on the material layer, wherein the first electrode is a laminate of two or more; A first region surrounded by a partition wall on the first electrode, a second region where a lowermost end portion of the first electrode and a material layer overlap, and a stack of the first electrodes A third region in which an end portion of the uppermost layer and the material layer overlap each other, and a partition wall is provided between each of the first region, the second region, and the third region, The first region overlaps at least the first electrode, the material layer, and the second electrode, and the second region includes at least the material layer and the second electrode. Overlap, the top layer of the end portion and the lowermost end portion of the first electrode is a semiconductor device which is a different position. Thus, even if the surface shape of the first electrode is complicated by forming the first electrode into two or more layers, the etching conditions and the layer material can be adjusted to obtain a plurality of memories. Variations in the write voltage across the cells can be reduced.

In the structure 3 or the structure 4, a thin film transistor may be further provided on the insulating surface, and the first electrode may be electrically connected to the thin film transistor to form an active matrix memory portion. . In the structure 3 or the structure 4, a thin film transistor and an antenna are provided on the insulating surface, the first electrode is electrically connected to the thin film transistor, and the circuit including the thin film transistor includes the antenna. A semiconductor device that can be electrically connected to and can exchange radio signals. Examples of the circuit electrically connected to the antenna include a writing circuit, a reading circuit, a sense amplifier, an output circuit, and a buffer.

  In each of the above structures, the first electrode has one part having different thicknesses and at least one step. Alternatively, one feature is that the first electrode has a portion having a different thickness and a side surface having at least two different taper angles.

  In each of the above structures, a plurality of regions on the first electrode form one memory cell, and one memory cell can store a plurality of bits.

In each of the above structures, the material layer includes an organic compound. By including an organic compound in the material layer, when someone else disassembles the memory cell in an attempt to counterfeit, the organic material that has come into contact with the atmosphere is easily altered, making it difficult to identify the material being used. It can be very difficult.

In addition, as a material layer of the memory element of the present invention, a low molecular material, a high molecular material, a singlet material, a triplet material, or the like may be used. For example, as a material layer of a memory element, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD) or 4,4′-bis [N- (3 -Methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD), 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA), 4, 4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) and 4,4′-bis (N- (4- (N, N -Di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond) and phthalocyanines (abbreviation: H ₂ Pc) Copper phthalocyanine A substance having a high hole-transport property such as a phthalocyanine compound such as (abbreviation: CuPc) or vanadyl phthalocyanine (abbreviation: VOPc) can be used. As another material of the material layer of the memory element, the electron transporting property can be used a high organic compound material, such as tris (8-quinolinolato) aluminum (abbreviation: Alq _3), tris (4-methyl-8 Quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation) : BAlq), a metal complex having a quinoline skeleton or a benzoquinoline skeleton, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- Oxazols such as (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) ₂ ) A material such as a metal complex having a ruthenium-based or thiazole-based ligand can also be used. In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, A compound such as 4-triazole (abbreviation: p-EtTAZ), bathocuproine (abbreviation: BCP), or the like can be used. In addition, the material layer may be made of not only an organic compound material but also a material partially including an inorganic compound.

  In order to prevent falsification and unauthorized use of information, when the material layer of the memory element is an organic material or an inorganic material that does not reversibly change phase, writing into the memory is performed once.

In addition, since the material layer of the memory element is reversibly used, an organic material (for example, bathophenanthroline (abbreviation: BPhen)) or an inorganic material (tellurium (Te), tellurium oxide (TeOx), antimony (for example) In the case of Sb), selenium (Se), bismuth (Bi), etc., data can be rewritten to the memory a plurality of times. Further, the reader / writer may be capable of both writing to and reading from the memory element using an organic material.

According to the present invention, multi-value memory elements can be achieved. That is, the storage capacity per unit area can be increased in the memory portion in which a plurality of memory elements are arranged.

By increasing the number of memory elements, high integration can be achieved, so that the area of the memory element can be reduced.

In addition, since the memory element of the present invention can be formed over the same substrate in common with a circuit for controlling the element and part of the process, a semiconductor device including the memory element can be manufactured at low cost. it can.

Furthermore, since the memory element of the present invention can be provided over a resin substrate using a peeling method or a transfer method, the semiconductor device including the memory element can be thinned, reduced in weight, and improved in impact resistance. it can.

  In addition, when the memory element and the antenna of the present invention are formed over the same resin substrate, the number of steps can be reduced and a semiconductor device with excellent impact resistance can be completed.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, a method for manufacturing a semiconductor device including a memory element over a glass substrate as an insulating substrate will be described. A method for forming the material layer of the memory element on the electrode step will be described. Note that a mode in which a memory element and a circuit (control circuit) for controlling the memory element are formed over the same substrate is shown.

First, as illustrated in FIG. 1A, a separation layer 402 is formed over a glass substrate 401. In addition to glass, quartz or the like can be used for the insulating substrate. As the separation layer 402, a film containing metal or a film containing silicon is formed over the entire surface of the substrate or selectively. By forming the release layer selectively at least, the glass substrate 401 can be peeled later. Examples of the metal include an element selected from W, Ti, Ta, Mo, Nd, Ni, Co, Zr, Zn, Ru, Rh, Pd, Os, and Ir, or an alloy material or compound material containing the element as a main component. A single layer made of the above or a laminate of these can be used. Examples of the compound material include oxides and nitrides of the above elements. Further, the state of the film containing silicon may be any of a crystalline state, an amorphous state, and a microcrystalline state. The removal rate of the release layer 402 can be controlled depending on the state.

Next, an insulating layer 403 is formed so as to cover the separation layer 402. The insulating layer 403 is formed using silicon oxide, silicon nitride, or the like. Then, a semiconductor layer is formed over the insulating layer 403 and crystallized by laser crystallization, thermal crystallization using a metal catalyst, or the like, and then patterned into a desired shape to form an island-shaped semiconductor layer. For laser crystallization, either a continuous wave laser or a pulsed laser can be used. Lasers include Ar laser, Kr laser, excimer laser, YAG laser, Y ₂ O ₃ laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor laser Alternatively, one or a plurality of gold vapor lasers can be used. For example, a pulse oscillation type excimer laser can be used. The semiconductor layer is formed to have a thickness of 0.2 μm or less, typically 40 nm to 170 nm, preferably 50 nm to 150 nm. Note that the semiconductor layer may be formed using an amorphous semiconductor, a microcrystalline semiconductor, a microcrystalline semiconductor, an organic semiconductor, or the like in addition to a crystalline semiconductor. The semiconductor layer may be formed using a material containing silicon, and may be formed from a mixed material of silicon and germanium, for example.

Next, a gate insulating layer 405 is formed so as to cover the semiconductor layer. The gate insulating layer 405 is formed using silicon oxide, silicon nitride, or the like. Such a gate insulating layer 405 can be formed by a CVD method, a thermal oxidation method, or the like. Alternatively, the semiconductor layer and the gate insulating layer 405 can be continuously formed by a CVD method and then patterned simultaneously. In this case, impurity contamination at the interface of each layer can be suppressed.

Then, the gate electrode layer 406 is formed. The gate electrode layer 406 is an element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), and copper (Cu), or an alloy material containing the element as a main component. Alternatively, it is formed of a compound material and then patterned into a desired shape. When patterning is performed by photolithography, the width of the gate electrode can be reduced when the resist mask is etched with plasma or the like and the width is reduced. As a result, the performance of the transistor can be improved. The gate electrode layer 406 may have a single-layer structure or a stacked structure. FIG. 1A illustrates the case where the gate electrode layer 406 has a stacked structure.

Next, an impurity region 407 is formed by adding an impurity element imparting conductivity to the semiconductor layer. The impurity region 407 is formed by forming a resist mask by photolithography and adding an impurity element such as phosphorus, arsenic, or boron. Depending on the impurity element, polarities such as an N-channel type and a P-channel type can be created.

Next, as shown in FIG. 1B, an insulating layer is formed using an insulator containing silicon, for example, silicon nitride, and the insulating layer is anisotropically etched in the vertical direction to be in contact with the side surface of the gate electrode. 409 (also referred to as a sidewall) is formed. When the sidewall is formed, the gate insulating layer 405 may be etched.

Next, impurities are further added to the semiconductor layer to form a first impurity region 410 immediately below the insulating layer (sidewall) 409 and a second impurity region 411 having an impurity concentration higher than that of the first impurity region. To do. A structure having such an impurity region is called an LDD (Lightly Doped Drain) structure. Further, in the case where the first impurity region overlaps with the gate electrode layer 406, it is referred to as a GOLD (Gate-drain Overlapped LDD) structure.

Next, as illustrated in FIG. 1C, an insulating layer is formed so as to cover the semiconductor layer and the gate electrode layer 406. The insulating layer is formed using an insulating inorganic material, organic material, or the like. As the insulating inorganic material, silicon oxide, silicon nitride, or the like can be used. As the organic material having insulating properties, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or polysilazane can be used. Siloxane is a resin including a bond between silicon (Si) and oxygen (O), and a skeleton structure is formed by a bond between silicon (Si) and oxygen (O). As a substituent that siloxane has, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. Further, a fluoro group may be used for the substituent. Furthermore, an organic group containing at least hydrogen as a substituent and a fluoro group may be used. Polysilazane is formed using a polymer material having a bond of silicon (Si) and nitrogen (N) as a starting material.

FIG. 1C illustrates a mode in which insulating layers are formed in a stacked structure, which are a first insulating layer 414a, a second insulating layer 414b, and a third insulating layer 414c in order from the bottom. The first insulating layer 414a is preferably formed by a plasma CVD method so that it contains a large amount of hydrogen. This is because dangling bonds in the semiconductor layer can be reduced by hydrogen.

The second insulating layer 414b is preferably formed from an organic material. This is because the flatness can be improved. The third insulating layer 414c is preferably formed from an inorganic material. This is for preventing release of moisture or the like from the second insulating layer 414b formed of an organic material or entry of moisture through the second insulating layer 414b.

Next, a contact hole exposing the second impurity region 411 is formed in the insulating layer, and a conductive layer 415 is formed so as to fill the contact hole as shown in FIG. The conductive layer 415 includes a film made of an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), an alloy film using these elements, or an alloy film of these elements and silicon. . The conductive layer 415 can be formed with a single-layer structure or a stacked structure. After that, the conductive layer 415 is patterned into a desired shape, and a source electrode, a drain electrode, and other electrodes are formed at the same time.

In order to reduce contact resistance between the source and drain electrodes and the second impurity region 411, silicide may be formed in the impurity region. For example, a film containing a metal element (typically Ni) is formed over the second impurity region 411, and a thermal annealing method using a furnace annealing furnace, a laser annealing method, or a rapid thermal annealing method (RTA method) is applied. And heat. As a result, a silicide containing the metal element and silicon is formed over the second impurity region, and an on-state current or a mobility can be improved.

In this manner, thin film transistors are completed in the control circuit portion 202 and the memory element region 201. In the control circuit portion 202, a circuit (eg, a writing circuit, a reading circuit, a sense amplifier, an output circuit, a buffer, or the like) is formed using the thin film transistor.

Next, an insulating layer 416 is formed so as to cover the conductive layer 415. The insulating layer 416 can be formed of an insulating inorganic material, organic material, or the like, and may be a single layer or a stacked layer. An inorganic material and an organic material similar to those of the first insulating layer 414a, the second insulating layer 414b, and the third insulating layer 414c can be used.

After that, as shown in FIG. 2A, a contact hole is formed in the insulating layer 416 so that the conductive layer 415 is exposed, and a conductive layer 417 is formed so as to fill the contact hole. The conductive layer 417 can be formed with a single-layer structure or a stacked structure. The conductive layer 417 includes a film made of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), an alloy film using these elements, an alloy film of these elements and silicon, or the like. . The conductive layer 417 can be formed using a light-transmitting material such as indium tin oxide (ITO), indium tin oxide containing silicon oxide, or indium oxide containing 2 to 20% zinc oxide. Thereafter, the conductive layer 417 is patterned into a desired shape. The patterned conductive layer 417 can function as a lower electrode of the memory element.

Note that although the lower electrode of the memory element is formed from the conductive layer 417 in this embodiment mode, it may be formed from the conductive layer 415. That is, the conductive layer 415 serving as a source electrode or a drain electrode of the thin film transistor and the lower electrode of the memory element may be shared.

Next, an insulating layer is formed so as to cover the patterned conductive layer 417, and a plurality of openings are provided. FIG. 2A shows an example in which two openings are provided. An opening 902 that exposes the conductive layer 417 and covers the end of the conductive layer 417 and an opening 901 that exposes the conductive layer 417 and exposes the end of the conductive layer 417 are provided. The partition wall 418 thus formed is formed. The partition wall 418 can be formed of an organic material, an inorganic material, or the like. An inorganic material and an organic material similar to those of the first insulating layer 414a, the second insulating layer 414b, and the third insulating layer 414c can be used. The side surface of the opening of the partition wall 418 preferably has a tapered shape. This is because breakage of a thin film to be formed later can be prevented.

Next, as shown in FIG. 2B, a material layer 408 of the memory element is formed in the opening of the partition wall. The material layer 408 of the memory element can be formed by a droplet discharge method typified by an evaporation method, a spin coating method, or an inkjet method.

The material layer 408 of the memory element can be formed using the same material as the electroluminescent layer included in the light-emitting element; therefore, the memory element and the light-emitting element can be formed using a common process. As the light-emitting element, an organic EL element that uses a layer containing an organic compound as an electroluminescent layer, or an inorganic EL element that uses an inorganic material for a light-emitting body can be used. That is, a memory device having a display function can be formed.

Next, a conductive layer to be the counter electrode 420 is formed. Since the counter electrode 420 can be formed over the entire memory element region, patterning by photolithography is not required. Of course, the counter electrode 420 may be selectively formed by patterning. The counter electrode 420 can function as an upper electrode of the memory element.

Then, the memory element 426 including the conductive layer 417, the memory element material layer 408, and the counter electrode 420 is formed.

More preferably, an insulating layer 421 that functions as a protective film is formed. In order to improve impact resistance, the insulating layer 421 is preferably thick. Therefore, the insulating layer 421 is preferably formed from an organic material such as an epoxy resin or a polyimide resin. In addition, a desiccant may be sprayed in the insulating layer 421 in order to provide hygroscopicity. This is because invasion of moisture can be prevented particularly when the material layer of the memory element is formed using an organic material. By filling and sealing the insulating layer 421 in this manner, unnecessary oxygen in addition to moisture can be prevented.

In this manner, a circuit including a thin film transistor provided in the control circuit portion 202 can be formed. The memory element 426 is formed over the same substrate using a process common to the circuit and provided in the memory element region 201. , And a thin film transistor connected to the memory element 426 can be formed. The memory element is controlled by a thin film transistor. A form in which a thin film transistor is connected to a memory element in this way is called an active matrix type.

In the memory device of the present invention, the memory element 426 and the control circuit can be manufactured over the same substrate using a common process, so that manufacturing cost can be reduced. Furthermore, since a process for mounting a memory element formed by a conventional IC is not necessary, there is no connection failure with the control circuit.

FIG. 3 shows a mode in which an antenna 430 for supplying power or the like to the memory element 426 is provided. In this embodiment mode, a mode in which an antenna 430 is formed in an opening provided in a partition wall is shown.

The antenna 430 can be formed so as to be connected to an electrode 419 which is electrically connected to a thin film transistor provided in the memory element region 201. As a conductive material of the antenna, aluminum (Al), titanium (Ti), silver Mainly selected from elements selected from (Ag), copper (Cu), gold (Au), platinum (Pt), nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum (Mo) An alloy material or a compound material as a component, which is formed in a single layer structure or a laminated structure can be used. The conductive material for the antenna is preferably formed of a low resistance material such as Cu (copper), Ag (silver), Al (aluminum), or the like. Further, in order to reduce the resistance of the antenna 430, the film thickness may be increased. Such an antenna 430 can be formed by a droplet discharge method typified by an evaporation method, a printing method, a plating method, or an inkjet method.

In this manner, by forming the antenna 430 over the same substrate as the thin film transistor, wireless communication with the reader / writer device can be performed. As a result, non-destructive information with multiple values of the memory element 426 can be obtained. For example, when an electromagnetic coupling method or an electromagnetic induction method (for example, 13.56 MHz band) is applied as a signal transmission method in a semiconductor device, an electromagnetic induction due to a change in magnetic field density is used, and thus a conductive layer that functions as an antenna. Are formed in a ring shape (for example, a loop antenna) or a spiral shape (for example, a spiral antenna). In addition, when a microwave method (for example, UHF band (860 to 960 MHz band), 2.45 GHz band, or the like) is applied as a signal transmission method in a semiconductor device, the wavelength of an electromagnetic wave used for signal transmission is considered. The length of the conductive layer functioning as an antenna may be set as appropriate. For example, the conductive layer functioning as an antenna may be linear (for example, a dipole antenna), flat (for example, a patch antenna), or ribbon type. It can be formed into a shape or the like. Further, the shape of the conductive layer functioning as an antenna is not limited to a linear shape, and may be provided in a curved shape, a meandering shape, or a combination thereof in consideration of the wavelength of electromagnetic waves.

Through the above steps, a semiconductor device including a memory element region and an antenna can be completed. After that, a groove is formed as illustrated in FIG. 4A, and an etching agent 441 is introduced into the groove. The glass substrate 401 may be peeled off. At this time, it is preferable that the resin substrate 440 bonded to the insulating layer 421 be used as a support because the glass substrate 401 can be easily peeled off. Note that the resin substrate 440 can also be attached using the bonding function of the insulating layer 421. For the resin substrate 440, a plastic typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES), or a synthetic resin such as acrylic can be used. Such a resin substrate is very thin and flexible. Therefore, the glass substrate 401 can be peeled in order by attaching the resin substrate 440 wound up in a roll shape to the insulating layer 421. Such a process is suitable for mass production.

There is no particular limitation on the etchant 441 as long as the peeling layer 402 can be selectively etched, and for example, a halogen compound can be used. In the case where amorphous silicon or tungsten is used for the separation layer, ClF ₃ (chlorine trifluoride) can be used for the etchant. In the case where silicon oxide is used for the peeling layer, HF (hydrogen fluoride) can be used for the etchant.

  Moreover, it is not limited to the peeling method which selectively etches a peeling layer with an etching agent, You may use another well-known peeling method. For example, if a metal oxide film (tungsten oxide film, molybdenum oxide film, etc.) is provided between a highly heat-resistant substrate and an integrated circuit, and the metal oxide film is weakened and then peeled off, it is provided on the metal oxide film. The integrated circuit including the TFT can be peeled off. For example, the peeling layer can be at least partially broken by laser light irradiation, and the integrated circuit including the TFT can be peeled from the substrate.

Then, as shown in FIG. 4B, a resin substrate 442 is attached instead of the peeled glass substrate 401. Note that the resin substrate 442 can be formed using a material similar to that of the resin substrate 440.

As a result of peeling the glass substrate 401 in this manner, a semiconductor device having a memory element can be made thinner and lighter, flexibility can be improved, and impact resistance can be improved.

Next, the semiconductor device having a memory element is divided for each semiconductor device, and a semiconductor device having a plurality of memory elements can be taken out from one substrate. As a result, the cost of a semiconductor device having a memory element can be reduced.

Further, a protective layer such as a gas barrier layer may be provided on both surfaces of the resin substrates 440 and 442. The protective layer can prevent entry of oxygen and alkali elements, and can improve reliability. The protective layer is formed using an inorganic material containing nitrogen, such as aluminum nitride or a silicon nitride film.

In this embodiment mode, the glass substrate 401 is removed and the resin substrates 440 and 442 are attached. However, the present invention is not limited to this. However, by removing the glass substrate 401, the semiconductor device including the memory element can be reduced in weight and thickness.

Although the thin film transistor described in this embodiment has a structure in which a semiconductor layer, a gate insulating layer, and a gate electrode layer are sequentially stacked over a substrate, the thin film transistor used in the present invention is not limited to this structure. It is also possible to adopt a structure in which an electrode layer, an insulating layer, and a semiconductor layer are sequentially stacked. In addition, the impurity region of the thin film transistor includes a first impurity region (also referred to as a low concentration impurity region) 410 or a second impurity region (also referred to as a high concentration impurity region) 411; It may be a single drain structure.

Alternatively, a multilayer structure in which a plurality of thin film transistors described in this embodiment is stacked may be used. In the case of manufacturing with such a multilayer structure, a low dielectric constant (low-k) material is preferably used as a material for the insulating layer in order to reduce parasitic capacitance generated in the insulating layer between the stacked thin film transistors. For example, in addition to the materials described above, resin materials such as epoxy resins and acrylic resins, organic materials such as siloxane, and the like can be given. By adopting a multilayer structure with reduced parasitic capacitance, it is possible to reduce the area of the memory device, increase the operation speed, and reduce power consumption.

As described above, according to the present invention, the memory cells can be multi-valued in one memory cell. In addition, the recording capacity of the memory area of the semiconductor device can be increased.

(Embodiment 2)
In this embodiment, a method for forming a memory element over a glass substrate as an insulating substrate will be described. An electrode is formed of a laminated film, and a memory element is formed on a plurality of electrode steps. Note that a mode in which a memory element and a circuit (control circuit) for controlling the memory element are formed over the same substrate using a common process is shown. The same steps as those in Embodiment 1 are described using the same drawings and the same reference numerals.

First, as in FIG. 1A, a separation layer 402 is formed over a glass substrate 401. In addition to glass, quartz or the like can be used for the insulating substrate. The separation layer 402 is formed by selectively forming a film containing metal or a film containing silicon over the entire surface of the substrate or selectively.

Next, as in Embodiment 1, an insulating layer 403 is formed so as to cover the separation layer 402. The insulating layer 403 is formed using silicon oxide, silicon nitride, or the like. Then, a semiconductor layer is formed over the insulating layer 403 and crystallized by laser crystallization, thermal crystallization using a metal catalyst, or the like, and then patterned into a desired shape to form an island-shaped semiconductor layer. For laser crystallization, either a continuous wave laser or a pulsed laser can be used.

Next, as in Embodiment 1, a gate insulating layer 405 is formed so as to cover the semiconductor layer. The gate insulating layer 405 is formed using silicon oxide, silicon nitride, or the like. Such a gate insulating layer 405 can be formed by a CVD method, a thermal oxidation method, or the like. Alternatively, the semiconductor layer and the gate insulating layer 405 can be continuously formed by a CVD method and then patterned simultaneously. In this case, impurity contamination at the interface of each layer can be suppressed.

Then, the gate electrode layer 406 is formed as in Embodiment Mode 1. The gate electrode layer 406 is an element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), and copper (Cu), or an alloy material containing the element as a main component. Alternatively, it is formed of a compound material and then patterned into a desired shape. When patterning is performed by photolithography, the width of the gate electrode can be reduced when the resist mask is etched with plasma or the like and the width is reduced. As a result, the performance of the transistor can be improved. The gate electrode layer 406 may have a single-layer structure or a stacked structure.

Next, as in Embodiment 1, an impurity region 407 is formed by adding an impurity element imparting a conductivity type to the semiconductor layer. The impurity region 407 is formed by forming a resist mask by photolithography and adding an impurity element such as phosphorus, arsenic, or boron. Depending on the impurity element, polarities such as an N-channel type and a P-channel type can be created.

Next, as in Embodiment Mode 1, as shown in FIG. 1B, an insulating layer is formed using an insulator containing silicon, for example, silicon nitride, and the insulating layer is subjected to anisotropic etching in the vertical direction. An insulating layer (also referred to as a sidewall) 409 that is in contact with the side surface of the gate electrode is formed. When the sidewall is formed, the gate insulating layer 405 may be etched.

Next, as in Embodiment Mode 1, an impurity is further added to the semiconductor layer, and the first impurity region 410 immediately below the insulating layer (sidewall) 409 and the first impurity region having a higher impurity concentration than the first impurity region. 2 impurity regions 411 are formed.

Subsequently, as in Embodiment Mode 1, an insulating layer is formed so as to cover the semiconductor layer and the gate electrode layer 406. The insulating layer is formed using an insulating inorganic material, organic material, or the like. As the insulating inorganic material, silicon oxide, silicon nitride, or the like can be used. As the organic material having insulating properties, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or polysilazane can be used.

Here, as in FIG. 1C, a mode in which an insulating layer is formed in a stacked structure is shown, and a first insulating layer 414a, a second insulating layer 414b, a third insulating layer 414c, To do. The first insulating layer 414a is preferably formed by a plasma CVD method so that it contains a large amount of hydrogen. This is because dangling bonds in the semiconductor layer can be reduced by hydrogen.
The second insulating layer 414b is preferably formed from an organic material. This is because the flatness can be improved. The third insulating layer 414c is preferably formed from an inorganic material. This is for preventing release of moisture or the like from the second insulating layer 414b formed of an organic material or entry of moisture through the second insulating layer 414b.

Next, a contact hole that exposes the second impurity region 411 is formed in the insulating layer, and a conductive layer 415 is formed so as to fill the contact hole, as in FIG. The conductive layer 415 includes a film made of an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), an alloy film using these elements, or an alloy film of these elements and silicon. . The conductive layer 415 can be formed with a single-layer structure or a stacked structure. After that, the conductive layer 415 is patterned into a desired shape, and a source electrode, a drain electrode, and other electrodes are formed at the same time.

In order to reduce contact resistance between the source and drain electrodes and the second impurity region 411, silicide may be formed in the impurity region. For example, a film containing a metal element (typically Ni) is formed over the second impurity region 411, and a thermal annealing method using a furnace annealing furnace, a laser annealing method, or a rapid thermal annealing method (RTA method) is applied. And heat. As a result, a silicide containing the metal element and silicon is formed over the second impurity region, and an on-state current or a mobility can be improved.

In this manner, thin film transistors are completed in the control circuit portion 202 and the memory element region 201. In the control circuit portion 202, a circuit is formed using the thin film transistor.

Next, as in Embodiment Mode 1, an insulating layer 416 is formed so as to cover the conductive layer 415. The insulating layer 416 can be formed of an insulating inorganic material, organic material, or the like, and may be a single layer or a stacked layer. The insulating layer 416 can be formed using an inorganic material or an organic material similar to those of the first insulating layer 414a, the second insulating layer 414b, and the third insulating layer 414c.

After that, as shown in FIG. 5A, a contact hole is formed so that the insulating layer 416 is selectively etched to expose the conductive layer 415, and the conductive layers 903 and 904 are filled to fill the contact hole. Are stacked. The conductive layers 903 and 904 are films made of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W) elements, alloy films using these elements, alloy films of these elements and silicon, or the like. Have The conductive layers 903 and 904 can be formed using a light-transmitting material such as indium tin oxide (ITO), indium tin oxide containing silicon oxide, or indium oxide containing 2 to 20% zinc oxide. In FIG. 5A, titanium is used for the conductive layer 903 and aluminum is used for 904. By setting the thickness of the conductive layer 904 to be larger than that of the conductive layer 903, two steps having different heights can be provided. The method is shown below.

As shown in FIG. 5B, the conductive layers 903 and 904 are processed into a desired shape. The conductive layers 903 and 904 are processed so that the surface of the conductive layer 904 is exposed. By making the conductive layer 904 thicker than the conductive layer 903, two steps having different heights are provided. Since the breakdown voltage of the memory element is considered to be lower as the level difference is higher, two memories having different breakdown voltages of the memory element can be created separately by providing two steps having different heights using the lower electrode. . That is, the conductive layers 903 and 904 can function not only as a lower electrode of the memory element but also as a step for adjusting a breakdown voltage of the memory element.

Next, as illustrated in FIG. 6A, an insulating layer is formed so as to cover the conductive layers 903 and 904, and a plurality of openings is provided. A partition wall 418 provided with openings 905, 906, and 907 is formed.

As described above, a conductive layer having a plurality of steps and a plurality of openings can be formed.

Note that although the lower electrode of the memory element is formed from the conductive layers 903 and 904 in this embodiment mode, the conductive layer 415 which serves as a source electrode or a drain electrode of the thin film transistor and the lower electrode of the memory element are shared. May be.

Next, as shown in FIG. 6B, a material layer 408 of the memory element is formed in the opening of the partition wall. The material layer 408 of the memory element can be formed by a droplet discharge method typified by an evaporation method, a spin coating method, or an inkjet method.

In addition, since the material layer 408 of the memory element can be formed using the same material as the electroluminescent layer included in the light-emitting element, the memory element and the light-emitting element can be formed over the same substrate using a common process. That is, a memory device having a display function can be formed.

Next, a conductive layer to be the counter electrode 420 is formed. Since the counter electrode 420 can be formed over the entire memory element region, patterning by photolithography is not required. Of course, the counter electrode 420 may be selectively formed by patterning. The counter electrode 420 can function as an upper electrode of the memory element.

Then, the memory element 426 including the conductive layer 417, the memory element material layer 408, and the counter electrode 420 is formed. In one memory cell, three memory elements corresponding to the three openings 905, 906, and 907 are formed, and this memory cell has three kinds of voltage values in which electric resistance changes. The voltage value at which the electrical resistance changes corresponds to a read voltage value (or read current value) or a write voltage value (or write current value).

A change in the read current value of the memory having the plurality of openings is further described in detail using mathematical expressions. The resistance value of the material layer of the memory before the short circuit is Ra, and the contact resistance between the counter electrode and the lower electrode after the short circuit is R1, R2, and R3 with respect to the openings 905, 906, and 907, respectively. Further, the voltage applied to the memory element at the time of reading is set to Vr. The read current value before writing is represented by the following equation.

However, approximation was performed as Ra >> R1, R2, R3. In the first writing, an upper and lower short circuit occurs in the opening 906. The read current value I1 after the short circuit is expressed by the following equation.

However, approximation was performed as Ra >> R1, R2, R3. At this time, the ratio of the current values before and after the first writing is as follows.

Next, in the second writing, an upper and lower short circuit occurs in the opening 905. The read current value I2 after the short circuit can be expressed by the following equation.

At this time, the ratio of the current values before and after the second writing can be expressed by the following equation.

Next, in the third writing, an upper and lower short circuit occurs in the opening 907. The read current value I3 after the short circuit can be expressed by the following equation.

At this time, the ratio of the current values before and after the third writing can be expressed by the following equation.

From equation (5), it can be seen that the relationship of R2> R1 should be satisfied in order to increase the ratio before and after writing. For example, the following method can be considered.

FIG. 13A shows a top view of a memory element and a thin film transistor which are being manufactured. A view cut along a dotted line AB in FIG. 13A is shown in FIG. The thin film transistor includes a gate electrode layer 406, an island-shaped semiconductor layer 404, and a conductive layer 415 functioning as a source electrode or a drain electrode. The conductive layer 415 is electrically connected to the island-shaped semiconductor layer 404 through contact holes 919 and 920 formed in the first insulating layer 414a, the second insulating layer 414b, and the third insulating layer 414c. Yes. One of the conductive layers 415 is electrically connected to the conductive layer 903 through a contact hole 921 formed in the insulating layer 416.

  A conductive layer 904 is stacked over the conductive layer 903, and the area of the conductive layer 903 is larger than that of the conductive layer 904 as illustrated in FIG.

  Further, the end surface (that is, the first step) of the conductive layer 903 is exposed at the opening 905 of the partition wall 418. Further, the end surface (that is, the second step) of the conductive layer 904 is exposed at the opening 906 of the partition wall 418. The second step is larger than the first step. Further, the upper surface of the conductive layer 904 is exposed in the opening 907 of the partition wall 418, and no step is formed. Note that the openings 905, 906, and 907 can be said to be regions surrounded by a part of the partition wall 418.

FIG. 13B shows a state in which the same process as the cross-sectional view shown in FIG. 6A is performed. After that, a material layer of a memory element is formed over the openings 905, 906, and 907, and a conductive layer is formed. Is stacked, the memory element and the thin film transistor illustrated in FIG. 6B are manufactured. For example, a material droplet that becomes a material layer of the memory element is dropped inside the openings 905, 906, and 907 surrounded by the partition wall 418 by an inkjet method.

Since the contact resistance is proportional to the area of the opening, the ratio of the contact resistance can be increased by increasing the area of the opening 905 compared to the opening 906, and the ratio of the current values before and after the second writing can be increased. Can be increased.

Further, as shown in the top view of FIG. 13C, it is also effective to devise the shape of the opening in order to increase the area of the opening. FIG. 13C illustrates an example in which the positions and shapes of the openings 905, 906, and 907 of the partition 418 are devised. The opening 905 in FIG. 13C has a larger area than the opening 905 shown in FIG. 13A, and the opening 907 in FIG. 13C has the opening shown in FIG. The area is larger than that of the portion 907. Further, the openings 905, 906, and 907 in FIG. 13A are arranged in one direction, but the openings 905, 906, and 907 in FIG. 13C are arranged in one direction. Not placed. As shown in FIG. 13C, the position of the opening is not particularly limited and may be freely arranged.

After that, an insulating layer 421 that functions as a protective film is formed. In order to improve impact resistance, the insulating layer 421 is preferably thick. Therefore, the insulating layer 421 is preferably formed from an organic material such as an epoxy resin or a polyimide resin. The insulating layer 421 may be sprayed with a desiccant in the insulating layer 421 in order to have hygroscopicity. This is because invasion of moisture can be prevented particularly when the material layer of the memory element is formed using an organic material. By filling and sealing the insulating layer 421 in this manner, unnecessary oxygen in addition to moisture can be prevented.

In this manner, a circuit including a thin film transistor provided in the control circuit portion 202 can be formed. The memory element 426 is formed over the same substrate as the circuit and is provided in the memory element region 201. A thin film transistor connected to can be formed.

In the semiconductor device of the present invention, since the memory element 426 and the control circuit can be manufactured over the same substrate, manufacturing cost can be reduced. Furthermore, since a process for mounting a memory element formed by a conventional IC is not necessary, there is no connection failure with the control circuit.

FIG. 7 shows a mode in which an antenna 430 for supplying power or the like to the memory element 426 is provided. In this embodiment mode, a mode in which an antenna 430 is formed in an opening provided in a partition wall is shown.

The antenna 430 can be formed so as to be connected to a thin film transistor provided in the memory element region 201, and is a conductive material, preferably a low-resistance material such as Cu (copper), Ag (silver), Al (aluminum), or the like. Formed from. Further, in order to reduce the resistance of the antenna 430, the thickness may be increased. Such an antenna 430 can be formed by a droplet discharge method typified by an evaporation method, a printing method, a plating method, or an inkjet method.

In this manner, by forming the antenna 430 over the same substrate as the circuit, communication with the reader / writer device can be performed wirelessly. As a result, non-destructive information with multiple values of the memory element 426 can be obtained.

Although the memory device can be completed through the above steps, a groove may be formed as shown in FIG. 8A, an etchant 441 may be introduced into the groove, and the glass substrate 401 may be peeled off. . At this time, it is preferable that the resin substrate 440 bonded to the insulating layer 421 be used as a support because the glass substrate 401 can be easily peeled off. Note that the resin substrate 440 can also be attached using the bonding function of the insulating layer 421. For the resin substrate 440, a plastic typified by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethersulfone (PES), or a synthetic resin such as acrylic can be used. Such a resin substrate is very thin and flexible. Therefore, the glass substrate 401 can be peeled in order by attaching the resin substrate 440 wound up in a roll shape to the insulating layer 421. Such a process is suitable for mass production.

There is no particular limitation on the etchant 441 as long as the peeling layer 402 can be selectively etched, and for example, a halogen compound can be used. In the case where amorphous silicon or tungsten is used for the separation layer, ClF ₃ (chlorine trifluoride) can be used for the etchant. In the case where silicon oxide is used for the peeling layer, HF (hydrogen fluoride) can be used for the etchant.

Then, as shown in FIG. 8B, a resin substrate 442 is attached instead of the peeled glass substrate 401. Note that the resin substrate 442 can be formed using a material similar to that of the resin substrate 440.

As a result of peeling the glass substrate 401 in this manner, a semiconductor device having a memory element and an antenna can be reduced in thickness and weight, flexibility can be increased, and impact resistance can be improved.

Next, the semiconductor device having a memory element is divided for each semiconductor device, and a semiconductor device having a plurality of memory elements can be taken out from one substrate. As a result, the cost of a semiconductor device having a memory element can be reduced.

Further, a protective layer such as a gas barrier layer may be provided on both surfaces of the resin substrates 440 and 442. The protective layer can prevent entry of oxygen and alkali elements, and can improve reliability. The protective layer is formed using an inorganic material containing nitrogen, such as aluminum nitride or a silicon nitride film.

In this embodiment mode, the glass substrate 401 is removed and the resin substrates 440 and 442 are attached. However, the present invention is not limited to this. However, by removing the glass substrate 401, the semiconductor device including the memory element can be reduced in weight and thickness.

Although the thin film transistor described in this embodiment has a structure in which a semiconductor layer, a gate insulating layer, and a gate electrode layer are sequentially stacked over a substrate, the thin film transistor used in the present invention is not limited to this structure. It is also possible to adopt a structure in which an electrode layer, an insulating layer, and a semiconductor layer are sequentially stacked. The impurity region of the thin film transistor includes a first impurity region (also referred to as a low-concentration impurity region) 410 and a second impurity region (also referred to as a high-concentration impurity region) 411; It may be a single drain structure.

Alternatively, a multilayer structure in which a plurality of thin film transistors described in this embodiment is stacked may be used. In the case of manufacturing with such a multilayer structure, a low dielectric constant (low-k) material is preferably used as a material for the insulating layer in order to reduce parasitic capacitance generated in the insulating layer between the stacked thin film transistors. For example, in addition to the materials described above, resin materials such as epoxy resins and acrylic resins, organic materials such as siloxane, and the like can be given. By adopting a multilayer structure with reduced parasitic capacitance, it is possible to reduce the area of the memory device, increase the operation speed, and reduce power consumption.

As described above, according to the present invention, the memory cells can be multi-valued in one memory cell. In addition, the recording capacity of the memory area of the semiconductor device can be increased.

Note that this embodiment mode can be freely combined with Embodiment Mode 1.

(Embodiment 3)
In the present embodiment, when a plurality of regions having different breakdown voltages (write voltage values) are formed in a memory cell, the read current margin is widened by utilizing the difference in contact resistance with the counter electrode for each region. Describe the method. The same steps as those in Embodiment 1 are described using the same drawings and the same reference numerals.

When forming multiple regions with different breakdown voltages in the memory cell, separate the lower electrode for each region, and use a conductive layer with a high contact resistance with the upper electrode in the region where the breakdown voltage is low. Use of a conductive layer with low contact resistance in a high voltage region is effective because the ratio of read current between bits can be increased. The method is shown below.

First, as in FIG. 1A, a separation layer 402 is formed over a glass substrate 401. In addition to glass, quartz, silicon, metal, or the like can be used for the insulating substrate. The separation layer 402 is formed by selectively forming a film containing metal or a film containing silicon over the entire surface of the substrate or selectively.

Next, as in Embodiment 1, an insulating layer 403 is formed so as to cover the separation layer 402. The insulating layer 403 is formed using silicon oxide, silicon nitride, or the like. Then, a semiconductor layer is formed over the insulating layer 403 and crystallized by laser crystallization, thermal crystallization using a metal catalyst, or the like, and then patterned into a desired shape to form an island-shaped semiconductor layer. For laser crystallization, either a continuous wave laser or a pulsed laser can be used.

Next, as in Embodiment 1, a gate insulating layer 405 is formed so as to cover the semiconductor layer. The gate insulating layer 405 is formed using silicon oxide, silicon nitride, or the like. Such a gate insulating layer 405 can be formed by a CVD method, a thermal oxidation method, or the like. Alternatively, the semiconductor layer and the gate insulating layer 405 can be continuously formed by a CVD method and then patterned simultaneously. In this case, impurity contamination at the interface of each layer can be suppressed.

Then, the gate electrode layer 406 is formed as in Embodiment Mode 1. The gate electrode layer 406 is an element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), and copper (Cu), or an alloy material containing the element as a main component. Alternatively, it is formed of a compound material and then patterned into a desired shape. When patterning is performed by photolithography, the width of the gate electrode can be reduced when the resist mask is etched with plasma or the like and the width is reduced. As a result, the performance of the transistor can be improved. The gate electrode layer 406 may have a single-layer structure or a stacked structure.

Next, as in Embodiment 1, an impurity region 407 is formed by adding an impurity element imparting a conductivity type to the semiconductor layer. The impurity region 407 is formed by forming a resist mask by photolithography and adding an impurity element such as phosphorus, arsenic, or boron. Depending on the impurity element, polarities such as an N-channel type and a P-channel type can be created.

Next, as in Embodiment Mode 1, as shown in FIG. 1B, an insulating layer is formed using an insulator containing silicon, for example, silicon nitride, and the insulating layer is subjected to anisotropic etching in the vertical direction. An insulating layer (also referred to as a sidewall) 409 that is in contact with the side surface of the gate electrode is formed. When the sidewall is formed, the gate insulating layer 405 may be etched.

Next, as in Embodiment Mode 1, an impurity is further added to the semiconductor layer, and the first impurity region 410 immediately below the insulating layer (sidewall) 409 and the first impurity region having a higher impurity concentration than the first impurity region. 2 impurity regions 411 are formed.

Subsequently, as in Embodiment Mode 1, an insulating layer is formed so as to cover the semiconductor layer and the gate electrode layer 406. The insulating layer is formed using an insulating inorganic material, organic material, or the like. As the insulating inorganic material, silicon oxide, silicon nitride, or the like can be used. As the organic material having insulating properties, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or polysilazane can be used.

Here, as in FIG. 1C, a mode in which an insulating layer is formed in a stacked structure is shown, and a first insulating layer 414a, a second insulating layer 414b, a third insulating layer 414c, To do. The first insulating layer 414a is preferably formed by a plasma CVD method so that it contains a large amount of hydrogen. This is because dangling bonds in the semiconductor layer can be reduced by hydrogen. The second insulating layer 414b is preferably formed from an organic material. This is because the flatness can be improved. The third insulating layer 414c is preferably formed from an inorganic material. This is for preventing release of moisture or the like from the second insulating layer 414b formed of an organic material or entry of moisture through the second insulating layer 414b.

Next, a contact hole that exposes the second impurity region 411 is formed in the insulating layer, and a conductive layer 415 is formed so as to fill the contact hole, as in FIG. The conductive layer 415 includes a film made of an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), an alloy film using these elements, or an alloy film of these elements and silicon. . The conductive layer 415 can be formed with a single-layer structure or a stacked structure. After that, the conductive layer 415 is patterned into a desired shape, and a source electrode, a drain electrode, and other electrodes are formed at the same time.

In order to reduce contact resistance between the source and drain electrodes and the second impurity region 411, silicide may be formed in the impurity region. For example, a film containing a metal element (typically Ni) is formed over the second impurity region 411, and a thermal annealing method using a furnace annealing furnace, a laser annealing method, or a rapid thermal annealing method (RTA method) is applied. And heat. As a result, a silicide containing the metal element and silicon is formed over the second impurity region, and an on-state current or a mobility can be improved.

In this manner, thin film transistors are completed in the control circuit portion 202 and the memory element region 201. In the control circuit portion 202, a circuit is formed using the thin film transistor.

Next, an insulating layer 416 is formed so as to cover the conductive layer 415. The insulating layer 416 can be formed of an insulating inorganic material, organic material, or the like, and may be a single layer or a stacked layer. The insulating layer 416 can be formed using an inorganic material or an organic material similar to those of the first insulating layer 414a, the second insulating layer 414b, and the third insulating layer 414c.

As shown in FIG. 9A, a contact hole is formed so that the insulating layer 416 is selectively etched to expose the conductive layer 415, and the conductive layers 911, 912, and 913 are filled to fill the contact hole. Are laminated. The conductive layers 911, 912, and 913 are films made of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W) elements, alloy films using these elements, or films of these elements and silicon. It has an alloy film. The conductive layers 911, 912, and 913 can be formed using a light-transmitting material such as indium tin oxide (ITO), indium tin oxide containing silicon oxide, or indium oxide containing 2 to 20% zinc oxide.

The contact resistance between the conductive layer 912 after the short circuit and the counter electrode 420 is R1, the contact resistance between the conductive layer 913 and the counter electrode 420 after the short circuit is R2, and the contact resistance between the conductive layer 911 and the counter electrode 420 after the short circuit is R3. It is important to select conductive layers 911 to 913 that satisfy the relationship of R2> R1> R3. The reason is as follows. In FIG. 9A, indium tin oxide (ITO) is used for the conductive layer 911, tungsten (W) is used for 912, and titanium (Ti) is used for 913.

Next, the conductive layers 911, 912, and 913 are processed into desired shapes. The conductive layers 911 to 913 not only function as a lower electrode of the memory element but also function as a step for adjusting the breakdown voltage.

Next, an insulating layer is formed so as to cover the conductive layers 911 to 913, and a plurality of openings are provided. A partition wall 418 provided with openings 914, 915, and 916 is formed.

Note that although the lower electrode of the memory element is formed from the conductive layers 911 to 913 in this embodiment mode, the conductive layer 415 which serves as a source electrode or a drain electrode of the thin film transistor and the lower electrode of the memory element are shared. May be.

Next, as shown in FIG. 9B, a material layer 408 of the memory element is formed in the opening of the partition wall. The material layer 408 of the memory element can be formed by a droplet discharge method typified by an evaporation method, a spin coating method, or an inkjet method.

Further, since the material layer 408 of the memory element can be formed using the same material as the electroluminescent layer included in the light-emitting element, the memory element and the light-emitting element can be formed over the same substrate. That is, a memory device having a display function can be formed.

Next, a conductive layer to be the counter electrode 420 is formed. Since the counter electrode 420 can be formed over the entire memory element region, patterning by photolithography is not required. Of course, the counter electrode 420 may be selectively formed by patterning. The counter electrode 420 can function as an upper electrode of the memory element.

Then, the memory element 426 including the conductive layer 417, the memory element material layer 408, and the counter electrode 420 is formed. In one memory cell, three memory elements corresponding to the three openings 914, 915, and 916 are formed, and this memory cell has three kinds of voltage values in which electric resistance changes.

The first writing, the second writing, and the third writing are performed in descending order of the writing voltage. At the time of the first writing, the upper and lower electrodes are short-circuited in the memory provided in the opening 915 having the largest electrode step. In the case where a semiconductor or an insulator is used as the memory layer, the current flowing through the memory provided in the opening 915 is much higher than the current flowing through the memory provided in the openings 914 and 916 where no short circuit occurs. Since the current is large, the current flowing through the memory cell is predominantly the current flowing through the memory provided in the opening 915. Next, an upper and lower short circuit occurs in the opening 914 during the second writing. Therefore, the current flowing through the entire memory cell is dominated by the sum of the memory provided in the opening 915 and the current flowing through the memory provided in the opening 914. Similarly, the current flowing through the entire memory cell after the third write is the sum of the current flowing through the memories provided in the openings 914, 915, and 916. Since the contact resistances R1 to R3 between the conductive layers 911 to 913 and the counter electrode 420 have a relationship of R2> R1> R3, the ratio between the current value flowing after the first writing and the current value flowing after the second writing is increased. And the reading margin can be increased.

Further details will be described using mathematical expressions. Let Ra be the resistance value of the memory layer before the short circuit. Further, the voltage applied to the memory element at the time of reading is set to Vr. The read current value before writing is expressed by equation (1) shown in the second embodiment. However, approximation was performed as Ra >> R2> R1> R3. In the first writing, an upper and lower short circuit occurs in the opening 915. The read current value I1 after the short circuit is expressed by the equation (2) shown in the second embodiment. However, approximation was performed as Ra >> R2> R1> R3. At this time, the ratio of the current values before and after the first writing is expressed by Equation (3) shown in the second embodiment.

Since there is a relationship of Ra >> R1, it can be said that the ratio of the read current is sufficiently large. Next, in the second writing, an upper and lower short circuit occurs at the opening 914. The read current value I2 after the short circuit is expressed by the equation (4) shown in the second embodiment. However, similarly, approximation was performed as Ra >> R2> R1> R3. At this time, the ratio of the current values before and after the second writing is expressed by Equation (5) shown in the second embodiment. By making R2 sufficiently larger than R1, the ratio of read currents can be increased. Next, in the third writing, an upper and lower short circuit occurs in the opening 916. The read current value I3 after the short circuit is expressed by Equation (6) shown in the second embodiment. However, similarly, approximation was performed as Ra >> R1> R2> R3. At this time, the ratio of the current values before and after the third writing is expressed by Equation (7) shown in the second embodiment. At this time, the ratio of the read current can be increased by making R3 sufficiently larger than R1 and R2.

In the present embodiment, the reading margin is increased by utilizing the difference in contact resistance. However, in addition to the contact resistance, the resistance values of the electrode materials of the conductive layers 911, 912, and 913 serving as the lower electrodes are set to R4 and R5. , R6 can be made of a material satisfying R4> R5> R6, and the reading margin can be increased.

As described above, according to the present invention, the memory cells can be multi-valued in one memory cell. In addition, the recording capacity of the memory device can be increased.

FIG. 10 shows a mode in which an antenna 430 for supplying power or the like to the memory element 426 is provided. In this embodiment mode, a mode in which an antenna 430 is formed in an opening provided in a partition wall is shown.

The antenna 430 can be formed so as to be connected to a thin film transistor provided in the memory element region 201, and is a conductive material, preferably a low-resistance material such as Cu (copper), Ag (silver), Al (aluminum), or the like. Formed from. Further, in order to reduce the resistance of the antenna 430, the thickness may be increased. Such an antenna 430 can be formed by a droplet discharge method typified by an evaporation method, a printing method, a plating method, or an inkjet method.

In this manner, by forming the antenna 430 over the same substrate as the thin film transistor, wireless communication with the reader / writer device can be performed. As a result, non-destructive information with multiple values of the memory element 426 can be obtained.

Note that this embodiment mode can be implemented freely combining with Embodiment Mode 1 or Embodiment Mode 2.

(Embodiment 4)
In this embodiment, a method for forming a memory element over a glass substrate as an insulating substrate will be described. A method for forming a memory element on a plurality of electrode steps will be described. Note that a mode in which a circuit (control circuit) for controlling a memory element is formed over the same substrate is shown. The same steps as those in Embodiment 1 are described using the same drawings and the same reference numerals.

First, as in FIG. 1A, a separation layer 402 is formed over a glass substrate 401. In addition to glass, quartz or the like can be used for the insulating substrate. The separation layer 402 is formed by selectively forming a film containing metal or a film containing silicon over the entire surface of the substrate or selectively.

Next, as in Embodiment 1, an insulating layer 403 is formed so as to cover the separation layer 402. The insulating layer 403 is formed using silicon oxide, silicon nitride, or the like. Then, a semiconductor layer is formed over the insulating layer 403 and crystallized by laser crystallization, thermal crystallization using a metal catalyst, or the like, and then patterned into a desired shape to form an island-shaped semiconductor layer. For laser crystallization, either a continuous wave laser or a pulsed laser can be used.

Next, as in Embodiment 1, a gate insulating layer 405 is formed so as to cover the semiconductor layer. The gate insulating layer 405 is formed using silicon oxide, silicon nitride, or the like. Such a gate insulating layer 405 can be formed by a CVD method, a thermal oxidation method, or the like. Alternatively, the semiconductor layer and the gate insulating layer 405 can be continuously formed by a CVD method and then patterned simultaneously. In this case, impurity contamination at the interface of each layer can be suppressed.

Then, the gate electrode layer 406 is formed as in Embodiment Mode 1. The gate electrode layer 406 is an element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), and copper (Cu), or an alloy material containing the element as a main component. Alternatively, it is formed of a compound material and then patterned into a desired shape. When patterning is performed by photolithography, the width of the gate electrode can be reduced when the resist mask is etched with plasma or the like and the width is reduced. As a result, the performance of the transistor can be improved. The gate electrode layer 406 may have a single-layer structure or a stacked structure.

Next, as in Embodiment Mode 1, the impurity region 407 is formed by adding an impurity element to the semiconductor layer. The impurity region 407 is formed by forming a resist mask by photolithography and adding an impurity element such as phosphorus, arsenic, or boron. Depending on the impurity element, polarities such as an N-channel type and a P-channel type can be created.

Next, as in Embodiment Mode 1, as shown in FIG. 1B, an insulating layer is formed using an insulator containing silicon, for example, silicon nitride, and the insulating layer is subjected to anisotropic etching in the vertical direction. An insulating layer (also referred to as a sidewall) 409 that is in contact with the side surface of the gate electrode is formed. When the sidewall is formed, the gate insulating layer 405 may be etched.

Next, as in Embodiment Mode 1, an impurity is further added to the semiconductor layer, and the first impurity region 410 immediately below the insulating layer (sidewall) 409 and the first impurity region having a higher impurity concentration than the first impurity region. 2 impurity regions 411 are formed.

Subsequently, as in Embodiment Mode 1, an insulating layer is formed so as to cover the semiconductor layer and the gate electrode layer 406. The insulating layer is formed using an insulating inorganic material, organic material, or the like. As the insulating inorganic material, silicon oxide, silicon nitride, or the like can be used. As the organic material having insulating properties, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or polysilazane can be used.

Here, as in FIG. 1C, a mode in which an insulating layer is formed in a stacked structure is shown, and a first insulating layer 414a, a second insulating layer 414b, a third insulating layer 414c, To do. The first insulating layer 414a is preferably formed by a plasma CVD method so that it contains a large amount of hydrogen. This is because dangling bonds in the semiconductor layer can be reduced by hydrogen. The second insulating layer 414b is preferably formed from an organic material. This is because the flatness can be improved. The third insulating layer 414c is preferably formed from an inorganic material. This is for preventing release of moisture or the like from the second insulating layer 414b formed of an organic material or entry of moisture through the second insulating layer 414b.

Next, a contact hole that exposes the second impurity region 411 is formed in the insulating layer, and a conductive layer 415 is formed so as to fill the contact hole, as in FIG. The conductive layer 415 is made of a film made of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), an alloy film using these elements, or an alloy film of these elements and silicon. Have. The conductive layer 415 can be formed with a single-layer structure or a stacked structure. After that, the conductive layer 415 is patterned into a desired shape, and a source electrode, a drain electrode, and other electrodes are formed at the same time.

In order to reduce contact resistance between the source and drain electrodes and the second impurity region 411, silicide may be formed in the impurity region. For example, a film containing a metal element (typically Ni) is formed over the second impurity region 411, and a thermal annealing method using a furnace annealing furnace, a laser annealing method, or a rapid thermal annealing method (RTA method) is applied. And heat. As a result, a silicide containing the metal element and silicon is formed over the second impurity region, and an on-state current or a mobility can be improved.

In this manner, thin film transistors are completed in the control circuit portion 202 and the memory element region 201. In the control circuit portion 202, a circuit is formed using the thin film transistor.

Next, as in Embodiment Mode 1, an insulating layer 416 is formed so as to cover the conductive layer 415. The insulating layer 416 can be formed of an insulating inorganic material, organic material, or the like, and may be a single layer or a stacked layer. The insulating layer 416 can be formed using an inorganic material or an organic material similar to those of the first insulating layer 414a, the second insulating layer 414b, and the third insulating layer 414c.

Next, as illustrated in FIG. 11A, a contact hole is formed in the insulating layer 416 so that the conductive layer 415 is exposed, and conductive layers 903 and 904 are stacked so as to fill the contact hole. The conductive layers 903 and 904 are films made of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W) elements, alloy films using these elements, or alloy films of these elements and silicon. Etc. The conductive layers 903 and 904 can be formed using a light-transmitting material such as indium tin oxide (ITO), indium tin oxide containing silicon oxide, or indium oxide containing 2 to 20% zinc oxide. In FIG. 11A, titanium is used for the conductive layer 903 and aluminum is used for 904.

Next, as illustrated in FIG. 11B, the conductive layer 903 is processed so that the taper angle is smaller than the taper angle of the conductive layer 904. Here, the side surface of the conductive layer 904 is about 90 ° with respect to the substrate surface and is not tapered, but this angle is called a taper angle. The taper angle of the conductive layer 903 is about 45 °. By processing the conductive layers 903 and 904 so that the surface of the conductive layer 904 is exposed, two steps with different taper angles can be provided. Since the breakdown voltage of the memory element is considered to be lower as the taper angle is larger, two memories having different breakdown voltages of the memory element can be created separately by providing two steps having different taper angles using the lower electrode. it can. That is, the conductive layers 903 and 904 can function not only as a lower electrode of the memory element but also as a step for adjusting a breakdown voltage of the memory element.

Next, as illustrated in FIG. 12A, an insulating layer is formed so as to cover the conductive layers 903 and 904, and a plurality of openings is provided. Openings 905, 906, and 907 of the partition wall 418 are formed by etching.

As described above, a conductive layer having a plurality of steps and a plurality of openings can be formed.

Note that although the lower electrode of the memory element is formed from the conductive layers 903 and 904 in this embodiment mode, the conductive layer 415 which serves as a source electrode or a drain electrode of the thin film transistor and the lower electrode of the memory element are shared. May be.

Next, as shown in FIG. 12B, a material layer 408 of the memory element is formed in the opening of the partition wall. The material layer 408 of the memory element can be formed by a droplet discharge method typified by an evaporation method, a spin coating method, or an inkjet method.

Further, since the material layer 408 of the memory element can be formed using the same material as the electroluminescent layer included in the light-emitting element, the memory element and the light-emitting element can be formed over the same substrate. That is, a memory device having a display function can be formed.

Next, a conductive layer to be the counter electrode 420 is formed. Since the counter electrode 420 can be formed over the entire memory element region, patterning by photolithography is not required. Of course, the counter electrode 420 may be selectively formed by patterning. The counter electrode 420 can function as an upper electrode of the memory element.

Then, the memory element 426 including the conductive layer 417, the memory element material layer 408, and the counter electrode 420 is formed. In one memory cell, three memory elements corresponding to the three openings 905, 906, and 907 are formed, and this memory cell has three kinds of voltage values in which electric resistance changes.

As described above, according to the present invention, the memory cells can be multi-valued in one memory cell. In addition, the recording capacity of the memory device can be increased.

  Further, according to Embodiment 1, an antenna for supplying power or the like to the memory element 426 can be provided. The antenna can be formed so as to be connected to an electrode 419 that is electrically connected to a thin film transistor provided in the memory element region 201, and is made of a conductive material, preferably a low-resistance material such as Cu (copper) or Ag (silver). ), Al (aluminum) or the like.

Although the semiconductor device including the memory element region and the antenna can be completed through the above steps, the glass substrate 401 may be peeled off in the step shown in Embodiment Mode 1 after that.

Then, instead of the peeled glass substrate 401, a flexible resin substrate is attached.

As a result of peeling the glass substrate 401 in this manner, a semiconductor device having a memory element can be made thinner and lighter, flexibility can be improved, and impact resistance can be improved.

Note that this embodiment mode can be implemented freely combining with Embodiment Mode 1, Embodiment Mode 2, or Embodiment Mode 3.

(Embodiment 5)
In this embodiment, a method for forming a memory element over a glass substrate as an insulating substrate will be described. A memory element is formed on the plurality of electrode steps. Note that a mode in which a memory element and a circuit (control circuit) for controlling the memory element are formed over the same substrate is shown. The same steps as those in Embodiment 1 are described using the same drawings and the same reference numerals.

First, as in FIG. 1A, a separation layer 402 is formed over a glass substrate 401. In addition to glass, quartz or the like can be used for the insulating substrate. The separation layer 402 is formed by selectively forming a film containing metal or a film containing silicon over the entire surface of the substrate or selectively.

Next, as in Embodiment 1, an insulating layer 403 is formed so as to cover the separation layer 402. The insulating layer 403 is formed using silicon oxide, silicon nitride, or the like. Then, a semiconductor layer is formed over the insulating layer 403 and crystallized by laser crystallization, thermal crystallization using a metal catalyst, or the like, and then patterned into a desired shape to form an island-shaped semiconductor layer. For laser crystallization, either a continuous wave laser or a pulsed laser can be used.

Next, as in Embodiment 1, a gate insulating layer 405 is formed so as to cover the semiconductor layer. The gate insulating layer 405 is formed using silicon oxide, silicon nitride, or the like. Such a gate insulating layer 405 can be formed by a CVD method, a thermal oxidation method, or the like. Alternatively, the semiconductor layer and the gate insulating layer 405 can be continuously formed by a CVD method and then patterned simultaneously. In this case, impurity contamination at the interface of each layer can be suppressed.

Then, the gate electrode layer 406 is formed as in Embodiment Mode 1. The gate electrode layer 406 is an element selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), and copper (Cu), or an alloy material containing the element as a main component. Alternatively, it is formed of a compound material and then patterned into a desired shape. When patterning is performed by photolithography, the width of the gate electrode can be reduced when the resist mask is etched with plasma or the like and the width is reduced. As a result, the performance of the transistor can be improved. The gate electrode layer 406 may have a single-layer structure or a stacked structure.

Next, as in Embodiment Mode 1, the impurity region 407 is formed by adding an impurity element to the semiconductor layer. The impurity region 407 is formed by forming a resist mask by photolithography and adding an impurity element such as phosphorus, arsenic, or boron. Depending on the impurity element, polarities such as an N-channel type and a P-channel type can be created.

Next, as in Embodiment Mode 1, as shown in FIG. 1B, an insulating layer is formed using an insulator containing silicon, for example, silicon nitride, and the insulating layer is subjected to anisotropic etching in the vertical direction. An insulating layer (also referred to as a sidewall) 409 that is in contact with the side surface of the gate electrode is formed. When the sidewall is formed, the gate insulating layer 405 may be etched.

Next, as in Embodiment Mode 1, an impurity is further added to the semiconductor layer, and the first impurity region 410 immediately below the insulating layer (sidewall) 409 and the first impurity region having a higher impurity concentration than the first impurity region. 2 impurity regions 411 are formed.

Subsequently, as in Embodiment Mode 1, an insulating layer is formed so as to cover the semiconductor layer and the gate electrode layer 406. The insulating layer is formed using an insulating inorganic material, organic material, or the like. As the insulating inorganic material, silicon oxide, silicon nitride, or the like can be used. As the organic material having insulating properties, polyimide, acrylic, polyamide, polyimide amide, resist, benzocyclobutene, siloxane, or polysilazane can be used.

Here, as in FIG. 1C, a mode in which an insulating layer is formed in a stacked structure is shown, and a first insulating layer 414a, a second insulating layer 414b, a third insulating layer 414c, To do. The first insulating layer 414a is preferably formed by a plasma CVD method so that it contains a large amount of hydrogen. This is because dangling bonds in the semiconductor layer can be reduced by hydrogen.
The second insulating layer 414b is preferably formed from an organic material. This is because the flatness can be improved. The third insulating layer 414c is preferably formed from an inorganic material. This is for preventing release of moisture or the like from the second insulating layer 414b formed of an organic material or entry of moisture through the second insulating layer 414b.

Next, a contact hole that exposes the second impurity region 411 is formed in the insulating layer, and a conductive layer 415 is formed so as to fill the contact hole, as in FIG. The conductive layer 415 includes a film made of an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), an alloy film using these elements, or an alloy film of these elements and silicon. . The conductive layer 415 can be formed with a single-layer structure or a stacked structure. After that, the conductive layer 415 is patterned into a desired shape, and a source electrode, a drain electrode, and other electrodes are formed at the same time.

In order to reduce contact resistance between the source and drain electrodes and the second impurity region 411, silicide may be formed in the impurity region. For example, a film containing a metal element (typically Ni) is formed over the second impurity region 411, and a thermal annealing method using a furnace annealing furnace, a laser annealing method, or a rapid thermal annealing method (RTA method) is applied. And heat. As a result, a silicide containing the metal element and silicon is formed over the second impurity region, and an on-state current or a mobility can be improved.

In this manner, thin film transistors are completed in the control circuit portion 202 and the memory element region 201. In the control circuit portion 202, a circuit is formed using the thin film transistor.

Next, as in Embodiment Mode 1, an insulating layer 416 is formed so as to cover the conductive layer 415. The insulating layer 416 can be formed of an insulating inorganic material, organic material, or the like, and may be a single layer or a stacked layer. The insulating layer 416 can be formed using an inorganic material or an organic material similar to those of the first insulating layer 414a, the second insulating layer 414b, and the third insulating layer 414c.

After that, as illustrated in FIG. 14A, a contact hole is formed in the insulating layer 416 so that the conductive layer 415 is exposed, and a conductive layer 903 is formed so as to fill the contact hole. The conductive layer 903 includes a film made of an element of aluminum (Al), titanium (Ti), molybdenum (Mo), tungsten (W), an alloy film using these elements, an alloy film of these elements and silicon, or the like. . The conductive layer 903 can be formed using a light-transmitting material such as indium tin oxide (ITO), indium tin oxide containing silicon oxide, or indium oxide containing 2 to 20% zinc oxide. In FIG. 14A, titanium is used for the conductive layer 903.

Next, the conductive layer 903 is processed into a desired shape. Since the breakdown voltage of the memory element is considered to be lower as the level difference is higher, two memories having different breakdown voltages of the memory element can be created separately by providing two steps having different heights using the lower electrode. . First, as shown in FIG. 14B, the conductive layer 903 is processed, and further, as shown in FIG. 14C, part of the processed conductive layer 903 is further processed. For the processing, a method such as half etching may be used. In this manner, two steps having different heights can be provided in the conductive layer 903. The conductive layer 903 can function not only as a lower electrode of the memory element but also as a step for adjusting the breakdown voltage of the memory element. Further, when an exposure method using an exposure mask having a semi-transmissive portion, also called a halftone exposure method, is used, the processing of the conductive layer 903 can be obtained in a short time. In addition, a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function including a diffraction grating pattern may be applied to a photolithography process for forming the conductive layer 903.

Next, as illustrated in FIG. 15A, an insulating layer is formed so as to cover the conductive layer 903, and a plurality of openings is provided. A partition wall 418 provided with openings 905, 906, and 907 is formed.

As described above, a conductive layer having a plurality of steps and a plurality of openings can be formed.

Note that although the lower electrode of the memory element is formed from the conductive layer 903 in this embodiment mode, the conductive layer 415 serving as a source electrode or a drain electrode of the thin film transistor and the lower electrode of the memory element can be shared. Good.

Next, as shown in FIG. 15B, a material layer 408 of the memory element is formed in the opening of the partition wall. The material layer 408 of the memory element can be formed by a droplet discharge method typified by an evaporation method, a spin coating method, or an inkjet method.

Further, since the material layer 408 of the memory element can be formed using the same material as the electroluminescent layer included in the light-emitting element, the memory element and the light-emitting element can be formed over the same substrate using a common process. That is, a memory device having a display function can be formed.

Next, a conductive layer to be the counter electrode 420 is formed. Since the counter electrode 420 can be formed over the entire memory element region, patterning by photolithography is not required. Of course, the counter electrode 420 may be selectively formed by patterning. The counter electrode 420 can function as an upper electrode of the memory element.

Then, the memory element 426 including the conductive layer 417, the memory element material layer 408, and the counter electrode 420 is formed. In one memory cell, three memory elements corresponding to the three openings 905, 906, and 907 are formed, and this memory cell has three kinds of voltage values in which electric resistance changes.

As described above, according to the present invention, the memory cells can be multi-valued in one memory cell. In addition, the recording capacity of the memory device can be increased.

  Further, according to Embodiment 1, an antenna for supplying power or the like to the memory element 426 can be provided. The antenna can be formed so as to be connected to an electrode 419 that is electrically connected to a thin film transistor provided in the memory element region 201, and is made of a conductive material, preferably a low-resistance material such as Cu (copper) or Ag (silver). ), Al (aluminum) or the like.

Although the semiconductor device including the memory element region and the antenna can be completed through the above steps, the glass substrate 401 may be peeled off in the step shown in Embodiment Mode 1 after that.

Then, instead of the peeled glass substrate 401, a flexible resin substrate is attached.

As a result of peeling the glass substrate 401 in this manner, a semiconductor device having a memory element can be made thinner and lighter, flexibility can be improved, and impact resistance can be improved.

Note that this embodiment mode can be implemented freely combining with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 3, or Embodiment Mode 4.

(Embodiment 6)
The configuration of the semiconductor device of this embodiment will be described with reference to FIG. As shown in FIG. 16A, a semiconductor device 620 of the present invention has a function of communicating data without contact, and includes a power supply circuit 611, a clock generation circuit 612, a data demodulation / modulation circuit 613, and other circuits. A control circuit 614 to be controlled, an interface circuit 615, a memory circuit 616 having a plurality of memory cells capable of storing multi-value information, a data bus 617, an antenna (antenna coil) 618, a sensor 621, and a sensor circuit 622 are provided.

The power supply circuit 611 is a circuit that generates various power supplies to be supplied to each circuit inside the semiconductor device 620 based on the AC signal input from the antenna 618. The clock generation circuit 612 is a circuit that generates various clock signals to be supplied to each circuit inside the semiconductor device 620 based on the AC signal input from the antenna 618. The data demodulation / modulation circuit 613 has a function of demodulating / modulating data communicated with the reader / writer 619. The control circuit 614 has a function of controlling the memory circuit 616 including a plurality of memory cells that can store multilevel information. The antenna 618 has a function of transmitting and receiving electromagnetic waves or radio waves. The reader / writer 619 controls communication with the semiconductor device, control, and processing related to the data. The semiconductor device is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and hardware dedicated to cryptographic processing are added.

A memory circuit 616 including a plurality of memory cells capable of storing multi-value information includes a memory element in which an insulating layer that is changed by an external electric action is sandwiched between a pair of conductive layers. Note that the memory circuit 616 including a plurality of memory cells that can store multilevel information may include only a memory element in which an insulating layer is sandwiched between a pair of conductive layers, or a memory circuit having another structure. You may have. The memory circuit having another configuration corresponds to one or more selected from, for example, DRAM, SRAM, mask ROM, PROM, EPROM, EEPROM, and flash memory.

The sensor 621 is formed of a semiconductor element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode. The sensor circuit 622 detects a change in impedance, reactance, inductance, voltage, or current, performs analog / digital conversion (A / D conversion), and outputs a signal to the control circuit 614.

Next, one mode of an electronic device in which the semiconductor device of the present invention is mounted will be described with reference to the drawings. An electronic device illustrated here is a mobile phone, which includes housings 700 and 706, a panel 701, a housing 702, a printed wiring board 703, operation buttons 704, and a battery 705 (see FIG. 16B). The panel 701 is detachably incorporated in the housing 702, and the housing 702 is fitted to the printed wiring board 703. The shape and size of the housing 702 are changed as appropriate in accordance with the electronic device in which the panel 701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 703, and the semiconductor device of the present invention can be used as one of them. The plurality of semiconductor devices mounted on the printed wiring board 703 have any of functions of a controller, a central processing unit (CPU), a memory, a power supply circuit, a sound processing circuit, a transmission / reception circuit, and the like.

The panel 701 is fixedly connected to the printed wiring board 703 via the connection film 708. The panel 701, the housing 702, and the printed wiring board 703 are housed in the housings 700 and 706 together with the operation buttons 704 and the battery 705. A pixel region 709 included in the panel 701 is arranged so as to be visible from an opening window provided in the housing 700.

As described above, the semiconductor device of the present invention is characterized in that it is small, thin, and lightweight. With the above characteristics, the limited space inside the casings 700 and 706 of the electronic device can be used effectively. .

In the semiconductor device of the present invention, as a memory included in the semiconductor device, an insulating layer (that is, a layer containing an organic compound sandwiched between a pair of electrodes) that changes due to an external electric action is provided between a pair of conductive layers. Since a memory element with a simple structure sandwiched is used, an electronic device using an inexpensive semiconductor device can be provided. In addition, since the semiconductor device of the present invention includes a plurality of memory cells capable of storing multi-value information and can be easily integrated, an electronic apparatus using a semiconductor device having a memory circuit with a large capacity per unit area Can be provided.

Note that the housings 700 and 706 are examples of the appearance of a mobile phone, and the electronic device according to this embodiment can be changed into various modes depending on functions and uses.

Another embodiment of an electronic device mounted with the semiconductor device of the present invention will be described with reference to FIG. An example is a portable music playback device provided with a recording medium, which includes a main body 2901, a display unit 2903, a recording medium 2907 (card type memory, small large-capacity memory, etc.) reading unit, operation keys 2902, 2906. The headphone speaker unit 2405 connected to the connection cord 2904 is included. Since the semiconductor device of the present invention includes a plurality of memory cells capable of storing multi-value information and can be easily integrated, a storage circuit having a large capacity per unit area is applied to the recording medium 2907 to reduce the weight. Can be realized. Further, according to the present invention, since the memory and the antenna can be formed over the same substrate, the music reproducing device can be downsized by integrating the antenna in the storage medium 2907. By integrating the antennas, the portable music player can communicate with the reader / writer device wirelessly.

Another embodiment of an electronic device mounted with the semiconductor device of the present invention will be described with reference to FIG. An example here is a portable computer that can be attached to an arm, and includes a main body 2911, a display portion 2912, a switch 2913, operation keys 2914, a speaker portion 2915, a semiconductor integrated circuit 2916, and the like. The display portion 2912 can perform various inputs and operations as a touch panel. Although not shown here, the portable computer has a cooling function for suppressing a temperature rise of the portable computer and a communication function such as an infrared port and a high-frequency circuit.

It is preferable that the portion that touches the person's arm 2910 is covered with a film such as plastic so that the person's arm 2910 does not feel uncomfortable. Therefore, it is preferable to form the semiconductor integrated circuit 2916 (memory, CPU, and the like) and the display portion 2912 over the plastic substrate. Further, the outer shape of the main body 2911 may be curved along the human arm 2910. The present invention can store multi-value information, and a memory circuit having a large capacity per unit area is formed on a flexible resin substrate and used as a part of a semiconductor integrated circuit 2916. A computer can be realized.

Further, the memory circuit of the present invention is applied to a semiconductor integrated circuit 2916 (a memory, a CPU, a high-frequency circuit, or the like) incorporated in a portable computer, a control circuit for a speaker portion 2915, and the like, so that mounting parts are reduced. A portable computer can be realized. For example, as shown in Embodiment Mode 1, by integrating a memory and an antenna over the same substrate, a portable computer can communicate with a reader / writer device wirelessly. In addition, a memory circuit having a plurality of memory cells capable of storing multi-value information according to the present invention and having a large capacity per unit area can reduce manufacturing costs, so that a portable computer can be provided at low cost. it can.

This embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 3, Embodiment Mode 4, or Embodiment Mode 5.

(Embodiment 7)
According to the present invention, a semiconductor device which has a plurality of memory cells capable of storing multi-value information and functions as a wireless chip can be formed. Applications of wireless chips are wide-ranging. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 18A), packaging containers (wrapping paper, Bottle, etc., see FIG. 18C), recording medium (DVD software, video tape, etc., see FIG. 18B), vehicles (bicycles, etc., see FIG. 18D), personal items (bags, glasses, etc.) ), Used on goods such as foods, plants, animals, human bodies, clothing, daily necessities, electronic devices, etc. and luggage tags (see FIGS. 18E and 18F). be able to. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like.

The semiconductor device 910 of the present invention is fixed to an article by being mounted on a printed board, pasted on a surface, or embedded. For example, a book is embedded in paper, or a package made of an organic resin is embedded in the organic resin and fixed to each article. Since the semiconductor device 910 of the present invention realizes a small size, a thin shape, and a light weight, the design of the article itself is not impaired even after being fixed to the article. Further, by providing the semiconductor device 910 of the present invention to bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and forgery can be prevented by utilizing this authentication function. Can do. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

In addition, this embodiment mode can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 3, Embodiment Mode 4, Embodiment Mode 5, or Embodiment Mode 6.

According to the present invention, variations in writing voltage and reading voltage in a plurality of memory cells can be reduced by precisely processing an electrode of a memory element, and a high yield can be achieved in a mass production process.

10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 10A and 10B illustrate a manufacturing process of a semiconductor device of the present invention. 9A and 9B illustrate a manufacturing process of a semiconductor device of Embodiment 2. 9A and 9B illustrate a manufacturing process of a semiconductor device of Embodiment 2. 9A and 9B illustrate a manufacturing process of a semiconductor device of Embodiment 2. 9A and 9B illustrate a manufacturing process of a semiconductor device of Embodiment 2. 9A and 9B illustrate a manufacturing process of a semiconductor device of Embodiment 3. 9A and 9B illustrate a manufacturing process of a semiconductor device of Embodiment 3. 9A and 9B illustrate a manufacturing process of a semiconductor device of Embodiment 4; 9A and 9B illustrate a manufacturing process of a semiconductor device of Embodiment 4; FIG. 6 is a cross-sectional view and a top view of the semiconductor device of the second embodiment. FIG. 6 illustrates a manufacturing process of a semiconductor device of Embodiment 5; FIG. 6 illustrates a manufacturing process of a semiconductor device of Embodiment 5; 8A and 8B illustrate a structure example of a semiconductor device of the present invention and an electronic device having the structural example. 6A and 6B illustrate an electronic device including a semiconductor device of the present invention. 4A and 4B each illustrate a usage pattern of a semiconductor device of the invention.

Explanation of symbols

201 Memory element region 202 Control circuit portion 401 Glass substrate 402 Release layer 403 Insulating layer 404 Island-like semiconductor layer 405 Gate insulating layer 406 Gate electrode layer 407 Impurity region 408 Material layer 409 Insulating layer (side wall)
410 first impurity region 411 second impurity region 414a first insulating layer 414b second insulating layer 414c third insulating layer 415 conductive layer 416 insulating layer 417 conductive layer 418 partition 419 electrode 420 counter electrode 421 insulating layer 426 Memory element 430 Antenna 440 Resin substrate 441 Etching agent 442 Resin substrate 611 Power supply circuit 612 Clock generation circuit 613 Data demodulation / modulation circuit 614 Control circuit 615 Interface circuit 616 Memory circuit 617 Data bus 618 Antenna (antenna coil)
619 Reader / writer 620 Semiconductor device 621 Sensor 622 Sensor circuit 700 Case 701 Panel 702 Housing 703 Printed wiring board 704 Operation button 705 Battery 706 Case 708 Connection film 709 Pixel region 901 Opening portion 902 Opening portion 903 Conductive layer 904 Conductive layer 905 Opening Portion 906 Opening portion 907 Opening portion 910 Semiconductor device 911 Conductive layer 912 Conductive layer 913 Conductive layer 914 Opening portion 915 Opening portion 916 Opening portion 919 Contact hole 920 Contact hole 921 Contact hole 2901 Main body 2902 Operation key 2903 Display portion 2904 Connection code 2905 Speaker Section 2906 Operation key 2907 Storage medium 2910 Human arm 2911 Main body 2912 Display section 2913 Switch 2914 Operation key 2915 Speaker section 2 916 Semiconductor integrated circuit

Claims (9)

A first memory element;
A second memory element;
A plurality of memory cells having one thin film transistor electrically connected to both the first memory element and the second memory element;
The first memory element and the second memory element include a common first electrode, a common material layer provided on the first electrode, and a common first electrode provided on the material layer . It has two electrodes,
A partition is provided between the first memory element and the second memory element,
The partition is provided between the first electrode and the material layer,
In the first memory element, an end portion of the first electrode, the material layer, and the second electrode overlap,
In the second memory element, a flat portion that is not the end of the first electrode, the material layer, and the second electrode overlap,
The semiconductor device, wherein the memory cell stores a plurality of bits. A first memory element;
A second memory element;
A plurality of memory cells having one thin film transistor electrically connected to both the first memory element and the second memory element;
The first memory element and the second memory element include a common first electrode having a first step and a second step, a common material layer provided on the first electrode, and have a common second electrodes provided on the material layer,
A partition is provided between the first memory element and the second memory element,
The partition wall is provided between the first step and the second step and between the first electrode and the material layer,
In the first memory element, the first step of the first electrode, the material layer, and the second electrode overlap,
In the second memory element, the second step of the first electrode, the material layer, and the second electrode overlap,
The memory cell stores multi-value information. A first memory element;
A second memory element;
A plurality of memory cells having one thin film transistor electrically connected to both the first memory element and the second memory element;
The first memory element and the second memory element include a common first electrode having a stacked structure including a first layer and a second layer, and a common provided on the first electrode. material layer, and have a common second electrodes provided on said material layer,
A partition is provided between the first memory element and the second memory element,
The end of the first layer and the end of the second layer do not match,
The partition is provided between an end of the first layer and an end of the second layer, and between the first electrode and the material layer,
In the first memory element, an end of the first layer of the first electrode, the material layer, and the second electrode overlap with each other,
In the second memory element, an end of the second layer of the first electrode, the material layer, and the second electrode overlap,
The memory cell stores multi-value information. Oite to claim 2, wherein a different from the taper angle of the taper angle of the first step and the second step. In claim 2 or the claims 4, a flat portion of the first electrode, the material layer, and wherein the third memory device and the second electrode are overlapped to have said memory cells Semiconductor device. 4. The semiconductor device according to claim 3 , wherein a taper angle at an end portion of the first layer is different from a taper angle at an end portion of the second layer. According to claim 3 or claim 6, wherein said flat portion of the first layer or the second layer of the first electrode, the material layer and the second electrode and overlap the third memory device The memory cell has a semiconductor device. Claim 3, wherein a different in claim 6 or claim 7, the film thickness of the first layer and the thickness of the second layer. In any one of claims 1 to 8, an antenna, a semiconductor device and performs wireless communication.

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