JP4771654B2 - メモリバンクへのアドレスのマッピングをするメモリコントローラ - Google Patents

メモリバンクへのアドレスのマッピングをするメモリコントローラ Download PDF

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Publication number
JP4771654B2
JP4771654B2 JP2003379250A JP2003379250A JP4771654B2 JP 4771654 B2 JP4771654 B2 JP 4771654B2 JP 2003379250 A JP2003379250 A JP 2003379250A JP 2003379250 A JP2003379250 A JP 2003379250A JP 4771654 B2 JP4771654 B2 JP 4771654B2
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bank
memory
address
banks
stride
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JP2004164641A (ja
JP2004164641A5 (enExample
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マーク・エイ・ヒープ
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Hewlett Packard Development Co LP
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Hewlett Packard Development Co LP
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Dram (AREA)
JP2003379250A 2002-11-12 2003-11-10 メモリバンクへのアドレスのマッピングをするメモリコントローラ Expired - Lifetime JP4771654B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/292,144 US6912616B2 (en) 2002-11-12 2002-11-12 Mapping addresses to memory banks based on at least one mathematical relationship
US10/292,144 2002-11-12

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JP2004164641A JP2004164641A (ja) 2004-06-10
JP2004164641A5 JP2004164641A5 (enExample) 2006-11-24
JP4771654B2 true JP4771654B2 (ja) 2011-09-14

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US (1) US6912616B2 (enExample)
JP (1) JP4771654B2 (enExample)

Cited By (1)

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US12443346B2 (en) 2021-12-24 2025-10-14 Socionext Inc. Memory access method and memory access control device

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JP3950831B2 (ja) * 2003-09-16 2007-08-01 エヌイーシーコンピュータテクノ株式会社 メモリインタリーブ方式
US7281114B2 (en) * 2003-12-26 2007-10-09 Tdk Corporation Memory controller, flash memory system, and method of controlling operation for data exchange between host system and flash memory
US7779198B2 (en) * 2004-11-23 2010-08-17 Efficient Memory Technology Method and apparatus of multiple abbreviations of interleaved addressing of paged memories
US8190809B2 (en) * 2004-11-23 2012-05-29 Efficient Memory Technology Shunted interleave for accessing plural memory banks, particularly those having partially accessed cells containing data for cache lines
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US8533430B2 (en) * 2005-04-14 2013-09-10 International Business Machines Corporation Memory hashing for stride access
WO2006129518A1 (ja) * 2005-05-30 2006-12-07 Megachips Corporation メモリアクセス方法
US7898551B2 (en) * 2006-06-20 2011-03-01 Via Technologies, Inc. Systems and methods for performing a bank swizzle operation to reduce bank collisions
US8072463B1 (en) * 2006-10-04 2011-12-06 Nvidia Corporation Graphics system with virtual memory pages and non-power of two number of memory elements
US7932912B1 (en) 2006-10-04 2011-04-26 Nvidia Corporation Frame buffer tag addressing for partitioned graphics memory supporting non-power of two number of memory elements
US7884829B1 (en) 2006-10-04 2011-02-08 Nvidia Corporation Partitioned graphics memory supporting non-power of two number of memory elements
US20090193227A1 (en) * 2008-01-25 2009-07-30 Martin John Dowd Multi-stream on-chip memory
WO2009125572A1 (ja) * 2008-04-08 2009-10-15 パナソニック株式会社 メモリ制御回路及びメモリ制御方法
JP5267166B2 (ja) * 2009-01-30 2013-08-21 ソニー株式会社 インターフェース装置、演算処理装置、インターフェース生成装置、および回路生成装置
US20100262751A1 (en) * 2009-04-09 2010-10-14 Sun Microsystems, Inc. Memory Control Unit Mapping Physical Address to DRAM Address for a Non-Power-of-Two Number of Memory Ranks Using Lower Order Physical Address Bits
JP5365336B2 (ja) * 2009-05-01 2013-12-11 ソニー株式会社 メモリ制御装置およびメモリ制御方法
US9348751B2 (en) * 2009-09-25 2016-05-24 Nvidia Corporation System and methods for distributing a power-of-two virtual memory page across a non-power-of two number of DRAM partitions
JP2011175450A (ja) * 2010-02-24 2011-09-08 Renesas Electronics Corp メモリアクセスシステムおよびメモリアクセス制御方法
US8799553B2 (en) 2010-04-13 2014-08-05 Apple Inc. Memory controller mapping on-the-fly
US9477597B2 (en) * 2011-03-25 2016-10-25 Nvidia Corporation Techniques for different memory depths on different partitions
US8701057B2 (en) 2011-04-11 2014-04-15 Nvidia Corporation Design, layout, and manufacturing techniques for multivariant integrated circuits
US9529712B2 (en) 2011-07-26 2016-12-27 Nvidia Corporation Techniques for balancing accesses to memory having different memory types
US9405681B2 (en) 2011-12-28 2016-08-02 Intel Corporation Workload adaptive address mapping
US9009570B2 (en) * 2012-06-07 2015-04-14 Micron Technology, Inc. Integrity of an address bus
US9323608B2 (en) 2012-06-07 2016-04-26 Micron Technology, Inc. Integrity of a data bus
US9268691B2 (en) * 2012-06-11 2016-02-23 Intel Corporation Fast mechanism for accessing 2n±1 interleaved memory system
US20140122807A1 (en) * 2012-10-31 2014-05-01 Hewlett-Packard Development Company, Lp. Memory address translations
KR102202575B1 (ko) * 2013-12-31 2021-01-13 삼성전자주식회사 메모리 관리 방법 및 장치
US9424181B2 (en) 2014-06-16 2016-08-23 Empire Technology Development Llc Address mapping for solid state devices
JP2016218721A (ja) 2015-05-20 2016-12-22 ソニー株式会社 メモリ制御回路およびメモリ制御方法
CN106356088A (zh) * 2015-07-15 2017-01-25 深圳市中兴微电子技术有限公司 一种数据处理方法及其装置
US10417198B1 (en) * 2016-09-21 2019-09-17 Well Fargo Bank, N.A. Collaborative data mapping system
US10817420B2 (en) * 2018-10-30 2020-10-27 Arm Limited Apparatus and method to access a memory location
US11669271B2 (en) * 2020-04-15 2023-06-06 Advanced Micro Devices, Inc. Memory operations using compound memory commands
CN112286844B (zh) * 2020-10-30 2022-09-02 烽火通信科技股份有限公司 一种可适配业务地址映射的ddr4控制方法及装置
WO2025128599A1 (en) * 2023-12-12 2025-06-19 Microchip Technology Incorporated Determining physical addresses of memory devices using division by prime numbers

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JPS6265148A (ja) * 1985-09-17 1987-03-24 Fujitsu Ltd メモリアクセス制御方式
JPS63225837A (ja) * 1987-03-13 1988-09-20 Fujitsu Ltd 距離付きベクトルアクセス方式
US5377340A (en) * 1991-06-18 1994-12-27 Hewlett-Packard Company Method and apparatus for memory interleaving using an improved hashing scheme
US6070227A (en) 1997-10-31 2000-05-30 Hewlett-Packard Company Main memory bank indexing scheme that optimizes consecutive page hits by linking main memory bank address organization to cache memory address organization
US6272594B1 (en) 1998-07-31 2001-08-07 Hewlett-Packard Company Method and apparatus for determining interleaving schemes in a computer system that supports multiple interleaving schemes
US6851039B2 (en) * 2002-09-30 2005-02-01 Lucent Technologies Inc. Method and apparatus for generating an interleaved address

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12443346B2 (en) 2021-12-24 2025-10-14 Socionext Inc. Memory access method and memory access control device

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Publication number Publication date
US20040093457A1 (en) 2004-05-13
JP2004164641A (ja) 2004-06-10
US6912616B2 (en) 2005-06-28

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