JP4763242B2 - Solid-state imaging device and manufacturing method thereof - Google Patents

Description

  The present invention. The present invention relates to a solid-state imaging device that outputs a voltage in accordance with the amount of received light for imaging and a manufacturing method thereof, and is particularly suitable for application to a CMOS image sensor.

  Solid-state imaging devices are used in various fields such as digital video cameras, digital still cameras, mobile phones with cameras, surveillance cameras, and in-vehicle cameras. Charge-coupled devices (hereinafter referred to as CCDs) are well known. . Further, as a solid-state imaging device having a structure different from that of a CCD, as disclosed in Non-Patent Document 1, a CMOS image sensor, an active pixel sensor type (or an in-pixel amplification type sensor, hereinafter referred to as APS) CMOS is disclosed. Image sensors are known.

  Since a CMOS image sensor can be created in the same process as a CMOS used for signal processing, it can be easily mixed with peripheral circuits, only one type of power supply is required, low power consumption, and high-speed response is possible. There is an advantage that a false image called smear does not occur. On the other hand, since it has been considered that the image quality is inferior to that of a CCD, so far, in applications where the image quality is important, such as a digital video camera or a digital still camera, the back of the CCD is often used.

In order to expand the application of CMOS image sensors, improving the image quality is one of the most important issues. For that purpose, it is necessary to improve various characteristics, but it is considered to be particularly important to suppress a current that is generated when light called a dark current is not being irradiated.
In the operation of the CMOS image sensor, a charge is accumulated in the photodiode by applying a reverse bias during normal initialization (reset). Next, the photodiode is disconnected from the power supply by turning off the MOS type reset element. Then, the charge accumulated in the photodiode is reduced by a current generated by the exposure to light, and a correlation detection circuit or the like is used to detect the difference between the retained charge at the time of initialization and after the exposure time.

  Here, when the dark current is large, the charge accumulated in the photodiode is reduced even when bright light is not incident. Therefore, if the exposure time is increased, whitish unevenness and scratches can be formed on the black portion of the image. In addition, since the dark current characteristic varies from pixel to pixel, the fixed noise increases, and the component in which the dark current fluctuates randomly becomes part of the random noise, which causes deterioration in image quality.

Conventionally, in order to reduce the dark current of the CMOS image sensor, various attempts have been made to devise the structure by paying attention to the photodiode portion. For example, Patent Document 1 discloses a method of forming a depletion layer in an active region at a distance L from a LOCOS (Local Oxidation of Silicon) end, which is one of the main sources of dark current. Patent Document 2 discloses a method in which the surface is covered with a p + layer having a conductivity type opposite to the n-type of the photodiode, and the depletion layer is disposed inside the substrate as much as possible. Non-Patent Document 2 discloses a method for devising conditions of a manufacturing process that generates stress. Non-Patent Document 3 discloses a method for reducing damage to the substrate surface by anisotropic dry etching. These measures were effective in reducing the dark current, although to some extent.
JP-A-10-98176 Japanese Patent Laid-Open No. 2-87668 Eric Fossum “Active Pixel Sensors: Are CCD's Dinauers?”, CCD and Solid state Optical Sensors III Proc. SPIE, 2-14, 1993, Eric Fossum “CMOS Imager Sensor Electronic Camera-On-A-Chip”, IEEE Trans. Elec. Dev. , Vol. 44, 1689-1698, 1997 IEEE Trans. Elec. Dev, Vol. 43, no. 11 (1996) p1989 International Symposium on Plasma Process-Induced Damage (1996) p198-201

However, the above countermeasure is focused on a photodiode that generates a photocurrent, and no dark current countermeasure has been taken by focusing on an element in contact with the photodiode, for example, a reset element.
Accordingly, an object of the present invention is to know the location and amount of dark current generation in a photodiode and an element adjacent to the photodiode as quantitatively as possible, and to the photodiode proximity element that has not been clearly treated until now. It is to provide a solid-state imaging device capable of reducing the dark current with a simple and practical measure that suppresses the dark current derived from the source, and has few changes to the existing CMOS process, and a manufacturing method thereof.

In order to solve the above-described problem, according to the solid-state imaging device according to claim 1, a photodiode for detecting light, a resetting device for supplying a charge for initializing the photodiode, and the photo In the solid-state imaging device having an element for detecting the potential of the diode, an element for selecting the pixel, and an element isolation region formed by selectively oxidizing the semiconductor substrate in the pixel, the reset The element is a MOS transistor (metal oxide film semiconductor element) having an asymmetric structure , and the high-concentration impurity region of the first conductivity type sandwiched between the exposure control element and the reset element is the high-concentration impurity region. The low-concentration first conductivity type impurity region covers the high-concentration impurity region and the element isolation region end so as to include the low-concentration impurity region. End of the reset element side of the impurity region, the high beyond the end of the doped region at a position that has entered the gate lower side of the reset element, and the dark current is minimized The reset element is located near the gate end on the high-concentration impurity region side.

According to a solid-state image pickup device according to claim 2, in the solid-state image pickup device according to claim 1, the semiconductor substrate is silicon.
The solid-state imaging device according to claim 3 is characterized in that, in the solid-state imaging device according to claim 1, the element forming the impurity region for covering the edge of the high- concentration impurity region is phosphorus.

According to the solid-state imaging device of claim 4, the photodiode for detecting light, the resetting device for supplying a charge for initializing the photodiode, and the potential of the photodiode are detected. In the solid-state imaging device, the pixel includes: an element for selecting a pixel; an element for controlling exposure; and an element isolation region formed by selectively oxidizing a semiconductor substrate. The reset element is a MOS transistor (metal oxide film semiconductor element) having an asymmetric structure , and the high-concentration impurity region of the first conductivity type sandwiched between the exposure control element and the reset element is the high-concentration impurity region. The first conductive type impurity region having a lower concentration than the impurity region is configured to cover the high concentration impurity region end and the element isolation region end so as to cover the high concentration impurity region. End of the reset element side of the impurity regions of the concentration is a position that has entered the gate lower side of the high concentration impurity regions end the reset element beyond the, and, a dark current is minimized The reset element is located near the gate end on the high-concentration impurity region side.

The solid-state imaging device according to claim 5 is characterized in that in the solid-state imaging device according to claim 4 , the semiconductor substrate is silicon.
According to the solid-state imaging device of claim 6, the element forming the impurity region for covering the edge of the high-concentration impurity region is phosphorus in the solid-state imaging device of claim 4 .

According to the method of manufacturing a solid-state imaging device according to claim 7, the step of selectively oxidizing the semiconductor substrate on the first conductivity type semiconductor substrate to form an element isolation region, and the second step A step of forming a photosensitive portion by introducing a conductivity type impurity; and a MOS transistor (metal oxide semiconductor device) which is an element for introducing a first conductivity type impurity into the semiconductor substrate to initialize the photosensitive portion. ), A step of forming an insulating film on the semiconductor substrate, a step of forming a gate electrode of the initialization element on the insulating film, and a step of forming the initialization element of the second conductivity type. A step of forming a diffusion layer, a step of ion implantation of a second conductivity type with a dose lower than the diffusion layer into a region covering the diffusion layer on the photosensitive portion side of the initialization element and the end of the element isolation region; In the ion implantation step. The region for injection, does not enter the gate immediately below the initialization element, its end, the gate and the dark current a slightly outer position than the gate terminal of the initialization element is minimized It is in the position near the end.

According to a method for manufacturing a solid-state image pickup device according to claim 8, in the method for manufacturing a solid-state image pickup device according to claim 7 , the second conductive type impurity is introduced into the first conductive type semiconductor substrate to form the photosensitive portion. The step of forming and the second conductivity type ion implantation of the region covering the diffusion layer on the photosensitive portion side of the initialization element and the end of the element isolation region are performed in the same step.

  As described above, according to the present invention, with respect to the diffusion layer end of the element in contact with the photodiode such as the reset MOS, which is considered as one of the main dark current generation locations, the diffusion layer end and the element isolation region end vicinity region By taking measures to prevent the formation of a depletion layer having a steep electric field gradient, the dark current of the CMOS image sensor can be reduced and the image quality can be improved. In addition, the manufacturing method of the present invention can be created by changing or adding a part of the conventional CMOS process.

  Hereinafter, an embodiment of the present invention will be described by taking a case where a 3-transistor CMOS image sensor is formed on a silicon substrate as an example. The present invention is not limited to this structure. In other pixel structures, the depletion layer of the high-concentration diffusion layer of the MOS type element having a function of holding charges in the vicinity of the photodiode is exposed on the surface. The present invention can be applied to suppress dark current in a portion where the current is present.

FIG. 1 is a circuit diagram showing an example of a pixel portion of an APS type CMOS image sensor.
In FIG. 1, an APS type CMOS image sensor includes a photodetection photodiode 11, a MOS type reset element 12 for initializing the photodiode 11, and a source for converting the charge and potential of the photodiode 11 into an output voltage. A follower element 13 and a pixel selection element 14 are provided.

2 is a plan view showing an example of a pixel layout of the APS type CMOS image sensor, FIG. 3 is a view showing an example of a cross-sectional structure of the MOS type reset element along the line A in FIG. 2, and FIG. It is a figure which shows an example of the cross-section of a photodiode and MOS type | mold reset element along line B of FIG. In FIG. 4, the structure of the contact 18 in FIG. 2 is omitted.
2 to 4, an active region 15 surrounded by a field region 16 is formed on a P-type silicon substrate 31. Here, an element isolation region 33 formed by the LOCOS method is formed in the field region 16, and a contact 18 is formed in the active region 15.

  A photodiode n-type region 41 is formed on the P-type silicon substrate 31 in correspondence with the photodetection photodiode 11 shown in FIG. In addition, gate electrodes 42 a to 42 c arranged so as to straddle the active region 15 are formed corresponding to the MOS reset element 12, the source follower element 13, and the pixel selection element 14, respectively. Note that the gate electrodes 42 a to 42 c can be constituted by, for example, a polysilicon gate disposed on the P-type silicon substrate 31 with the gate oxide film 44 interposed therebetween.

  Here, a P-well region 32 is formed on the P-type silicon substrate 31 with a predetermined distance from the photodiode n-type region 41. On both sides of the gate electrode 42a, n + diffusion layers 34 and 43 respectively corresponding to the source and drain portions of the MOS reset element 12 are formed. The n + diffusion layer 34 is formed on the n-type region 41 for the photodiode. Has been stretched. The n + diffusion layer 34 extended on the photodiode n-type region 41 is connected to the gate electrode 42 b through the metal wiring 19.

The n-type region 41 for the photodiode can be an n-type region in which the dopant impurity dose and the ion implantation acceleration energy are optimized. Alternatively, an N well for forming a PMOS can be used to reduce the number of process steps. The photocurrent generated in the depletion layer formed between the photodiode n-type region 41 and the P-type silicon substrate 31 can be used for detecting the incident light intensity.
Further, since the layout of FIG. 2 is used when designing a mask, when an actual solid-state imaging device is viewed from above, the end of the n-type region 41 for the photodiode is hidden under the device isolation region. .

FIG. 5 and FIG. 6 are plan views showing pixel layout examples (patterns with n-type regions 41 for photodiodes) used for estimating the dark current generation location, and FIG. 7 is a diagram in the case of the pattern of FIG. 2 is a diagram illustrating an example of a cross-sectional structure of a photodiode 11 and a MOS-type reset element 12 corresponding to line 2 of FIG.
In the series of FIG. 5, the n-type regions 41 a to 41 c for photodiodes are configured by N wells, and the areas and peripheral lengths of the n-type regions 41 a to 41 c for photodiodes are changed from small to large.

In the series of FIG. 6, there is no N well corresponding to the n-type region 41 for the photodiode of FIG. 2, and the P well 32 extends to the region of the photodiode 11 as shown in FIG. 7. Further, the high concentration n + diffusion layers 34a to 34c are greatly expanded on the P well 32 extended to the region of the photodiode 11, and a depletion layer between the P well 32 and the n + diffusion layers 34a to 34c is used. It has a photodiode structure that performs photoelectric conversion. Also for these pixels, the perimeter and area of the n + diffusion layers 34a to 34c are changed from small to large.
Table 1 shows the measurement results of the area and peripheral length of the diffusion layer (source) portion of the photodiode 11 and the MOS type reset element 12 of each pixel structure of FIGS. 5 and 6 and the dark current for each pixel.

  8 shows the relationship between the area of the photodiode n-type regions 41a to 41b and the dark current when the depletion layer is formed in the photodiode n-type regions 41a to 41c and the P-type silicon substrate 31 of FIG. FIG. 9 shows the relationship between the length and the dark current. FIG. 10 shows the relationship between the area of the n + diffusion layers 34a to 34c and the dark current when the depletion layer is formed by the n + diffusion layers 34a to 34c and the P well 32 in FIG. 11 shows.

8 to 11, it can be seen that the dark current of the pixel increases almost in proportion to the area and the peripheral length of the photodiode n-type regions 41 a to 41 c or the n + diffusion layers 34 a to 34 c. Based on the above measurement results, the dark current generation rate of each depletion layer in the pixel is estimated.
First, the following model formula was assumed for the photodiode in which a depletion layer was formed by the n + diffusion layers 34a to 34c and the P well 32 in FIG. 6 (hereinafter referred to as a diffusion layer type photodiode).

I _dark = I _{PDn + bulk} + I _{PDn + surf} + I _offset (1)
I _{PDn + bulk} = _{Gn + bulk} × Area _{PDn +} × Dn _{+ bottom}
+ G _{n + bulk} × Peri _{PDn +} × W _{n + side} × D _{n + side} (2)
I _{PDn + surf} = G _{n + surf} × Peri _{PDn +} × W _{n + surf} (3)
I _offset ≒ I _rstsrc = I _rstsrcbulk + I _rstsrcsurf (4)
I _rstsrcbulk = G _{n + bulk} × Area _rstsrc × D _{n + bottom}
+ G _{n + bulk} × Peri _rstsrc × W _{n + side} × D _{n + side} (5)
I _rstsrcsurf = G _{n + surf} × Peri _rstsrc × W _{n + surf} (6)

Here, I _{dark in the} equation (1) is dark current generated in the entire pixel, I _{PDn + bulk} is dark current generated in the depletion layer inside the P-type silicon substrate 31 of the diffusion layer type photodiode, and I _{PDn + Surf} is a dark current generated on the surface of the depletion layer (Si / SiO 2 interface) around the diffusion layer type photodiode, and I _offset is a dark current generated in a region other than the diffusion layer type photodiode. I _rstsrc represents a dark current generated in the depletion layer in the source region of the MOS reset element 12. There are various other factors that affect I _offset , such as dark current generated around the contact of the diffusion layer type photodiode and channel leakage current of the MOS type reset element 12. Since it is assumed to be smaller than the dark current of the depletion layer in the source region, it was ignored in this analysis.

G _{n + bulk} is the dark current generation rate per unit volume generated in the depletion layer inside the P-type silicon substrate 31 of the n + diffusion layers 34a to 34c, and G _{n + surf} is the Si and SiO ₂ interface of the n + diffusion layers 34a to 34c. The dark current generation rate per unit area generated in the depletion layer. These values vary depending on the concentration of n + diffusion layers 34a to 34c, the concentration of P well region 32, and process conditions such as annealing.

Area _{PDn +} and Peri _{PDn +} are respectively the area and perimeter of the diffusion layer type photodiode, and correspond to the area and length surrounded by the thick dotted line in FIG. 12A, and were measured from the mask used in the prototype. Area _rstsrc and Peri _rstsrc represent the area and perimeter of the source region of the MOS reset element 12, and correspond to the area and length of the region sandwiched between the thick dotted lines in FIG. However, it is considered that it is more appropriate to analyze this peripheral length by excluding the mutual boundary length between the diffusion layer type photodiode and the MOS type reset element 12 when substituting into the expressions (5) and (6). In addition, it is appropriate that Peri _rstsrc further excludes the gate end of the MOS reset element 12. It should be noted that these corrected values are entered in the perimeter of Table 1 (Perimeter).

D _{n + bottom} represents the depletion layer width at the bottom of the n + diffusion layer. W _{n + side} and D _{n + side} are the depletion layer width and depth in the lateral direction of the n + diffusion layers 34a to 34c, and W _{n + surf} is the depletion layer width of the surface portion of the n + diffusion layers 34a to 34c. . Here, in order to estimate the width and depth of the depletion layer, the pixel structure of the CMOS image sensor was created by process simulation based on the process flow and layout used for creating the measurement sample. Next, the width of the depletion layer was estimated from the potential distribution and the electron and hole distribution using device simulation.

FIG. 13 is a diagram showing the relationship between the potential distribution of the n + diffusion layer-p well type pixel and the depletion layer width obtained by device simulation. Note that the solid contour lines in FIG. 13 represent the equipotential surface. A dotted line in the P-type silicon substrate 31 represents a boundary between the depletion layer and the neutral region.
In FIG. 13, the depletion layer width and depth D _{n + bottom} , W _{n + side} , D _{n + side} , and W _{n + surf} defined above are shown. However, the shape of the depletion layer on the side cannot be expressed by a simple figure, but since the model formula is simplified to a rectangle approximation, the values of D _{n + side} and W _{n + side} are set so that the areas are almost equal. Chose.

In the case of this pixel structure, since the source region of the MOS type reset element 12 and the region of the diffusion layer type photodiode are substantially the same structure, the dark current generation rate and the depletion layer width of the bulk and the surface are common. For this reason, the dark current generation rate can be estimated by fitting the result of the model formula and the measurement result. Table 2 shows values of the parameters G _{n + bulk} and G _{n + surf} thus obtained.

Next, a photodiode using an N well corresponding to the photodiode n-type regions 41a to 41c in FIG. 5 and a depletion layer of the P-type silicon substrate 31 (hereinafter referred to as an N-well photodiode) is shown in FIG. As in the case of the diffusion type photodiode, the following model formula was assumed.
I _dark = I _PDnwbulk + I _PDnwsurf + I _offset (7)
I _PDnwbulk = G _nwbulk × Area _PDnw × D _nwbottom
+ G _nwbulk × Peri _PDnw × W _nwside × D _nwside (8)
I _PDnwsurf = G _nwsurf × Peri _PDnw × W _nwsurf (9)
I _offset ≒ I _rstsrc (10)

Here, I _dark is the dark current of the entire pixel, I _PDnwbulk is the dark current generated in the depletion layer inside the P-type silicon substrate 31 of the N-well photodiode, and I _PDnwsurf is the periphery of the n-type regions 41a to 41c for the photodiode. Dark current generated on the surface of the depletion layer. The I _offset is different from the I _{offset of} the pixel in which the diffusion layer type photodiode is formed, but the dark current generation rates G _{n + bulk} and G _{n + surf} are considered to be common. Since these values have already been obtained, they can be easily calculated from the peripheral length and area of the MOS reset element 12.

G _nwbulk is the dark current generation rate per unit volume generated in the depletion layer inside the P-type silicon substrate 31 of the N-well photodiode, and G _nwsurf is the depletion layer on the surface of the N-well photodiode (interface between Si and SiO 2). This is the dark current generation rate per unit area. These values vary depending on process conditions such as N-well concentration, P-substrate concentration, and annealing.

Area _PDnw and Peri _PDnw are the area and perimeter of the N-well photodiode, respectively, corresponding to the area represented by the thick dotted line in FIG. 14 (a), and obtained from the mask used in the prototype as before. . D _nwbottom is the depletion layer width at the bottom of the n-type regions 41a to 41c for photodiodes, W _nwside and D _nwside are the width and depth of the depletion layer in the lateral direction of the n-type regions 41a to 41c for photodiodes, and W _nwsurf is the photo This is the depletion layer width of the surface portions of the diode n-type regions 41a to 41c. The width and depth of the depletion layer were estimated from the process and device simulation as in the case of the diffusion layer type photodiode.

FIG. 15 is a diagram showing the relationship between the potential distribution and the depletion layer width of the N well-P substrate type pixel obtained by device simulation.
In FIG. 15, the shape of the side depletion layer cannot be represented by a simple figure, but the values of D _nwside and W _nwside are selected so that the areas are almost equal in order to prevent the error from being increased by rectangular approximation. Using these values, the model equation and the measurement result were fitted to obtain a dark current generation rate parameter satisfying the measurement value. Table 2 shows the values of the parameters G _nwbulk and G _nwsurf obtained.
By obtaining all the parameters of the model formula by the above method, the dark current generation rate for each component can be estimated.

FIG. 16 is a diagram illustrating an analysis result of a dark current generation location for each pixel type.
In FIG. 16, it can be seen that the depletion layer on the surface (Si-SiO2 interface) has a higher dark current generation rate than the bulk region. In addition, it can be understood that the depletion layer of the n + diffusion layers 34 a to 34 c has a higher dark current generation rate than the depletion layer between the photodiode n-type regions 41 a to 41 c and the P-type silicon substrate 31. Since the peripheral length and area of the photodiode n-type region 41 are larger than those of the n + diffusion layer 34 of FIG. Of course, the countermeasure against dark current of the photodiode 11 is important, but the end of the diffusion layer 34 of the MOS reset element 12 has a very large dark current generation rate, and the influence is great even if the peripheral length is short. It is considered that the dark current countermeasure is effective for reducing the dark current.

The reason why the dark current generation rate on the end surface of the diffusion layer 34 is large can be estimated as follows.
First, when the element isolation region 33 is formed, stress is easily generated at the end of the element isolation structure such as LOCOS, and the defect density is increased. The depletion layer of the n + diffusion layer 34 is formed in the vicinity of the end portion of the element isolation region 33 such as the LOCOS end because the ion implantation energy is relatively low. Here, defects are considered to be various crystal structures and misalignments such as dangling bonds at the interface between the silicon substrate and the silicon oxide film, vacancies in silicon atoms, interstitial atoms, unintended impurity atoms, dislocations, etc. It is done. These defects form an impurity level in the energy level between the band gaps of silicon, and mediate the generation of electron-hole pairs of Shockley-Lead-Hole type.

  Second, the junction formed by the n + diffusion layer 34 and the P well 32 has a steep impurity concentration gradient as compared to the junction formed by the photodiode n-type region 41 and the P-type silicon substrate 31. For this reason, in the junction formed by the n + diffusion layer 34 and the P well 32, a tunneling phenomenon is easily generated via an impurity level between the band gaps, and electrons in the valence band escape to the conduction band. Generate electron-hole pairs. In addition, due to the high concentration of the n + diffusion layer 34, atoms and clusters that could not be fully activated by annealing remain, and it is easy to cause an increase in defects.

  For the above reasons, it can be understood that the periphery of the diffusion layer type photodiode and the end of the source region of the MOS type reset element 12 are dark current generation sources that cannot be ignored. As for the photodiode 1, there is no problem if a diffusion layer type photodiode is not used, but a structure that is a source of dark current is connected to the photodiode 11 like the MOS type reset element 12. It was recognized that this was one of the challenges for dark current countermeasures. Therefore, the MOS type reset element 12 directly connected to the photodiode 11 is stopped from being designed as a normal MOS transistor and considered to be changed to a special structure.

17 is a plan view showing an example of a pixel layout including the diffusion layer end cover structure of the present invention, and FIG. 18 shows an example of a cross-sectional structure taken along line A in FIG. 17 of the diffusion layer end cover structure of the present invention. FIG. 19 is a diagram showing an example of a cross-sectional structure taken along line B in FIG. 17 of the diffusion layer end cover structure of the present invention.
17 to 19, the MOS type reset element 12 ′ has an asymmetric structure, and a diffusion layer cover region 171 is formed on the P type silicon substrate 31 so as to widely cover the n + diffusion layer 34 and the end of the element isolation region. Has been. Here, the impurity concentration of the diffusion layer cover region 171 is preferably set lower than that of the n + diffusion layer 34. As a result, the position where the depletion layer is formed by the pn junction can be separated from the end of the n + diffusion layer 34 and the element isolation region 33, and the electric field gradient can be reduced by relaxing the impurity concentration gradient of the pn junction. The generation of dark current can be suppressed. When the MOS reset element 12 'is an n-type MOS transistor, for example, an impurity such as phosphorus is ion-implanted widely so as to cover the entire n + diffusion layer 34 and the end of the element isolation region 33 in a direction parallel to the gate electrode 42a. Then, the diffusion layer cover region 171 can be formed by diffusing.

  However, the MOS-type reset element 12 ′ provided with the diffusion layer cover region 171 has a deep source region, which causes channel punch-through immediately below the gate electrode 42a. On the other hand, if the gate electrode 42a is widened or the channel impurity concentration is increased in order to prevent channel punch-through, the current driving force is reduced. For this reason, in the method of disposing the diffusion layer cover region 171 so as to cover the n + diffusion layer 34, a normal MOS design is considered in which the source / drain regions are formed as shallow as possible to enhance the channel control power of the gate electrode 42a. It will be against the guidelines.

  However, the MOS-type reset element 12 ′ serves to supply charge to the photodiode 11 when turned on and to block charge so as not to generate a leakage current when turned off in accordance with an external control signal. You can do it. Further, in view of the capacitance of the photodiode 11, the current driving force is not so much required. Further, in the MOS type reset element 12 ', a high voltage is always applied to the drain side in normal operation. Therefore, in the MOS type reset element 12 ′, even if the source region is deepened, the disadvantage due to the structure in which the diffusion layer cover region 171 is provided is not a big problem, and the advantage that the generation of dark current can be suppressed is utilized. Is considered more valuable.

FIG. 20 is a diagram showing a potential distribution when the distance between the gate electrode 42a and the diffusion layer cover region 171 obtained by device simulation is 0.2 μm.
In FIG. 20, since the potential distribution is a distribution in which the source side of the MOS type reset element 12 ′ protrudes deeply in the channel direction, it is important to adjust the position of the mask edge for forming the diffusion layer cover region 171. It is. If the mask is too close to the channel side compared to the gate length of the MOS type reset element 12 ′, the MOS type reset element 12 ′ does not operate due to punch-through, so that the gap between the gate electrode 42 a and the diffusion layer cover region 171 is not affected. It is necessary to carefully optimize the distance.

  As described above, in the above-described embodiment, by analyzing the generation source of the dark current of the CMOS image sensor, the surface of the transistor diffusion layer of the element in contact with the photodiode 11 which is a considerable dark current generation source among them. The MOS structure for preventing dark current from the depletion layer has been described by taking the NMOS type MOS reset element 12 ′ and the photodiode n type region 41 as examples.

  However, the present invention is not effective only for the above structure, and is applied to a structure in which a MOS transistor other than the MOS type reset element 12 'is in contact with the photodiode 11, or a pixel structure in which n-type and p-type are inverted. You may make it do. Also, phosphorus is the most preferable n-type dopant for covering the end of the n + diffusion layer 34, but arsenic or the like may be used.

  In addition, even when one element serves as a function of a plurality of elements in the pixel in the above description, another functional element may be included in the pixel. In addition, the substrate may be a silicon germanium substrate, a silicon germanium epitaxial layer on a silicon substrate, a silicon carbide substrate, or a silicon carbide epitaxial layer on a silicon substrate. If there is a layer, it is possible to deal with it similarly.

As Example 1 of the present invention, an N well of a CMOS transistor, an n type well for the photodiode 11, and an n type diffusion layer cover region 171 covering the diffusion layer end of the MOS reset element 12 ′ are formed separately. The case where it does is demonstrated.
FIG. 21 is a flowchart showing the manufacturing process of the first embodiment of the present invention.
In FIG. 21, a process surrounded by a solid line is a standard CMOS process, a process surrounded by a dotted line is a process for a CMOS image sensor, and a process surrounded by a chain line is a process added in the first embodiment.

  The manufacturing process includes an element isolation region forming step (P1), a P well forming step (P2), an N well forming step (P3), a photodiode N well forming step (P4), and a diffusion layer end type cover region forming step. (P5), gate oxidation step (P6), polysilicon gate formation step (P7), LDD ion implantation / sidewall formation step (P8), source / drain diffusion layer formation step (P9), silicide layer formation step (P10) ), An interlayer insulating layer and contact formation step (P11), and a wiring step (P12).

22 to 33 are cross-sectional views illustrating manufacturing steps of Example 1 of the present invention.
In FIG. 22, the stress-reducing silicon oxide film 222 is formed on the P-type silicon substrate 31 by performing thermal oxidation of the P-type silicon substrate 31. Then, a silicon nitride film 221 is formed on the entire surface of the P-type silicon substrate 31 by a method such as CVD, and the silicon nitride film 221 is patterned by using a photolithography technique and an etching technique, thereby forming a film on the field region 16. The silicon nitride film 221 is removed. Then, by selectively oxidizing the P-type silicon substrate 31 using the silicon nitride film 221 as a mask, the element isolation region 33 is formed on the P-type silicon substrate 31 and the active region 15 surrounded by the field region 16 is formed. (P1 in FIG. 21). When the element isolation region 33 is formed on the P-type silicon substrate 31, the silicon nitride film 221 and the stress relaxation silicon oxide film 222 are removed from the P-type silicon substrate 31. Further, a screen oxide film 231 for ion implantation is formed on the P-type silicon substrate 31.

  Next, as shown in FIG. 23, a photoresist 232a covering the photodiode portion is formed on the P-type silicon substrate 31 by using a photolithography technique. Then, B (boron) ion implantation 233 for forming a P well is performed on the P-type silicon substrate 31 using the photoresist 232a as a mask, thereby forming a P well region 32 (P2 in FIG. 21).

  Next, as shown in FIG. 24, an N well for a CMOS transistor is formed by performing ion implantation 241 of an N type impurity such as P on the P type silicon substrate 31 (P3 in FIG. 21). When forming the N well for the CMOS transistor, the entire pixel of the APS type CMOS image sensor is protected by the photoresist 232b, so that the N type impurity for forming the CMOS transistor is not implanted into the pixel. When the N well for the CMOS transistor is formed on the P-type silicon substrate 31, the photoresist 232b is removed from the P-type silicon substrate 31.

  Next, as shown in FIG. 25, a photoresist 232c patterned so as to expose the photodiode portion is formed on a P-type silicon substrate 31 by using a photolithography technique. Then, using the photoresist 232c as a mask, ion implantation 251 of N-type impurities such as P is performed on the P-type silicon substrate 31 to form an n-type region 41 for a photodiode for an image sensor (P4 in FIG. 21). . When the photodiode n-type region 41 is formed on the P-type silicon substrate 31, the photoresist 232 c is removed from the P-type silicon substrate 31.

  Next, as shown in FIG. 26, a photoresist 232d patterned so as to expose the end of the diffusion layer 34 of the MOS reset element 12 'is exposed on the P-type silicon substrate 31 by using a photolithography technique. To form. Then, using the photoresist 232d as a mask, ion implantation 261 of N-type impurities such as P is performed on the P-type silicon substrate 31 to form a diffusion layer cover region 171 (P5 in FIG. 21). When the diffusion layer cover region 171 is formed on the P-type silicon substrate 31, the photoresist 232 d is removed from the P-type silicon substrate 31.

  At this time, the distance from the element isolation region 33 to the mask end of the diffusion layer cover region 171 may be 0.3 to 0.4 μm or more, depending on the lithography accuracy. Further, the distance X between the end of the gate electrode 42a and the mask end of the MOS reset element 12 ′ shown in FIG. 17 is diffused by the diffusion layer cover region 171 to the end of the gate electrode 42a at the end of the process. It is desirable to make the conditions so that the end of the substrate is sufficiently covered. In this case, although it depends on the dopant species, the concentration thereof, and the diffusion distance by annealing, for example, in the case of phosphorus, it is preferable that the distance between the gate end and the mask end is set to about 0.1 to 0.3 μm.

Next, as shown in FIG. 27, after removing the screen oxide film 231 once, the surface of the P-type silicon substrate 31 is thermally oxidized to form a gate oxide film 44 on the surface of the P-type silicon substrate 31 (FIG. 21). P6).
Next, as shown in FIG. 28, a polysilicon layer is stacked by a method such as CVD, and the polysilicon layer is patterned using a photolithography technique and an etching technique, whereby the gate electrode 42a is placed on the P-type silicon substrate 31. (P7 in FIG. 21).

Next, as shown in FIG. 29, ion implantation 291 of an N-type impurity such as P is performed in the P-type silicon substrate 31 using the element isolation region 33 and the gate electrode 42a as a mask, thereby forming both sides of the gate electrode 42a. An LDD region 302 is formed.
Further, an insulating film such as a silicon oxide film or a silicon nitride film is stacked on the P-type silicon substrate 31 on which the gate electrode 42a is formed by a method such as CVD, and anisotropic etching of the insulating film is performed. Sidewalls 292 are formed on the side walls of the gate electrode 42a (P8 in FIG. 21).
Next, as shown in FIG. 30, a high dose As (arsenic) ion implantation 301 is performed in the P-type silicon substrate 31 using the element isolation region 33, the gate electrode 42a, and the sidewall 292 as a mask. High-concentration impurity diffusion layers 34 and 43 are formed on both sides of the side wall 292 (P9 in FIG. 21).

  Next, as shown in FIG. 31, a photoresist 232 e that covers the high-concentration impurity diffusion layer 34 is formed on the P-type silicon substrate 31 by using a photolithography technique. Then, Ti is deposited on the P-type silicon substrate 31 on which the photoresist 232e is formed by a method such as sputtering. Then, by performing heat treatment on the P-type silicon substrate 3 on which Ti is formed, the silicon of the gate electrode 42a and the high-concentration impurity diffusion layer 43 is reacted with Ti, so that the gate electrode 42a and the high-concentration impurity diffusion layer 43 are formed on the gate electrode 42a and the high-concentration impurity diffusion layer 43. A metal silicide 311 is formed. When the metal silicide 311 is formed on the gate electrode 42a and the high-concentration impurity diffusion layer 43, unreacted Ti is removed from the P-type silicon substrate 31 (P10 in FIG. 21).

  As a result, the metal silicide 311 can be formed on the drain and gate of the MOS reset element 12 ′, and the metal silicide 311 is not formed on the source of the MOS reset element 12 ′. it can. Then, when the metal silicide 311 is formed on the gate electrode 42 a and the high concentration impurity diffusion layer 43, the photoresist 232 e is removed from the P-type silicon substrate 31.

  Next, as shown in FIG. 32, an interlayer insulating film 321 is deposited on the P-type silicon substrate 31 by a method such as CVD. Then, by patterning the interlayer insulating film 321 using a photolithography technique and an etching technique, a contact hole 322 exposing the metal silicide 311 on the high concentration impurity diffusion layer 43 is formed in the interlayer insulating film 321 (FIG. 21). P11).

  Next, as shown in FIG. 33, a metal layer is formed on the interlayer insulating film 321 in which the contact holes 322 are formed by a method such as sputtering. Then, by patterning the metal layer using the photolithography technique and the etching technique, the metal wiring 332 connected to the metal silicide 311 on the high concentration impurity diffusion layer 43 through the contact 331 is formed (P12 in FIG. 21). ).

  In the first embodiment, the method of separately forming the photodiode n-type region 41 and the diffusion layer cover region 171 provided in the MOS reset element 12 ′ has been described. However, the impurity concentration and depth of the diffusion layer cover region 171 are described. There is a fairly wide tolerance for this. For this reason, in order to reduce the number of steps, it is also possible to simultaneously form the n-type region 41 for the photodiode and the n-type cover region 171 of the MOS-type reset element 12 ′.

When the leakage current of the MOS reset element 12 ′ increases due to the P-well region 32 optimized for the photodiode 11, the position of the diffusion layer cover region 171 (for example, X in FIG. 17) is adjusted. can do. Alternatively, the gate length of the MOS-type reset element 12 ′ can be widened to adjust the leak current to be equal to or lower than the target level. If it is not desired to increase the gate length of the MOS type reset element 12 ', the number of processes is increased, but additional impurity ion implantation may be performed on the channel of the MOS type reset element 12'.
Table 3 shows the change rate of the dark current when the prototype is manufactured by changing the distance (X in FIG. 17) between the gate end of the MOS type reset element 12 and the diffusion layer cover region 171.

  Here, as the distance between the gate end of the MOS type reset element 12 and the diffusion layer cover region 171 (X in FIG. 17) is reduced from 0.70 μ to 0.15 μ, the dark current decreases smoothly. However, it can be seen that dark current increases when the diffusion layer cover region 171 is brought closer to the gate end of the MOS type reset element 12 '. In particular, when the diffusion layer cover region 171 enters the gate electrode 42c by 0.15 μm, the optical response is lost and the image sensor does not operate. Therefore, it can be understood that bringing the diffusion layer cover region 171 to the optimum distance is important for suppressing the dark current and operating normally.

  In the second embodiment, the photodiode n-type region 41 and the diffusion layer cover region 171 of the MOS reset element 12 ′ are formed in the same process. What is the process for forming the N well of the PMOS transistor of the peripheral circuit element? It was formed in a separate process. In order to make the CMOS image sensor process compatible with the standard CMOS process as much as possible and further reduce the number of steps, a photodiode is used in an ion implantation step (ion implantation 241 in FIG. 24) for forming an N well in the PMOS region. It is also possible to form the n-type region 41 for use and the diffusion layer cover region 171 of the MOS-type reset element 12 ′.

Examples 1 to 3 relate to a pixel in which the MOS type reset element 12 ′ is in contact with the photodiode 11, but the present invention is also effective when the exposure control element is in contact with the photodiode 11. Conceivable.
FIG. 34 is a plan view showing an example of a pixel layout including the diffusion layer cover region 343 in the case of the fourth embodiment of the present invention.

  34, on a P-type silicon substrate, a photodetection photodiode 11, a MOS-type reset element 12 for initializing the photodiode 11, and a source for converting the charge and potential of the photodiode 11 into an output voltage A follower element 13 and a pixel selecting element 14 are provided. Here, the photodiode may be formed exposed at the interface of the silicon oxide film, or may be formed by covering the surface with a layer of a different conductivity type and embedding a depletion layer inside the substrate. An exposure control element 341 is provided between the photodetection photodiode 11 and the MOS reset element 12, and the exposure control element 341 is provided with a gate electrode 42d.

  Further, a floating diffusion region (FD) 342 is provided between the gate electrode 42a of the MOS reset element 12 and the gate electrode 42d of the exposure control element 341, and the floating diffusion region 342 is interposed via the metal wiring 19 '. Are connected to the gate electrode 42 b of the source follower element 13. Further, a diffusion layer cover region 343 arranged so as to cover the floating diffusion region 342 is formed on the P-type silicon substrate between the gate electrode 42a of the MOS reset element 12 and the gate electrode 42d of the exposure control element 341. Is formed.

  Then, the exposure control element 341 transfers the charge accumulated in the photodiode 11 to the floating diffusion region 342 between the exposure control element 341 and the MOS type reset element 12. Then, the light incident on the photodiode 11 can be detected by reading the potential of the floating diffusion region 342 with the source follower element 13. Here, the width of the floating diffusion region 342 is not designed to be long, and since the time for which electric charges are held in the floating diffusion region 342 is short, the dark current generated in the floating diffusion region 342 is not usually so much of a problem.

  However, when a moving subject is imaged, the subject is deformed and imaged when the exposure timing is shifted. As one means for solving this problem, there is a method in which the exposure control elements 341 are simultaneously turned on to transfer charges to the floating diffusion region 342 and sequentially read them out. In this case, the pixel read in the later order is added with the offset due to the photocurrent caused by stray light to the floating diffusion region 342 and the dark current of the floating diffusion region 342, which adversely affects the image quality. For this reason, a light shielding structure for preventing stray light is essential, but by providing the diffusion layer cover region 343 in the floating diffusion region 342, generation of dark current in the floating diffusion region 342 can be further suppressed.

  Here, if the diffusion layer cover region 343 is provided in the floating diffusion region 342, the exposure control element 341 has a deep drain portion. Therefore, the mask position adjustment described in the second embodiment and the MOS type exposure control element are described. Preferably, the gate length adjustment of 341 and the channel impurity ion implantation adjustment are combined to optimize reduction of leakage current, reduction of dark current, and reduction of residual charge transfer.

It is a circuit diagram which shows an example of the pixel part of an Active Pixel Sensor type | mold CMOS image sensor. It is a top view which shows an example of the pixel layout of an Active Pixel Sensor type | mold CMOS image sensor. FIG. 3 is a diagram showing an example of a cross-sectional structure of a MOS reset element along line A in FIG. 2. FIG. 3 is a diagram illustrating an example of a cross-sectional structure of a photodiode and a MOS reset element along line B in FIG. 2. It is a top view which shows the pixel layout example (pattern with an N well for photodiodes) used in order to estimate the generation | occurrence | production location of a dark current. It is a top view which shows the pixel layout example (pattern without an N well for photodiodes) used in order to estimate the generation | occurrence | production location of a dark current. 6 is a diagram illustrating an example of a cross-sectional structure of a photodiode and a MOS type reset element corresponding to the line B in FIG. 2 in the case of the pattern of FIG. It is a figure which shows the relationship of the area and dark current of the photodiode which formed the depletion layer with the n <-> layer of N well, and the p board | substrate. It is a figure which shows the relationship between the circumference of the photodiode which formed the depletion layer with the n- layer of N well, and the p board | substrate, and dark current. It is a figure which shows the relationship between the area of the photodiode which formed the depletion layer in the n + layer of the diffused layer, and the p- layer of P well, and dark current. It is a figure which shows the relationship between the surrounding length of the photodiode which formed the depletion layer in the n + layer of the diffused layer, and the p- layer of P well, and dark current. It is a top view which shows the area and peripheral length of the photodiode which formed the depletion layer in the n + layer of the diffused layer, and the p- layer of P well. It is a figure which shows the relationship between the potential distribution and depletion layer width | variety of the n + diffusion layer-P well type | mold pixel obtained by device simulation. It is a top view which shows the area and peripheral length of the photodiode which formed the depletion layer with the n <-> layer of N well, and the p board | substrate. It is a figure which shows the relationship between the potential distribution of an N well-p board | substrate type pixel obtained by device simulation, and the depletion layer width. It is a figure which shows the analysis result of the dark current generation location for every pixel kind. It is a top view which shows an example of the pixel layout containing the diffused layer end cover structure of this invention. It is a figure which shows an example of the cross-sectional structure along the line A of FIG. 17 of the diffusion layer end cover structure of this invention. It is a figure which shows an example of the cross-sectional structure along the line B of FIG. 17 of the diffusion layer end cover structure of this invention. It is a figure which shows potential distribution in case the distance between masks of the gate end and diffusion layer end cover structure obtained by device simulation is 0.2 μm. It is a flowchart which shows the manufacturing process of Example 1 of this invention. It is sectional drawing which shows the structure at the time of element isolation region formation of the manufacturing process of Example 1 of this invention. It is sectional drawing at the time of P well formation of the manufacturing process of Example 1 of this invention. It is sectional drawing at the time of N well formation of the manufacturing process of Example 1 of this invention. It is sectional drawing at the time of the n-type well formation for photodiodes of the manufacturing process of Example 1 of this invention. It is sectional drawing at the time of diffusion layer edge n-type cover structure formation of the manufacturing process of Example 1 of this invention. It is sectional drawing at the time of the gate oxidation of the manufacturing process of Example 1 of this invention. It is sectional drawing at the time of the polysilicon gate formation of the manufacturing process of Example 1 of this invention. It is sectional drawing about the structure at the time of the ion implantation for LDD of the manufacturing process of Example 1 of this invention, and sidewall formation. It is sectional drawing at the time of the source / drain diffused layer formation of the manufacturing process of Example 1 of this invention. It is sectional drawing at the time of the silicide layer formation of the manufacturing process of Example 1 of this invention. It is sectional drawing of the structure at the time of the formation of the coating layer and contact of the manufacturing process of Example 1 of this invention. It is sectional drawing at the time of wiring layer formation of the manufacturing process of Example 1 of this invention. It is a top view which shows an example of the pixel layout containing the diffused layer end cover structure in the case of Example 4 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Photodiode 12, 12 'MOS type reset element 13 Source follower element 14 Selection element 15 Active area 16 Field area 18 Contact 19 Metal wiring 31 P type silicon substrate 32 P well area 33 Element isolation area (LOCOS)
34 n + diffusion layer (MOS type reset element source part)
41 n-type regions 42a to 42c for photodiodes gate electrode 43 n + diffusion layer (MOS-type reset element drain portion)
44 Gate oxide film 171 Diffusion layer cover region 221 Silicon nitride film 222 Stress relaxation silicon oxide film 231 Ion implantation screen oxide film 232 Photoresist 233 P well B (boron) ion implantation 241 N well P (phosphorus) ion implantation 251 N-well P (phosphorus) ion implantation for photodiode 261 P (phosphorus) ion implantation for diffusion layer edge n-type cover structure 291 P (phosphorus) ion implantation 292 for LDD Side wall 301 As (arsenic) ion implantation for forming a diffusion layer 302 Low concentration drain extension (LDD)
311 Silicide 321 Interlayer insulating film 322 Contact hole 331 Contact portion 332 Metal wiring layer 341 Exposure control element 342 Floating diffusion region (FD)
343 Cover region covering high-concentration impurity edge between exposure control element and MOS type reset element

Claims (8)

A photodiode for detecting light, a resetting element for supplying a charge to initialize the photodiode, an element for detecting the potential of the photodiode, and an element for selecting a pixel; In a solid-state imaging device having an element isolation region formed by selectively oxidizing a semiconductor substrate in a pixel,
The reset element is an asymmetric MOS transistor (metal oxide semiconductor element),
The high-concentration impurity region of the first conductivity type on the photodiode side of the resetting element is an impurity region of the first conductivity type having a lower concentration than the high-concentration impurity region, and the element isolation from the end of the high-concentration impurity region. Comprising a region covering the region end,
The end of the low-concentration impurity region covering the high-concentration impurity region on the resetting element side is a position where the end of the high-concentration impurity region passes under the gate of the resetting element. The solid-state imaging device is located near the gate end on the high-concentration impurity region side of the resetting device that minimizes dark current.   2. The solid-state image pickup device according to claim 1, wherein the semiconductor substrate is silicon.   2. The solid-state imaging device according to claim 1, wherein the element forming the impurity region for covering the edge of the high concentration impurity region is phosphorus. A photodiode for detecting light, a resetting element for supplying a charge to initialize the photodiode, an element for detecting the potential of the photodiode, and an element for selecting a pixel; In a solid-state imaging device having an element for controlling exposure and an element isolation region formed by selectively oxidizing a semiconductor substrate in a pixel,
The reset element is an asymmetric MOS transistor (metal oxide semiconductor element),
A high-concentration impurity region of the first conductivity type sandwiched between the exposure control element and the resetting element is replaced with the first-concentration impurity region having a lower concentration than the high-concentration impurity region. It has a structure covering so as to include the region end and the element isolation region end,
The end of the low-concentration impurity region covering the high-concentration impurity region on the resetting element side is a position where the end of the high-concentration impurity region passes under the gate of the resetting element. The solid-state imaging device is located near the gate end on the high-concentration impurity region side of the resetting device that minimizes dark current.   5. The solid-state image pickup device according to claim 4, wherein the semiconductor substrate is silicon.   5. The solid-state imaging device according to claim 4, wherein the element forming the impurity region for covering the edge of the high concentration impurity region is phosphorus. Forming a device isolation region by selectively oxidizing the semiconductor substrate on the first conductivity type semiconductor substrate;
Introducing a second conductivity type impurity into the semiconductor substrate to form a photosensitive portion;
Forming a well of an MOS transistor (metal oxide semiconductor element) which is an element for initializing the photosensitive portion by introducing a first conductivity type impurity into the semiconductor substrate;
Forming an insulating film on the semiconductor substrate;
Forming a gate electrode of the initialization element on the insulating film;
Forming a diffusion layer of the initialization element of the second conductivity type;
Performing ion implantation of a dose amount lower than that of the diffusion layer in the second conductivity type into a region covering the diffusion layer on the photosensitive portion side of the initialization element and the end of the element isolation region,
The region where ion implantation is performed in the step of performing ion implantation does not enter directly under the gate of the initialization element, and its end is located slightly outside the gate end of the initialization element and A method for manufacturing a solid-state imaging device, wherein the solid-state imaging device is located near the gate end where the dark current is minimized.   8. The method of manufacturing a solid-state imaging device according to claim 7, wherein a step of forming a photosensitive portion by introducing a second conductive type impurity into a first conductive type semiconductor substrate, a diffusion layer on the photosensitive portion side of the initialization element, and the device A method of manufacturing a solid-state imaging device, wherein the second conductivity type ion implantation of the region covering the edge of the separation region is performed in the same step.

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