JP4753968B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit having an analog circuit including an operational amplifier and the like, and a bias circuit for supplying a bias voltage to the analog circuit, and configured by a CMOS or the like, and in particular, the semiconductor integrated circuit in which the bias circuit includes a resistor. It relates to the circuit.

  As an operational amplifier and a bias circuit used in a conventional semiconductor integrated circuit, for example, there is one disclosed in Patent Document 1. The bias circuit disclosed in Patent Document 1 generates a bias voltage with a reference voltage as an input, an amplifying unit having a resistor (hereinafter referred to as a reference resistor) as a load, the input reference voltage and the amplification Differential amplifying means that works so that the output voltages of the means become the same, and current / voltage converting means for generating a bias voltage by converting the current flowing through the reference resistor into a voltage. The operational amplifier includes a constant current transistor, and the bias voltage from the bias circuit is supplied to the gate electrode of the constant current transistor to determine the current values of the differential stage and the output stage. is there. In the operational amplifier and the bias circuit, the current value of the operational amplifier is determined only by the bias voltage, and the bias voltage is determined only by the reference voltage and the reference resistance. Therefore, the current value of the operational amplifier becomes constant without depending on the threshold value of the MOS transistor constituting the operational amplifier and the bias circuit and the fluctuation of the power supply voltage, and thus the operation of the operational amplifier can be stabilized.

  On a conventional semiconductor integrated circuit, one or a plurality of bias circuits having the above configuration and an analog circuit are formed. The analog circuit includes, for example, a plurality of load elements such as load resistors and a plurality of driving means such as operational amplifiers configured as described above for driving these load elements, or the constant current transistors included in the operational amplifiers described above. A plurality of constant current sources are formed. Both the driving means and the constant current source constituting the analog circuit are supplied with a bias voltage from the bias circuit.

In addition, in a conventional semiconductor integrated circuit, a constant current source such as a constant current transistor used in an operational amplifier that can be powered down at the same time is integrated, that is, a current source in an analog circuit is used from the viewpoint of power down control. In summary, the analog circuit is divided into a plurality of analog circuit blocks, a bias circuit is provided for each analog circuit block, and unnecessary analog circuit blocks are selected and powered down. In such a conventional semiconductor integrated circuit having a plurality of analog circuit blocks, when the analog circuit block is powered down, the output voltage of the corresponding bias circuit is switched to 0 [V], for example, The current of the constant current source was stopped.
JP-A-9-219629

However, when a plurality of driving means are formed on a semiconductor integrated circuit and there are a plurality of types of constituent materials of the load resistance driven by these driving means, the temperature characteristics and manufacturing variations of these load resistances are different. There is a problem that the analog circuit may not operate stably. As the load resistor, a resistor formed on the semiconductor integrated circuit or a resistor externally attached to the semiconductor integrated circuit (hereinafter referred to as an external load resistor) is used. Similarly, a resistor formed on the semiconductor integrated circuit or a resistor externally attached to the semiconductor integrated circuit (hereinafter referred to as an external reference resistor) is used as the reference resistor of the bias circuit. For example, a polycrystalline silicon resistor (hereinafter referred to as a polycrystalline Si resistor) and a diffused resistor are used as a load resistor formed on a semiconductor integrated circuit, and a metal film resistor is used as an external load resistor. Consider the case of mixing in a semiconductor integrated circuit. In this case, the reference resistance of the bias circuit is a polycrystalline Si resistance, a diffusion resistance, or an external reference resistance. Hereinafter, the load resistance and reference resistance made of diffusion resistance are called diffusion load resistance and diffusion reference resistance, respectively, and the load resistance and reference resistance made of polycrystalline Si resistance are called polycrystalline Si load resistance and polycrystalline Si reference resistance, respectively.
The metal film resistance is highly accurate and has a small temperature coefficient. Therefore, the external load resistance and the external reference resistance can be highly accurate and have a small temperature coefficient. Polycrystalline Si resistors have about 10% to 20% of manufacturing variation between semiconductor integrated circuits, but the relative accuracy of resistance values in the same semiconductor integrated circuit is quite good, and the temperature coefficient is small. In addition, the diffusion resistance has a large temperature coefficient, and the resistance value decreases at low temperatures.

  For this reason, when the bias voltage of the bias circuit having the polycrystalline Si reference resistance is supplied to the driving means for driving the diffusion load resistance, the resistance value of the diffusion load resistance is lowered at a low temperature, but the bias voltage does not change. Therefore, there is a problem that the drive current does not increase and the output waveform is distorted due to insufficient drive capability of the drive means. Similarly, when the bias voltage generated by the bias circuit using the external reference resistor is supplied to the drive circuit for driving the diffusion load resistor, there is a problem that the output waveform is distorted at a low temperature. In addition, when the bias voltage of the bias circuit having the polycrystalline Si reference resistance is supplied to the driving means for driving the external load resistance, the resistance value of the polycrystalline Si reference resistance is larger than the design value due to manufacturing variations. As a result, the bias voltage becomes smaller than the design value, and thereby the drive current becomes small, which causes a problem that the output waveform is distorted. In order to prevent these waveform distortions, the drive current values of the drive means for driving the diffusion load resistor and the drive means for driving the external load resistor need to be set large in advance. There was a problem of getting bigger. Further, when the bias voltage of the bias circuit having the diffusion reference resistance is supplied to the driving means for driving the polycrystalline Si load resistance or the driving means for driving the external load resistance, the bias voltage becomes large at a low temperature, There has been a problem that current consumption in the driving means becomes large.

  In addition, in the conventional semiconductor integrated circuit having a plurality of analog circuit blocks summarized from the viewpoint of power down control, the number of bias circuits is required for the number of analog circuit blocks, and in particular, the number of reference resistors on the semiconductor integrated circuit increases. There is a drawback that the chip size of the semiconductor integrated circuit increases.

The present invention is all SANYO has been made in order to solve the conventional problems, it is an object to provide a semiconductor integrated circuit which can reduce the switch Ppusaizu.

Semiconductors integrated circuit of the present invention,
A first analog circuit block including one or a plurality of first constant current sources whose current values are determined by a first bias voltage;
A second analog circuit block including one or a plurality of second constant current sources whose current values are determined by a second bias voltage;
Generates a single reference current from the input reference voltage, have a bias circuit for generating the first and second bias voltage based on the reference current,
The bias circuit comprises:
A reference current generating means for generating the reference current, including a reference resistor for flowing the reference current;
A first current / voltage conversion circuit that generates the first bias voltage by converting the reference current into a voltage;
A second current / voltage conversion circuit that generates the second bias voltage by converting the reference current into a voltage;
The first current / voltage conversion circuit generates the first bias voltage when the first control signal is at the first level, and applies the first bias voltage to the first constant current source. By supplying the first analog circuit block, the first analog circuit block is activated, and when the first control signal is at the second level, the supply of the first bias voltage is stopped, whereby the first analog circuit is stopped. The block is powered down,
The second current / voltage conversion circuit generates the second bias voltage when the second control signal is at the first level, and applies the second bias voltage to the second constant current source. By supplying the second analog circuit block, the second analog circuit block is activated, and when the second control signal is at the second level, the supply of the second bias voltage is stopped, whereby the second analog circuit is stopped. To put the block in a power down state
It is characterized by this.

According to the present invention, it is possible to reduce the area occupied by the bias circuit, thus it is possible to realize a semiconductor integrated circuit is small chip size, to reduce the cost of the semiconductor integrated circuit by reducing the chip size Is possible.

Embodiment 1
FIG. 1 is a circuit block diagram showing a semiconductor integrated circuit 1 according to the first embodiment of the present invention. The semiconductor integrated circuit 1 includes a reference voltage generation circuit 10, a bias circuit 20-1 having a diffusion reference resistance, a bias circuit 20-2 having a polycrystalline Si reference resistance, and a bias circuit 20 using an external reference resistance 80. -3, operational amplifiers (drive means) 30-1, 30-2, 30-3 having the same internal configuration, a diffusion load resistor 60 serving as a load element of the operational amplifier 30-1, and a load of the operational amplifier 30-2 A load connection for connecting a polycrystalline Si load resistor 70 as an element, a reference resistance connection terminal 90 for connecting an external reference resistor 80, and an external load resistor 81 as a load element of the operational amplifier 30-1. Terminal 91. The internal configurations of the bias circuits 20-1 and 20-2 are the same except that the constituent materials of the reference resistance are different. The internal configuration of the bias circuit 20-3 is the same as that of the bias circuits 20-1 and 20-2 except that the reference resistor is not incorporated.

  FIG. 2 is a circuit diagram showing a configuration of the bias circuit 20-i (i is an arbitrary integer of 1 to 3). In FIG. 2, the bias circuit 20-i includes a voltage dividing circuit 100 that generates a divided voltage of the positive power supply VDD, a differential amplifier 110, a common source amplifier circuit 120, a current / voltage conversion circuit 130, and a reference voltage. Input terminal 116 and a bias voltage output terminal 133.

  The voltage dividing circuit 100 includes a p-channel MOS transistor (hereinafter referred to as pMOS) 101 and an n-channel MOS transistor (hereinafter referred to as nMOS) 102, and outputs a divided voltage from a node N5. The source electrode of the pMOS 101 is connected to the positive power supply VDD, and the source electrode of the nMOS 102 is connected to the ground power supply GND. The gate and drain electrodes of the pMOS 101 and the nMOS 102 are connected to the node N5. The voltage dividing circuit 100 is a circuit that biases the differential amplifier 110.

  The differential amplifier 110 includes nMOSs 111 and 112 serving as input transistors, pMOSs 113 and 114 serving as load transistors, and an nMOS 115 serving as a constant current transistor. The gate electrode of the nMOS 111 serves as an inverting input terminal and an input terminal 116 for a reference voltage. The gate electrode of the nMOS 112 is connected to the node N7 as a non-inverting input terminal. The drain electrode of the nMOS 111 is connected to the node N6 and the drain electrode of the pMOS 113, and the drain electrode of the nMOS 112 is connected to the gate electrode and the drain electrode of the pMOS 114. The source electrodes of the nMOS 111 and nMOS 112 are both connected to the drain electrode of the nMOS 115.

  The gate electrode of the pMOS 113 is connected to the gate electrode of the pMOS 114. The source electrodes of the pMOS 113 and 114 are both connected to the positive power supply VDD. The gate electrode of the nMOS 115 is connected to the node N5, and the source electrode is connected to the ground power supply GND. The differential amplifier 110 amplifies the difference between the input reference voltage and the voltage at the node N7 and outputs the amplified difference to the node N6.

  The common source amplifier circuit 120 includes a pMOS 121 and a reference resistor 122 in the bias circuits 20-1 and 20-2, and a pMOS 121 in the bias circuit 20-3. The gate electrode of the pMOS 121 is connected to the node N6 serving as an input terminal, the source electrode is connected to the positive power supply VDD, and the drain electrode is connected to a node N7 serving as an output terminal. The load resistor 122 is provided between the node N7 and the ground power supply GND. In the bias circuit 20-3, the node N7 is connected not to the load resistor 122 but to the reference resistor connection terminal 90 (see FIG. 1). The grounded source amplifier circuit 120 amplifies the voltage of the node N6 and outputs the amplified voltage to the node 7, and allows a reference current to flow through the reference resistor 122 or the external reference resistor 80 (see FIG. 1).

  The differential amplifier 110 and the grounded source amplifier circuit 120 constitute reference current generating means for generating a reference current from the input reference voltage. The differential amplifier 110 is configured to input the input reference voltage and the source grounded amplifier. Since the voltage (node N6 voltage) that is input to the common source amplifier circuit 120 is generated so that the level of the output voltage of the circuit 120 (voltage of the node N7) is the same, the voltage of the node N7 is equal to the reference voltage. Become. Therefore, the current value of the reference current is determined only by the value of the reference voltage and the resistance value of the reference resistor 122 or the external reference resistor 80.

  The current / voltage conversion circuit 130 includes a pMOS 131 and an nMOS 132. The gate electrode of the pMOS 131 is connected to the node N6 as an input terminal, the source electrode is connected to the positive power supply VDD, and the drain electrode is connected to the drain electrode and gate electrode of the nMOS 132 and the bias voltage output terminal 133. The source electrode of the nMOS 132 is connected to the ground power supply GND. The pMOS 131 and the pMOS 121 of the common source amplifier circuit 120 constitute a current mirror circuit, and a transistor having the same conductance as the pMOS 121 is used for the pMOS 131. At this time, the current flowing through the pMOS 131 is equal to the reference current flowing through the reference resistor 122 of the common source amplifier circuit 120 or the external reference resistor 80 (see FIG. 1). Therefore, the current / voltage conversion circuit 130 generates a bias voltage by converting the reference current into a voltage.

  As described above, the bias circuit 20-i inputs the reference voltage to the inverting input terminal of the differential amplifier 110, inputs the output voltage of the differential amplifier to the common source amplifier circuit 120, and outputs the output voltage of the common source amplifier circuit 120. Is fed back to the non-inverting input terminal of the differential amplifier 110 to provide a voltage equal to the reference voltage between the terminals of the reference resistor 122 or the external reference resistor 80, generate a reference current, and the pMOS 121 of the common-source amplifier circuit 120. The current / voltage conversion circuit 130 having the pMOS 131 constituting the current mirror circuit generates a bias voltage determined only by the current value of the reference current.

  A bias circuit 20-1 shown in FIG. 1 uses a diffused resistor arranged on the semiconductor integrated circuit 1 as a constituent material of the reference resistor 122 in the bias circuit shown in FIG. 2. A bias circuit 20-2 shown in FIG. 1 uses a polycrystalline Si resistor arranged on the semiconductor integrated circuit 1 as a constituent material of the reference resistor 122 in the bias circuit shown in FIG. Further, the bias circuit 22-3 shown in FIG. 1 uses an external reference resistor 80 connected to the load connection terminal 90 of the semiconductor integrated circuit 1 without incorporating a reference resistor.

  FIG. 3 is a circuit diagram showing a configuration of the reference voltage generating circuit 10. In FIG. 3, the reference voltage generation circuit 10 includes an operational amplifier 11, npn-type bipolar transistors 12 and 13, resistors 14, 15 and 16, and a reference voltage output terminal 17. The inverting input terminal of the operational amplifier 11 is connected to the emitter electrode of the transistor 13, and the output terminal is connected to the base electrodes of the transistors 12 and 13 and the output terminal 17. The collector electrodes of the transistors 12 and 13 are connected to the positive power supply VDD. The resistor 14 is provided between the emitter electrode of the transistor 12 and the non-inverting input terminal of the operational amplifier 11, the resistor 15 is provided between the non-inverting input terminal of the operational amplifier 11 and the ground power supply GND, and the resistor 16 is provided as the operational amplifier. 11 inverting input terminals and the ground power supply GND. The reference voltage generation circuit 10 is a known band gap reference circuit, and outputs a reference voltage from the output terminal 17.

  The output voltage of the operational amplifier 11 serving as the reference voltage is the sum of the base-emitter voltage of the transistor 12 and the voltage drop across the resistors 14 and 15. Since the potentials of the inverting input terminal and the non-inverting input terminal of the operational amplifier 11 are equal, the differential voltage between the base-emitter voltage of the transistor 13 and the base-emitter voltage of the transistor 12 becomes the terminal voltage of the resistor 14. The current flowing from the transistor 12 to the resistors 14 and 15 is determined by the resistor 14 and the above-described base-emitter differential voltage, and the voltage drop across the resistors 14 and 15 is the temperature, the emitter area of the transistors 12 and 13, the resistors 14 and 15, It is a function of 16 resistance values. The base-emitter voltage of the transistor 12 is a function of the band gap voltage and temperature of silicon, which is a semiconductor substrate. By selecting the resistance values of the resistors 14, 15, and 16, the temperature coefficient and the emitter area included in the output voltage of the operational amplifier 11 can be compensated. The output voltage of the operational amplifier 11 is a silicon bandgap voltage ( It is approximately equal to approximately 1.1 [V]), and is a stable voltage that is not affected by temperature variations, manufacturing variations, and power supply voltage variations.

  FIG. 4 is a circuit diagram showing a configuration of the operational amplifier 30-i. In FIG. 4, an operational amplifier 30-i includes a differential stage, an output stage, a phase compensation circuit, differential input terminals 150 and 151, an output terminal 152, and a bias input terminal 153 to which a bias voltage is input. Composed. The differential stage includes nMOSs 141 and 142 serving as input transistors, pMOSs 143 and 144 serving as load transistors, and an nMOS 145 serving as a constant current transistor. The output stage includes a pMOS 146 serving as an output transistor and an nMOS 147 serving as a load transistor and a constant current transistor. The phase compensation circuit includes an nMOS 148, a pMOS 149, and a capacitor C1.

  In the differential stage, the gate electrode of the nMOS 141 is connected to the differential input terminal 150, and the drain electrode is connected to the drain electrode and gate electrode of the pMOS 143 and the gate electrode of the pMOS 144. The gate electrode of the nMOS 142 is connected to the differential input terminal 151, and the drain electrode is connected to the drain electrode of the pMOS 144. The source electrodes of the nMOS 141 and nMOS 142 are both connected to the drain electrode of the nMOS 145. The source electrodes of the pMOSs 143 and 144 are both connected to the positive power supply VDD. The gate electrode of the nMOS 145 is connected to the bias input terminal 153, and the source electrode is connected to the ground power supply GND. In the output stage, the gate electrode of the pMOS 146 is connected to the drain electrode of the differential stage pMOS 144, the source electrode is connected to the positive power supply VDD, and the drain electrode is connected to the drain electrode of the nMOS 147 and the output terminal 152. The gate electrode of the nMOS 147 is connected to the bias input terminal 153, and the source electrode is connected to the ground power supply GND.

  The operational amplifier 30-i is a class A CMOS amplifier, and drives a load element connected to the output terminal 152 by flowing or drawing a drive current from the output terminal. The higher the bias voltage, the larger the current flowing through the constant current nMOS 147, and a larger drive current can be drawn from the output terminal 152. That is, the higher the bias voltage, the greater the load driving capability of this class A CMOS amplifier. The constant current nMOSs 145 and 147 constitute a current mirror circuit with the nMOS 132 of the current / voltage conversion circuit 130 of the bias circuit 20-i. As the constant current nMOSs 145 and 147, transistors having the same conductance as the nMOS 132 or a conductance proportional to the nMOS 132 are used. The constant currents flowing through the constant current nMOSs 145 and 147 become the currents that are constantly consumed in the operational amplifier 30-i.

  In FIG. 1, the output terminal (the output terminal 17 in FIG. 3) of the reference voltage generating circuit 10 is the input terminal (the input terminal 116 in FIG. 2) of the bias circuits 20-1, 20-2, 20-3 via the node N1. )It is connected to the. The output terminal (the output terminal 133 in FIG. 2) of the bias circuit 20-1 having the diffusion reference resistance is connected to the bias input terminal (the bias input terminal 153 in FIG. 4) of the operational amplifier 30-1 via the node N2. Yes. A diffusion load resistor 60 is connected as a load element to the output terminal of the operational amplifier 30-1 (the output terminal 152 in FIG. 4). The output terminal of the bias circuit 20-2 having a polycrystalline Si reference resistor is connected to the bias input terminal of the operational amplifier 30-2 via the node N3. A polycrystalline Si load resistor 70 is connected to the output terminal of the operational amplifier 30-2 as a load element. The output terminal of the bias circuit 20-3 using the external reference resistor is connected to the bias input terminal of the operational amplifier 30-3 via the node N4. The output terminal of the operational amplifier 30-3 is connected to a load connection terminal 91, and an external load resistor 81 is connected to the load connection terminal 91.

  Next, the operation of the semiconductor integrated circuit 1 shown in FIG. 1 will be described. The reference voltage generation circuit 10 outputs a stable reference voltage that is not affected by temperature variation, manufacturing variation, and power supply voltage variation, and this reference voltage is supplied to the bias circuits 20-1, 20-2, and 20-3 via the node N1. The voltage is supplied to the reference voltage input terminal 116.

  In the bias circuit 20-i, the reference voltage from the reference voltage generating circuit 10 is input to the inverting input terminal (gate electrode of the nMOS 111) of the differential amplifier 110 through the reference voltage input terminal 116. The differential amplifier 110 amplifies the potential difference between the inverting input terminal and the non-inverting input terminal (the gate electrode of the nMOS 112 connected to the node N7), and outputs the amplified difference from the output terminal (the drain electrode of the nMOS 111) to the node N6. The common-source amplifier circuit 120, which receives the output of the differential amplifier 110 as an input, inverts and amplifies the voltage change at the node N6 and outputs it to the node N7. Due to the functions of the differential amplifier 110 and the common source amplifier circuit 120, the voltage of the node N7 becomes equal to the reference voltage input to the reference voltage input terminal 116. That is, when there is a difference between the input reference voltage and the voltage at the node N7, the differential amplifier 110 amplifies the difference voltage and applies the same to the common source amplifier circuit 120. The common source amplifier circuit 120 receives the differential amplifier 110 from the differential amplifier 110. Since the differential voltage thus amplified is inverted and amplified and output to the node N7 (because it is fed back to the non-inverting input terminal of the differential amplifier 110), the voltage at the node N7 is finally the reference voltage input to the reference voltage input terminal 116 Is equal to

  In the common source amplifier circuit 120, the current that the pMOS 121 passes through the reference resistor 122 (the external reference resistor 80 in the bias circuit 20-3) is the reference current. The current value of the reference current is obtained by dividing the voltage of the node N7 equal to the reference voltage by the resistance value of the reference resistor 122 (external reference resistor 80), and only the resistance value of the reference voltage and the reference resistor (external reference resistor). And does not depend on the power supply voltage and the characteristic variation (manufacturing variation) of other active elements.

  The current / voltage conversion circuit 130 converts the reference current flowing through the common-source amplifier circuit 120 into a bias voltage. The bias voltage supplied from the node N6 to the operational amplifier 30-i is input to the output of the node N6. Is output. Since the pMOS 131 is a transistor having the same conductance as the pMOS 121, the current flowing through the pMOS 131 and the nMOS 132 has the same value as the reference current flowing through the pMOS 121 and the reference resistor 122 (external reference resistor 80), and the reference voltage and the reference resistor (external reference) It is determined only by the resistance value of the resistor, and does not depend on the power supply voltage and the characteristic variation (manufacturing variation) of other active elements. Therefore, the bias voltage is determined only by the reference current and the impedance of the nMOS 132.

  On the other hand, in the operational amplifier 30-i, the bias voltage from the output terminal 133 of the bias circuit 20-i is input to the gate electrodes of the constant current nMOSs 145 and 147. The constant current nMOSs 145 and 147 are transistors having the same conductance or proportional conductance as the nMOS 132 of the current / voltage conversion circuit 130, and constitute a current mirror circuit with the nMOS 132. Therefore, the constant current nMOSs 145 and 147 include The flowing current has a value equal to or proportional to the reference current, and the current consumption of the differential stage and the output stage of the operational amplifier 30-i has a stable value that does not depend on the power supply voltage or the like. After all, the value of the current consumption of the operational amplifier 30-i is determined by the value of the reference voltage and the resistance value of the reference resistor 122 (external reference resistor 80). Does not depend on

  The diffusion load resistor 60 has a small resistance value at a low temperature. However, since the reference resistor 122 of the bias circuit 20-1 is a diffusion reference resistor, the resistance value of the diffusion reference resistor is also small like the diffusion load resistor 60. The reference current increases, and the current flowing through the pMOS 132 also increases in the same way as the reference current. As a result, the bias voltage rises, and the current flowing through the constant current nMOSs 145 and 147 of the operational amplifier 30-1 increases in the same way as the current flowing through the pMOS 132. Therefore, the operational amplifier 30-1 has a load resistance with a smaller resistance value. Can be driven. That is, when the resistance value of the diffusion load resistor 60 decreases at a low temperature, the driving capability of the operational amplifier 30-1 that drives the diffusion load resistor 60 increases, so that the output waveform of the operational amplifier 30-1 does not distort. .

  In conventional operational amplifiers (drive means) for semiconductor integrated circuits, power supply voltage fluctuations, temperature fluctuations, fluctuations in operational amplifier characteristics due to fluctuations in resistance values of reference resistors due to manufacturing fluctuations, and fluctuations in resistance values of load resistors are taken into account. Thus, the current value that flows through the constant current source transistor in the output stage of the operational amplifier is set to a current value that is significantly larger than the current value that needs to flow through the load resistor. However, in the operational amplifier (driving means) 30-1 of the semiconductor integrated circuit 1 of the present invention, the current value that flows through the constant current nMOS 147 in the output stage is slightly larger than the current value that needs to flow through the diffusion load resistor 60. The current value may be used, and the current consumed by the operational amplifier 30-1 can be significantly reduced.

  Further, the resistance values of a plurality of resistance elements formed on the same semiconductor integrated circuit vary to some extent as absolute values when the constituent materials of the resistance elements are the same, but are finished with relatively high accuracy as relative values. Therefore, even if the resistance value of the polycrystalline Si load resistor 70 decreases due to manufacturing variations, the polycrystalline Si reference resistance of the bias circuit 20-2 also decreases proportionally, and the reference current flowing through the polycrystalline Si reference resistor Therefore, the bias voltage generated by the bias circuit 20-2 increases. As a result, the current flowing through the constant current nMOSs 145 and 147 of the operational amplifier 30-2 that drives the polycrystalline Si load resistor 70 is increased, and the drive capability of the operational amplifier 30-2 is increased. The waveform will not be distorted. Also, in the operational amplifier (driving means) 30-2, similarly to the operational amplifier 30-1, the current value that flows in the constant current nMOS 147 in the output stage is larger than the current value that needs to flow in the polycrystalline Si load resistor 70. A slightly larger current value may be used, and the current consumed by the operational amplifier 30-2 can be significantly reduced.

  Further, the resistance values of the external reference resistor 80 and the external load resistor 81 are highly accurate and have little temperature fluctuation, as described above. The bias circuit 20-3 uses the external reference resistor 80, and the operational amplifier 30-3 drives the external load resistor 81. Therefore, the bias circuit 20-3 is biased regardless of temperature variations and manufacturing variations of the resistance elements on the semiconductor integrated circuit. Circuit 20-3 generates a stable bias voltage. Since the bias voltage and the resistance value of the external load resistor 81 are stable, the output waveform of the operational amplifier 30-3 is not distorted. Also in the operational amplifier (driving means) 30-3, as in the operational amplifiers 30-1 and 30-2, the current that needs to flow through the constant current nMOS 147 in the output stage must be passed through the external load resistor 81. The current value is slightly larger than the current value, and the current consumed by the operational amplifier 30-3 can be greatly reduced.

  As described above, according to the first embodiment, the operational amplifier 30-1 that drives the diffusion load resistor 60, the operational amplifier 30-2 that drives the polycrystalline Si load resistor 70, and the operational amplifier 30 that drives the external load resistor 81. -3, a bias circuit 20-1 having a diffusion reference resistance, a bias circuit 20-2 having a polycrystalline Si reference resistance, and a bias circuit 20-3 using an external reference resistance are provided, and a bias having a diffusion reference resistance is provided. The bias voltage generated by the circuit 20-1 is supplied to the operational amplifier 30-1, the diffusion load resistor 60 is driven by the operational amplifier 30-1, and the bias circuit 20-2 having the polycrystalline Si reference resistance is generated. A bias voltage is supplied to the operational amplifier 30-2, the polycrystalline Si load resistor 70 is driven by the operational amplifier 30-2, and an external reference resistor is used. The bias voltage generated by the bias circuit 20-3 is supplied to the operational amplifier 30-3, and the external load resistor 81 is driven by the operational amplifier 30-3. Thus, it is possible to realize a stable semiconductor integrated circuit in which the output waveform of the operational amplifier is not distorted.

  That is, the load resistance component material driven by the operational amplifier (driving means) and the reference resistance component material of the bias circuit for supplying a bias voltage to the operational amplifier are made the same, and the external load resistance is driven. If the bias voltage supplied to the amplifier is generated by a bias circuit using an external reference resistor, and the resistance value of the load resistor of the operational amplifier decreases due to temperature fluctuations or manufacturing variations, the resistance value of the reference resistor of the bias circuit And the load driving capability of the operational amplifier is increased, so that a stable semiconductor integrated circuit without fear of distortion of the output waveform of the operational amplifier can be realized.

  Further, unlike the conventional semiconductor integrated circuit, the current value flowing through the constant current transistor at the output stage of the operational amplifier does not need to be much larger than the current value required to flow through the load resistor. Since a current value that is slightly larger than the current value that needs to flow through the resistor may be used, the current consumed by the semiconductor integrated circuit can be significantly reduced.

  As a resistor formed on a semiconductor integrated circuit, a diffused resistor generally has a high sheet resistance. Therefore, a resistor having a high resistance value can be realized in the same area, but a slight harmonic distortion occurs. In addition, the polycrystalline Si resistor has a characteristic that hardly generates harmonic distortion. In the first embodiment, using the resistance characteristics of different constituent materials, a diffused resistor and a polycrystalline Si resistor are mixed on the same semiconductor integrated circuit. The invention is effective when the crystal Si resistance is properly used, and a first bias circuit having a reference resistance of the first constituent material is provided for the operational operational amplifier that drives the load resistance of the first constituent material. The operational amplifier that drives the load resistance of the second constituent material is provided with a second bias circuit having a reference resistance of the second constituent material. Furthermore, the first embodiment is characterized in that a third bias circuit using an external reference resistor is provided for an operational amplifier that drives an external load resistor.

  The semiconductor integrated circuit 1 according to the first embodiment includes a first analog circuit block including a plurality of load resistors composed of a first constituent material and an operational amplifier that drives the load resistor, and a load composed of a second constituent material. A resistor and a second analog circuit block including a plurality of operational amplifiers for driving the resistor may be mixed. In this case, the first bias circuit is connected to the first analog circuit block. And the second bias circuit may be provided for the second analog circuit block.

  The semiconductor integrated circuit 1 of the first embodiment includes the first and second analog circuit blocks, a load connection terminal for connecting an external load resistor, and an operational amplifier for driving the external load resistor. May be mixed with a third analog circuit block including a plurality of. In this case, the third bias circuit may be provided for the third analog circuit block. Alternatively, the first analog circuit block and the third analog circuit block may be mixed on the same semiconductor integrated circuit. In this case, the first and third bias circuits may be provided.

  In the first embodiment, the case where the first and second load elements formed on the semiconductor integrated circuit are diffused resistors and polycrystalline Si resistors, and the external load elements are external load resistors is described. However, either the first load element or the second load element may be a capacitor, and the external load element may be a capacitor. Since the capacitor has high accuracy and small temperature fluctuation, when the load element (external load element) is a capacitor, the bias circuit 20-3 using an external reference resistor may be used as the bias circuit of the operational amplifier. In addition, a bias circuit 20-2 having a polycrystalline Si reference resistance may be used as long as manufacturing variations in the polycrystalline Si resistance are allowed. If manufacturing variations of the polycrystalline Si resistor are allowed, either the bias circuit 20-2 having the polycrystalline Si reference resistor or the bias circuit 20-3 using the external reference resistor is deleted, and the other bias is applied. The bias voltage generated by the circuit may be supplied to the operational amplifier 30-2 that drives the polycrystalline Si load resistor 70 and the operational amplifier 30-3 that drives the external load resistor 81.

  That is, the semiconductor integrated circuit 1 according to the first embodiment is a semiconductor integrated circuit in which two or more types of load elements having different electrical characteristics such as temperature characteristics are mixed or formed on the semiconductor integrated circuit. The load element may be mixed with a load connection terminal for connecting an external load element having an electrical characteristic such as a temperature characteristic different from that of the load element. In this case, a bias circuit may be provided for each load element having different electrical characteristics or external load elements, and a resistor having a similar electrical characteristic to the corresponding load element may be used as the reference resistance of each bias circuit.

  Further, in the semiconductor integrated circuit in which the first to third analog circuit blocks are mixed, a second load element included in the second analog circuit block and an external load element connected to the third analog circuit block If the electrical characteristics of the second and third analog circuit blocks are similar to each other, the second load element and the third load circuit are connected to a reference resistor (external resistor) having similar electrical characteristics to the second load element and the external load element. It is sufficient to provide one bias circuit using a reference resistance.

Embodiment 2
FIG. 5 is a circuit diagram showing a semiconductor integrated circuit 160 according to the second embodiment of the present invention. The semiconductor integrated circuit 160 of FIG. 5 includes a reference voltage generation circuit 10, a control circuit 161, a bias circuit 210, a first analog circuit block 190, a second analog circuit block 200, and external connection terminals 162 and 163. And a power supply connection terminal 164 connected to the ground power supply GND and a power supply connection terminal 165 connected to the positive power supply VDD. The first analog circuit block 190 and the second analog circuit block 200 are functional blocks summarized from the viewpoint of power-down control. In FIG. 5, the same components as those in FIG.

  In FIG. 5, the control circuit 161 includes a first input terminal connected to the external connection terminal 162 of the semiconductor integrated circuit 160, a second input terminal connected to the external connection terminal 163 of the semiconductor integrated circuit 160, and a node N10. The first analog circuit block 190 has a first output terminal connected to it and a second output terminal connected to the node N13. The first analog circuit block 190 is externally input to the first and second input terminals. A first control signal indicating whether to operate or power down is output to the first output terminal, and a second control signal indicating whether to operate or power down the second analog circuit block 200 is output to the second control signal. Output to the output terminal.

  The bias circuit 210 includes a voltage dividing circuit 100, a differential amplifier 110, a common source amplifier circuit 120, a first current / voltage conversion circuit 170, and a second current / voltage conversion circuit 180. That is, the bias circuit 210 is obtained by providing current / voltage conversion circuits 170 and 180 instead of the current / voltage conversion circuit 130 in the bias circuit 20-i of FIG. Although the bias circuit 210 includes the reference resistor 122, an external reference resistor may be used as in the bias circuit 20-3 of FIG. Therefore, also in FIG. 5, the reference voltage from the reference voltage generating circuit 10 is input to the inverting input terminal of the differential amplifier 110 (the gate electrode of the nMOS 111).

  The first current / voltage conversion circuit 170 includes pMOSs 171 and 173, nMOSs 172, 174 and 175, and an inverter 176. The gate electrode of the pMOS 173 is connected to the node N10 connected to the first output terminal of the control circuit 161, the drain electrode is connected to the node N9, and the source electrode is connected to the positive power supply VDD. The gate electrode of the nMOS 174 is connected to the node N10, the drain electrode is connected to the node N9, and the source electrode is connected to the node N6 (the node to which the gate electrode of the pMOS 121 of the common-source amplifier circuit 120 is connected). . The gate electrode of the pMOS 171 is connected to the node N9, the source electrode is connected to the positive power supply VDD, and the drain electrode is connected to the node N12. The conductance of the pMOS 171 is assumed to be the same as that of the pMOS 121 of the common source amplifier circuit 120.

  The input terminal of the inverter 176 is connected to the node N10, and the output terminal is connected to the node N11. The gate electrode of the nMOS 175 is connected to the node N11, the source electrode is connected to the ground power supply GND, and the drain electrode is connected to the node N12. The gate electrode and drain electrode of the nMOS 172 are connected to the node N12, and the source electrode is connected to the ground power supply GND. The input terminal of the first current / voltage conversion circuit 170 is the node N6, the control input terminal is the node N10, and the output terminal is the node N12. The first current / voltage conversion circuit 170 operates or powers down the first analog circuit block 190 in accordance with the first control signal input from the control circuit to the control input terminal.

  The second current / voltage conversion circuit 180 includes pMOSs 181 and 183, nMOSs 182, 184 and 185, and an inverter 186. The second current / voltage conversion circuit 180 has the same configuration as that of the first current / voltage conversion circuit 170. The pMOSs 181 and 183 correspond to the pMOSs 171 and 173 of the first current / voltage conversion circuit 170, respectively. , 184, 185 correspond to the nMOSs 172, 174, 175 of the first current / voltage conversion circuit 170, respectively, and the inverter 186 corresponds to the inverter 176 of the first current / voltage conversion circuit 170. The conductance of the pMOS 181 is assumed to be the same as that of the pMOS 121 of the common source amplifier circuit 120. The nodes N13 and N14 of the second current / voltage conversion circuit 180 correspond to N10 and N12 of the first current / voltage conversion circuit 170, respectively. The input terminal of the second current / voltage conversion circuit 180 is a node N6, the control input terminal is a node N13 connected to the second output terminal of the control circuit 161, and the output terminal is a node N14. The second current / voltage conversion circuit 180 operates or powers down the second analog circuit block 200 in accordance with the second control signal input from the control circuit 161 to the control input terminal.

  As described above, the bias circuit 210 generates a single reference current from the input reference voltage, and generates a plurality of bias voltages from the reference current. In other words, the bias circuit 210 is composed of one reference current generating means including a differential amplifier 110 and a common-source amplifier circuit 120 including one reference resistor 122, and a plurality of current / voltage conversion circuits. A plurality of bias voltages are generated from a single reference resistor formed on the circuit.

  The first analog circuit block 190 includes operational amplifiers 30-11, 30-12, and the like, and the second analog circuit block 200 includes operational amplifiers 30-13, 3-14, and the like. The internal configuration of the operational amplifier 30-j (j is an arbitrary integer from 11 to 14) is the same as that of the operational amplifier of the first embodiment shown in FIG. The bias input terminals (the bias input terminal 153 in FIG. 4) of the operational amplifiers 30-11 and 30-12 of the first analog circuit block 190 are connected to the node N12 that is the output terminal of the first current / voltage conversion circuit 170. The bias input terminals of the operational amplifiers 30-13 and 30-14 of the second analog circuit block 200 are connected to the node N 14 that is the output terminal of the second current / voltage conversion circuit 180. The first analog circuit block 190 operates normally when a bias voltage according to the potential of the node N6 is output to the node N12 by the first current / voltage conversion circuit, and when the node N12 is at the GND potential. Power down. Similarly, the second analog circuit block 200 operates normally when a bias voltage according to the potential of the node N6 is output to the node N14 by the second current / voltage conversion circuit, and the node N14 becomes the GND potential. Power down when you are.

  Note that the analog circuit blocks 190 and 200 are not limited to circuits having operational amplifiers, and may be any circuit having a current source such as a constant current transistor that receives a bias voltage. For example, the analog circuit blocks 190 and 200 may be comparators or PLL circuits having constant current transistors.

  Next, the operation of the semiconductor integrated circuit 160 in FIG. 5 will be described. The reference voltage generation circuit 10 supplies the reference voltage to the inverting input terminal (gate electrode of the nMOS 111) of the differential amplifier 110 of the bias circuit 210. In the bias circuit 210, the voltage of the node N7 becomes equal to the reference voltage by the action of the differential amplifier 110 and the common source amplifier 120.

  The control circuit 161 includes, for example, a logic gate and a buffer, and the potential level of the first control signal and the potential of the second control signal are determined according to two external control signals input via the external connection terminals 162 and 163. The level is set to the high level (VDD potential) or the low level (GND potential), respectively, and the first control signal is output to the node N10, and the second control signal is output to the node N13. Here, when the first control signal of the control circuit 161 is at a high level, it means that the first analog circuit block 190 is operated. When the first control signal is at a low level, This means that the first analog circuit block 190 is powered down. Similarly, when the second control signal of the control circuit 161 is at a high level, it means that the second analog circuit block 200 is operated. When the second control signal is at a low level, the second control signal is second. This means that the analog circuit block 200 is powered down. That is, when the control circuit 161 sets the first control signal to a high level, the first current / voltage conversion circuit 170 operates the first analog circuit block 190, and the control circuit 161 operates the first control signal. Is set to a low level, the first current / voltage conversion circuit 170 powers down the first analog circuit block 190. Similarly, when the control circuit 161 sets the second control signal to a high level, the second current / voltage conversion circuit 180 operates the second analog circuit block 200, and the control circuit 161 performs the second control signal. By setting the signal to a low level, the second current / voltage conversion circuit 180 powers down the second analog circuit block 200.

  When the first control signal is at a high level, in the first current / voltage conversion circuit 170, the node N10 is at a high level, so that the pMOS 173 is turned off and the nMOS 174 is turned on. Since the pMOS 173 is OFF and the nMOS 174 is ON, the voltage of the node N6 is applied to the gate electrode of the pMOS 171 and the pMOS 171 operates in the saturation region. Further, the first control signal is inverted by the inverter 176 and the node N11 becomes low level, so that the nMOS 175 is turned off. Therefore, when the first control signal is at a high level, the first current / voltage conversion circuit 170 has the same configuration as the current / voltage conversion circuit 130 of FIG. 2 (pMOS 171 corresponds to pMOS 131 of FIG. 2 and nMOS 172 2 corresponds to the nMOS 132 in FIG. 2), a current having the same current value as the reference current generated by the common-source amplifier 120 flows through the pMOS 171 and the nMOS 172, and a bias voltage determined by this current and the impedance of the nMOS 172 is generated at the node N12. The This bias voltage is supplied to the gate electrodes of the constant current sources nMOS 145 and 147 (shown in FIG. 4) of the operational amplifiers 30-11 and 30-12 of the first analog circuit block 190, and the first analog circuit block 190 is normal. Operate.

  Similarly, when the second control signal is at a high level, in the second current / voltage conversion circuit 180, the pMOS 183 is turned off and the nMOS 184 is turned on, so that the voltage of the node N6 is applied to the gate electrode of the pMOS 181. The pMOS 181 operates in the saturation region. Further, the nMOS 185 is turned off by the inverter 186. Therefore, when the second control signal is at a high level, the second current / voltage conversion circuit 180 has the same configuration as the current / voltage conversion circuit 130 of FIG. 2, and the pMOS 181 and the nMOS 182 generate the common source amplifier 120. A current having the same current value as the reference current flows, and a bias voltage determined by this current and the impedance of the nMOS 182 is generated at the node N14. This bias voltage is supplied to the bias input terminals of the operational amplifiers 30-13 and 30-14 of the second analog circuit block 200, and the second analog circuit block 200 operates normally.

  Next, when the first control signal is at a low level, in the first current / voltage conversion circuit 170, the node N10 is at a low level, so that the pMOS 173 is turned on and the nMOS 174 is turned off. Thereby, the gate electrode of the pMOS 171 becomes a high level (VDD potential), and the pMOS 171 is turned OFF. Further, since the node N11 becomes high level by the inverter 176, the nMOS 175 is turned ON. Therefore, when the first control signal is at low level, the node N12 is at low level (GND potential). Since the node N12 becomes the GND potential, the gate electrodes of the constant current sources nMOS 145 and 147 (see FIG. 4) of the operational amplifiers 30-11 and 30-12 of the first analog circuit block 190 become the GND potential, and the constant current nMOS 145 And 147 are turned OFF. When the constant current nMOSs 145 and 147 are turned off, the consumption current does not flow in the operational amplifiers 30-11 and 30-12, and the first analog circuit block 190 enters the power down state.

  Similarly, when the second control signal is at the low level, the pMOS 183 is turned on and the nMOS 184 is turned off in the second current / voltage conversion circuit 180, so that the gate electrode of the pMOS 181 is at the high level (VDD potential). , PMOS 181 is turned OFF. Further, the nMOS 185 is turned on by the inverter 186. Therefore, when the second control signal is at the low level, the node N14 is at the low level (GND potential), and the constant current sources nMOS 145 and 147 (the operational amplifiers 30-13 and 30-14 of the second analog circuit block 190) ( 4) is turned off, current consumption does not flow in the operational amplifiers 30-13 and 30-14, and the second analog circuit block 200 enters a power-down state.

  It should be noted that even if there is a constant current source such as a constant current transistor that does not constitute an operational amplifier and inputs a bias voltage in the first analog circuit block 190 or the second analog circuit block 200, By setting the bias voltage to a low level, no current flows through the constant current source, and the entire analog circuit block can be put into a power-down state.

  As described above, according to the second embodiment, one reference current generating unit including one reference resistor 122 is provided on the semiconductor integrated circuit 160 having a plurality of analog circuit blocks collected from the viewpoint of power-down control. A plurality of current / voltage conversion circuits corresponding to the respective analog circuit blocks, provided with a bias circuit to which a reference voltage and a plurality of control signals corresponding to the respective analog circuit blocks are input, and the reference current generating means described above Generates a single reference current from the reference voltage, and generates a separate bias voltage from the single reference current by each current / voltage conversion circuit, and generates a corresponding analog circuit block based on the corresponding control signal. Since the bias voltage is output or the output is stopped, the standard that has been formed for the number of analog circuit blocks in the past It is possible to reduce the number of anti. Since the resistors on the semiconductor integrated circuit require a wide pattern area, the area occupied by the bias circuit on the semiconductor integrated circuit can be reduced by reducing the number of reference resistors, and thus the semiconductor integrated circuit having a small chip size. A circuit can be realized, and the cost reduction of the semiconductor integrated circuit can be achieved by reducing the chip size.

  In addition, since the number of the voltage dividing circuit 100, the differential amplifier 110, and the common-source amplifier circuit 120 is reduced as compared with the conventional circuit, the current consumption of these circuits can be reduced as compared with the conventional circuit, and thus the current consumption of the semiconductor integrated circuit is reduced. can do.

  In FIG. 5, when both the first analog circuit block 190 and the second analog circuit block 200 are powered down, the voltage dividing circuit 100, the differential amplifier 110, and the common source amplifier circuit 120 are powered down. Although no circuit is provided, this circuit can be easily added.

  The control circuit 161 is not always necessary, and the first and second control signals may be supplied from the outside to the first current / voltage conversion circuit 170 and the second current / voltage conversion circuit 180.

  In addition, when a plurality of analog circuit blocks that require different values of bias voltages are mixed on the semiconductor integrated circuit, for example, when the power down control is unnecessary, the current / voltage conversion circuit 170, Instead of the current / voltage conversion circuit 180, the current / voltage conversion circuits 130 shown in FIG. 2 may be provided for the number of analog circuit blocks. This makes it possible to reduce the chip size of the semiconductor integrated circuit and reduce the cost as compared with the conventional case where a bias circuit is provided for each analog circuit block. Can be small.

  In the first and second embodiments, the semiconductor integrated circuit mainly composed of MOS transistors has been described. However, the transistors constituting the semiconductor integrated circuit are not limited to MOS.

  The features of the present invention are summarized below.

(1) a load connection terminal for connecting a load element formed on the semiconductor integrated circuit and / or an external load element;
A plurality of drive means for individually driving the load element or the external load element with a drive current according to a bias voltage;
A bias circuit that generates the bias voltage based on an input reference voltage and a reference resistor formed on a semiconductor integrated circuit, and / or generates the bias voltage based on an input reference voltage and an external reference resistor A bias circuit,
The reference resistance of the bias circuit or / and the external reference resistance is a reference resistance having electrical characteristics similar to the corresponding load element or / and the external load element, or is electrically connected to the corresponding load element or / and the external load element. A semiconductor integrated circuit characterized in that it is an external reference resistor with similar characteristics.

(2) The semiconductor integrated circuit according to (1), wherein the driving means is an operational amplifier including a constant current transistor, and the bias voltage is input to a control electrode of the constant current transistor. .

(3) a first load element;
A second load element;
First driving means for driving the first load element with a driving current according to a first bias voltage;
Second driving means for driving the second load element with a driving current corresponding to a second bias voltage;
A first bias circuit including a first reference resistor made of a first constituent material and generating the first bias voltage based on the input reference voltage and the first reference resistor;
And a second bias circuit including a second reference resistor made of a second constituent material, and generating a second bias voltage based on the input reference voltage and the second reference resistor. A semiconductor integrated circuit.

(4) The first load element is a load resistor made of the first constituent material, and the second load element is a capacitor or a load resistor made of the second constituent material. The semiconductor integrated circuit according to (3) above.
(5) The semiconductor integrated circuit according to (4), wherein the first constituent material is a diffusion resistance layer, and the second constituent material is a polycrystalline silicon resistance layer.
(6) Further, a first analog circuit block including a plurality of the first load elements and the first driving means, and a second analog circuit block including a plurality of the second load elements and the second driving means. The semiconductor integrated circuit according to (4), further comprising an analog circuit block.
(7) The first bias circuit includes the first reference resistor as a load, and a first amplifier circuit that supplies a reference current corresponding to an output voltage to the first reference resistor, and an input reference A first differential amplifier for generating a voltage to be input to the first amplifier circuit, and converting the reference current into a voltage so that the voltage and the output voltage level of the first amplifier circuit are the same. And a first current / voltage conversion circuit for generating the first bias voltage. The second bias circuit includes the second reference resistor as a load and corresponds to the output voltage. A second amplifier circuit that causes the reference current to flow through the second reference resistor, and the second amplifier circuit so that the input reference voltage and the output voltage level of the second amplifier circuit are the same. A second differential amplifier for generating a voltage to be input to The semiconductor integrated circuit according to (3), further comprising: a second current / voltage conversion circuit that generates the second bias voltage by converting the reference current into a voltage.
(8) Further, it has a load connection terminal for connecting an external load element, and third drive means for driving the external load element with a drive current according to a second bias voltage. The semiconductor integrated circuit according to (3) above.
(9) Furthermore, a load connection terminal for connecting an external load element, a third drive means for driving the external load element with a drive current corresponding to a third bias voltage, and an external reference resistor (3), comprising: a reference resistance connection terminal for connection; and a third bias circuit that generates the third bias voltage based on the input reference voltage and the external reference resistance. The semiconductor integrated circuit as described.
(10) The amplification circuit that causes the third bias circuit to pass a reference current corresponding to the output voltage to the external reference resistor, and the level of the input reference voltage and the output voltage of the amplification circuit are the same As described above, a differential amplifier that generates a voltage to be input to the amplifier circuit, and a current / voltage conversion circuit that generates the third bias voltage by converting the reference current into a voltage. The semiconductor integrated circuit according to (9) above.

(11) a load element, a first drive means for driving the load element with a drive current corresponding to the first bias voltage, a load connection terminal for connecting an external load element, and a second bias voltage A second driving means for driving the external load element with a corresponding driving current; and a first bias that includes a reference resistance and generates the first bias voltage based on the input reference voltage and the reference resistance A circuit, a reference resistor connection terminal for connecting an external reference resistor, and a second bias circuit for generating the second bias voltage based on the input reference voltage and the external reference resistor A semiconductor integrated circuit.

(12) The semiconductor integrated circuit according to (11), wherein the load element and the reference resistor are diffused resistors.
(13) Further, a first analog circuit block including a plurality of the load elements and the first drive means, and a second analog circuit block including a plurality of the load connection terminals and the second drive means. The semiconductor integrated circuit as set forth in (11) above, characterized in that it has.
(14) The first bias circuit includes the reference resistor as a load, and a first amplifier circuit that flows a reference current corresponding to an output voltage to the reference resistor; an input reference voltage; A first differential amplifier that generates a voltage that is input to the first amplifier circuit, and the reference current is converted into a voltage so that the level of the output voltage of the amplifier circuit is the same; A first current / voltage conversion circuit that generates one bias voltage, and the second bias circuit causes the reference current corresponding to the output voltage to flow through the external reference resistor; A second differential amplifier for generating a voltage to be input to the second amplifier circuit so that the input reference voltage and the level of the output voltage of the second amplifier circuit are the same, and the reference By converting current to voltage, The semiconductor integrated circuit according to (11), further comprising: a second current / voltage conversion circuit that generates a second bias voltage.
(15) The above (11), further comprising: a second load element; and third drive means for driving the second load element with a drive current corresponding to the second bias voltage. The semiconductor integrated circuit as described.
(16) The semiconductor integrated circuit according to (15), wherein the second load element is a capacitor or a polycrystalline silicon resistor.
(17) The semiconductor integrated circuit according to (15), further comprising an analog circuit block including a plurality of the second load elements and the third driving means.

(18) A first constant current source whose current value is determined by the first bias voltage, a second constant current source whose current value is determined by the second bias voltage, and an input reference voltage. 1. A semiconductor integrated circuit comprising: a bias circuit that generates one reference current and generates the first and second bias voltages based on the reference current.
(19) The semiconductor integrated circuit as described in (18) above, wherein the first and second constant current sources are constant current transistors in which the first and second bias voltages are applied to a control electrode. circuit.
(20) The bias circuit includes a reference resistor through which the reference current flows, and generates the first bias voltage by converting the reference current into a voltage, and a reference current generating unit that generates the reference current. The above-mentioned (18), comprising: a first current / voltage conversion circuit; and a second current / voltage conversion circuit that generates the second bias voltage by converting the reference current into a voltage. The semiconductor integrated circuit as described.
(21) The reference current generating means includes the reference resistor as a load, and an amplifier circuit that flows a reference current according to the output voltage to the reference resistor, and the input reference voltage and the level of the output voltage of the amplifier circuit are The semiconductor integrated circuit according to (20), further comprising a differential amplifier that generates a voltage to be input to the amplifier circuit so as to be the same.
(22) The first current / voltage conversion circuit generates the first bias voltage when the first control signal is at the first level, and the second current / voltage conversion circuit includes the second current / voltage conversion circuit The semiconductor integrated circuit according to (21), wherein the second bias voltage is generated when the control signal is at the first level.
(23) In the amplifier circuit, a control electrode is connected to an output of the differential amplifier, a first electrode is connected to a first power supply, and a second electrode is connected to a second power supply via the reference resistor. The first or second current / voltage conversion circuit has a first transistor, the control signal is input to a control electrode, and the first electrode is connected to the first power source. A third transistor in which the control signal is input to the control electrode, the first electrode is connected to the second electrode of the first transistor, and the second electrode is connected to the second electrode of the second transistor. A control electrode connected to the second electrode of the second transistor, a first electrode connected to the first power supply, and a second electrode serving as an output terminal for the bias voltage; An inverted signal of the control signal is input to the electrode A fifth transistor having a first electrode connected to the second power supply, a second electrode connected to the bias voltage output terminal, a first electrode connected to the second power supply, a control electrode, The semiconductor integrated circuit according to (22), wherein the second electrode has a sixth transistor connected to the bias voltage output terminal.
(24) Further, a first analog circuit block including one or a plurality of the first constant current sources and a second analog circuit block including one or a plurality of the second constant current sources are provided. The first current / voltage conversion circuit supplies the first bias voltage to the first constant current source when the first control signal is at the first level. An analog circuit block is put into an operating state, and when the first control signal is at a second level, the supply of the first bias voltage is stopped to bring the first analog circuit block into a power-down state. The second current / voltage conversion circuit supplies the second bias voltage to the second constant current source by supplying the second bias voltage when the second control signal is at the first level. The analog circuit block When the second control signal is at the second level, the supply of the second bias voltage is stopped to bring the second analog circuit block into a power-down state. The semiconductor integrated circuit according to (22), characterized in that it is characterized in that:
(25) The first analog circuit block includes an operational amplifier configured by using the first constant current source and having a consumption current value determined by the first bias voltage. The circuit integrated circuit according to (24), wherein the circuit block includes an operational amplifier configured by using the second constant current source and having a current consumption value determined by the second bias voltage. .

1 is a circuit block diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of a bias circuit in the semiconductor integrated circuit according to the first embodiment of the present invention. It is a circuit diagram which shows the structure of the reference voltage preparation circuit used for the semiconductor integrated circuit of this invention. It is a circuit diagram which shows the structure of the operational amplifier used for the semiconductor integrated circuit of this invention. It is a circuit diagram which shows the semiconductor integrated circuit of Embodiment 2 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,160 Semiconductor integrated circuit, 10 Reference voltage preparation circuit, 20,210 Bias circuit, 30 Operational amplifier, 60 Diffusion load resistance, 70 Polycrystalline Si load resistance, 80 External reference resistance, 81 External load resistance, 90 Reference resistance Connection terminal, 91 load connection terminal, 110 differential amplifier, 120 source ground amplification circuit, 130, 170, 180 current / voltage conversion circuit, 145, 147 constant current nMOS, 161 control circuit, 121, 171, 173, 181 183 pMOS, 172,174,175,182,184,185 nMOS, 190,200 Analog circuit block.

Claims (7)

A first analog circuit block including one or a plurality of first constant current sources whose current values are determined by a first bias voltage;
A second analog circuit block including one or a plurality of second constant current sources whose current values are determined by a second bias voltage;
Generates a single reference current from the input reference voltage, have a bias circuit for generating the first and second bias voltage based on the reference current,
The bias circuit comprises:
A reference current generating means for generating the reference current, including a reference resistor for flowing the reference current;
A first current / voltage conversion circuit that generates the first bias voltage by converting the reference current into a voltage;
A second current / voltage conversion circuit that generates the second bias voltage by converting the reference current into a voltage;
The first current / voltage conversion circuit generates the first bias voltage when the first control signal is at the first level, and applies the first bias voltage to the first constant current source. By supplying the first analog circuit block, the first analog circuit block is activated, and when the first control signal is at the second level, the supply of the first bias voltage is stopped, whereby the first analog circuit is stopped. The block is powered down,
The second current / voltage conversion circuit generates the second bias voltage when the second control signal is at the first level, and applies the second bias voltage to the second constant current source. By supplying the second analog circuit block, the second analog circuit block is activated, and when the second control signal is at the second level, the supply of the second bias voltage is stopped, whereby the second analog circuit is stopped. A semiconductor integrated circuit characterized in that the block is put into a power-down state .   2. The semiconductor integrated circuit according to claim 1, wherein the first and second constant current sources are constant current transistors in which the first and second bias voltages are applied to a control electrode. The reference current generating means is
An amplifying circuit including the reference resistor as a load and flowing a reference current according to the output voltage to the reference resistor;
Level of the input reference voltage and the output voltage of the amplifier circuit so are the same, the semiconductor integrated according to claim 1, characterized in that it has a differential amplifier for generating a voltage as an input of the amplifier circuit circuit. The amplifier circuit is
A first transistor having a control electrode connected to the output of the differential amplifier, a first electrode connected to a first power supply, and a second electrode connected to a second power supply via the reference resistor; ,
The first or second current / voltage conversion circuit includes:
A second transistor in which the control signal is input to a control electrode, and a first electrode is connected to the first power source;
The control signal is input to the control electrode, a first electrode connected to said control electrode of said first transistor, a third transistor second electrode is coupled to the second electrode of the second transistor ,
A control electrode connected to the second electrode of the second transistor, a first electrode connected to said first power supply, and a fourth transistor having a second electrode serves as an output terminal of said bias voltage,
A fifth transistor in which an inverted signal of the control signal is input to a control electrode, a first electrode is connected to the second power supply, and a second electrode is connected to the bias voltage output terminal;
The semiconductor integrated circuit according to claim 3 , further comprising: a sixth transistor having a first electrode connected to the second power source and a control electrode and a second electrode connected to the bias voltage output terminal. The first analog circuit block includes an operational amplifier configured by using the first constant current source and having a current consumption value determined by the first bias voltage.
The second analog circuit block, the second is constituted by using a constant current source, according to claim 1, wherein the consumption current value is characterized in that it comprises an operational amplifier is determined by said second bias voltage Semiconductor integrated circuit.   According to the external control signal input from the outside
  Outputting the first control signal indicating whether to operate or power down the first analog circuit block;
  2. The semiconductor integrated circuit according to claim 1, further comprising a control circuit that outputs the second control signal indicating whether the second analog circuit block is operated or powered down.   The first power source is a positive power source;
  The second power source is a ground power source;
  The first, second and fourth transistors are pMOS transistors;
  The third, fifth, and sixth transistors are nMOS transistors.
  5. The semiconductor integrated circuit according to claim 4, wherein:

Images