JP4097989B2 - Bandgap reference circuit - Google Patents

Description

ここで、ＲＭ１≪Ｒ１である。
【００２２】

ここで、ＲＭ４≪（Ｒ２＋Ｒ３）である。
【００２３】
また、ＲＭ１〜ＲＭ４≪Ｒ１〜Ｒ３の関係にあるので、Ｉ２、Ｉ３≫Ｉ１、Ｉ４となる。

とすると、Ｉ２、Ｉ３は上記のように大きいので、ΔＶＢＥも大きくなる。このとき、ノード電圧ＶＮ３は、（３）式、（８）式および（１７）式を参照して求めると次の（２１）式のようになる。
【００２４】

ここで、ΔＶＢＥ＝ＶＢＥ（Ｑ１）＋ＶＢＥ（Ｑ２）−｛ＶＢＥ（Ｑ３）＋ＶＢＥ（Ｑ４）｝＝ＶＮ１−｛ＶＢＥ（Ｑ３）＋ＶＢＥ（Ｑ４）｝である。
【００２５】
従って、（２１）式からノード電圧ＶＮ３とノード電圧ＶＮ１の差の電圧（ＶＮ３−ＶＮ１）を求めると、次の（２２）式のようになる。
（ＶＮ３−ＶＮ１）＝｛ＶＤＤ−〔ＶＢＥ（Ｑ４）＋ＶＢＥ（Ｑ３）〕｝／｛Ｒ３／（Ｒ２＋Ｒ３）｝−ΔＶＢＥ・・・・（２２）
【００２６】
【発明が解決しようとする課題】
ところで、（２２）式において、Ｒ３／（Ｒ２＋Ｒ３）は温度特性を打ち消すために決められ、一般に１／１０〜１／５程度である。
このため、｛ＶＤＤ−〔ＶＢＥ（Ｑ４）＋ＶＢＥ（Ｑ３）〕｝／｛Ｒ３／（Ｒ２＋Ｒ３）｝＜ΔＶＢＥとなり得る。
【００２７】
このようにＶＮ３−ＶＮ１＜０なってＶＮ３＜ＶＮ１となると、オペアンプ１３の出力電圧ＰＢは下がろうとするので、ＶＳＳ＝０になったままである。この結果、この異常状態から抜け出すことができない。
一方、電源電圧ＶＤＤが高くなると、｛ＶＤＤ−〔ＶＢＥ（Ｑ４）＋ＶＢＥ（Ｑ３）〕｝／｛Ｒ３／（Ｒ２＋Ｒ３）｝の増加の方が、ΔＶＢＥの増加よりも大きい。このため、ＶＮ３−ＶＮ１＞０となってＶＮ３＞ＶＮ１となり、オペアンプ１３の出力電圧ＰＢが上がるので、正常動作をする。
【００２８】
つまり、低電圧動作の回路では上述のような異常動作が起こり易く、低電圧動作の回路設計を困難にするという、不都合があった。
そこで、本発明の目的は、上記の点に鑑み、電源の立ち上げや雑音などに起因する低電圧での異常動作の発生を防止し、より低電圧の下で安定動作する回路設計が実現できるバンドギャップリファレンス回路を提供することにある。
【００２９】
【課題を解決するための手段】
上記課題を解決して本発明の目的を達成するために、請求項１〜請求項３に記載の発明は、以下のように構成した。
すなわち、請求項１に記載の発明は、同一のサイズからなる第１のトランジスタ及び第２のトランジスタをダーリントン接続した第１のダーリントン回路と、前記第１のトランジスタに直列に接続されて第１のトランジスタに電流を供給する第１の電流源と、前記第２のトランジスタに直列に接続されて第２のトランジスタに電流を供給する第２の電流源と、前記第１および第２のトランジスタのＮ（Ｎは２以上の整数）倍のサイズからなる第３のトランジスタ及び第４のトランジスタをダーリントン接続し、かつ前記第１のトランジスタのベースと前記第３のトランジスタのベースとを共通接続した第２のダーリントン回路と、前記第３のトランジスタに直列に接続されて第３のトランジスタに電流を供給する第３の電流源と、前記第４のトランジスタに直列に接続される第１の抵抗及び第２の抵抗と、前記第４のトランジスタと前記第１及び第２の抵抗を介して直列に接続され、その第４のトランジスタに電流を供給する第４の電流源と、前記第１のトランジスタと前記第１の電流源の接続点の電位と、前記第１の抵抗と前記第２の抵抗の接続点の電位が同じになるように、前記第１、前記第２、前記第３及び前記第４の電流源の各電流を制御する電流制御手段と、を有するバンドギャップリファレンス回路において、前記第２及び第３の電流源から供給される各電流をそれぞれ制限する電流制限手段を備えたことを特徴とするものである。
【００３０】
請求項２に記載の発明は、請求項１に記載のバンドギャップリファレンス回路において、前記電流制限手段は、前記第２の電流源と前記第２のトランジスタとの間に介在させ、前記第２の電流源が供給する電流を制限する第１の電流制限抵抗と、前記第３の電流源と前記第３のトランジスタとの間に介在させ、前記第３の電流源が供給する電流を制限する第２の電流制限抵抗と、からなることを特徴とするものである。
【００３１】
請求項３に記載の発明は、請求項１に記載のバンドギャップリファレンス回路において、前記電流制限手段は、前記第２の電流源と前記第２のトランジスタとの間に介在させ、前記第２の電流源が供給する電流を制限する第１のＭＯＳトランジスタと、前記第３の電流源と前記第３のトランジスタとの間に介在させ、前記第３の電流源が供給する電流を制限する第２のＭＯＳトランジスタと、からなることを特徴とするものである。
【００３２】
このような構成からなる本発明によれば、電源の立ち上げや雑音などに起因する低電圧での異常動作の発生を防止でき、より低電圧の下で安定動作する回路設計が実現できる。
【００３３】
【発明の実施の形態】
以下、本発明のバンドギャップリファレンス回路の実施形態について、図面を参照して説明する。
図１は、本発明のバンドギャップリファレンス回路の第１実施形態の構成を示す回路図である。
【００３４】
この第１実施形態に係るバンドギャップリファレンス回路は、図１に示すように、ＰＮＰ型のトランジスタＱ１、Ｑ２をダーリントン接続したダーリントン回路１１と、ＰＮＰ型のトランジスタＱ３、Ｑ４をダーリントン接続したダーリントン回路１２と、電流制御手段として機能するオペアンプ（演算増幅器）１３と、電流源として機能するＰチャネル型のＭＯＳトランジスタＭ１〜Ｍ４と、抵抗Ｒ１〜Ｒ３と、電流制限抵抗Ｒ１１、Ｒ１２とを備え、これらにより基準電圧を生成するようになっている。
【００３５】
ここで、トランジスタＱ１とトランジスタＱ２のサイズは同一であり、トランジスタＱ３とトランジスタＱ４のサイズは同一である。また、トラジスタＱ３、Ｑ４のエミッタ面積は、トランジスタＱ１、Ｑ２のエミッタ面積のＮ（Ｎは正の整数）倍である。さらに、ＭＯＳトランジスタＭ１〜Ｍ４の各サイズは同一である。
【００３６】
このように、この第１実施形態に係るバンドギャップリファレンス回路は、その主要部が図３に示すバンドギャップリファレンス回路と同様に構成され、電流制限抵抗Ｒ１１、Ｒ１２を追加した点が異なる。
従って、以下ではその同様に構成される部分の説明は省略し、その電流制限抵抗Ｒ１１、Ｒ１２について主に説明する。
【００３７】
電流制限抵抗Ｒ１１、Ｒ１２は、後述のように、電源の立ち上げ時などにおいて、オペアンプ１３の出力電圧ＰＢがＶＳＳ＝０〔Ｖ〕になったときに、ＭＯＳトランジスタＭ２、Ｍ３がトランジスタＱ２、Ｑ３に供給する電流Ｉ２、Ｉ３を制限して、ＶＮ３＜ＶＮ１となるのを防止し、動作の安定化を図るようにするものである。
【００３８】
このため、電流制限抵抗Ｒ１１は、第２の電流源であるＭＯＳトランジスタＭ２がトランジスタＱ２に供給する電流を制限する抵抗であり、ＭＯＳトランジスタＭ２とトランジスタＱ２との間に挿入されている。すなわち、電流制限抵抗Ｒ１１は、ＭＯＳトランジスタＭ２のドレインとトランジスタＱ２のエミッタとの間に接続されている。
【００３９】
また、電流制限抵抗Ｒ１２は、第３の電流源であるＭＯＳトランジスタＭ３がトランジスタＱ３に供給する電流を制限する抵抗であり、ＭＯＳトランジスタＭ３とトランジスタＱ３との間に挿入されている。すなわち、電流制限抵抗Ｒ１２は、ＭＯＳトランジスタＭ３のドレインとトランジスタＱ３のエミッタとの間に接続されている。
【００４０】
次に、このような構成からなる第１実施形態において、電源の立ち上げ、ノイズなどに起因して、オペアンプ１３の出力電圧ＰＢが、ＶＳＳ＝０〔Ｖ〕になった場合の動作について説明する。
この場合には、ＭＯＳトランジスタＭ１〜Ｍ４は線形領域となり、電流源動作ではなく、抵抗動作となる。
【００４１】
また、このときの各ＭＯＳトランジスタＭ１〜Ｍ４がトランジスタＱ１〜Ｑ４に供給する電流Ｉ１〜Ｉ４は、正常動作時よりも大きくなり、ＭＯＳトランジスタＭ１〜Ｍ４の抵抗値をＲＭ１〜ＲＭ４とすると、次のようになる。

ここで、ＲＭ１≪Ｒ１である。
【００４２】

ここで、ＲＭ２≪Ｒ１１である。

ここで、ＲＭ３≪Ｒ１２である。
【００４３】
Ｉ４＝｛ＶＤＤ−（ＶＢＥ（Ｑ４）＋ＶＢＥ（Ｑ３）｝／（ＲＭ４＋Ｒ２＋Ｒ３）≒｛ＶＤＤ−（ＶＢＥ（Ｑ４）＋ＶＢＥ（Ｑ３）｝／（Ｒ２＋Ｒ３）・・・・（２６）
ここで、ＲＭ４≪（Ｒ２＋Ｒ３）である。
ＲＭ１〜ＲＭ４≪Ｒ１〜Ｒ３の関係にあるが、電流制限抵抗Ｒ１１、Ｒ１２の抵抗値を適当に選ぶと、ＭＯＳトランジスタＭ１〜Ｍ４に流れる電流Ｉ１、Ｉ２、Ｉ３、Ｉ４は、ほぼ同じ電流値にすることができる。
【００４４】
また、電流Ｉ１〜Ｉ４はあまり大きな値にならないので、ΔＶＢＥ１＝ＶＢＥ（Ｑ２）−ＶＢＥ（Ｑ３）と、ΔＶＢＥ２＝ＶＢＥ（Ｑ１）−ＶＢＥ（Ｑ４）はあまり大きくならない。この結果、ΔＶＢＥ＝ΔＶＢＥ１＋ΔＶＢＥ２も大きくならない。
このとき、ノード電圧ＶＮ３は、次の（２７）式のようになる。
【００４５】

ここで、ΔＶＢＥ＝ＶＢＥ（Ｑ１）＋ＶＢＥ（Ｑ２）−｛ＶＢＥ（Ｑ３）＋ＶＢＥ（Ｑ４）｝＝ＶＮ１−｛ＶＢＥ（Ｑ３）＋ＶＢＥ（Ｑ４）｝である。
【００４６】
従って、（２７）式からノード電圧ＶＮ３とノード電圧ＶＮ１の差の電圧（ＶＮ３−ＶＮ１）を求めると、次の（２８）式のようになる。
（ＶＮ３−ＶＮ１）＝｛ＶＤＤ−〔ＶＢＥ（Ｑ４）＋ＶＢＥ（Ｑ３）〕｝／｛Ｒ３／（Ｒ２＋Ｒ３）｝−ΔＶＢＥ・・・・（２８）
ところで、（２８）式において、Ｒ３／（Ｒ２＋Ｒ３）は温度特性を打ち消すために決められ、一般に１／１０〜１／５程度である。しかし、上記のようにΔＶＢＥがあまり大きくならない。
【００４７】
このため、従来のように｛ＶＤＤ−〔ＶＢＥ（Ｑ４）＋ＶＢＥ（Ｑ３）〕｝／｛Ｒ３／（Ｒ２＋Ｒ３）｝＜ΔＶＢＥにはならないので、ＶＮ３−ＶＮ１＜０にもならない。
この結果、容易にＶＮ３−ＶＮ１＞０となるので、つまりＶＮ３＞ＶＮ１となるので、これによりオペアンプ１３の出力電圧ＰＢは上がり、出力電圧ＰＢはＶＳＳ＝０の状態から抜け出すことができる。このため、正常な安定点となり、正常な動作になる。
【００４８】
以上説明したように、この第１実施形態では、ＭＯＳトランジスタＭ２、Ｍ３がトランジスタＱ１〜Ｑ４に供給する電流Ｉ２、Ｉ３を制限する電流制限抵抗Ｒ１１、Ｒ１２を備えるようにした。このため、電源の立ち上げや雑音などに起因する低電圧での異常動作の発生を防止でき、これにより、より低電圧の下で安定動作する回路設計が実現できる。
【００４９】
次に、本発明のバンドギャップリファレンス回路の第２実施形態について、図２を参照して説明する。
この第２実施形態に係るバンドギャップリファレンス回路は、図２に示すように、図１の第１実施形態の電流制限抵抗Ｒ１１、Ｒ１２を、電流制限用のＭＯＳトランジスタＭ１１、Ｍ１２に置き換えたものである。
【００５０】
さらに詳述すると、ＭＯＳトランジスタＭ１１は、第２の電流源であるＭＯＳトランジスタＭ２がトランジスタＱ２に供給する電流を制限するものであり、ＭＯＳトランジスタＭ２とトランジスタＱ２との間に挿入されている。すなわち、ＭＯＳトランジスタＭ１１のソースはＭＯＳトランジスタＭ２のドレインと接続され、ＭＯＳトランジスタＭ１１のドレインはトランジスタＱ２のエミッタに接続されている。
【００５１】
ＭＯＳトランジスタＭ１２は、第３の電流源であるＭＯＳトランジスタＭ３がトランジスタＱ３に供給する電流を制限するものであり、ＭＯＳトランジスタＭ３とトランジスタＱ３との間に挿入されている。すなわち、ＭＯＳトランジスタＭ１２のソースはＭＯＳトランジスタＭ３のドレインと接続され、ＭＯＳトランジスタＭ１２のドレインはトランジスタＱ３のエミッタに接続されている。
【００５２】
さらに、ＭＯＳトランジスタＭ１１、１２の各ゲートは、ＭＯＳトランジスタＭ１３のゲートに接続され、これによりＭＯＳトランジスタＭ１１、１２の抵抗値が任意に設定できるようになっている。ＭＯＳトランジスタ１３は、ソースに電源電圧ＶＤＤが供給され、ドレインは電流源１９を介して接地され、ゲートとドレインが共通接続されている。
【００５３】
このような構成からなる第２実施形態によれば、第１実施形態と同様の効果が得られる。
【００５４】
【発明の効果】
以上説明したように、本発明によれば、電源の立ち上げや雑音などに起因する低電圧での異常動作の発生を防止でき、より低電圧の下で安定動作する回路設計が実現できる。
【図面の簡単な説明】
【図１】本発明のバンドギャップリファレンス回路の第１実施形態の構成を示す回路図である。
【図２】本発明のバンドギャップリファレンス回路の第２実施形態の構成を示す回路図である。
【図３】従来のバンドギャップリファレンス回路の構成を示す回路図である。
【符号の説明】
Ｑ１〜Ｑ６ トランジスタ
Ｍ１〜Ｍ４ ＭＯＳトランジスタ（電流源）
Ｒ１〜Ｒ３ 抵抗
Ｒ１１、Ｒ１２ 電流制限抵抗
Ｍ１１、Ｍ１２ 電流制限用のＭＯＳトランジスタ
１１、１２ ダーリントン回路
１３ オペアンプ（電流制御手段）
１８ 出力端子
１９ 電流源[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bandgap reference circuit that generates an accurate reference voltage.
[0002]
[Prior art]
As an example of a conventional band gap reference circuit, the one shown in FIG. 3 is known.
As shown in FIG. 3, the band gap reference circuit includes a Darlington circuit 11 in which PNP transistors Q1 and Q2 are connected in Darlington, a Darlington circuit 12 in which PNP transistors Q3 and Q4 are connected in Darlington, an operational amplifier 13, P-channel MOS transistors M1 to M4 functioning as current sources and resistors R1 to R3 are provided to generate a reference voltage.
[0003]
Here, the sizes of the transistors Q1 and Q2 are the same, and the sizes of the transistors Q3 and Q4 are the same. The emitter areas of the transistors Q3 and Q4 are N (N is a positive integer) times the emitter area of the transistors Q1 and Q2. Further, the sizes of the MOS transistors M1 to M4 are the same.
[0004]
More specifically, the collector of the transistor Q1 is grounded, and its base is connected to the emitter of the transistor Q2. The emitter of the transistor Q1 is supplied with the power supply voltage VDD via the resistor R1 and the MOS transistor M1. The collector of the transistor Q2 is grounded, and its base is connected to the base of the transistor Q3 and grounded. The emitter of the transistor Q2 is connected to the base of the transistor Q1, and the power supply voltage VDD is supplied via the MOS transistor M2.
[0005]
The collector of the transistor Q3 is grounded, and its base is connected to the base of the transistor Q2 and grounded. The emitter of the transistor Q3 is connected to the base of the transistor Q4, and the power supply voltage VDD is supplied via the MOS transistor M3. The collector of the transistor Q4 is grounded, and its base is connected to the emitter of the transistor Q3. The emitter of the transistor Q4 is supplied with the power supply voltage VDD via the resistor R3, the resistor R2, and the MOS transistor M4.
[0006]
The operational amplifier 13 generates a control voltage for controlling the gate voltages of the MOS transistors M1 to M4 based on the potential at the connection point between the emitter of the transistor Q1 and the resistor R1 and the potential at the connection point between the resistors R2 and R3. Thus, the current flowing through the MOS transistors M1 to M4 is controlled.
Therefore, the negative input terminal of the operational amplifier 13 is connected to the connection point between the emitter of the transistor Q1 and the resistor R1, the positive input terminal is connected to the connection point between the resistor R2 and the resistor R3, and its output terminal is the MOS transistor M1. To M4 gate terminals, respectively.
[0007]
Further, a connection point between the drain of the MOS transistor M4 and the resistor R2 is connected to the output terminal 18, and a desired output voltage Vout can be obtained from the output terminal 18.
Next, an operation example of the band gap reference circuit having such a configuration will be described.
[0008]
First, currents flowing through the MOS transistors M1 to M4 constituting the current source are I1 to I4, and the currents I1 to I4 are supplied to the corresponding transistors Q1 to Q4, respectively.
Further, if the voltage between the base and the emitter of the transistor Q1 is VBE (Q1) and the voltage between the base and the emitter of the transistor Q2 is VBE (Q2), the node at the connection point between the emitter of the transistor Q1 and the resistor R1 The voltage VN1 is as follows.
[0009]
VN1 = VBE (Q1) + VBE (Q2) (1)
Here, the transistors Q1 and Q2 have the same currents I1 and I2 supplied from the MOS transistors M1 and M2 and the same transistor size, so that VBE (Q1) = VBE (Q2). As a result, the node voltage VN1 in the equation (1) can be expressed by the following equation.
[0010]
VN1 = 2 × VBE (Q1) (2)
On the other hand, if the voltage between the base and the emitter of the transistor Q3 is VBE (Q3) and the voltage between the base and the emitter of the transistor Q4 is VBE (Q4), the node of the connection point between the emitter of the transistor Q4 and the resistor R3 The voltage VN2 is as follows.
[0011]
VN2 = VBE (Q3) + VBE (Q4) (3)
Here, the transistors Q3 and Q4 have the same currents I3 and I4 supplied from the MOS transistors M3 and M4 and the same transistor size, so that VBE (Q3) = VBE (Q4). As a result, the node voltage VN2 in the equation (3) can be expressed by the following equation.
[0012]
VN2 = 2 × VBE (Q4) (4)
Since the emitter area of the transistor Q4 is N times the emitter area of the transistor Q1, the voltage VBE (Q1) between the base and emitter of the transistor Q1 and the voltage VBE (Q4 between the base and emitter of the transistor Q1) ) And the potential difference ΔVBE with the following equation.
[0013]
ΔVBE = VBE (Q1) −VBE (Q4) (5)
When this equation (5) is solved for VBE (Q4), the following equation is obtained.
VBE (Q4) = VBE (Q1) −ΔVBE (6)
Substituting equation (6) into equation (4), equation (4) becomes the following equation.
VN2 = 2 {VBE (Q1) −ΔVBE} (7)
When the current I4 flows through the resistor R3, a voltage VR3 of the following expression is generated at both ends of the resistor R3.
[0014]
VR3 = I4 × R3 (8)
The node voltage VN3 at the connection point of the resistors R2 and R3 is expressed by the following equation from the equations (7) and (8).
VN3 = 2 {VBE (Q1) −ΔVBE} + (I4 × R3) (9)
Here, the node voltage VN1 and the node voltage VN3 are input to the operational amplifier 13, and the operational amplifier 13 controls the gate voltages of the MOS transistors M1 to M4 so that the node voltage VN1 and the node voltage VN3 are equal.
[0015]
That is, when the node voltage VN3 is lower than the node voltage VN1, the output potential PB of the operational amplifier 13 decreases, so that the currents I1 to I4 flowing through the MOS transistors M1 to M4 increase. As a result, the voltage VR3 across the resistor R3 increases and the node voltage VN3 increases. Conversely, when the node voltage VN1 is lower than the node voltage VN3, the same operation is performed and the node voltage VN1 increases. Therefore, it becomes stable at the potential of VN1 = VN3.
[0016]
Therefore, from the equations (2) and (9), when VN1 = VN3 and solving this, the following equation is obtained.
2 × ΔVBE = I4 × R3 (10)
With such an operation, the output voltage Vout obtained from the output terminal 18 is expressed by the following equation with reference to the equation (2).
[0017]
Vout = (I4 × R2) + VN1 = (I4 × R2) + {2 × VBE (Q1)} (11)
Here, when I4 is obtained from the equation (10), the following equation is obtained.
I4 = (2 × ΔVBE) / R3 (12)
When this equation (12) is substituted into equation (11), equation (11) becomes the following equation.
[0018]
Vout = {(R2 / R3) × (2 × ΔVBE)} + {2 × VBE (Q1)} (13)
In equation (13), VBE (Q1) has a negative temperature coefficient, and ΔVBE has a positive temperature coefficient. Therefore, the temperature coefficient can be canceled by setting (R2 / R3) to an appropriate value.
[0019]
Therefore, this band gap reference circuit can generate a desired output voltage Vout without depending on temperature, and this output voltage Vout is used as a reference voltage.
By the way, when the equation (11) is solved, there are two stable points. One is the case where the current I4 is zero and ΔVBE = VR3 = 0. The second case is a normal value. In order to avoid the case where the current I4 = 0, a startup circuit (not shown) is provided.
[0020]
If the resistance value of the resistor R1 is equal to the resistance value of the resistor R2, VN1 = VN3 and I1 = I4. Therefore, the node voltage VN4 at the connection point between the drain of the MOS transistor M1 and the resistor R1 and the output voltage Vout becomes equal. Even when the current source composed of the MOS transistor M1 or the MOS transistor M4 is not ideal (the output resistance is finite), the resistor R1 is inserted so that I1 = I4.
[0021]
Next, an operation when the output voltage PB of the operational amplifier 13 becomes VSS = 0 [V] due to power-on, noise, and the like will be described.
In this case, the MOS transistors M1 to M4 are in a linear region, and not a current source operation but a resistance operation.
Further, currents I1 to I4 supplied to the transistors Q1 to Q4 by the MOS transistors M1 to M4 at this time are larger than those during normal operation, and the resistance values of the MOS transistors M1 to M4 are RM1 to RM4. It becomes like this.

Here, RM1 << R1.
[0022]

Here, RM4 << (R2 + R3).
[0023]
Since RM1 to RM4 << R1 to R3, I2, I3 >> I1, I4.

Then, since I2 and I3 are large as described above, ΔVBE also becomes large. At this time, the node voltage VN3 can be obtained by the following equation (21) by referring to the equations (3), (8), and (17).
[0024]

Here, ΔVBE = VBE (Q1) + VBE (Q2) − {VBE (Q3) + VBE (Q4)} = VN1− {VBE (Q3) + VBE (Q4)}.
[0025]
Accordingly, when the voltage (VN3−VN1) of the difference between the node voltage VN3 and the node voltage VN1 is obtained from the equation (21), the following equation (22) is obtained.
(VN3−VN1) = {VDD− [VBE (Q4) + VBE (Q3)]} / {R3 / (R2 + R3)} − ΔVBE (22)
[0026]
[Problems to be solved by the invention]
By the way, in the equation (22), R3 / (R2 + R3) is determined in order to cancel the temperature characteristic, and is generally about 1/10 to 1/5.
For this reason, {VDD− [VBE (Q4) + VBE (Q3)]} / {R3 / (R2 + R3)} <ΔVBE.
[0027]
As described above, when VN3−VN1 <0 and VN3 <VN1, the output voltage PB of the operational amplifier 13 tends to decrease, so that VSS = 0 remains. As a result, it is impossible to get out of this abnormal state.
On the other hand, when the power supply voltage VDD increases, the increase in {VDD− [VBE (Q4) + VBE (Q3)]} / {R3 / (R2 + R3)} is larger than the increase in ΔVBE. For this reason, VN3−VN1> 0 and VN3> VN1, and the output voltage PB of the operational amplifier 13 increases, so that normal operation is performed.
[0028]
That is, the low voltage operation circuit tends to cause abnormal operation as described above, which makes it difficult to design a low voltage operation circuit.
Therefore, in view of the above points, an object of the present invention is to prevent the occurrence of abnormal operation at a low voltage due to power-up or noise, and to realize a circuit design that operates stably at a lower voltage. The object is to provide a bandgap reference circuit.
[0029]
[Means for Solving the Problems]
In order to solve the above-described problems and achieve the object of the present invention, the inventions according to claims 1 to 3 are configured as follows.
That is, according to the first aspect of the present invention, the first Darlington circuit in which the first transistor and the second transistor having the same size are Darlington connected, and the first transistor connected in series to the first transistor. A first current source for supplying current to the transistor; a second current source connected in series to the second transistor for supplying current to the second transistor; and N of the first and second transistors A second transistor in which a third transistor and a fourth transistor having a double size (N is an integer of 2 or more) are Darlington-connected, and the base of the first transistor and the base of the third transistor are connected in common. A Darlington circuit, a third current source connected in series to the third transistor and supplying current to the third transistor, and the fourth current source A first resistor and a second resistor connected in series to the transistor, the fourth transistor and the first and second resistors are connected in series, and current is supplied to the fourth transistor. The potential of the connection point of the fourth current source, the first transistor and the first current source, and the potential of the connection point of the first resistor and the second resistor are the same. Current control means for controlling each current of the first, second, third, and fourth current sources, and a bandgap reference circuit that is supplied from the second and third current sources. The present invention is characterized by comprising current limiting means for limiting each current.
[0030]
According to a second aspect of the present invention, in the bandgap reference circuit according to the first aspect, the current limiting means is interposed between the second current source and the second transistor, and A first current limiting resistor for limiting a current supplied from the current source; and a first current limiting resistor interposed between the third current source and the third transistor for limiting the current supplied by the third current source. 2 current limiting resistors.
[0031]
According to a third aspect of the present invention, in the bandgap reference circuit according to the first aspect, the current limiting unit is interposed between the second current source and the second transistor, A first MOS transistor for limiting the current supplied from the current source, and a second MOS transistor interposed between the third current source and the third transistor for limiting the current supplied by the third current source. And a MOS transistor.
[0032]
According to the present invention having such a configuration, it is possible to prevent the occurrence of an abnormal operation at a low voltage due to power-on or noise, and to realize a circuit design that operates stably at a lower voltage.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the band gap reference circuit of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a bandgap reference circuit of the present invention.
[0034]
As shown in FIG. 1, the band gap reference circuit according to the first embodiment includes a Darlington circuit 11 in which PNP transistors Q1 and Q2 are connected in Darlington, and a Darlington circuit 12 in which PNP transistors Q3 and Q4 are connected in Darlington. An operational amplifier (operational amplifier) 13 that functions as current control means, P-channel MOS transistors M1 to M4 that function as current sources, resistors R1 to R3, and current limiting resistors R11 and R12. A reference voltage is generated.
[0035]
Here, the sizes of the transistors Q1 and Q2 are the same, and the sizes of the transistors Q3 and Q4 are the same. The emitter areas of the transistors Q3 and Q4 are N (N is a positive integer) times the emitter area of the transistors Q1 and Q2. Further, the sizes of the MOS transistors M1 to M4 are the same.
[0036]
As described above, the band gap reference circuit according to the first embodiment is configured in the same manner as the band gap reference circuit shown in FIG. 3, except that the current limiting resistors R11 and R12 are added.
Therefore, in the following, description of the similarly configured portion is omitted, and the current limiting resistors R11 and R12 will be mainly described.
[0037]
As will be described later, when the output voltage PB of the operational amplifier 13 becomes VSS = 0 [V], the current limiting resistors R11 and R12 are connected to the transistors Q2 and Q3 when the output voltage PB of the operational amplifier 13 becomes VSS = 0 [V]. The currents I2 and I3 supplied to the circuit are limited to prevent VN3 <VN1 and to stabilize the operation.
[0038]
For this reason, the current limiting resistor R11 is a resistor that limits the current supplied to the transistor Q2 by the MOS transistor M2 as the second current source, and is inserted between the MOS transistor M2 and the transistor Q2. That is, the current limiting resistor R11 is connected between the drain of the MOS transistor M2 and the emitter of the transistor Q2.
[0039]
The current limiting resistor R12 is a resistor that limits the current supplied to the transistor Q3 by the MOS transistor M3, which is the third current source, and is inserted between the MOS transistor M3 and the transistor Q3. That is, the current limiting resistor R12 is connected between the drain of the MOS transistor M3 and the emitter of the transistor Q3.
[0040]
Next, in the first embodiment having such a configuration, an operation when the output voltage PB of the operational amplifier 13 becomes VSS = 0 [V] due to power-up, noise, and the like will be described. .
In this case, the MOS transistors M1 to M4 are in a linear region, and not a current source operation but a resistance operation.
[0041]
Further, currents I1 to I4 supplied to the transistors Q1 to Q4 by the MOS transistors M1 to M4 at this time are larger than those during normal operation, and the resistance values of the MOS transistors M1 to M4 are RM1 to RM4. It becomes like this.

Here, RM1 << R1.
[0042]

Here, RM2 << R11.

Here, RM3 << R12.
[0043]
I4 = {VDD− (VBE (Q4) + VBE (Q3)} / (RM4 + R2 + R3) ≈ {VDD− (VBE (Q4) + VBE (Q3)} / (R2 + R3)} (26)
Here, RM4 << (R2 + R3).
RM1 to RM4 << R1 to R3, but if the resistance values of the current limiting resistors R11 and R12 are appropriately selected, the currents I1, I2, I3, and I4 flowing through the MOS transistors M1 to M4 have substantially the same current value. can do.
[0044]
Further, since the currents I1 to I4 do not become very large values, ΔVBE1 = VBE (Q2) −VBE (Q3) and ΔVBE2 = VBE (Q1) −VBE (Q4) do not become so large. As a result, ΔVBE = ΔVBE1 + ΔVBE2 does not increase.
At this time, the node voltage VN3 is expressed by the following equation (27).
[0045]

Here, ΔVBE = VBE (Q1) + VBE (Q2) − {VBE (Q3) + VBE (Q4)} = VN1− {VBE (Q3) + VBE (Q4)}.
[0046]
Therefore, when the voltage (VN3−VN1) of the difference between the node voltage VN3 and the node voltage VN1 is obtained from the equation (27), the following equation (28) is obtained.
(VN3−VN1) = {VDD− [VBE (Q4) + VBE (Q3)]} / {R3 / (R2 + R3)} − ΔVBE (28)
By the way, in the equation (28), R3 / (R2 + R3) is determined in order to cancel the temperature characteristic, and is generally about 1/10 to 1/5. However, ΔVBE is not so large as described above.
[0047]
For this reason, since {VDD− [VBE (Q4) + VBE (Q3)]} / {R3 / (R2 + R3)} <ΔVBE as in the conventional case, VN3−VN1 <0 is not satisfied.
As a result, VN3−VN1> 0 is easily satisfied, that is, VN3> VN1, so that the output voltage PB of the operational amplifier 13 is increased, and the output voltage PB can escape from the state of VSS = 0. For this reason, a normal stable point is obtained and normal operation is performed.
[0048]
As described above, in the first embodiment, the current limiting resistors R11 and R12 for limiting the currents I2 and I3 supplied to the transistors Q1 to Q4 by the MOS transistors M2 and M3 are provided. For this reason, it is possible to prevent an abnormal operation from occurring at a low voltage due to a power-on or noise, thereby realizing a circuit design that operates stably at a lower voltage.
[0049]
Next, a second embodiment of the band gap reference circuit of the present invention will be described with reference to FIG.
As shown in FIG. 2, the band gap reference circuit according to the second embodiment is obtained by replacing the current limiting resistors R11 and R12 of the first embodiment of FIG. 1 with current limiting MOS transistors M11 and M12. is there.
[0050]
More specifically, the MOS transistor M11 limits the current supplied to the transistor Q2 by the MOS transistor M2, which is the second current source, and is inserted between the MOS transistor M2 and the transistor Q2. That is, the source of the MOS transistor M11 is connected to the drain of the MOS transistor M2, and the drain of the MOS transistor M11 is connected to the emitter of the transistor Q2.
[0051]
The MOS transistor M12 limits the current supplied to the transistor Q3 by the MOS transistor M3, which is the third current source, and is inserted between the MOS transistor M3 and the transistor Q3. That is, the source of the MOS transistor M12 is connected to the drain of the MOS transistor M3, and the drain of the MOS transistor M12 is connected to the emitter of the transistor Q3.
[0052]
Further, the gates of the MOS transistors M11 and M12 are connected to the gate of the MOS transistor M13, whereby the resistance values of the MOS transistors M11 and M12 can be set arbitrarily. In the MOS transistor 13, the power supply voltage VDD is supplied to the source, the drain is grounded via the current source 19, and the gate and the drain are commonly connected.
[0053]
According to the second embodiment having such a configuration, the same effect as the first embodiment can be obtained.
[0054]
【The invention's effect】
As described above, according to the present invention, it is possible to prevent the occurrence of abnormal operation at a low voltage due to the start-up of a power supply or noise, and to realize a circuit design that operates stably at a lower voltage.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a bandgap reference circuit of the present invention;
FIG. 2 is a circuit diagram showing a configuration of a second embodiment of a bandgap reference circuit of the present invention;
FIG. 3 is a circuit diagram showing a configuration of a conventional bandgap reference circuit;
[Explanation of symbols]
Q1 to Q6 Transistors M1 to M4 MOS transistors (current sources)
R1 to R3 Resistors R11 and R12 Current limiting resistors M11 and M12 Current limiting MOS transistors 11 and 12 Darlington circuit 13 Operational amplifier (current control means)
18 Output terminal 19 Current source

Claims (3)

A first Darlington circuit in which a first transistor and a second transistor having the same size are connected by Darlington;
A first current source connected in series to the first transistor to supply current to the first transistor;
A second current source connected in series to the second transistor for supplying current to the second transistor;
A third transistor and a fourth transistor having a size N (N is an integer greater than or equal to 2) times the first and second transistors are Darlington-connected, and the base of the first transistor and the third transistor A second Darlington circuit commonly connected to the bases of the transistors;
A third current source connected in series to the third transistor for supplying current to the third transistor;
A first resistor and a second resistor connected in series to the fourth transistor;
A fourth current source connected in series with the fourth transistor via the first and second resistors and supplying a current to the fourth transistor;
The first, second, A band gap reference circuit having current control means for controlling each current of the third and fourth current sources;
A bandgap reference circuit comprising current limiting means for limiting each current supplied from the second and third current sources. The current limiting means includes
A first current limiting resistor interposed between the second current source and the second transistor to limit a current supplied by the second current source;
A second current limiting resistor interposed between the third current source and the third transistor for limiting a current supplied by the third current source;
The band gap reference circuit according to claim 1, comprising: The current limiting means includes
A first MOS transistor that is interposed between the second current source and the second transistor and limits a current supplied by the second current source;
A second MOS transistor that is interposed between the third current source and the third transistor and limits a current supplied by the third current source;
The band gap reference circuit according to claim 1, comprising:

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