JP2003330556A - Band gap reference circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize the design of a circuit which prevents the occurrence of abnormal operation at a low voltage resulted from power start-up or the like and operates stably at a lower voltage. <P>SOLUTION: A band gap reference circuit has a PNP-type transistor Q1, a Darlington circuit 11 in which Q2 is connected in a Darlington configuration, a Darlington circuit 12 in which PNP-type transistors Q3, Q4 are connected in a Darlington configuration, an operational amplifier 13 which functions as a current control means, P channel type MOS transistors M1 to M4 which function as current sources, resistors R1 to R3, and current-limiting resistors R11, R12, with these generating a reference voltage. The current-limiting resistors R11, R12, at the power start-up or the like, if an output voltage PB of the operational amplifier 13 reaches VSS=0 [V], restrict currents I2, I3 passing through the MOS transistors M2, M3 in order to prevent VN3 from dropping to a level less than VN1, thus stabilizing the operation. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bandgap reference circuit for generating a highly accurate reference voltage.

[0002]

2. Description of the Related Art As an example of a conventional bandgap reference circuit, the one shown in FIG. 3 is known. As shown in FIG. 3, this bandgap reference circuit includes a Darlington circuit 11 in which PNP transistors Q1 and Q2 are connected in Darlington, a Darlington circuit 12 in which PNP transistors Q3 and Q4 are connected in Darlington, and an operational amplifier 13. P that functions as a current source
Channel type MOS transistors M1 to M4 and resistor R
1 to R3, and a reference voltage is generated by them.

Here, the transistors Q1 and Q2 have the same size, and the transistors Q3 and Q4 have the same size. Also, Transistor Q
The emitter areas of 3 and Q4 are N (N is a positive integer) times the emitter area of the transistors Q1 and Q2. further,
The sizes of the MOS transistors M1 to M4 are the same.

More specifically, the collector of the transistor Q1 is grounded and its base is connected to the emitter of the transistor Q2. The power supply voltage VDD is supplied to the emitter of the transistor Q1 via the resistor R1 and the MOS transistor M1. The collector of the transistor Q2 is grounded, and its base is connected to the base of the transistor Q3 and is also grounded. The emitter of the transistor Q2 is the transistor Q1.
Connected to the base of the MOS transistor M
The power supply voltage VDD is supplied via the line 2.

The collector of the transistor Q3 is grounded,
Its base is connected to the base of the transistor Q2 and is grounded. The emitter of the transistor Q3 is
MO is connected to the base of the transistor Q4 and
The power supply voltage VDD is supplied via the S transistor M3. The collector of the transistor Q4 is grounded and its base is connected to the emitter of the transistor Q3. The emitter of the transistor Q4 has a resistor R
3, the power supply voltage VDD is supplied via the resistor R2 and the MOS transistor M4.

The operational amplifier 13 controls the gate voltage of the MOS transistors M1 to M4 based on the potential at the connection point between the emitter of the transistor Q1 and the resistor R1 and the potential at the connection point between the resistors R2 and R3. Occurs,
As a result, the current flowing through the MOS transistors M1 to M4 is controlled. Therefore, the operational amplifier 1
The-input terminal of 3 is the emitter of the transistor Q1 and the resistor R
1 is connected to the connection point, the + input terminal is connected to the connection point between the resistors R2 and R3, and the output terminal is a MOS
The gate terminals of the transistors M1 to M4 are respectively connected.

Further, the connection point between the drain of the MOS transistor M4 and the resistor R2 is connected to the output terminal 18, and the desired output voltage Vout can be obtained from this output terminal 18. Next, an operation example of the bandgap reference circuit having such a configuration will be described.

First, it is assumed that the currents flowing in the MOS transistors M1 to M4 forming the current source are I1 to I4 and the respective currents I1 to I4 are respectively supplied to the corresponding transistors Q1 to Q4. Further, the voltage between the base and the emitter of the transistor Q1 is VBE (Q1), and the voltage between the base and the emitter of the transistor Q2 is VBE (Q1).
Assuming (Q2), the node voltage VN1 at the connection point between the emitter of the transistor Q1 and the resistor R1 is given by the following equation.

VN1 = VBE (Q1) + VBE (Q2) ... (1) Here, the transistors Q1 and Q2 have equal currents I1 and I2 supplied from the MOS transistors M1 and M2, respectively.
Since the transistor sizes are the same, VBE (Q1) = V
It becomes BE (Q2). As a result, the node voltage VN1 of the equation (1) can be expressed by the following equation.

VN1 = 2 × VBE (Q1) (2) On the other hand, the voltage between the base and the emitter of the transistor Q3 is VBE (Q3), and the voltage between the base and the emitter of the transistor Q4 is VBE. (Q4), the node voltage V at the connection point between the emitter of the transistor Q4 and the resistor R3
N2 is given by the following equation.

VN2 = VBE (Q3) + VBE (Q4) ... (3) Here, in the transistors Q3 and Q4, the currents I3 and I4 supplied from the MOS transistors M3 and M4 are equal,
Since the transistor sizes are the same, VBE (Q3) = V
It becomes BE (Q4). As a result, the node voltage VN2 in the expression (3) can be expressed by the following expression.

VN2 = 2 × VBE (Q4) (4) The emitter area of the transistor Q4 is equal to that of the transistor Q1.
N times the area of the emitter of the transistor Q1, the voltage VBE (Q1) between the base and the emitter of the transistor Q1 and the voltage VBE between the base and the emitter of the transistor Q1.
The potential difference ΔVBE from (Q4) is given by the following equation.

ΔVBE = VBE (Q1) −VBE (Q4) ... (5) When this equation (5) is solved for VBE (Q4), the following equation is obtained. VBE (Q4) = VBE (Q1) -ΔVBE ... (6) When the expression (6) is substituted into the expression (4), the expression (4) becomes the following expression. VN2 = 2 {VBE (Q1) -ΔVBE} ... (7) When the current I4 flows through the resistor R3, the resistor R3
A voltage VR3 of the following equation is generated at both ends of.

VR3 = I4 × R3 (8) The node voltage VN3 at the connection point of the resistors R2 and R3 is
The following equation is obtained from the equations (7) and (8). VN3 = 2 {VBE (Q1) −ΔVBE} + (I4 × R3) (9) Here, the node voltage VN1 and the node voltage VN3 are input to the operational amplifier 13, and the operational amplifier 13 outputs the node voltage. The gate voltages of the MOS transistors M1 to M4 are controlled so that VN1 is equal to the node voltage VN3.

That is, when the node voltage VN3 is lower than the node voltage VN1, the output potential PB of the operational amplifier 13 drops, so that the currents I1 to I4 flowing through the MOS transistors M1 to M4 increase. As a result, the voltage VR3 across the resistor R3 increases and the node voltage VN3 increases. Conversely, when the node voltage VN1 is lower than the node voltage VN3, the same operation is performed and the node voltage VN1 rises. Therefore, it becomes stable at the potential of VN1 = VN3.

Therefore, from equations (2) and (9), VN1
= VN3 and solving this gives the following equation. 2 × ΔVBE = I4 × R3 ... (10) With such an operation, the output voltage Vout obtained from the output terminal 18 becomes as shown in the following equation with reference to the equation (2).

Vout = (I4 × R2) + VN1 = (I4 × R2) + {2 × VBE (Q1)} (11) Here, when I4 is obtained from the equation (10), the following equation is obtained. . I4 = (2 × ΔVBE) / R3 ... (12) When this equation (12) is substituted into the equation (11), the equation (11) becomes the following equation.

Vout = {(R2 / R3) × (2 × ΔVBE)} + {2 × VBE (Q1)} ... (13) In the equation (13), VBE (Q1) is a negative temperature coefficient. Since ΔVBE has a positive temperature coefficient, (R2 / R
The temperature coefficient can be canceled by setting 3) to an appropriate value.

Therefore, the bandgap reference circuit has a desired output voltage Vo without depending on the temperature.
ut can be generated, and this output voltage Vout is used as a reference voltage. By the way, there are two stable points when the equation (11) is solved. One is that the current I4 is zero and ΔVBE = VR
This is the case when 3 = 0. The second is the case of normal values. In order to avoid the case of the current I4 = 0, a start-up circuit (not shown) is provided.

When the resistance value of the resistor R1 and the resistance value of the resistor R2 are equal, VN1 = VN3 and I1 = I
4, the node voltage VN4 at the connection point between the drain of the MOS transistor M1 and the resistor R1 and the output voltage Vou
t becomes equal. MOS transistor M1 or MOS
Even when the current source formed by the transistor M4 is not ideal (the output resistance is finite), I1 = I4
The resistor R1 is inserted.

Next, the output voltage PB of the operational amplifier 13 becomes VSS = 0 due to the rise of power source, noise, and the like.
The operation when [V] is reached will be described. In this case, the MOS transistors M1 to M4 are in the linear region, and not the current source operation but the resistance operation. Further, the currents I1 to I4 supplied to the transistors Q1 to Q4 by the MOS transistors M1 to M4 at this time are larger than those during normal operation, and if the resistance values of the MOS transistors M1 to M4 are RM1 to RM4, Like I1 = (VDD-VN1) / (RM1 + R1) = {VDD- [VBE (Q1) + VBE (Q2)]} / (RM1 + R1) ≈ {VDD- [VBE (Q1) + VBE (Q2)]} / R1 ... (14) Here, RM1 << R1.

[0022]   I2 = (VDD-VBE (Q2)) / RM2 ... (15)   I3 = (VDD-VBE (Q3)) / RM3 ... (16)   I4 = (VDD-VN2) / (RM4 + R2 + R3)       = {VDD- [VBE (Q4) + VBE (Q3)]} / (RM4 + R2 + R3) ≈ {VDD- [VBE (Q4) + VBE (Q3)]} / (R2 + R3) ... (17) Here, RM4 << (R2 + R3).

Further, because of the relationship of RM1 to RM4 << R1 to R3, I2, I3 >> I1, I4. Here, ΔVBE1≡VBE (Q2) -VBE (Q3) ... (18) ΔVBE2≡VBE (Q1) -VBE (Q4) ... (19) ΔVBE≡ΔVBE1 + ΔVBE2 ... (20) Then, since I2 and I3 are large as described above, ΔV
BE also becomes large. At this time, the node voltage VN3 is
Equation (21) below is obtained by referring to equations (3), (8) and (17).

VN3 = VN2 + VR3 = VN2 + (I4 × R3) = VBE (Q3) + VBE (Q4) + {VDD− [VBE (Q4) + VBE (Q3)]} / {R3 / (R2 + R3)} ≈VN1-ΔVBE + {VDD− [VBE (Q4) + VBE (Q3)]} / {R3 / (R2 + R3)} ... (21) where ΔVBE = VBE (Q1) + VBE (Q2) −
{VBE (Q3) + VBE (Q4)} = VN1- {VB
E (Q3) + VBE (Q4)}.

Therefore, from the equation (21), the node voltage VN3
When the voltage (VN3−VN1) of the difference between the node voltage VN1 and the node voltage VN1 is obtained, the following expression (22) is obtained. (VN3-VN1) = {VDD- [VBE (Q4) + VBE (Q3)]} / {R3 / (R2 + R3)}-ΔVBE ... (22)

[0026]

By the way, in the equation (22), R3 / (R2 + R3) is determined to cancel the temperature characteristic, and is generally about 1/10 to 1/5.
Therefore, {VDD- [VBE (Q4) + VBE (Q
3)]} / {R3 / (R2 + R3)} <ΔVBE.

Thus, VN3−VN1 <0 and VN
When 3 <VN1, the output voltage PB of the operational amplifier 13 tends to decrease, and therefore VSS = 0 remains.
As a result, it is impossible to get out of this abnormal state.
On the other hand, if the power supply voltage VDD becomes high, {VDD- [VB
E (Q4) + VBE (Q3)]} / {R3 / (R2 + R
3)} is larger than the increase of ΔVBE. Therefore, VN3-VN1> 0 and VN3> VN1, and the output voltage PB of the operational amplifier 13 rises, so that normal operation is performed.

That is, there is a disadvantage in that the abnormal operation as described above is likely to occur in the low voltage operation circuit, which makes it difficult to design the low voltage operation circuit. Therefore, in view of the above points, an object of the present invention is to prevent the occurrence of abnormal operation at a low voltage due to power supply startup, noise, etc., and realize a circuit design that operates stably under a lower voltage. It is to provide a bandgap reference circuit.

[0029]

In order to solve the above problems and achieve the object of the present invention, the inventions described in claims 1 to 3 are configured as follows. That is, claim 1
According to the invention described in 1), a first Darlington circuit in which a first transistor and a second transistor of the same size are connected in Darlington, and a current is supplied to the first transistor by being connected in series to the first transistor And a second current source connected in series to the second transistor to supply a current to the second transistor, and N of the first and second transistors (N is 2 or more). A second Darlington circuit in which a third transistor and a fourth transistor each having a size of an integer) times the Darlington connection are connected, and the base of the first transistor and the base of the third transistor are commonly connected. A third current source connected in series to the third transistor to supply a current to the third transistor; and a third current source connected in series to the fourth transistor. A fourth current that is connected in series to the first resistor and the second resistor that are connected to the fourth transistor through the first and second resistors, and that supplies a current to the fourth transistor. Source, the potential of the connection point of the first transistor and the first current source, and the potential of the connection point of the first resistor and the second resistor are the same, A bandgap reference circuit having a second, a third and a fourth current source for controlling respective currents of the current sources;
The current limiting means for limiting each current supplied from the current source is provided.

According to a second aspect of the present invention, in the bandgap reference circuit according to the first aspect, the current limiting means is interposed between the second current source and the second transistor, The first current limiting resistor that limits the current supplied by the second current source and the current supplied by the third current source are interposed between the third current source and the third transistor. And a second current limiting resistor that limits the current.

According to a third aspect of the present invention, in the bandgap reference circuit according to the first aspect, the current limiting means is interposed between the second current source and the second transistor, A first MOS transistor that limits the current supplied by the second current source, and a third MOS source interposed between the third current source and the third transistor to limit the current supplied by the third current source. And a second MOS transistor.

According to the present invention having such a configuration,
It is possible to prevent abnormal operation at low voltage due to power-on and noise, and realize a circuit design that operates stably at a lower voltage.

[0033]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a bandgap reference circuit of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the bandgap reference circuit of the present invention.

In the bandgap reference circuit according to the first embodiment, as shown in FIG. 1, a Darlington circuit 11 in which PNP type transistors Q1 and Q2 are Darlington connected and a PNP type transistors Q3 and Q4 are Darlington connected. Darlington circuit 12, operational amplifier (operational amplifier) 13 functioning as current control means,
P-channel type MOS transistors M1 to M4 functioning as a current source, resistors R1 to R3, and a current limiting resistor R1
1 and R12, and a reference voltage is generated by them.

Here, the transistors Q1 and Q2 have the same size, and the transistors Q3 and Q4 have the same size. Also, Transistor Q
The emitter areas of 3 and Q4 are N (N is a positive integer) times the emitter area of the transistors Q1 and Q2. further,
The sizes of the MOS transistors M1 to M4 are the same.

As described above, the main part of the bandgap reference circuit according to the first embodiment is configured similarly to the bandgap reference circuit shown in FIG.
The difference is that current limiting resistors R11 and R12 are added. Therefore, in the following, the description of the portion having the same configuration is omitted, and the current limiting resistors R11 and R12 will be mainly described.

As will be described later, the current limiting resistors R11 and R12 are provided for the operational amplifier 13 when the power source is turned on.
When the output voltage PB of the device becomes VSS = 0 [V], M
OS transistors M2 and M3 are transistors Q2 and Q3
Currents I2 and I3 supplied to VN3 <VN1
It is intended to prevent the above and stabilize the operation.

Therefore, in the current limiting resistor R11, the MOS transistor M2 which is the second current source is the transistor Q.
2 is a resistor that limits the current supplied to 2, and is inserted between the MOS transistor M2 and the transistor Q2. That is, the current limiting resistor R11 is connected between the drain of the MOS transistor M2 and the emitter of the transistor Q2.

The current limiting resistor R12 is a resistor that limits the current supplied to the transistor Q3 by the third current source MOS transistor M3, and is inserted between the MOS transistor M3 and the transistor Q3. That is, the current limiting resistor R12 is connected to the MOS transistor M.
3 and the emitter of the transistor Q3.

Next, in the first embodiment having such a configuration, due to power-on, noise, etc.,
The operation when the output voltage PB of the operational amplifier 13 becomes VSS = 0 [V] will be described. In this case, M
The OS transistors M1 to M4 are in a linear region, and do not operate as a current source but operate as a resistor.

Further, at this time, each MOS transistor M
1 to M4 supply current I1 to the transistors Q1 to Q4
~ I4 becomes larger than in normal operation, and the resistance values of the MOS transistors M1 to M4 are RM1 to RM4,
It looks like this: I1 = {VDD- [VBE (Q1) + VBE (Q2)]} / (RM1 + R1) ≈ {VDD- [VBE (Q1) + VBE (Q2)]} / R1 ... (23) where RM1 << R1 Is.

[0042]   I2 = (VDD-VBE (Q2)) / (RM2 + R11)       ≈ (VDD-VBE (Q2)) / R11 ... (24)   Here, RM2 << R11.   I3 = (VDD-VBE (Q3)) / (RM3 + R12)       ≈ (VDD-VBE (Q3)) / R12 ... (25) Here, RM3 << R12.

I4 = {VDD− (VBE (Q4) + VBE (Q3)} / (RM4 + R2 + R3) ≈ {VDD− (VBE (Q4) + VBE (Q3)} / (R2 + R3) ... (26) where , RM4 << (R2 + R3) .RM1 to RM
4 << R1 to R3, but the current limiting resistor R11,
If the resistance value of R12 is properly selected, the MOS transistor M
The currents I1, I2, I3, and I4 flowing through 1 to M4 can have substantially the same current value.

Further, since the currents I1 to I4 do not have a very large value, ΔVBE1 = VBE (Q2) -VBE
(Q3) and ΔVBE2 = VBE (Q1) −VBE (Q
4) does not grow so much. As a result, ΔVBE = Δ
VBE1 + ΔVBE2 also does not increase. At this time, the node voltage VN3 is expressed by the following equation (27).

VN3 = VN2 + VR3 = VN2 + (I4 × R3) = VBE (Q3) + VBE (Q4) + {VDD− [VBE (Q4) + VBE (Q3)]} / {R3 / (R2 + R3)} ≈VN1-ΔVBE + {VDD− [VBE (Q4) + VBE (Q3)]} / {R3 / (R2 + R3)} ... (27) where ΔVBE = VBE (Q1) + VBE (Q2) −
{VBE (Q3) + VBE (Q4)} = VN1- {VB
E (Q3) + VBE (Q4)}.

Therefore, from the equation (27), the node voltage VN3
When the voltage (VN3−VN1) of the difference between the node voltage VN1 and the node voltage VN1 is obtained, the following equation (28) is obtained. (VN3-VN1) = {VDD- [VBE (Q4) + VBE (Q3)]} / {R3 / (R2 + R3)}-ΔVBE ... (28) By the way, in the equation (28), R3 / (R2 + R3).
Is determined to cancel the temperature characteristic, and is generally 1/10.
It is about 1/5. However, as described above, ΔVBE does not become so large.

For this reason, {VDD- [VB
E (Q4) + VBE (Q3)]} / {R3 / (R2 + R
3)} <ΔVBE does not hold, so VN3-VN1 <
It will not be 0. As a result, VN3-VN1> 0 can be easily obtained.
Therefore, since VN3> VN1, the output voltage PB of the operational amplifier 13 rises, and the output voltage PB can escape from the state of VSS = 0. Therefore, it becomes a normal stable point and operates normally.

As described above, in the first embodiment, the MOS transistors M2 and M3 are the transistors Q1.
The current limiting resistors R11 and R12 that limit the currents I2 and I3 supplied to Q4 are provided. Therefore, it is possible to prevent the abnormal operation at a low voltage due to the start-up of the power supply, noise, etc., and to realize a circuit design that operates stably under a lower voltage.

Next, a second embodiment of the bandgap reference circuit of the present invention will be described with reference to FIG. In the bandgap reference circuit according to the second embodiment, as shown in FIG. 2, the current limiting resistors R11 and R12 of the first embodiment of FIG. 1 are replaced with current limiting MOS transistors M11 and M12. is there.

More specifically, the MOS transistor M
Reference numeral 11 limits the current supplied to the transistor Q2 by the MOS transistor M2, which is the second current source, and is inserted between the MOS transistor M2 and the transistor Q2. That is, the MOS transistor M1
The source of 1 is connected to the drain of the MOS transistor M2, and the drain of the MOS transistor M11 is connected to the emitter of the transistor Q2.

The MOS transistor M12 limits the current supplied to the transistor Q3 by the MOS transistor M3, which is the third current source, and is inserted between the MOS transistor M3 and the transistor Q3. That is, the source of the MOS transistor M12 is connected to the drain of the MOS transistor M3, and the drain of the MOS transistor M12 is connected to the emitter of the transistor Q3.

Further, the MOS transistors M11, 12
Is connected to the gate of the MOS transistor M13 so that the resistance values of the MOS transistors M11 and M12 can be set arbitrarily. In the MOS transistor 13, the power supply voltage VDD is supplied to the source, the drain is grounded via the current source 19, and the gate and the drain are commonly connected.

According to the second embodiment having such a structure, the same effect as that of the first embodiment can be obtained.

[0054]

As described above, according to the present invention,
It is possible to prevent abnormal operation at low voltage due to power-on and noise, and realize a circuit design that operates stably at a lower voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a bandgap reference circuit of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a second embodiment of a bandgap reference circuit of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a conventional bandgap reference circuit.

[Explanation of symbols]

Q1 to Q6 transistors M1 to M4 MOS transistors (current source) R1 to R3 resistance R11, R12 Current limiting resistor M11, M12 MOS transistors for current limiting 11, 12 Darlington circuit 13 Operational amplifier (current control means) 18 output terminals 19 Current source

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5H420 BB12 CC02 DD02 EA11 EA12                       EA24 EA39 EA42 EB37 FF03                       FF23 KK01 LL07 NA12 NA15                       NA16 NA23 NA27 NB01 NB12                       NB22 NB24 NB36 NC02 NC03                       NC12 NC23 NC26 NC32 NE23                       NE26 NE28                 5J092 AA03 AA58 CA05 CA11 FA04                       FA20 HA02 HA10 HA18 HA19                       HA25 KA01 KA05 KA08 MA06                       MA21

Claims (3)

[Claims] 1. A first transistor in which a first transistor and a second transistor having the same size are Darlington-connected.
A Darlington circuit, a first current source connected in series to the first transistor to supply a current to the first transistor, and a second current source connected in series to the second transistor to supply a current to the second transistor. A second current source to be supplied, a third transistor having a size N times (N is an integer of 2 or more) times the first and second transistors, and a fourth transistor
A second Darlington circuit in which the transistors of No. 1 and Darlington are connected, and the base of the first transistor and the base of the third transistor are commonly connected, and the third transistor is connected in series to the third transistor. Through a third current source that supplies a current to the first transistor, a first resistor and a second resistor that are connected in series with the fourth transistor, and the fourth transistor and the first and second resistors. Connected in series and supplying a current to the fourth transistor, a potential at a connection point between the first transistor and the first current source, the first resistor and the first resistor. The first, the second, and the third so that the potentials of the connection points of the two resistors are the same.
And a current control unit that controls each current of the fourth current source, and a current limiting unit that limits each current supplied from the second and third current sources. A bandgap reference circuit characterized by that. 2. The current limiting means includes a first current limiting resistor interposed between the second current source and the second transistor to limit a current supplied from the second current source. A second current limiting resistor interposed between the third current source and the third transistor to limit a current supplied by the third current source. 1. The bandgap reference circuit according to 1. 3. The first current limiting means is interposed between the second current source and the second transistor, and limits the current supplied by the second current source, and a first MOS transistor, 2. A second MOS transistor, which is interposed between the third current source and the third transistor and limits the current supplied by the third current source. Bandgap reference circuit described.