KR20080003048A - Refrence generation circuit - Google Patents

Abstract

A reference voltage generation circuit is provided to maintain the level of a reference voltage constant regardless of the level variation of an external voltage, by controlling a current flowing to an MOS transistor of an operational amplifier part according to the level of the external voltage. A reference voltage generation circuit(200) divides a first current generated by a first voltage, and generates a second voltage, a third voltage and a reference voltage by using the divided current. An operational amplifier(300) generates the first voltage using potential difference between a first node and a second node generated by the second and the third voltage, and controls the level of the first voltage by controlling the potential of the first and the second node according to the level of an external voltage in a test mode.

Description

Reference voltage generation circuit {REFRENCE GENERATION CIRCUIT}

1 is a circuit diagram showing a bandgap reference voltage generation circuit according to the prior art.

2 is a circuit diagram illustrating a bandgap reference voltage generator circuit according to an exemplary embodiment of the present invention.

3 is a circuit diagram illustrating an example of the operational amplifier 300 of FIG. 2.

The present invention relates to a reference voltage generator circuit, and more particularly to a bandgap reference voltage generator circuit for generating a reference voltage insensitive to temperature.

In general, semiconductor memory devices use various types of internal voltage generation circuits, and band-gap reference voltage generation circuits are circuits for supplying reference voltages to various types of internal voltage generators in a memory device. It is widely used. Therefore, the bandgap reference voltage generation circuit needs to be implemented so as not to be affected by external environmental changes such as temperature. A typical bandgap reference voltage generator circuit is implemented to be insensitive to changes in temperature by making a positive temperature coefficient component and a negative temperature coefficient component by using a bipolar transistor to offset each other.

That is, as shown in FIG. 1, the conventional bandgap reference voltage generator circuit operates by the power-up pulse signal PWRUP to determine the initial level of the voltage VO output from the operational amplifier 20. A bias unit 10 operating by the power-up pulse signal PWRUP to generate a bias voltage VBIAS, a reference voltage generator 20 operating by the output voltage VO to generate a reference voltage VREF insensitive to temperature changes, and a bias Operation amplification unit 30 is biased by the voltage VBIAS and receives the two voltages VA and VC and outputs the voltage VO.

Here, the reference voltage generator 20 is composed of PMOS transistors P1, resistors R1 to R3, and PNP type bipolar transistors Q1 and Q2, and the size of the resistor R1 is a resistor R2. It is preferable that the same as). The reference voltage generator 20 having such a configuration includes a reference whose temperature is compensated by the resistors R1 to R3 having a positive temperature coefficient and the PNP type bipolar transistors Q1 and Q2 having a negative temperature coefficient in a specific region. Generate the voltage VREF.

In addition, the operational amplifier 30 includes PMOS transistors P2 and P3 and NMOS transistors N2 and N3, and outputs a low level voltage VO by the NMOS transistor N1. The voltages VA and VC input to the operational amplifier 30 are controlled to be the same.

The conventional bandgap reference voltage generator having such a configuration operates stably after the saturation region at the normal external voltage VDD, but when the voltage VDD + α having a level higher than the normal external voltage VDD is applied, the non-ideal initial voltage (early voltage) is applied. ), The reference voltage VREF increases.

Id = 1 / (2 * L) * (μ * Cox * W) * (Vgs-Vt) ^ 2 * (1 + λ * Vds)

Here, 'Id' represents a drain current flowing through each of the NMOS transistors N2 and N3, and 'λ * Vds' represents an initial voltage of each of the NMOS transistors N2 and N3.

As shown in Equation 1, the voltage between the drain and the source of each of the NMOS transistors N2 and N3 increases as the external voltage VDD rises, thereby increasing the non-ideal initial voltage effect. Because of the non-ideal initial voltage effect, the level of the reference voltage VREF may rise in the saturation region, and thus, the reference voltage VREF becomes unstable, and thus the operation of the semiconductor memory device may not operate stably.

Accordingly, an object of the present invention is to maintain the reference voltage at a constant level regardless of the level change of the external voltage by operating in the test mode and adjusting the amount of current flowing through the MOS transistor of the operational amplifier according to the level of the external voltage. have.

The reference voltage generating circuit for achieving the above object divides the first current generated by the first voltage, and then generates a second and third voltage and a reference voltage using the divided current. Generator; And generating the first voltage by using the potential difference between the first and second nodes generated by the second and third voltages, and in the test mode, the potentials of the first and second nodes according to the level of an external voltage. And an operational amplifier for adjusting the level of the first voltage.

In the above configuration, the reference voltage generator preferably compensates the temperature change with respect to the reference voltage by making the ratio of the divided currents constant by using temperature compensation elements.

In the above configuration, the operational amplifier includes first MOS transistors driven by the second and third voltages when the external voltage is less than a predetermined voltage, and the second and third voltages when the external voltage is above a predetermined voltage. It is preferable to adjust the level of the first voltage by means of second MOS transistors driven by.

In the above configuration, the first MOS transistors are preferably devices having a longer gate length than the second MOS transistors.

In the above configuration, the operational amplifier section, pull-up means for operating the pull-up by the potential of the second node; First pull-down means configured to pull-down by the first test signal and the first and second voltages input when the external voltage is less than a predetermined voltage; And second pull-down means configured to pull down by the second test signal input when the external voltage is greater than or equal to a predetermined voltage and the first and second voltages.

In the above configuration, the pull-up means may include: a first PMOS transistor having a source receiving the external voltage and a drain connected to the first node; And a second PMOS transistor having a gate connected to a gate of the first PMOS transistor, a drain connected to the gate and the second node, and a source for receiving the external voltage.

In the above configuration, the first pull-down means includes: a first NMOS transistor having a gate receiving the first test signal and a drain connected to the first node; A second NMOS transistor having a gate receiving the first voltage, a drain connected to a source of the first NMOS transistor, and a source receiving a bias voltage; A third NMOS transistor having a gate receiving the first test signal and a drain connected to the second node; And a fourth NMOS transistor having a gate receiving the second voltage, a drain connected to a source of the third NMOS transistor, and a source receiving the bias voltage.

In the above configuration, the second pull-down means may include: a fifth NMOS transistor having a gate receiving the second test signal and a drain connected to the first node; A sixth NMOS transistor having a gate receiving the first voltage, a drain connected to a source of the fifth NMOS transistor, and a source receiving a bias voltage; A seventh NMOS transistor having a gate configured to receive the second test signal and a drain connected to the second node; And an eighth NMOS transistor having a gate receiving the second voltage, a drain connected to a source of the seventh NMOS transistor, and a source receiving the bias voltage.

In the above configuration, the first NMOS transistor, the third NMOS transistor, the fifth NMOS transistor, and the seventh NMOS transistor all have the same size, and the second NMOS transistor has the same size as the fourth NMOS transistor. The sixth NMOS transistor is preferably the same size as the eighth NMOS transistor.

In the above configuration, the sixth and eighth NMOS transistors are preferably devices having a longer gate length than the second and fourth NMOS transistors.

In the above configuration, the reference voltage generator includes: a third PMOS transistor having a gate for receiving the first voltage, a drain for providing the first current, and a source for receiving the external voltage; A first resistor having one end connected to a drain of the third PMOS transistor; A first BJT transistor having a base receiving a ground voltage, a collector connected to the other end of the first resistor, and an emitter receiving the ground voltage; A second resistor, one end of which is connected to the drain of the third PMOS transistor; A third resistor having one end connected to the other end of the second resistor; And a second BJT transistor having a base receiving the ground voltage, a collector connected to the other end of the third resistor, and an emitter receiving the ground voltage.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The circuit of FIG. 2 is disclosed as an embodiment of the present invention, and the embodiment of the present invention adjusts the level of the voltage VO output from the operational amplifier 300 according to the level of the external voltage VDD in the test mode, thereby operating voltage VDD. The reference voltage VREF having a constant level can be generated regardless of the level change of.

Specifically, the embodiment of FIG. 2 is operated by the power-up pulse signal PWRUP and the NMOS transistor N4 which determines the initial level of the voltage VO output from the operational amplifier 200 by operating by the power-up pulse signal PWRUP. The bias unit 100 for generating the bias voltage VBIAS divides the current I1 generated by the voltage VO, and then uses the divided currents I2 and I3 to divide the voltages VA and VC having the same level with the reference voltage VREF having a different level. A reference voltage generator 200 for compensating for a temperature change with respect to the reference voltage VREF by generating a constant and maintaining a ratio of the divided currents I2 and I3 using the temperature compensating elements R4 to R6, Q3 and Q4. And an operational amplifier 300 configured to generate the voltage VO by the voltages VA and VC and to selectively enable the test signals TEST1 to TESTn according to the level of the external voltage VDD in the test mode to adjust the level of the voltage VO. do.

Here, the reference voltage generator 200 receives a voltage VO as a gate and an external voltage VDD as a source to supply a current I1 as a drain and a drain of the PMOS transistor P4 and a BJT transistor Q3. Resistor (R4) connected between the collectors, BJT transistor (Q3) receiving the ground voltage to the base and emitter, resistor (R5) connected to the drain and resistor (R6) of the PMOS transistor (P4), resistor (R5) And a resistor R6 connected between the collector and the collector of the BJT transistor Q4, and the BJT transistor Q4 that receives a ground voltage as a base and an emitter. At this time, the size of the resistor R4 is preferably the same as the resistor R5.

As illustrated in FIG. 3, the operational amplifier 300 is connected to the PMOS transistor P5 receiving the external voltage VDD as a source and the gate of the PMOS transistor P5 receiving the external voltage VDD as a source. A PMOS transistor P6 having a gate and a drain, an NMOS transistor N5 having a drain connected to the drain of the PMOS transistor P5 and receiving a test signal TEST1 inputted according to the level of the external voltage VDD in a test mode; An NMOS transistor N6 having a voltage VA and a bias voltage VBIAS as a gate and a source, respectively, having a drain connected to the source of the NMOS transistor N5, and a test signal TEST2 input according to the level of the external voltage VDD in a test mode. NMOS transistor N7 having a drain input thereto and connected to the drain of PMOS transistor P5, and voltage VA and bias voltage VBIAS as gate and source, respectively. An NMOS transistor N8 having a drain connected to the source of the NMOS transistor N7, an NMOS transistor N9 having a drain input to the gate of the test signal TEST2 and connected to a drain of the PMOS transistor P6, and a voltage VC NMOS transistor N10 having an over bias voltage VBIAS as a gate and a source, respectively, and having a drain connected to the source of the NMOS transistor N9, and a drain connected to the drain of the PMOS transistor P6 after receiving the test signal TEST1 as a gate. And an NMOS transistor N12 having a drain connected to a source of the NMOS transistor N11 and receiving a voltage VC and a bias voltage VBIAS as a gate and a source, respectively.

In the operational amplifier 300 having the configuration as shown in FIG. 3, the test signal TEST1 is enabled and the test signal TEST2 is applied when a voltage having a normal external voltage VDD, that is, a voltage having a level below the reference voltage level is applied to the external voltage VDD. Is disabled, the test signal TEST2 is enabled and the test signal TEST1 is disabled when a high voltage VDD + α, that is, a voltage having a level above the reference voltage level is applied to the external voltage VDD.

The NMOS transistors N5, N7, N9 and N11 have the same size, the NMOS transistor N6 has the same size as the NMOS transistor N12, and the NMOS transistor N8 has the same size as the NMOS transistor N10. Is the same as Here, the NMOS transistors N5, N7, N9, and N11 may have any size, and the NMOS transistors N8 and N10 may have the same gate width as compared to the NMOS transistors N6 and N12. It is preferable to have a gate length longer than the NMOS transistors N6 and N12.

An embodiment of the present invention having such a configuration may generate a constant reference voltage VREF regardless of the level change of the external voltage VDD, and a detailed operation thereof will be described below.

First, the NMOS transistor N4 is operated by the power up pulse signal PWRUP to keep the initial level of the output voltage VO low. The bias unit 100 operates by the power-up pulse signal PWRUP to provide a low level bias voltage VBIAS. Here, since the bias unit 100 is a circuit well known in the art, a detailed structure thereof will be omitted.

The reference voltage generator 200 may turn on the PMOS transistor P4 by the initial voltage VO to transfer the constant current I1, and the current I1 may be represented by Equation 2 below.

I1 = I2 + I3

In addition, since the levels of the two voltages VA and VC input to the operational amplifier 300 are the same, Equations 3 and 4 below hold.

I2 * R4 = I3 * R5

VQBE3 = VQBE4 + I3 * R6

Here, VQBE3 represents the voltage between the base and emitter of BJT transistor Q3, and VQBE4 represents the voltage between the base and emitter of BJT transistor Q4.

By the equations (3) and (4), the voltage across the resistor R6 can be expressed as shown in Equation 5 below.

I3 * R6 = VQBE3-VQBE4 = VTHRM * In (I2 / I3) = VTHRM * In (R5 / R4)

Here, VTHRM represents a thermal voltage.

In addition, according to Equation 5, the current I3 may be represented by Equation 6 below.

I3 = (R5 / R4) * (VTHRM / R6) * ln (R5 / R4)

The reference voltage VREF may be represented by Equation 7 below.

VREF = VQBE3 + I3 * R4

Therefore, the reference voltage VREF can be expressed by Equation 8 below by Equations 6 and 7.

VREF = VQBE3 + {VTHRM * (R5 / R6)} * ln (R5 / R4)

As described above, since the ratio of the currents I2 and I3 has a constant value regardless of the temperature, the reference voltage generator 200 may minimize the change in the level of the reference voltage VREF according to the change in temperature.

The operational amplifier 300 outputs the voltage VO by the NMOS transistor N4 during initial driving, and then receives the voltages VA and VC having the same level to maintain the voltage level of the voltage VO constant.

When the level of the external voltage VDD is less than or equal to the predetermined voltage when operating in the test mode, the NMOS transistors N5, N6, N11, and N12 are turned on to output the same voltage VO as in the normal mode, and operate in the test mode. When the level of the external voltage VDD is greater than or equal to a predetermined voltage, the NMOS transistors N7 to N10 are turned on to raise the level of the voltage VO. In this case, since the gate length of the NMOS transistors N8 and N10 is greater than that of the NMOS transistors N6 and N11, the operational amplifier 300 may apply a voltage between the drain and the source of the MOS transistor that changes in response to the external voltage VDD level. The change may be compensated for (see Equation 1). The operational amplifier 300 may adjust the level of the voltage VO using NMOS transistors having various gate lengths.

That is, the operational amplifier 300 adjusts the level of the voltage VO according to the external voltage VDD, thereby adjusting the driving capability of the PMOS transistor P4 of the reference voltage generator 200 to always change the level of the external voltage VDD. Can send a constant current I1.

Accordingly, the embodiment of the present invention has the effect of generating a constant reference voltage VREF even when the level of the external voltage VDD is changed by using the MOS transistors having various gate lengths in the operational amplifier 300 in the test mode.

As described above, the present invention selectively turns on MOS transistors having various gate lengths provided in the operational amplifier according to the level of the external voltage VDD by using the test signal, so that the reference voltage VREF is constant even if the level of the external voltage VDD changes. There is an effect that can generate.

While the invention has been shown and described with reference to specific embodiments, the invention is not limited thereto, and the invention is not limited to the scope of the invention as defined by the following claims. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (11)

A reference voltage generator for distributing a first current generated by a first voltage and generating second and third voltages and a reference voltage using the divided currents; And The first voltage is generated by using the potential difference between the first and second nodes generated by the second and third voltages, and in the test mode, the potentials of the first and second nodes are changed according to the level of the external voltage. And an operational amplifier configured to adjust the level of the first voltage by adjusting. The method of claim 1, And the reference voltage generator compensates for the temperature change with respect to the reference voltage by using a temperature compensating element to make the ratio of the divided currents constant. The method of claim 1, The operational amplifier may include first MOS transistors driven by the second and third voltages when the external voltage is less than a predetermined voltage and second and third voltages driven by the second and third voltages when the external voltage is greater than or equal to a predetermined voltage. A reference voltage generator circuit, characterized in that the level of the first voltage is adjusted by two MOS transistors. The method of claim 3, wherein And the first MOS transistors are devices having a longer gate length than the second MOS transistors. The method of claim 1, The operational amplifier, Pull-up means for operating pull-up by the potential of the second node; First pull-down means configured to pull-down by the first test signal and the first and second voltages input when the external voltage is less than a predetermined voltage; And And a second pull-down means configured to pull down by the second test signal input when the external voltage is equal to or greater than a predetermined voltage and the first and second voltages. The method of claim 5, The pull-up means, A first PMOS transistor having a source receiving the external voltage and a drain connected to the first node; And And a second PMOS transistor having a gate connected to the gate of the first PMOS transistor, a drain connected to the gate and the second node, and a source for receiving the external voltage. The method of claim 5, The first pull down means, A first NMOS transistor having a gate receiving the first test signal and a drain connected to the first node; A second NMOS transistor having a gate receiving the first voltage, a drain connected to a source of the first NMOS transistor, and a source receiving a bias voltage; A third NMOS transistor having a gate receiving the first test signal and a drain connected to the second node; And And a fourth NMOS transistor having a gate receiving the second voltage, a drain connected to a source of the third NMOS transistor, and a source receiving the bias voltage. The method of claim 5, The second pull down means, A fifth NMOS transistor having a gate receiving the second test signal and a drain connected to the first node; A sixth NMOS transistor having a gate receiving the first voltage, a drain connected to a source of the fifth NMOS transistor, and a source receiving a bias voltage; A seventh NMOS transistor having a gate receiving the second test signal and a drain connected to the second node; And And an eighth NMOS transistor having a gate receiving the second voltage, a drain connected to a source of the seventh NMOS transistor, and a source receiving the bias voltage. The method according to any one of claims 6 to 8, The first NMOS transistor, the third NMOS transistor, the fifth NMOS transistor, and the seventh NMOS transistor all have the same size, the second NMOS transistor is the same size as the fourth NMOS transistor, and the sixth And the NMOS transistor has the same size as the eighth NMOS transistor. The method according to any one of claims 6 to 8, And the sixth and eighth NMOS transistors are devices having a longer gate length than the second and fourth NMOS transistors. The method of claim 1, The reference voltage generator, A third PMOS transistor having a gate for receiving the first voltage, a drain for providing the first current, and a source for receiving the external voltage; A first resistor having one end connected to a drain of the third PMOS transistor; A first BJT transistor having a base receiving a ground voltage, a collector connected to the other end of the first resistor, and an emitter receiving the ground voltage; A second resistor, one end of which is connected to the drain of the third PMOS transistor; A third resistor having one end connected to the other end of the second resistor; And And a second BJT transistor having a base receiving the ground voltage, a collector connected to the other end of the third resistor, and an emitter receiving the ground voltage.

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