JP2000267749A - Starting circuit and voltage supplying circuit using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a starting circuit resistant to the dispersion in manufacture capable of reducing the power consumption to the irreducible minimum, and a voltage supplying circuit using this starting circuit. SOLUTION: The voltage supplying circuit is constituted by using a starting circuit 10a and a band gap reference voltage circuit 20, and starting currents IST are supplied to a node n2 of the band gap reference voltage circuit 20 by the starting circuit 10a at the time of start so that the band gap reference voltage circuit 2 can be actually started. After the band gap reference voltage circuit 20 starts to operate, the output signal voltage of an operating amplifier OPA1 starts to decrease, and when the output signal voltage reaches a voltage level enough to turn on a pMOS transistor PT1 in the starting circuit 10a, the supply of the starting currents IST stops, and the band gap reference voltage circuit 20 operates under the control of a feedback loop constituted of the operating amplifier OPA1, and supplies a constant voltage VOUT without power supply voltage dependency and temperature dependency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a starting circuit which is incorporated in a voltage supply circuit, for example, a bandgap reference voltage circuit, and which operates when the bandgap reference voltage circuit is started to surely start the reference voltage circuit. The present invention relates to a voltage supply circuit configured using the same.

[0002]

2. Description of the Related Art Conventionally, as in a band gap reference voltage circuit utilizing feedback of an operational amplifier circuit (hereinafter, simply referred to as an operational amplifier for convenience), a certain signal is supplied to a feedback loop of the operational amplifier when the circuit is started. In a circuit that does not normally start operation unless it is started, a starting circuit that has a simple circuit configuration and can start the circuit reliably is required.

FIG. 14 is a circuit diagram showing an example of a voltage supply circuit including a conventional starter circuit. As shown in the figure, the voltage supply circuit of the present example includes a starter circuit 10 and a bandgap reference voltage circuit 20. The starting circuit 10
It comprises an inverter INV101, a NAND gate NA101 and a delay circuit D101. Note that p
Since the MOS transistors T104 and T105 and the inverter INV102 also contribute to the operation of the bandgap reference voltage circuit 20, a circuit constituted by these circuit elements can be regarded as a part of the start-up circuit.

[0006] Upon receiving the standby signal STB, a start circuit 10 receives a signal S for reliably operating the bandgap reference voltage circuit 20 in accordance with the standby signal STB.
1 and S2 are generated. The bandgap reference voltage circuit 20 includes an operational amplifier circuit (op amp) OPA1, pMO
S transistors T101, T102, T103 and diode-connected npn transistor B101,
B102 and B103. Transistors T101, supply line and a reference potential of the resistor element R101 and the diode the attached transistor B101 is the power supply voltage V _CC, for example, connected in series between the supply line of the ground potential GND, and is a transistor T102 and a diode connected transistor B102 is connected in series between the supply line and the ground potential GND of the power supply voltage V _CC, transistor T
103, a resistor R102 and a diode the attached transistor B103 is connected in series between the supply line and the ground potential GND of the power supply voltage V _CC. Transistor T
The gates of 101, T102, and T103 are connected to the output terminal of the operational amplifier OPA1, and the operational amplifier OP
The currents I1, I2, and I3 are output according to the output signal of A1.

[0005] The non-inverting input terminal (+) of the operational amplifier OPA1 is connected to a node n1 which is a connection point between the transistor T101 and the resistance element R101, and the inverting input terminal (-) is connected to the transistor T102 and the transistor B102. It is connected to a node n2 consisting of a connection midpoint. The output signal of the operational amplifier OPA1 is applied to the gates of the transistors T101, T102 and T103, respectively. Therefore, a feedback loop is formed by the operational amplifier OPA1, and the currents I1, I2, and I3 of the transistors T101, T102, and T103 are controlled by the control of the feedback loop so that the voltages of the nodes n1 and n2 become equal during normal operation. Is done.

In the standby (stop) state, the output terminal of the operational amplifier OPA1, that is, the node n3 is in a high impedance state. At this time, the standby signal STB
Is at the high level, the output terminal of the inverter INV102 is held at the low level, and the transistor T10
Since node 5 is turned on, node n3 is substantially held at the level of power supply voltage V _CC . Therefore, transistors T101, T101
Since 102 and T103 are turned off and no DC current flows, the voltages of the nodes n1 and n2 are undefined. At the start of operation, as the standby signal STB switches from high level to low level, the output terminal of the inverter INV102 switches from low level to high level, so that the transistor T105 turns off, and the operational amplifier OPA1 switches the input nodes n1 and n2. , The voltage of the node n3 is controlled, and the transistors T101 and T1 are accordingly controlled.
02 and the currents I1, I2, I3 of T103 are controlled.

However, if there is no starting circuit and the node n1
Is higher than the voltage V _{n2 of the} node _n 2, that is, when V _n1 > V _n2 , the operational amplifier OPA 1 outputs the signal voltage input to the non-inverting input terminal (+) to its inverting input terminal (+). −), The signal voltage is higher than the signal voltage applied to the transistors T101 and T101.
102 and T103 remain off. In such a state, the bandgap reference voltage circuit 20 cannot operate normally.

As described above, the standby signal STB is
When the voltage supply circuit is stopped, it is kept at a high level, and when the voltage supply circuit starts operating, it switches from a high level to a low level. In response to this, the starting circuit 10 shown in the figure, from the falling edge of the standby signal STB, the low level of the signal S1 is output during the delay time Delta] t _d of the delay circuit D101. At other times, the signal S1 is held at a high level.

Since the transistor T104 is turned on while the signal S1 is at the low level, the current flowing through the transistor T104 is input to the node n2. The emitter area of the diode-connected bipolar transistor B101 is formed larger than the emitter area of the transistor B102. Therefore, when the same current is applied to these transistors or when the transistor B102
When the current flows only through the node n2 in the initial stage of the operation.
Voltage V _n2 of becomes always higher than the voltage V _n1 of the node n1. Therefore, in the operational amplifier OPA1, the input signal voltage at the inverting input terminal (-) is higher than the input signal voltage at the non-inverting input terminal (+), and the output signal is held at a low level. In response, the transistors T101, T101
102 and T103 are turned on, and currents I1, I2 and I3 are output.

[0010] signal S1 applied to the gate of the transistor T104 is held at low level only time set by the delay time of the delay circuit D101 Delta] t _d, then switched again to a high level. Transistor T104
Turns on only while the signal S1 is at the low level, and then turns off. Therefore, the bandgap reference voltage circuit 20 is controlled by the feedback loop formed by the operational amplifier OPA1, and the power supply voltage V _CC and the temperature are output from the output terminal T _OUT. A stable and independent voltage V _OUT is output.

[0011]

In the above-described conventional voltage supply circuit, a control is performed such that the transistor T105 is turned off, the transistor T104 is turned on for a certain fixed time, and then turned off by the start circuit 10 after the circuit is started. As a result, normal startup is possible regardless of the voltages of the nodes n1 and n2 when stopped. Here, if the transistor T104 remains on, the feedback loop including the operational amplifier OPA1 cannot operate normally, and the operational amplifier OPA
1 cannot control the transistors T101, T012, and T103, so that the control signal S for controlling the ON time of the transistor T104 by the delay time of the delay circuit D101.
1 is generated.

However, the switching of the level of the signal S1 is not performed after confirming the operation state of the bandgap reference voltage circuit 20, but is set empirically. Therefore, the level is always set to an optimum value. Not necessarily. If the switching time is too long, the rise time of the voltage supply circuit is extended more than necessary, and the rise characteristic deteriorates. If the switching time is too short, the start circuit stops before the voltage V _{n2 of the} node n2 becomes sufficiently high. As a result, the bandgap reference voltage circuit 20 may not start normally.
Therefore, this starting circuit requires a great care in designing, and has a disadvantage that it is easily affected by variations in manufacturing and fluctuations in circuit operating conditions.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object a simple circuit configuration and easy design, which is resistant to manufacturing variations, has no dependency on temperature and power supply voltage, and has low power consumption. And a voltage supply circuit using the same.

[0014]

To achieve the above object, a starting circuit according to the present invention is a starting circuit that supplies a starting current to a predetermined function circuit and starts the function circuit.
A start-up current supply unit that receives the start-up signal and supplies the start-up current to the function circuit; and when the voltage of a predetermined operation node of the function circuit reaches a predetermined value, the start-up current supply unit And activation control means for stopping the supply of power.

Further, the voltage supply circuit of the present invention receives a start signal and supplies start-up current for supplying a start-up current, and starts upon receiving the start-up current and outputs a stable voltage during normal operation after start-up. A voltage generation circuit; and a start control unit for stopping the supply of the start current to the start current supply unit when a voltage of a predetermined operation node of the voltage generation circuit reaches a predetermined value.

Specifically, a voltage supply circuit according to the present invention includes a first voltage supply circuit connected between a power supply voltage supply line and a first node.
A current supply transistor, a first resistor element connected in series between the first node and a reference potential line, a first diode directed in a forward direction toward the reference potential line, and a power supply voltage. A second current supply transistor connected between the supply line and the second node; and a second current supply transistor connected between the second node and the reference potential line, wherein the second current supply transistor is connected in a forward direction toward the reference potential line. A second diode, a third current supply transistor connected between the power supply voltage supply line and a third node, and a series connection between the third node and the reference potential line. A second resistor element, a third diode going forward toward the reference potential line, a first input terminal connected to the first node, and a second input terminal connected to the second input terminal. The first and second input terminals connected to a node Amplifying circuit for applying a voltage signal corresponding to a difference between signals input to the first, second and third current supply transistors to the control terminal of the first, second and third current supply transistors; A starting current supply unit that supplies a current, and a starting control unit that stops the supply of the starting current when an output voltage of the amplifier circuit reaches a predetermined reference value.

In the present invention, preferably, the activation control means receives the activation signal as a first input signal and an output signal of the amplifier circuit as a second input signal, and A bistable logic circuit controlled to the first and second states in response to a second input signal, and a signal corresponding to a logical operation result of the start signal and an output signal of the bistable logic circuit; And a logic gate. Further, the bistable logic circuit has first and second transistors connected in series between a power supply voltage supply line and a reference potential line, and the gate of the first transistor is connected to the gate of the first transistor. An output voltage is applied, and the start signal is applied to a gate of the second transistor.

Further, as another specific example, a voltage supply circuit according to the present invention comprises a first current supply transistor connected between a power supply voltage supply line and a first node; A first node connected in series with a third node;
A first diode in a forward direction toward the third node, a second current supply transistor connected between the power supply voltage supply line and a second node, A second diode connected between the third node and the third node, and connected in a forward direction toward the third node; and a second diode connected between the third node and a reference potential line. A second resistor element, a first input terminal is connected to the first node, and a second input terminal is connected to the second node.
And an amplifier circuit connected to the first and second nodes for applying a voltage signal corresponding to a difference between signals input to the first and second input terminals to control terminals of the first and second current supply transistors. Starting current supplying means for supplying a starting current to the second node in response to a starting signal; and starting control means for stopping supply of the starting current when an output voltage of the amplifier circuit reaches a predetermined reference value. Having.

Further, the voltage supply circuit according to the present invention includes a power supply circuit connected in parallel between a power supply voltage supply line and a first node.
(M is a natural number)
, A first resistor element connected in series between the first node and the third node, and the third
A first diode going forward toward the node of
A second transistor group consisting of n (n is a natural number) current supply transistors connected in parallel between the power supply voltage supply line and a second node; and a second transistor group including the second node and the third node. A second diode connected between the third diode and the third node, the second diode having a forward direction toward the third node;
A second resistance element connected between the first node and the reference potential line, a first input terminal connected to the first node, and a second input terminal connected to the second node. An amplifier circuit for applying a voltage signal corresponding to a difference between signals input to the first and second input terminals to control terminals of the respective transistors of the first and second transistor groups, And a start-up current supply unit for responsively supplying a start-up current to the second node; and a start-up control unit for stopping supply of the start-up current when an output voltage of the amplifier circuit reaches a predetermined reference value.

Further, the voltage supply circuit according to the present invention includes a first transistor group including m (m is a natural number) current supply transistors connected in parallel between the power supply voltage supply line and the first node. A first resistance element connected in series between the first node and the third node, a first diode going forward toward the third node, and a power supply voltage supply line A second transistor group consisting of n (n is a natural number) current supply transistors connected in parallel between the second node and the second node, and between the second node and the third node A second diode connected in a forward direction toward the third node, and a second diode connected between the third node and a reference potential line.
And a third transistor group consisting of j (j is a natural number) current supply transistors connected in parallel between the power supply voltage supply line and the fourth node, and the fourth node A third resistor element connected in series between the reference potential line and a third diode in a forward direction toward the reference potential line; and a first input terminal connected to the first input terminal.
, A second input terminal is connected to the second node, and a voltage signal corresponding to a difference between signals input to the first and second input terminals is supplied to the first, second, and third input terminals. Third
An amplifying circuit applied to the control terminal of each transistor of the transistor group; a starting current supply means for supplying a starting current to the second node in response to a starting signal at the time of starting; Starting control means for stopping the supply of the starting current when the value reaches the value.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a circuit diagram showing a first embodiment of a starting circuit according to the present invention. As shown in FIG.
a is a pMOS transistor PT1, PT2, PT3,
nMOS transistor NT1, inverters INV1, I
It is composed of NV2 and NAND gate NA1.

The transistors PT1 and NT1 are connected in series between the ground potential GND and the supply line of the power supply voltage V _CC. The gate of the transistor PT1 is connected to the signal terminal SN1, and the gate of the transistor NT1 is connected to the input terminal IN1.
It is connected to the. The connection point between the drains of the transistors PT1 and NT1 is connected to the node ND1.
The input terminal of the inverter INV1 is connected to the input terminal IN1, and the input terminal of the inverter INV2 is connected to the node ND1. Both input terminals of the NAND gate NA1 are connected to output terminals of the inverters INV1 and INV2, respectively. The gate of the transistor PT2 is NA
Is connected to the output terminal of the ND gate NA1, its source is connected to the supply line of the power supply voltage V _CC, the drain is connected to the output terminal OUT1. The gate of the transistor PT3 is connected to the output terminal of the inverter INV1, the source is connected to the supply line of the power supply voltage V _CC , and the drain is connected to the signal terminal SN1.

The starting circuit 10a thus configured
A standby signal STB which is set to a high level when stopped and set to a low level after the operation starts is applied to the input terminal IN1, and an output terminal is connected to an operation node which requires a current to flow temporarily (voltage increase) in order to start. OUT1 is connected, is fixed to the voltage of the power supply voltage V _CC at the time of operation stop, the operation starts after the power supply voltage need some operation node signal terminal SN1 is connected to the lowering from V _CC to a voltage sufficient to turn on the pMOS transistor Have been.

Hereinafter, the operation of the starting circuit according to the present embodiment will be described with reference to FIG. The standby signal STB is input to the input terminal IN1. The standby signal STB is output while the circuit is stopped (standby state).
At the high level, and when the circuit starts operating, it is switched to the low level.

In the standby state, the inverter IN
The output terminal of V1 is at low level. Further, the transistor NT1 is turned on, and the node ND1 is held at a low level, for example, the level of the ground potential GND. Since the output terminal of the NAND gate NA1 is held at a high level according to the output signals of the inverters INV1 and INV2,
The transistor PT2 turns off. On the other hand, transistor P
Since the gate of T3 is at the low level, the transistor PT3 is turned on, and the signal terminal SN1 is held at the high level, for example, at the power supply voltage V _CC or a level close thereto.

After the voltage supply circuit starts operating, the standby signal STB switches from the high level to the low level. In response, the transistor NT1 is turned off from on. The output terminal of the inverter INV1 switches from low level to high level.
Although T3 is turned off, the signal terminal SN1 is kept at a high level unless a new signal comes in from the signal terminal SN1. Therefore, the transistors PT1 and NT
1 are both turned off, the node ND1 is in a high impedance state, and its voltage does not change and is kept at a low level.

At this time, since both the input terminals of the NAND gate NA1 are at the high level, the output terminal thereof is held at the low level. In response, the transistor PT2 is turned on, and the starting current I _ST is supplied to the output terminal OUT1. In response to the current I _ST supplied from the output terminal OUT1, for example, the band gap reference voltage circuit starts operating, and the voltage of the signal terminal SN1 starts to decrease. When the voltage at the terminal drops to a value sufficient to turn on the pMOS transistor PT1, the transistor PT1 turns on, and the node ND1 is raised from a low level to a high level, for example, the power supply voltage V _CC or a level close thereto.

The voltage at node ND1 is equal to the voltage at inverter INV2.
Is exceeded, the output terminal of the inverter INV2 switches from the high level to the low level, and the output terminal of the NAND gate NA1 switches from the low level to the high level. Therefore, the transistor PT2 is turned off, and the supply of the current to the output terminal OUT1 is stopped. After the supply of the starting current _IST is stopped, the bandgap reference voltage circuit starts operating normally.

As described above, the starting circuit 1 of the present embodiment
Oa operates when the voltage supply circuit is started, and supplies a start current I _ST required for the bandgap reference voltage circuit, for example.
Since the operation is stopped after the operation of the bandgap reference voltage circuit is confirmed, the voltage supply circuit can be reliably started. In addition, the supply of the starting current I _ST to the band gap is automatically stopped according to the operation state of the band gap, so that the supply timing of the starting current I _ST can be appropriately set, and the power consumption at the time of starting can be reduced. It is possible to suppress it to the minimum necessary. The circuit configuration is simple, the application range is wide, and the design is easy. Furthermore, there is a characteristic that it is resistant to process variations.

Second Embodiment FIG. 2 is a circuit diagram showing a starting circuit according to a second embodiment of the present invention. Compared to the first embodiment of the start-up circuit shown in FIG. 1, the start-up circuit 10b of this embodiment is different from the first embodiment in that an inverter INV3 and an nMOS transistor NT2 are provided on the output side of the NAND gate NA1 instead of the pMOS transistor PT2. Different. The other parts are substantially the same as those of the first embodiment shown in FIG. 1, and therefore, in FIG. 2, the same components of the circuit are denoted by the same reference numerals as in FIG.

As shown in FIG. 2, the input terminal of the inverter INV3 is connected to the output terminal of the NAND gate NA1, and the output terminal is connected to the gate of the transistor NT2. The source of the transistor NT2 is grounded,
The drain is connected to the output terminal OUT2.

In the start-up circuit of this embodiment, a current flows into the output terminal OUT2 at the time of start-up. Therefore, the output terminal OUT2 is connected to an operation node which needs to temporarily draw current (reduce the voltage) after the operation starts. I have.

Hereinafter, the operation of the starting circuit 10b according to the present embodiment will be briefly described with reference to FIG. In the standby state, the standby signal STB input to the input terminal IN1 is held at a high level. In response, the output terminal of the inverter INV1 is held at low level, the transistor PT3 turns on, and the signal terminal SN1
Is held at a high level. The transistor NT1 is turned on, the node ND1 is held at low level, and the output terminal of the inverter INV2 is at high level. At this time, N
Since the output terminal of the AND gate NA1 is at the high level, the output terminal of the inverter INV3 is at the low level, and the transistor NT2 is turned off.

After the circuit starts operating, the standby signal STB
Is switched from a high level to a low level. In response to this, the output terminal of the inverter INV1 changes to the high level, and the transistor PT3 turns off.
Unless a new signal is input to N1, the voltage does not change and is maintained at a high level. On the other hand, the transistor NT1 is turned off, the node ND1 enters a high impedance state, and its voltage is kept at a low level.
The output terminal of the inverter INV2 also remains at the high level.

Therefore, both input terminals of the NAND gate NA1 are at the high level, the output terminal thereof is at the low level, and the output terminal of the inverter INV3 is at the high level, so that the transistor NT2 is turned on and the output terminal O
A drawn current flows through UT2.

In response to the current drawn from the output terminal OUT2, for example, the band gap reference voltage circuit starts operating. Accordingly, when the voltage of the signal terminal SN1 decreases and the voltage decreases to a voltage sufficient to turn on the pMOS transistor PT1, the transistor PT1 turns on and the node ND1 is raised from a low level to a high level. Therefore, the inverter INV2, the NAND
The output signal level of the gate NA1 and the output signal of the inverter INV3 are sequentially switched. As a result, the output terminal of the inverter INV3 becomes low level, and the transistor NT2 is turned off.

After the transistor NT2 is turned off, no current flows into the output terminal OUT2, and the bandgap reference voltage circuit enters a normal operation state. For example, the output voltage is stabilized by a feedback loop including an operational amplifier. To supply a desired constant voltage.

Third Embodiment FIG. 3 is a circuit diagram showing a starting circuit according to a third embodiment of the present invention. As shown in FIG.
c denotes pMOS transistors PT1, PT2, nMOS
It comprises transistors NT1 and NT3, an inverter INV4 and a NAND gate NA1.

The transistors PT1 and NT1 are connected in series between the supply line of the power supply voltage V _CC and the ground potential GND. The gate of the transistor PT1 is connected to the inverter INV4.
, And the gate of the transistor NT1 is connected to the signal terminal SN2. Transistor PT1
The connection point between the drains of the transistors NT1 and NT1 is connected to the node ND1. Note that the input terminal of the inverter INV1 is connected to the input terminal IN1. The input terminal I
The standby signal STB is applied to N1.

The two input terminals of the NAND gate NA1 are connected to the node ND1 and the output terminal of the inverter INV4, respectively. The gate of the transistor PT2 is N
Connected to the output terminal of the AND gate NA1, the source is connected to the supply line of the power supply voltage V _CC, the drain output terminal O
Connected to UT1. The gate of the transistor NT3 is connected to the input terminal IN1, and the drain is the signal terminal SN.
2 and the source is grounded.

In the starter circuit 10c of this embodiment, a standby signal STB which is set to a high level when stopped and set to a low level after the operation is started is applied to the input terminal IN1. The output terminal OUT1 is connected to an operation node to which a current needs to be temporarily supplied for activation, fixed to the ground potential GND when the operation is stopped, and changed from the ground potential GND to nM after the operation starts.
The signal terminal SN2 is connected to an operation node that needs to be raised to a voltage sufficient to turn on the OS transistor.

Hereinafter, the operation of the starting circuit according to the present embodiment will be described with reference to FIG. In the standby state, since the high-level standby signal STB is input, the output terminal of the inverter INV4 is held at the low level, and the transistor PT1 is turned on. At this time, since the transistor NT3 is turned on, the signal terminal SN
2 is kept at a low level, for example, at the ground potential GND level, and the transistor NT1 is turned off. For this reason, the node ND1 is substantially held at the level of the power supply voltage V _CC . At this time, the output terminal of the NAND gate NA1 is held at the high level, so that the transistor PT2 is turned off.

After the operation of the voltage supply circuit starts, the standby signal STB switches from the high level to the low level. In response, the output terminal of the inverter INV4 switches from low level to high level, and the transistor P
T1 turns off. On the other hand, the transistor NT3 is turned off,
The signal terminal SN2 is kept at a low level, and the transistor NT1 remains off. Therefore, the node ND1 is in the high impedance state, and the voltage thereof is also maintained at the high level.

At this time, both the input terminals of the NAND gate NA1 are at the high level, the output terminal thereof is changed to the low level, and the transistor PT2 is turned on. In response to this, the starting current I _ST is supplied to the output terminal OUT1. In response to the current I _ST supplied from the output terminal OUT1, for example, the band gap reference voltage circuit starts operating, and the voltage of the signal terminal SN2 starts to rise from a low level. When the voltage of the terminal SN2 is the nMOS transistor NT1
, The transistor NT1 turns on, and the node ND1 switches from the high level to the low level. Accordingly, switches the output terminal of the NAND gate NA1 is from a low level to a high level, the transistor PT2 is turned off, the supply of the starting current I _ST stops. After the supply of the starting current _IST is stopped, the bandgap reference voltage circuit starts operating normally.

As described above, the starting circuit 1 of the present embodiment
Oc operates when the voltage supply circuit is started, and supplies a start current _IST necessary for the bandgap reference voltage circuit, for example.
Since the operation is stopped after the operation of the bandgap reference voltage circuit is confirmed, the voltage supply circuit can be reliably started. In addition, the supply of the starting current I _ST to the band gap is automatically stopped according to the operation state of the band gap, so that the supply timing of the starting current I _ST can be appropriately set, and the power consumption at the time of starting can be reduced. It is possible to suppress it to the minimum necessary. The circuit configuration is simple, the application range is wide, and the design is easy. Furthermore, there is a characteristic that it is resistant to process variations.

Fourth Embodiment FIG. 4 is a circuit diagram showing a starting circuit according to a fourth embodiment of the present invention. Compared with the start-up circuit of the third embodiment shown in FIG.
A pMOS transistor PT is connected to the output side of the D gate NA1.
2 in that an inverter INV3 and an nMOS transistor NT2 are provided instead of 2. The other parts are substantially the same as those of the third embodiment shown in FIG. 3, and therefore, in FIG. 4, the same components as those of the starter circuit are denoted by the same reference numerals as in FIG.

As shown in FIG. 4, the input terminal of the inverter INV3 is connected to the output terminal of the NAND gate NA1, and the output terminal is connected to the gate of the transistor NT2. The source of the transistor NT2 is grounded,
The drain is connected to the output terminal OUT2.

In the start-up circuit of the present embodiment, a current is drawn into the output terminal OUT2 at the time of start-up. Therefore, the output terminal OUT2 is connected to an operation node that needs to draw current (temporarily reduce voltage) after the start of operation. I have.

Hereinafter, the operation of the starting circuit 10d according to the present embodiment will be briefly described with reference to FIG. In the standby state, the standby signal STB input to the input terminal IN1 is held at a high level. In response, the output terminal of inverter INV4 is held at low level, pMOS transistor PT1 is turned on, and node ND1 is held at high level. At this time, the NAND
Since the output terminal of the gate NA1 is at a high level, the output terminal of the inverter INV3 is at a low level, and the transistor NT2 is turned off.

After the operation of the voltage supply circuit starts, the standby signal STB switches from the high level to the low level. In response, the output terminal of the inverter INV4 switches from low level to high level, and the transistor P
T1 turns off. On the other hand, the transistor NT3 is turned off,
The signal terminal SN2 is kept at a low level, and the transistor NT1 remains off. Therefore, the node ND1 is in the high impedance state, and the voltage thereof is also maintained at the high level.

[0051] At this time, switches NAND gate NA1 output terminal to the low level, the transistor NT2 is turned on in response to this, pull I _ST to flow to the output terminal OUT2. According to the drawing current I _ST of the output terminal OUT2,
For example, the bandgap reference voltage circuit starts operating,
The voltage of the signal terminal SN2 starts to rise from the low level. When the voltage at the terminal SN2 rises to the threshold voltage of the nMOS transistor NT1, the transistor NT1 turns on, and the node ND1 switches from high level to low level. Thus, the transistor NT2 is turned off, not draw current I _ST to flow. Thereafter, the bandgap reference voltage circuit starts a normal operation, and supplies a constant voltage having a desired level without dependency on the power supply voltage and the temperature.

Fifth Embodiment FIG. 5 is a circuit diagram showing a starting circuit according to a fifth embodiment of the present invention. As shown in FIG.
e is the node N compared to the first embodiment shown in FIG.
It has substantially the same configuration except that a delay circuit DLY1 is connected between D1 and the input terminal of the inverter INV2. In FIG. 5, the same parts of the starting circuit are denoted by the same reference numerals as in FIG.

Hereinafter, the configuration and operation of the activation circuit 10e of the present embodiment will be described focusing on the differences from the activation circuit of the first embodiment. As shown in FIG.
The input terminal of LY1 is connected to the node ND1, and the output terminal of LY1 is connected to the input terminal of the inverter INV2. The delay circuit DLY1 is configured by, for example, an even-numbered inverter connected in series or an RC circuit including a resistance element and a capacitor.

FIG. 6 shows two configuration examples of the delay circuit DLY1. As shown in FIG.
Y1-1 is composed of even-numbered inverters connected in series. In this case, the delay circuit DLY1-
One delay time Δt _d is determined by the sum of the delay times of the respective inverters. The delay circuit DLY shown in FIG.
1-2 includes a resistance element R and a capacitor C. As shown, the delay circuits DLY1-2 have substantially the same configuration as the integration circuit. By setting the resistance value of the resistance element R and the capacitance value of the capacitor C, the delay time of the delay circuit can be controlled.

Hereinafter, the operation of the starting circuit 10e of the present embodiment will be described. As described above, this embodiment is obtained by adding the delay circuit DLY1 to the first embodiment, and operates basically in the same manner as the first embodiment. Will be described.

First, in the standby state, the standby signal STB is at the high level, and the transistor NT1
Is turned on, and the node ND1 is held at a low level. At this time, the output terminal of the NAND gate NA1 is at a high level, and the transistor PT2 is turned off.

After the voltage supply circuit starts operating, the standby signal STB switches from the high level to the low level. In response, the transistor NT1 is turned off from on. While the node ND1 is held at the low level, the output signal thereof is also at the low level. The output terminal of the inverter INV1 switches from a low level to a high level according to the level change of the standby signal STB. At this time, N
Since both the input terminals of the AND gate NA1 are at the high level, the output terminal thereof is held at the low level. In response, the transistor PT2 is turned on, and the starting current I _ST is supplied to the output terminal OUT1. Output terminal OU
In response to the current I _ST supplied from T1, for example, the band gap reference voltage circuit starts operating, and the signal terminal SN1
Voltage starts to drop. When the voltage at the terminal drops to a value sufficient to turn on the pMOS transistor PT1, the transistor PT1 turns on, the node ND1 is charged by the current flowing through the transistor PT1, and its high level rises.

After the delay time Δt _d of the delay circuit DLY1 has elapsed, the output terminal of the delay circuit DLY1 also switches from the low level to the high level. The inverter I
The output signals of NV2 and NAND gate NA1 are sequentially switched. When the output signal of the NAND gate NA1 switches to a high level, the transistor PT2 turns off and the supply of the start-up current I _ST stops. After the supply of the starting current _IST is stopped, the bandgap reference voltage circuit starts to operate normally and supplies a desired constant voltage to the outside.

That is, the starting circuit 10e of the present embodiment supplies the starting current _IST to, for example, the band gap reference voltage circuit in response to the falling edge of the standby signal STB, and in response to the level change of the signal terminal SN1. To control the supply of the starting current. In the starter circuit 10a according to the first embodiment shown in FIG. 1, when the voltage level of the signal terminal SN1 drops and the transistor PT1 is turned on, the transistor PT2 is turned off accordingly, and the start-up current I
_ST was stopped. However, the starting circuit 10e of the present embodiment
Then, the voltage of the signal terminal SN1 drops and the transistor P
After T1 is turned on, the delay time Δt of the delay circuit DLY1
_{After e} has elapsed, the transistor PT2 is turned off, and the supply of the starting current I _ST is stopped.

In the bandgap reference voltage circuit constituting the voltage supply circuit, the voltage of the signal terminal SN1 drops to reach a level at which the pMOS transistor is turned on in accordance with operating conditions, manufacturing variations, and the like. After a period of time, the circuit reaches a normal operating state. Therefore, if the supply of the starting current _IST is stopped immediately after the voltage of the signal terminal SN1 drops and reaches a predetermined value, the bandgap reference voltage circuit may not be able to start normally. By using the starting circuit 10e of the present embodiment, the time from when the voltage of the signal terminal SN1 reaches a predetermined value to when the supply of the starting current I _ST is stopped is adjusted by adjusting the delay time Δt _d of the delay circuit DLY1. Since the control can be appropriately performed, the voltage supply circuit can be reliably started.

It should be noted that the logic portion in the starting circuit of each of the above-described embodiments, that is, the portion constituted by the inverter and the logic gate, for example, the NAND gate, is replaced by another logic circuit having a logic equivalent or a function equivalent. be able to. Needless to say, even when an equivalent circuit having the same logic or function is used, the activation circuit has a similar function.

Embodiment of Voltage Supply Circuit Using Startup Circuit FIG. 7 is a circuit diagram showing an embodiment of a voltage supply circuit configured using a starter circuit according to the present invention. As shown in the figure, the voltage supply circuit of the present example includes the starting circuit 10a and the bandgap reference voltage circuit 20 shown in the first embodiment. Output terminal O in starting circuit 10a
UT1 is connected to the node n of the bandgap reference voltage circuit 20.
2 and a signal terminal SN1 is connected to a node n3,
Output terminal of operational amplifier OPA1 and transistor T10
1, T102 and T103 are connected to the connection points with the gates.

The input terminal IN1 of the starting circuit 10a has a standby signal STB which switches to a high level in a standby state and to a low level after the voltage supply circuit starts to operate.
Is entered. The activation circuit 10a outputs the standby signal ST
In response to the fall of B, the starting current _IST is supplied from the output terminal OUT1 to the node n2 of the bandgap reference voltage circuit 20.
, The operating state of the bandgap reference voltage circuit 20 is confirmed based on the level of the node n3, and the supply timing of the starting current I _ST is controlled. Specifically, after the bandgap reference voltage circuit 20 is activated and the voltage of the node n3 decreases to reach a level sufficient to turn on the transistor PT1, the activation circuit 10a turns off the transistor PT2. The supply of the starting current _IST is stopped. For this reason, after the supply of the starting current I _ST is stopped, the bandgap reference voltage circuit 20 performs a normal operation, and based on the control of the feedback circuit formed by the operational amplifier OPA1, the power supply voltage and the constant voltage having no temperature dependency. Supply V _OUT .

First Embodiment of Bandgap Reference Voltage Circuit FIG. 8 is a circuit diagram showing a first embodiment of the bandgap reference voltage circuit 20. As illustrated, the bandgap reference voltage circuit 20 includes an operational amplifier circuit OPA1, a pMOS
The transistors T101, T102, T103, the resistance elements R101, R102, and the diode-connected n
It is composed of pn transistors B101, B102, B103.

Transistor T101, resistance element R101
And a diode-connected transistor B101
Supply voltage V _CC is connected in series between a supply line ground potential GND, the transistor B102, which is the transistor T102 and the diode connection is connected in series between the supply line and the ground potential GND of the power supply voltage V _CC, transistor T103 is
It is resistive element R102 and the diode-connected transistor B103 is the power supply voltage V _CC supply line and the ground potential G of
It is connected in series between ND. Transistor T101,
The gates of T102 and T103 are both operational amplifiers OPA
1 and outputs currents I1, I2 and I3 according to the output signal of the operational amplifier OPA1.

The non-inverting input terminal (+) of the operational amplifier OPA1 is connected to a node n1, which is a connection point between the transistor T101 and the resistance element R101, and the inverting input terminal (-) is connected to the transistor T102 and the transistor B102. It is connected to a node n2 consisting of a connection midpoint. An output terminal of the bandgap reference voltage circuit 20 is formed by a connection point between the transistor T103 and the resistor R102, and outputs a constant voltage _VOUT having no power supply voltage and temperature dependency from the output terminal during normal operation. . The output signal of the operational amplifier OPA1 is a transistor T
It is applied to the gates of 101, T102 and T103, respectively. Therefore, a feedback loop is formed by the operational amplifier OPA1, and the transistors T101, T102, and T1 are controlled by the feedback loop such that the voltages V _n1 and V _n2 of the nodes n1 and n2 become equal during normal operation.
03 currents I1, I2 and I3 are controlled.

Since the transistors T101, T102 and T103 have the same characteristics such as channel width, the currents I1, I2 and I2 flowing through these transistors during normal operation are controlled by controlling the feedback loop formed by the operational amplifier OPA1. I3 becomes equal. The emitter size of the transistor B101 is
It is formed ten times the emitter size of No. 02. Note that the emitter sizes of the transistors B102 and B103 are equal.

Hereinafter, the operation principle of the bandgap reference voltage circuit 20 will be described in detail using equations. The base-emitter voltage V _BE of the bipolar transistor is
It is calculated by the following equation.

[0069]

V _BE = V _T ln (I _C / I _S ) (1)

Here, V _T = kT / q, k is Boltzmann's constant, T is absolute temperature, and q is the charge of electrons. I
_C is the collector current of the transistor, the I _S is a constant current value proportional to the emitter size of the transistor.

In the bandgap reference voltage circuit 20, the voltages V _n1 and V _n1 of the nodes n1 and n2 during the normal operation.
_{Since n2} has a relationship of _Vn1 = _Vn2 , the following equation is obtained accordingly.

[0072]

## EQU2 ## I ₁ R ₁ + V _BE1 = V _BE2 (2)

[0073] Here, each V _BE1 and V _BE2 are bases of the transistors B101 and B 102 - with emitter voltage, R ₁ is the resistance value of the resistance element R1. By substituting equation (1) into equation (2), the following equation is obtained.

[0074]

## EQU3 ## I ₁ R ₁ + V _T ln (I ₁ / I _S1 ) = V _T ln (I ₂ / I _S2 ) (3)

In the equation (3), I ₁ and I ₂ are currents I ₁ and I ₂ flowing through the transistors T 101 and T 102, respectively.
2 is the current value. As described above, the transistor B1
The emitter size of 01 is formed ten times the emitter size of transistors B102 and B103.
That is, I _S1 = 10I _S2 . By substituting this into equation (3), the current I ₁ is obtained.

[0076]

I ₁ = V _T (ln10) / R ₁ (4)

[0077] Further, when the current value of the current I3 flowing through the transistor T103 and I _3, holds _{I 1 = I 2 = I 3} . Based on this, the bandgap reference voltage circuit 2
The output voltage V _{OUT of} 0 is obtained by the following equation.

[0078]

(Equation 5)

In the equation (5), V _BE3 is a base-emitter voltage of the transistor B103, and R ₂ is a resistance element R
102 is the resistance value.

[0080] formula (5), the base of the transistor - emitter voltage V _BE3 has a negative temperature characteristic, for example, a _{d (V BE3) / dT =} -2mV / K. Therefore, by setting the temperature characteristic of the second term on the right side of the equation (5) to 2 mV / K, the temperature dependency of the output voltage V _OUT can be completely eliminated. Since V _T = kT / q, the condition for eliminating the temperature dependency of the output voltage V _OUT can be obtained by the following equation.

[0081]

(Equation 6)

[0082] That is, the resistance element R ₁ and R ₂ of the resistor element R101 and R102 is time to satisfy the relation shown in Equation (6), independent of the output voltage V _OUT to a temperature change, always constant voltage value. When the condition shown in the equation (6) is satisfied, the temperature T becomes 3
At 00K (27 ° C.), the second term on the right side of the equation (5) is (R ₂ V _T (ln10) / R ₁ ) = 0.6 V. Further, assuming that the base-emitter voltage V _BE3 of the transistor B103 is 0.65 V, the output voltage V _OUT of the bandgap reference voltage circuit 20 becomes 1.25 V according to equation (5). That is, by selecting the resistance values R ₁ and R ₂ of the resistance elements R101 and R102 so as to satisfy the equation (6), the band gap reference voltage circuit 2 shown in FIG.
With 0, a constant voltage V _OUT that is completely independent of power supply voltage and temperature can be obtained.

FIG. 9 is a timing chart showing the operation at the time of starting the voltage supply circuit shown in FIG. Hereinafter, the operation of the voltage supply circuit of the present example will be described with reference to FIGS.

As shown in FIG. 9A, when the circuit operation is stopped (at the time of standby), the standby signal STB is held at a high level, for example, at the level of the power supply voltage V _CC. It is kept at a low level, for example, at the ground potential GND.

As shown in FIG. 13B, the node ND2, ie, the output terminal of the inverter INV1, switches from low level to high level slightly after the fall of the standby signal STB. Also, as shown in (e) of FIG.
The output signal of the gate NA1 switches to a low level, and in response to this, the starting circuit 10a starts supplying the starting current _IST to the bandgap reference voltage circuit 20. Accordingly, the voltage V _n2 at the node n2, as shown in FIG. (F) begins to rise. FIG (g), the output voltage of the operational amplifier OPA1 according to the voltage V _n1, V _n2 at the node n1 and n2, that is, the voltage of the node n3. As illustrated, the voltage at the node n3 decreases as the voltage Vn2 at the node _n2 increases. The voltage of the node n3 decreases, and the activation circuit 10a
When a voltage sufficient to turn on the pMOS transistor PT1 is reached, the transistor PT1 turns on,
In response, the node ND1 is charged and its voltage rises as shown in FIG.

As shown in FIG. 9D, when the voltage at the node ND1 exceeds the logic threshold voltage of the inverter INV2, the output of the inverter INV2 is inverted. In response to this, as shown in FIG.
1 output is also inverted, so the high level, the transistor PT2 is turned off, the supply of the starting current I _ST stops. After that, the band gap reference voltage circuit 20
Is controlled by a feedback loop consisting of PA1, the output voltage of the operational amplifier OPA1 is held constant, the voltage V _n1, V _n2 at the node n1 and n2 accordingly also is maintained substantially constant, the power supply from the band gap reference voltage circuit 20 A constant voltage V _{OUT that} is independent of voltage and temperature is supplied.

In the bandgap reference voltage circuit 20, the voltage V _n2 of the node _n2 is accidentally changed to the node n during startup.
If the voltage V _n1 is higher than 1, the activation circuit 10a hardly operates, and the bandgap reference voltage circuit 20 can start a normal operation state.

As described above, according to the voltage supply circuit of the present embodiment, a voltage supply circuit is formed by using the start-up circuit 10a and the bandgap reference voltage circuit 20. reliably activates the band gap reference voltage circuit 20 by supplying the starting current I _ST to the node n2 of the reference voltage circuit 20, after the start of the band gap reference voltage circuit 20 is operating, the output signal voltage of the operational amplifier OPA1 reduction First, the output signal voltage is applied to the pMO in the starting circuit 10a.
When the voltage reaches a voltage sufficient to turn on the S transistor PT1, the supply of the starting current I _ST is stopped, and the bandgap reference voltage circuit 20 operates under the control of the feedback loop formed by the operational amplifier OPA1, and Provides a constant voltage V _OUT without voltage dependency and temperature dependency.

Second Embodiment of Bandgap Reference Voltage Circuit FIG. 10 is a circuit diagram showing a second embodiment of the bandgap reference voltage circuit. As illustrated, the bandgap reference voltage circuit 20a of the present embodiment includes an operational amplifier circuit OPA1,
pMOS transistors T101 and T102, resistance element R
101, R100 and diode connected np
It comprises n transistors B101 and B102.

Transistor T101, resistance element R101
And a diode-connected transistor B101
It is serially connected between the power supply voltage V _CC supply line and a node n4 of the transistor B102, which is the transistor T102 and the diode connection are connected in series between the supply line and a node n4 of the power supply voltage V _CC. Transistor T1
The gates of 01 and T102 are connected to the output terminal of the operational amplifier OPA1, and output currents I1 and I2 according to the output signal of the operational amplifier OPA1, respectively.

The non-inverting input terminal (+) of the operational amplifier OPA1 is connected to a node n1 which is a connection point between the transistor T101 and the resistance element R101, and the inverting input terminal (-) is connected to the transistor T102 and the transistor B102. It is connected to a node n2 consisting of a connection midpoint. Further, an output terminal of the bandgap reference voltage circuit 20a is formed at the node n2, and a constant voltage V _{OUT having} no power supply voltage and temperature dependency is output from the output terminal during normal operation.
Is output.

The output signal of the operational amplifier OPA1 is applied to the gates of the transistors T101 and T102. Therefore, a feedback loop is formed by the operational amplifier OPA1, and the output currents of the transistors T101 and T102 are controlled so that the voltages V _n1 and V _n2 of the nodes n1 and n2 become equal during normal operation.
1 and I2 are controlled. Here, the transistor T10
Assuming that the channel widths of 1 and T102 are set equal, the output currents I1 and I2 of these transistors also become equal. The emitter size of the transistor B101 is
It is formed ten times the emitter size of the transistor B102.

Band gap reference voltage circuit 2 shown in FIG.
Compared with 0, the bandgap reference voltage circuit 20a of the present embodiment omits the transistor T103, the resistor R102 and the transistor B103, and
A reference voltage V _OUT is output from a connection point n2 between 02 and B102. Further, the connection point between the emitters of the transistors B101 and B102 is grounded via the resistance element R100. Hereinafter, the operation of the bandgap reference voltage circuit 20a of the present embodiment will be described with reference to FIG.

In the bandgap reference voltage circuit 20 of the first embodiment shown in FIG. 8, the voltages at the nodes n1 and n2 are input to the operational amplifier OPA1, respectively.
The output signal of A1 is applied to the gates of transistors T101, T102 and T103. By this feedback control,
The voltages V _n1 and V _{n2 of the} nodes n1 and n2 are controlled to be substantially equal. For example, the voltage V _n1 and V _n2 at the node n1 and n2 is controlled to about 0.7 V, the output voltage V _OUT is held at about 1.25V. Therefore, the transistors T101, T102 and T103 having the same control voltage applied to the gates
In this case, the source-drain voltages V _{ds of} the transistors T101 and T102 are equal to each other.
3 is different only in the source-drain voltage.

There is a slight difference ΔI in the current flowing through the transistors T101 (T102) and T103 due to the source-drain voltage difference. Due to the fluctuation of the power supply voltage V _CC , the transistors T101, T102 and T103
Is changed, the current difference ΔI
And the output voltage V _OUT slightly depends on the power supply voltage.

Hereinafter, the dependency of the output voltage V _{OUT on} the power supply voltage will be described in more detail by using mathematical expressions. The following relationship is established between the current _{Ids of the} MOS transistor and the source-drain voltage _Vds .

[0097]

(Equation 7)

In equation (7), V _gs is the gate-source voltage of the MOS transistor, V _th is the threshold voltage, k
Is a constant determined by the size of the transistor, etc.
Is a proportionality constant representing the dependence of I _ds on V _ds . In equation (7), the dependence of I _ds on V _ds is approximated by a linear expression, but strictly speaking, this approximate expression has second-order or higher-order terms.

If the currents of the transistors T101 and T103 are ideally equal, the output voltage V _OUT can be expressed by the following equation.

[0100]

(Equation 8)

In equation (8), V _BE3 is the base-emitter voltage of the transistor B103, I ₁ and I ₃ are the current values of the currents I1 and I3, respectively, and R ₂ is the resistance element R ₁₀₂
Represents the resistance value. In fact, since there is a difference ΔI between the currents I ₃ and I ₁ , the output voltage V _OUT is expressed by the following equation.

[0102]

(Equation 9)

Since the difference current ΔI has a power supply voltage dependency,
The output voltage V _OUT also has power supply voltage dependency. Further, FIG.
Since the output currents I1 and I2 of the transistors T101 and T102 flow directly to the ground potential GND in the bandgap reference voltage circuit 20 shown in FIG.

[0104] In the second embodiment of the band gap reference voltage circuit 20a shown in FIG. 10, the control of the operational amplifier OPA 1, the voltage V _n1 and V _n2 at the node n1 and n2 are held equal, (V _n1 −V _E = V _n2 −V _E ). Here, V _E is the voltage at the node n4. Thereby, the following equation is established.

[0105]

## _EQU10 ## I ₁ R ₁ + V _BE1 = V _BE2 (10)

Here, I ₁ is the current value of the current I1, R ₁ is the resistance value of the resistor R101, and V _BE1 and V _BE2 are the base-emitter voltages of the transistors B101 and B102, respectively. That is, the following equation is established.

[0107]

V _BE1 = V _{T In} (I _C1 / I _S1 ) (11)

[0108]

V _BE2 = V _T ln (I _C2 / I _S2 ) (12)

[0109] Equation (11), into equation (10) to (12), _{further, I c1 = I 1, I} C2 = it 2 and the emitter size of the transistor B101 is the transistor B102
, Ie, I _S1 = 10I _S2
By using the condition, the following expression is obtained.

[0110]

I ₁ = V _T (In10) / R ₁ (13)

Here, the resistance value of the resistance element R100 is set to R ₁₀
And The current I3 flowing through the resistance element R100 is the current I3
It is the sum of 1 and I2. That is, when the current value of the current I3 and _{I 3, I 3 = (I} 1 + I 2) = 2I 1 is obtained. Therefore, the output voltage V _OUT is obtained by the following equation.

[0112]

[Equation 14]

Transistor base-emitter voltage V
_BE2 has a negative temperature characteristic, for example, d ( _VBE2 ) /
dT = −2 mV / K. Therefore, by setting the temperature characteristic of the second term on the right side of Equation (14) to 2 mV / K, the temperature dependency of the output voltage V _OUT can be completely eliminated. Since V _T = kT / q, the output voltage V
_The condition for eliminating the temperature dependency of _OUT is obtained by the following equation.

[0114]

(Equation 15)

The resistance elements R100 and R101 are given by the following equation (15).
When the condition shown in (1) is satisfied, the output voltage V _OUT always has a constant voltage value without depending on the temperature change. Note that the expression (1)
5), when the temperature T is 300 K (27 ° C.), the second term on the right side of the equation (14) becomes (2V _T (ln1
_{0) R 10 / R 1)} = a 0.6V. Further, the base-emitter voltage V _BE3 of the transistor B103 is set to 0.6.
When the voltage is 5 V, the output voltage V _OUT of the bandgap reference voltage circuit 20 becomes 1.25 V according to the equation (14).

As described above, in the bandgap reference voltage circuit 20a of this embodiment, a constant output voltage V _OUT can be obtained without depending on the temperature change. Further, when operating normally, feedback control of the operational amplifier circuit OPA1 is controlled so that the drain potentials of the transistors T101 and T102 become equal. That is, since the drain-source voltages V _{ds of} the transistors T101 and T102 are controlled to be equal, the currents I1 and I
2 is always set equal. Therefore, the output voltage V _OUT
Of the power supply voltage can be suppressed.

Third Embodiment of Bandgap Reference Voltage Circuit FIG. 11 is a circuit diagram showing a third embodiment of the bandgap reference voltage circuit. As shown in the figure, the bandgap reference voltage circuit 20b of this embodiment includes a transistor group 22, 24 composed of a plurality of pMOS transistors, an operational amplifier OPA1, resistance elements R101, R100, and diode-connected npn transistors B101, B10.
2.

As shown, the bandgap reference voltage circuit 20b of this embodiment is different from the bandgap reference voltage circuit 20a shown in FIG.
1, a transistor group 2 composed of a plurality of MOS transistors connected in parallel instead of T102
2 and 24 are provided. The transistor group 22 includes
For example, it is composed of m (m is a natural number) pMOS transistors. These transistors are connected in parallel between the supply line of power supply voltage V _CC and node n1. Almost similarly, the transistor group 24 includes, for example, n
(N is a natural number) pMOS transistors. These transistors are connected in parallel between the supply line of power supply voltage V _CC and node n2.

The gates of the transistors constituting the transistor groups 22 and 24 are connected to the output terminal of the operational amplifier OPA1, that is, the node n3. The other parts of the bandgap reference voltage circuit 20b are substantially the same as the bandgap reference voltage circuit 20a shown in FIG. For example, the non-inverting input terminal and the inverting input terminal of the operational amplifier OPA1 are connected to nodes n1 and n2, respectively. A resistance element R10 is connected between the nodes n1 and n4.
1, a transistor B101 diode-connected is connected in series, and a transistor B102 diode-connected is connected between nodes n2 and n4. Further, the node n4 is grounded via the resistance element R100.

The sizes of the transistors constituting the transistor groups 22 and 24, for example, the channel widths are all set the same. Further, the emitter sizes of the transistors B101 and B102 are set in the same manner.

In the bandgap reference voltage circuit 20b configured as described above, the transistor group 22
The output current of each transistor group can be controlled by appropriately setting the number of transistors of the transistor group. For example, here, the number of transistors in the transistor group 22 is set to 1
And the number of transistors in the transistor group 24 is ten. That is, if m = 1 and n = 10, the current values I ₁ and I 2 of the output currents I ₁ and I 2 of the transistor groups 22 and 24 are
₂ satisfies the relationship 10I ₁ = I ₂ . Based on this, the current values I ₁ and I ₂ are obtained as follows.

[0122] the control of the operational amplifier OPA 1, the voltage V _n1 and V _n2 at the node n1 and n2 are held equal. That is, (V _n1 −V _E = V _n2 −V _E ) holds. Therefore, the above-described equations (10) to (12) also hold in the bandgap reference voltage circuit 20b of the present embodiment.
However, in this embodiment, the transistors B101 and B10
Since the emitter sizes of the two are equal, I _S1 = I _S2 . on the other hand,
Since I _c1 = I ₁ and I _C2 = I ₂ , I _C2 = 10I _c1 . Based on these conditions, the currents I ₁ and I ₂ are respectively obtained by the following equations.

[0123]

## EQU16 ## I ₁ = V _T (In10) / R ₁ (16)

[0124]

I ₂ = 10V _T (ln10) / R ₁ (17)

That is, I ₂ = 10I ₁ . For this reason,
The output voltage V _OUT is obtained by the following equation.

[0126]

(Equation 18)

In equation (18), V _BE2 has a negative temperature characteristic, for example, a temperature characteristic of −2 mV / K. On the other hand, V
_{Since T} has a positive temperature characteristic, the resistance elements R100 and R1
By appropriately setting the resistance values R ₁₀ and R ₁ of 01, the temperature dependency of the output voltage V _OUT can be canceled. Further, as can be seen from equation (18), the output voltage V _OUT does not depend on the power supply voltage.

As described above, the bandgap reference voltage circuit 20b of this embodiment can provide a stable voltage V _OUT without temperature dependency and power supply voltage dependency. Furthermore, by appropriately setting the number of transistors in the transistor groups 22 and 24, the ratio between the current values of the currents I1 and I2 can be set arbitrarily.
Therefore, for example, by setting the number n of transistors in the transistor group 24 to be large, the output current I2 of the transistor group 24 can be controlled to be large. As shown in FIG. 11, by increasing the current I2, the output current I _OUT to be supplied to the load circuit is increased, for example, when driving a capacitive load as shown, the charging current to the load capacitance C _L And the load rising characteristics can be improved. Further, as shown in Expression (18), the output voltage V _OUT
Is added to the second term on the right side of the equation (11).
The resistance value R ₁₀ of the 100 can be set small, can be reduced in layout area.

As described above, in the bandgap reference voltage circuit 20b of the present embodiment, the number of transistors in the transistor groups 22 and 24 composed of a large number of transistors having the same characteristics such as channel size are appropriately set. Thus, the output currents I1 and I2 from the respective transistor groups can be controlled.
Here, it goes without saying that the same effect can be achieved by appropriately setting the channel size of each transistor constituting the transistor group.

By setting the channel sizes of the transistors T101 and T102 of the bandgap reference voltage circuit 20a of the second embodiment shown in FIG. 10, almost the same effects as in the present embodiment using the transistor groups 22 and 24 are obtained. Is obtained. Further, in the above description, the emitter sizes of the diode-connected transistors B101 and B102 are assumed to be equal. However, the emitter sizes of these transistors are set differently. It can be set to k times the emitter size. In this case, ln (10) of the second term on the right side of the output voltage V _OUT shown in Expression (18) is ln (10k). As described above, by appropriately setting the emitter sizes of the transistors B101 and B102, the expression (18) is obtained.
Can change the coefficient of the second term of the right side of the output voltage V _OUT shown in, the resistance value R ₁₀ of which the resistance element R100
May be reduced, and the layout area may be reduced.

Fourth Embodiment of Bandgap Reference Voltage Circuit FIG. 12 is a circuit diagram showing a fourth embodiment of the bandgap reference voltage circuit. As shown in the figure, the bandgap reference voltage circuit 20c of the present embodiment includes transistor groups 22 and 24 each including a plurality of pMOS transistors, an operational amplifier circuit OPA1, resistance elements R101 and R100, and diode-connected npn transistors B101 and B101.
102.

The bandgap reference voltage circuit 2 of this embodiment
0c is the bandgap reference voltage circuit 2 of the third embodiment.
This is almost the same as 0b except that the resistor R101 and the diode-connected transistor B101 are replaced with each other. That is, in the bandgap reference voltage circuit 20b of the third embodiment, the resistance element R101
Has one terminal connected to the node n1, and the other terminal connected to the collector and the base of the transistor B101. On the other hand, in the bandgap reference voltage circuit 20c of the present embodiment, the connection point between the base and the collector of the transistor B101 is connected to the node n1, and the resistor R101 is connected between the emitter of the transistor B101 and the node n4. Have been.

The band gap reference voltage circuit 2 of this embodiment
0c is the bandgap reference voltage circuit 2 of the third embodiment.
This embodiment is almost the same as the third embodiment except that the connection relationship described above is different from that of the third embodiment. Here, assuming that the number of transistors in the transistor groups 22 and 24 is m and n, respectively, a more general formula for calculating the output voltage V _OUT is obtained.

The transistors forming the transistor groups 22 and 24 have the same size, and
It is assumed that the sizes of 101 and B102 are set similarly. That is, the output current I of the transistor groups 22 and 24
1 and the current value I ₁ and I ₂ of the I2 is the following relationship is established.

[0135]

I ₁ / m = I ₂ / n nI ₁ = mI ₂ (19)

That is, I ₂ = (n / m) I ₁ . In the transistors B101 and B102, I _c1 = I ₁ and I _C2 = I
₂ Further, since I _S1 = I _S2 , the currents I ₁ and I ₂ are obtained by the following equations according to the equations (10) to (12).

[0137]

I ₁ = V _T (ln (n / m)) / R ₁ (20)

[0138]

(Equation 21)

Since the current I3 flowing through the resistance element R100 is an addition current of the currents I1 and I2, I ₃ = I ₁ + I
A _{2 = (m + n) I} 1 / m. Thus, the output voltage V _OUT is given by the following equation.

[0140]

V _OUT = V _BE2 + I ₃ R ₁₀ = V _BE2 + (m + n) V _T (ln (n / m)) R ₁₀ / (R ₁ m) (22)

For example, in the bandgap reference voltage circuit 20b of the third embodiment, m = 1 and n = 10
, The output voltage V _OUT is V _OUT = V _BE2 + 11V _T
ln (10) R ₁₀ / R ₁ .

The resistance value R of the resistance elements R100 and R101
By setting the ₁₀ and R ₁ as appropriate, the output voltage V _OUT
Temperature dependence can be canceled. Equation (22)
As can be seen from the above, the output voltage V _OUT does not depend on the power supply voltage. Further, in the equation (22), the coefficient (m + n) / m is added to the second term on the right side of the output voltage V _OUT.
The resistance value R ₁₀ of the 100 can be set small, can be reduced in layout area.

In the above description, it is assumed that the emitter sizes of the diode-connected transistors B101 and B102 are equal.
The emitter size ratio of 102 can also be set appropriately. For example, when the emitter size of the transistor B101 is set to k times the emitter size of the transistor B102, ln (n / n /
m) becomes ln (nk / m). This gives R ₁₀ /
Coefficient attached to R ₁ is changed. That is, the transistor B101
If by appropriately setting the emitter size ratio of B 102, it is possible to reduce the resistance value R ₁₀ of the resistor element R100, the effect can be obtained that can realize a reduction in a layout area.

Fifth Embodiment of Bandgap Reference Voltage Circuit FIG. 13 is a circuit diagram showing a fifth embodiment of the bandgap reference voltage circuit 20. As shown, the bandgap reference voltage circuit 20d of the present embodiment includes a plurality of p
Transistor groups 22 and 24 composed of MOS transistors
And 26, an operational amplifier OPA1, a resistor R101,
R102, R100 and diode-connected n
It is composed of pn transistors B101, B102, B103.

As shown, in the bandgap reference voltage circuit 20d of the present embodiment, the transistor group 22,
24, an operational amplifier circuit OPA1, a transistor B101,
The portion constituted by 102 and the resistance elements R101 and R100 has substantially the same configuration as the bandgap reference voltage circuit 20b of the third embodiment shown in FIG. That is, the present embodiment can be regarded as a configuration in which the transistor group 26, the transistor B103, and the resistor R102 are added to the bandgap reference voltage circuit 20b of the third embodiment.

A plurality of transistor groups 26, for example, j
(J is a natural number) pMOS transistors. These transistors are connected in parallel between the supply line of the power supply voltage V _CC and the node n5, and each gate is connected to the output terminal of the operational amplifier OPA1, that is, the node n3. Node n5 and ground potential GN
D and a diode-connected transistor B
103 and the resistance element R102 are connected in series. Note that the connection order of the transistor B103 and the resistor R102 is not particularly limited.

Here, the transistor groups 22, 24 and 2
6 have the same channel size, and are diode-connected transistors B1.
Assume that the emitter sizes of 01, B102 and B103 are also equal. Assuming that the numbers of transistors of the transistor groups 22 and 24 are m and n, respectively, as in the band gap reference voltage circuit 20c of the fourth embodiment, the equation (20)
And (21) hold.

[0148] Further, in this embodiment, the current value of the output current I4 of the transistor group 26 and I _4, the resistance element R
The resistance value of 102 is R ₂ . As described above, since the number of transistors constituting the transistor group 26 is j, I ₄ / I ₁ = j / m holds. Based on this condition, the output voltage V _OUT is given by the following equation.

[0149]

Equation 23] _{V OUT = V BE3 + I 4} R 2 = V BE3 + jV T (ln (n / m)) R 2 / (R 1 m) ... (23)

[0150] formula (23), V _BE3 is negative temperature characteristic, for example, has a temperature characteristic of -2 mV / K. On the other hand, V
_{Since T} has a positive temperature characteristic, the resistance elements R102 and R1
By appropriately setting the resistance values R ₂ and R ₁ of 01, the temperature dependency of the output voltage V _OUT can be canceled. Further, as can be seen from equation (23), the output voltage V _OUT does not depend on the power supply voltage.

As described above, the bandgap reference voltage circuit 20d of the present embodiment can provide a stable voltage V _OUT without dependency on temperature and power supply voltage. Since the partial circuit for supplying the output voltage V _OUT is provided independently of the feedback loop for voltage control, no influence is exerted on the feedback loop even if any load is applied. Therefore, a stable output voltage V _OUT can be supplied without being affected by the characteristics of the load circuit.

In each of the embodiments described above, the voltage supply circuit constituted by the starting circuit of the present invention and the bandgap reference voltage circuit has been described as an example. It goes without saying that the present invention can be applied not only to the circuit but also to other functional circuits. For example, in a PLL circuit, a voltage controlled oscillation circuit (V
The startup circuit of the present invention can also be applied to a case where a startup current is supplied to the VCO and the like to start the VCO.

[0153]

As described above, according to the starting circuit of the present invention and the voltage supply circuit configured using the same,
The circuit configuration is simple, the design is easy and the application range is wide,
A voltage supply circuit that is resistant to variations in the manufacturing process and that is independent of temperature and power supply voltage can be realized. Further, the starting circuit of the present invention generates a constant voltage, for example, confirms the operating state of the bandgap reference voltage circuit, and controls the supply timing of the starting current in accordance with the state. It is possible to supply only the starting current necessary for starting the circuit according to the operating conditions of the circuit, and to set the starting time of the circuit appropriately, thereby reducing the power consumption of the starting circuit to the minimum necessary. is there. Further, in the bandgap reference voltage circuit constituting the voltage supply circuit of the present invention, a stable voltage having no temperature dependency and no power supply voltage dependency can be supplied, low voltage operation can be realized, and low power consumption can be realized. . Also, by appropriately setting the number of transistors in the transistor group constituting the bandgap reference voltage circuit and the emitter size of the bipolar transistor connected in diode, the resistance value of the resistance element can be freely changed and the layout area can be reduced. In addition, the output current value can be set arbitrarily, and the output rising characteristics can be improved. Furthermore, by providing the voltage output circuit independently from the feedback control loop, it is possible to avoid the influence of the load characteristics on the feedback loop,
There is an advantage that the stability of the operation of the voltage supply circuit can be improved without being affected by the load fluctuation.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a starting circuit according to the present invention.

FIG. 2 is a circuit diagram illustrating a starter circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of a start-up circuit according to the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of a starting circuit according to the present invention.

FIG. 5 is a circuit diagram illustrating a starting circuit according to a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating a configuration example of a delay circuit.

FIG. 7 is a circuit diagram of a voltage supply circuit including a start circuit and a band gap reference voltage circuit.

FIG. 8 is a circuit diagram showing a first embodiment of the bandgap reference voltage circuit.

9 is a timing chart of the voltage supply circuit shown in FIG.

FIG. 10 is a circuit diagram showing a second embodiment of the bandgap reference voltage circuit.

FIG. 11 is a circuit diagram showing a third embodiment of the bandgap reference voltage circuit.

FIG. 12 is a circuit diagram showing a fourth embodiment of the bandgap reference voltage circuit.

FIG. 13 is a circuit diagram showing a fifth embodiment of the bandgap reference voltage circuit.

FIG. 14 is a circuit diagram illustrating an example of a conventional voltage supply circuit.

[Explanation of symbols]

10, 10a, 10b, 10c, 10d, 10e start circuit, 20, 20a, 20b, 20c, 20d band gap reference voltage circuit, 22, 24, 26 ... transistor group, PT1, PT2, PT3, T101, T102,
T103: pMOS transistor, NT1, NT2, N
T3: nMOS transistor, B101, B102, B
103 npn transistor, NA1 NAND gate, INV1, INV2, INV3, INV4 inverter, DLY1 delay circuit, OPA1 operational amplifier, R
100, R101, R102 ... resistance element, V _CC ... power supply voltage, GND ... ground potential.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5H410 BB04 CC02 DD02 EA11 EB37 HH00 KK01 5H420 BB12 CC02 DD02 EA14 EA39 EB37 HJ01 KK01 NA23 NA27 NB02 NB12 NB22 NB24 NB25 NE02

Claims (24)

[Claims] 1. A start-up circuit for supplying a start-up current to a predetermined function circuit and starting the function circuit, the start-up current supply means receiving a start-up signal and supplying the start-up current to the function circuit. A start control unit for stopping the supply of the start current to the start current supply unit when a voltage of a predetermined operation node of the functional circuit reaches a predetermined reference value. 2. The system according to claim 1, wherein said activation control means transmits said activation signal to a first terminal.
Receiving the voltage of the operation node of the functional circuit as a second input signal as the input signal of
A bistable logic circuit controlled to a first state and a second state in response to an input signal, and a logic gate for outputting a signal corresponding to a logical operation result of the start signal and an output signal of the bistable logic circuit The starting circuit according to claim 1, comprising: 3. The bistable logic circuit has first and second transistors connected in series between a supply terminal for a predetermined voltage and a reference potential line, and a gate of the first transistor. 3. The activation circuit according to claim 2, wherein a voltage of said operation node of said functional circuit is applied to said first circuit, and said activation signal is applied to a gate of said second transistor. 4. The starting current supply means has a switching circuit connected between a power supply voltage supply line and a starting current input terminal of the functional circuit, and turned on / off according to an output signal of the logic gate. Item 2. The starting circuit according to Item 2. 5. The starting circuit according to claim 4, wherein said switching circuit comprises a transistor having a control terminal to which an output signal of said logic gate is applied. 6. The starting circuit according to claim 2, further comprising a delay circuit for inputting a delay signal obtained by delaying an output signal of said bistable logic circuit by a predetermined time to said logic gate. 7. The starting circuit according to claim 6, wherein said delay circuit comprises an even number of inverters connected in series. 8. The start-up circuit according to claim 6, wherein said delay circuit has a resistor connected between an input terminal and an output terminal, and a capacitor connected between said output terminal and a reference potential line. circuit. 9. The function circuit, comprising: a first current supply transistor connected between a power supply voltage supply line and a first node; and a series connection between the first node and a reference potential line. A first diode connected in a forward direction toward the reference potential line, and a second current supply transistor connected between the power supply voltage supply line and a second node. And connected between the second node and the reference potential line;
A second diode that is forwardly directed toward the reference potential line, a third current supply transistor connected between the power supply voltage supply line and a third node, A second resistance element connected in series between the reference potential line and a third diode that is forwardly directed toward the reference potential line; a first input terminal connected to the first node; A second input terminal is connected to the second node, and a voltage signal corresponding to a difference between signals input to the first and second input terminals is supplied to the first, second, and third current supply transistors. And an amplifying circuit for applying the starting current from the starting circuit to the second node at the time of starting, and using the output voltage of the amplifying circuit as a voltage of the operating node as the starting control means. Claim 1 which is input to Start-up circuit of. 10. The starting circuit according to claim 9, wherein said current supply transistor comprises a field effect transistor. 11. The function circuit according to claim 1, further comprising a power supply voltage supply line and a first power supply line.
A first current supply transistor connected between the first node and the third node; a first resistance element connected in series between the first node and the third node; A first diode connected in a forward direction, a second current supply transistor connected between the power supply voltage supply line and a second node, and a second diode connected to the second node and the third node. A second diode connected between the third node and a reference potential line; a second diode connected in a forward direction toward the third node; An input terminal is connected to the first node, a second input terminal is connected to the second node, and a voltage signal corresponding to a difference between signals input to the first and second input terminals is output from the input terminal. An additional voltage applied to the control terminals of the first and second current supply transistors. A start-up current supplied from the start-up circuit to the second node at the time of start-up, and an output voltage of the amplifier circuit is input to the start-up control means as a voltage of the operation node. Starter circuit as described. 12. The function circuit according to claim 1, further comprising a power supply voltage supply line and a first power supply line.
A first transistor group consisting of m (m is a natural number) current supply transistors connected in parallel between the first and third nodes; and a first transistor group connected in series between the first and third nodes. A first resistance element, a first diode directed forward toward the third node, and n (n is a natural number) connected in parallel between the power supply voltage supply line and the second node. A) a second transistor group consisting of a plurality of current supply transistors; and a second diode connected between the second node and the third node and directed forward toward the third node. A second resistance element connected between the third node and a reference potential line; a first input terminal connected to the first node; and a second input terminal connected to the second input terminal. Connected to the first and second input terminals And an amplifier circuit for applying a voltage signal corresponding to a difference between input signals to control terminals of the respective transistors of the first and second transistor groups. 2. The starting circuit according to claim 1, wherein said starting current is supplied, and an output voltage of said amplifier circuit is inputted to said starting control means as a voltage of said operating node. 13. The function circuit according to claim 1, further comprising: a power supply voltage supply line;
A first transistor group consisting of m (m is a natural number) current supply transistors connected in parallel between the first and third nodes; and a first transistor group connected in series between the first and third nodes. A first resistance element, a first diode directed forward toward the third node, and n (n is a natural number) connected in parallel between the power supply voltage supply line and the second node. A) a second transistor group consisting of a plurality of current supply transistors; and a second diode connected between the second node and the third node and directed forward toward the third node. A second resistance element connected between the third node and the reference potential line; and j (j is a natural number) connected in parallel between the power supply voltage supply line and the fourth node. ) Current supply transistors A group of transistors; a third resistor element connected in series between the fourth node and the reference potential line; a third diode in a forward direction toward the reference potential line; A terminal is connected to the first node, a second input terminal is connected to the second node, and a voltage signal corresponding to a difference between signals input to the first and second input terminals is output to the second node. An amplifier circuit for applying to the control terminal of each transistor of the first, second and third transistor groups, wherein the starting current from the starting circuit is supplied to the second node at the time of starting; 2. The starting circuit according to claim 1, wherein an output voltage is inputted to said starting control means as a voltage of said operating node. 14. A starting current supply means for outputting a starting current in response to a starting signal; a voltage generating circuit for starting in response to the starting current and outputting a stable voltage during normal operation; A voltage supply circuit having activation control means for stopping supply of the activation current to the activation current supply means when a voltage of a predetermined operation node reaches a predetermined reference value. 15. A first current supply transistor connected between a power supply voltage supply line and a first node, and a first current supply transistor connected in series between the first node and a reference potential line. A first diode in a forward direction toward the reference potential line; a second current supply transistor connected between the power supply voltage supply line and a second node; Is connected between the node and the reference potential line,
A second diode that is forwardly directed toward the reference potential line, a third current supply transistor connected between the power supply voltage supply line and a third node, A second resistance element connected in series between the reference potential line and a third diode that is forwardly directed toward the reference potential line; a first input terminal connected to the first node; A second input terminal is connected to the second node, and a voltage signal corresponding to a difference between signals input to the first and second input terminals is supplied to the first, second, and third current supply transistors. An amplifying circuit applied to the control terminal of the above, starting current supply means for supplying a starting current to the second node according to a starting signal at the time of starting, and when an output voltage of the amplifier circuit reaches a predetermined reference value
A voltage supply circuit comprising: a start control unit for stopping supply of the start current. 16. The start control means receives the start signal as a first input signal and the output signal of the amplifier circuit as a second input signal, and responds to the first and second input signals. 16. A bistable logic circuit controlled to a first state and a second state, respectively, and a logic gate for outputting a signal according to a result of a logical operation of the start signal and an output signal of the bistable logic circuit. Voltage supply circuit as described. 17. The bistable logic circuit has first and second transistors connected in series between a power supply voltage supply line and a reference potential line, and the first transistor has a gate connected to the first transistor. 17. The voltage supply circuit according to claim 16, wherein an output voltage of the amplifier circuit is applied, and the start signal is applied to a gate of the second transistor. 18. The starting current supply means includes a switching circuit connected between a supply terminal for supplying a predetermined voltage and the second node, and turned on / off according to an output signal of the logic gate. 16. The voltage supply circuit according to 15. 19. The voltage supply circuit according to claim 18, wherein said switching circuit comprises a transistor having a control terminal to which an output signal of said logic gate is applied. 20. The voltage supply circuit according to claim 15, wherein said current supply transistor comprises a field effect transistor. 21. The voltage supply circuit according to claim 16, further comprising a delay circuit for inputting a delay signal obtained by delaying an output signal of said bistable logic circuit by a predetermined time to said logic gate. 22. A first current supply transistor connected between a power supply voltage supply line and a first node, and a first current supply transistor connected in series between the first node and a third node. A first diode connected in a forward direction toward the third node; a second current supply transistor connected between the power supply voltage supply line and a second node; A second diode connected between a second node and the third node and directed forward toward the third node; and a second diode connected between the third node and a reference potential line. A second resistor element, a first input terminal is connected to the first node, a second input terminal is connected to the second node, and an input is applied to the first and second input terminals. Supply a voltage signal corresponding to the difference between the first and second currents. An amplifying circuit applied to a control terminal of a transistor; a starting current supply means for supplying a starting current to the second node in response to a starting signal at the time of starting; ,
A voltage supply circuit comprising: a start control unit for stopping supply of the start current. 23. A first transistor group consisting of m (m is a natural number) current supply transistors connected in parallel between a power supply voltage supply line and a first node; A first resistive element connected in series between the third node and a first diode, a first diode extending in a forward direction toward the third node, and a power supply voltage supply line and a second node. A second transistor group consisting of n (n is a natural number) current supply transistors connected in parallel to the second node and the third node connected between the second node and the third node. A second diode connected in the forward direction to the second node, a second resistor connected between the third node and a reference potential line, and a first input terminal connected to the first node. And the second input terminal is connected to the second node. An amplifier circuit for applying a voltage signal corresponding to a difference between signals input to the first and second input terminals to control terminals of the respective transistors of the first and second transistor groups; Starting current supply means for supplying a starting current to the second node according to the following: when the output voltage of the amplifier circuit reaches a predetermined reference value,
A voltage supply circuit comprising: a start control unit for stopping supply of the start current. 24. A first transistor group comprising m (m is a natural number) current supply transistors connected in parallel between a power supply voltage supply line and a first node; A first resistive element connected in series between the third node and a first diode, a first diode extending in a forward direction toward the third node, and a power supply voltage supply line and a second node. A second transistor group consisting of n (n is a natural number) current supply transistors connected in parallel to the second node and the third node connected between the second node and the third node. A second diode in a forward direction toward the second node, a second resistance element connected between the third node and a reference potential line, and a second diode between the power supply voltage supply line and a fourth node. J (j is a natural number) connected in parallel to A third transistor group composed of a current supply transistor; a third resistor element connected in series between the fourth node and the reference potential line; and a third transistor in a forward direction toward the reference potential line. And a first input terminal connected to the first node, a second input terminal connected to the second node, and a difference between signals input to the first and second input terminals. Amplifying circuit for applying a voltage signal according to the above to the control terminals of the respective transistors of the first, second and third transistor groups, and starting to supply a starting current to the second node according to a starting signal at the time of starting Current supply means, when the output voltage of the amplifier circuit reaches a predetermined reference value,
A voltage supply circuit comprising: a start control unit for stopping supply of the start current.