556070 A7 五、發明說明（/ 本發明係關於-種令參考電流源與輸出電流間可為任 何放大比例’且多組電源流同時工作時係各個獨立而不致 相互干擾之定電流電路。 第一圖為習知的Bip〇lar冑晶體電流鏡電路，圖中又 可區分為卿電晶體電流鏡電路（如第一圖A所示）及 P二電晶體電流鏡電路（如第一圖B所示），其運作原理 疋完全相同的。假設電流鏡兩側的NpN(或是pNp)電晶體 元，大小幾何完全相同的話，由第一圖可看出兩側的NpN( 或是PNP)元件基極（Base)及射極（Emitter)是接在一起的 ，因此v·，則輸入電流h將幾乎等於輸出電流η， 其差異在於輸入電流h須額外提供基極電流Ιβ給電流鏡兩 側的電晶體，其相互關係為IlX万/(石+ 2)，其中点 為Bipolar元件的順向電流增益，其定義為万=ic/iB， 線 其典型值約在數十至數百之間’此值與元件類型及幾何形 狀有關，且與製程參數及工作溫度有關。因此^與h的相 互關係會隨著/3值而產生變化，万值越低，Ιβ就越大，因 此I!與h的差異就越大。此電路由一組參考電流輸入（電 流鏡左側）來產生一組輸出電流輸出（電流鏡右側），對於 電源電流的消耗相當大’因此並不適用於多組且大電流輸 出的應用。 若第一圖電流鏡電路左右兩側的比值不是丨：丨的關 係，而是1: N的關係的話，則輸出端電流將有放大的效 果’輸出端電流12与N X 11，其精確的關係為12= I丨χ 3 / (ys+ 1+ Ν)。因此當Ν接近於点值時，電流放大的倍數將 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐 556070 A7 ________ ___B7__ 五、發明說明（> ) 會急驟的縮小，這項因素限制了該電流鏡電路電流放大的 比例，另外由於Bipolar電晶體元件無法做精確的分割， 所以僅能提供整數倍率的放大，例如··丨：5，2: 3，1〇: 7等等，這也限制了此類電流鏡電路電流可放大的比例。 第二圖為習知的CMOS電晶體電流鏡電路，圖中又可 區分為NM0S電晶體電流鏡電路（如第二圖a所示）及 PM0S電晶體電流鏡電路（如第二圖B所示），其運作原理 與Bipolar電晶體電流鏡電路是完全相同的。當電流鏡兩 側的NM0S(或是PM0S)電晶體元件大小幾何（L，W)完全相 同時，由於閘極（Gate)電壓及源極（Source)完全相同，Vgsi =Vgm，且閘極無須任何輸入驅動電流，所以輸入電流h 將等於輸出電流h，唯一的差異在於輸出端電流斜率並非 為零，而是隨著輸出電壓Vds2做緩慢的變化，因此當輸出 電壓Vds2不等於閘極電壓VGS2時，輸入電流丨1與輸出電流 h將有些微的差距。 由於CMOS元件幾何形狀（L，W)為可調整的，因此 CMOS電晶體電流鏡電路可輕易的做成非整數比例的電流放 大電流鏡電路，而且由於無須擔心閘極電流對於輸入電流 的影響，也可輕易完成大倍數電流的放大，但是由於CM〇s 電晶體元件天生的低電流驅動能力、低轉導值 (Transconductance，gm)、耐電壓及ESD等問題，因此在 而要較大輸出電流及高耐電壓的場合，以CM〇s電晶體做 成的電流鏡電路常常會比Bip〇lar電晶體做成的電流鏡電 路的面積為大，因而增加了電路所須的成本。 _____ 4 本纸张尺度適用中關家標準（CNS)A4規格（21Q X 297公爱) " ---- ^----------------訂---------線"^^丨 (請先閱讀背面之注意事項再填寫本頁) 556070 A7 B7 五、發明說明（多） 第二圖為習知的具增益的Bipolar電晶體電流鏡電路 ’圖中同樣又區分為NPN電晶體及PNP電晶體兩種類型。 此類電流鏡電路加上一額外的增益電晶體來提供電流鏡輸 入輪出端所須的基極電流，輸入電流h與輸出電流l2的相 互關係變為ΙιΧ(/52+ /5 )/(冷2+ /3+ 2)，不論分子 分母皆變成/5的平方關係，因此常數項2就顯得微不足道 ’此時輸入電流I i與輸出電流12的比例會變得相當準確， 不易叉到冷變化的影響，電流放大比例也不限定於1 : 1 的關係’ 1: N的關係可輕易的達到，只要n遠小於冷2即 可（因為 l2= IlX(/52+ 召）/(/52+ /3+ N+ 1))。若將額外 增加的增益電晶體換成一個達靈頓對（Dari ington Pair) 的活，則輸入電流I!與輸出電流I?的比例會變得更為準確 ，且放大比例N也可更大（只要遠小於万3即可）。 然而，第三圖的電路運用在一些負載電路上沒有問題 ’但是在某些應用上則會有意想不到的問題發生，例如開 集極（Open—Collector)的應用，當輸出端有接負載且工 作於順向活性區（Forward Active Region)時其工作仍然 正常，但當輸出端浮接或是工作於飽和區（Saturati〇n Region)時，此時會有一極大的電流由電源經增益用電晶 體流向輸出端電晶體，造成額外的電源耗電流及發熱，且 基極互相連接的所有電晶體都會受到影響而大幅降低電流 ，而不論各個電晶體是否有接負載及其原先的工作區域為 ^ 何。 第四圖為習知以M0S作為增益電晶體的Bip〇lar電晶 1本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）556070 A7 V. Description of the invention (/ This invention is about-a kind of order that the reference current source and the output current can be any amplification ratio ', and when multiple sets of power supply currents work at the same time, they are independent constant current circuits without mutual interference. First The picture shows a conventional Biplarar crystal current mirror circuit, which can be divided into a crystal transistor current mirror circuit (as shown in the first figure A) and a P two transistor current mirror circuit (as shown in the first figure B). (Shown), its operating principle is exactly the same. Assuming that the NpN (or pNp) transistor elements on both sides of the current mirror are of the same size and geometry, the NpN (or PNP) elements on both sides can be seen from the first figure. The Base and Emitter are connected together, so v ·, the input current h will be almost equal to the output current η. The difference is that the input current h must additionally provide the base current Ιβ to both sides of the current mirror Transistor, its mutual relationship is IlX million / (stone + 2), where the point is the forward current gain of the bipolar element, which is defined as 10,000 = ic / iB, and its typical value is between tens to hundreds 'This value is related to component type and geometry, and The parameters are related to the operating temperature. Therefore, the correlation between ^ and h will change with the value of / 3. The lower the 10,000 value, the larger the Iβ, so the greater the difference between I! And h. This circuit is referenced by a group Current input (left side of the current mirror) to generate a set of output current output (right side of the current mirror), which consumes a lot of power supply current, so it is not suitable for multiple groups and high current output applications. If the first picture is about the current mirror circuit The ratio of the two sides is not a 丨: 丨 relationship, but a 1: N relationship, the output current will have an amplified effect. The output current 12 and NX 11 have a precise relationship of 12 = I 丨 χ 3 / (ys + 1+ Ν). Therefore, when Ν is close to the point value, the current magnification will apply the paper size to the Chinese National Standard (CNS) A4 specification (210 X 297 mm 556070 A7 ________ ___B7__ V. Description of the invention) ) Will shrink sharply. This factor limits the current amplification ratio of the current mirror circuit. In addition, because Bipolar transistor elements cannot be accurately divided, they can only provide integer magnifications, such as ·· 丨: 5, 2: 3, 1 : 7 and so on, which also limits the current magnification ratio of this type of current mirror circuit. The second picture is a conventional CMOS transistor current mirror circuit, which can be divided into NM0S transistor current mirror circuits (such as the second Figure a) and PM0S transistor current mirror circuit (as shown in the second figure B), its operation principle is exactly the same as Bipolar transistor current mirror circuit. When the NM0S (or PM0S) on both sides of the current mirror is When the size and geometry (L, W) of the crystal elements are completely the same, the gate voltage and source are the same, Vgsi = Vgm, and the gate does not require any input drive current, so the input current h will be equal to the output current h, the only difference is that the output current slope is not zero, but changes slowly with the output voltage Vds2, so when the output voltage Vds2 is not equal to the gate voltage VGS2, the input current 丨 1 and the output current h will be slightly difference. Because the geometry (L, W) of the CMOS element is adjustable, the CMOS transistor current mirror circuit can be easily made into a non-integer ratio current amplification current mirror circuit, and because there is no need to worry about the effect of the gate current on the input current, Amplification of large multiples of current can be easily accomplished, but due to the inherent low current drive capability, low transconductance (gm), withstand voltage, and ESD of the CMOS transistor element, it requires a large output current. In the case of high withstand voltage, the current mirror circuit made of CMOS transistor is often larger than the current mirror circuit made of Bipolar transistor, which increases the cost of the circuit. _____ 4 This paper size applies the Zhongguanjia Standard (CNS) A4 specification (21Q X 297 public love) " ---- ^ ---------------- Order ---- ----- Line " ^^ 丨 (Please read the notes on the back before filling this page) 556070 A7 B7 V. Description of the invention (multiple) The second picture shows the conventional Bipolar transistor current mirror circuit with gain 'The figure is also divided into two types of NPN transistor and PNP transistor. This type of current mirror circuit is coupled with an additional gain transistor to provide the base current required at the output end of the input wheel of the current mirror. The correlation between the input current h and the output current l2 becomes Ιιχ (/ 52 + / 5) / ( Cold 2+ / 3 + 2), regardless of the numerator and denominator, it becomes a square relationship of / 5, so the constant term 2 seems trivial. At this time, the ratio of the input current I i to the output current 12 will become quite accurate, and it is not easy to cross to cold. The effect of change is also not limited to the relationship of 1: 1: 1: The relationship of N can be easily achieved, as long as n is far less than cold 2 (because l2 = IlX (/ 52 + zhao) /// 52 + / 3 + N + 1)). If the additional gain transistor is replaced with a Darlington Pair, the ratio of the input current I! To the output current I? Becomes more accurate, and the amplification ratio N can be larger. (As long as it is far less than 10,000). However, the circuit in the third figure has no problem when applied to some load circuits. However, unexpected problems occur in some applications, such as the application of Open-Collector, when the output is connected to the load and works. It works normally in the forward active region, but when the output is floating or working in the saturation region, a large current will be passed from the power source through the gain transistor Flowing to the output transistor, causing additional power consumption and heating, and all transistors connected to the base will be affected to reduce the current, regardless of whether each transistor is connected to the load and its original working area . The fourth picture shows the conventional Bipola transistor with M0S as the gain transistor. 1 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm).
(請先閱讀背面之注意事項再填寫本頁) -----------------線 556070 A7(Please read the notes on the back before filling this page) ----------------- line 556070 A7
五、發明說明（f ) 體電流鏡電路’第三圖中以NPN < PNP電晶體構成的增益 電曰曰體換成了 NM0S或電晶體，如此的改變將使得電 流鏡兩側電晶體所須的基極電流完全由_s電晶體（pM〇s 電晶體）來提.供’完全不會影響輸人端的電流，因此完全 不受㈣變化的影響，對於製程飄移及X作溫度完全不敏 感，因此只要M0S增益電晶體的電流驅動能力夠大的話， 輸出電流12可無限制的放大。 然而，第w圖的電路設計當然也存在輸出端浮接或是 工作於飽和n (Saturation Region)時所產生的大電源電 流及所有輸出端同時受到單一輸出端不正常工作的影響等 問題。此外由於額外增加了—個增益電晶體，輸入端所須 要的壓降至少要有vBE+ Vbe或是Vbe+ Vgs才能確保工作正常 ，此額外增加的壓降Vb"戈Vcs，而限制了此類電流鏡電路 在低電源電壓時的應用。 第五圖為具開關的習用Bipolar電晶體電流鏡電路， 其中開關電路可由丽os、PM0S或CMOS傳輸閘（Trans— mission Gate)實現。各個傳輸間TG必須完全相同（包含 幾何大小W/L’幾何形狀以及偏麼等等）才能確保電流鏡 正常的功能，其中輸入端的傳輸問TG僅供平衡輸出入端 的負載之用，因此是永遠打開的狀態，每個輸出端都有一 傳輸閘TG來做個別的開關及切換控制，因此可輕易的控 制輸出端電流的開關狀態’如果能預知或偵測輸出端的^ 接與否及工作狀態的話，則可對針對各別的輸出端來做控 制或切換，若是無此類電路的加入的話，其實傳輸問本身 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 556070 A7 Γ —_____Β7 五、發明說明（艾） 的阻抗及壓降亦會降低及限制此類不正常的大電流，因此 也同時降低各個輸出端相互之間的影響與干擾。 若輸出端的放大比例大於1時，則傳輸閘與Bip〇lar 電晶體須以相同的比例放大，例如若電流放大倍數為三倍 的°舌則傳輸閘大小（W/L)放大二倍而Bipolar電晶體也 同時增大二倍（原大小重覆複製三次），如此才能確保在傳 輸閘TG上的壓降Vtg完全相同（NPN電晶體的基極電壓也才 會相同）。 然而此類電流鏡的基極電流IB完全由輸入電流h來提 供，因此電流鏡的功能隨著冷的變化影響很大，若要改善 此問題可採用如第三圖及第四圖所使用的增益電晶體或是 達靈頓對來改善。另外傳輸閘所產生的壓降VTG亦會使得 此類電流鏡電路又需要額外的電壓才可正常工作，因此對 於低工作電壓的應用上更為不利。 第六圖為習知的定電流源電路，其組成包含左側的參 考電流源電路以及右側的電流鏡電路（以虛線隔開），輸出 ^疋電流源數目通常為8 B i t或16 B i ΐ。參考電流源電路 是由能帶間隙（Band—Gap)電壓產生器及PM0S電流鏡所組 成（所有M0S電路皆可由B i po 1 ar相對應的元件所取代）， 因此對於溫度改變所產生的影響相當小，所以其所產生的 參考電流對溫度變化極不敏感，右側的電流鏡電路由於是 採用NPN增益電晶體來提供所有輸出端的基極電流，如此 反而因此造成對溫度及製程的敏感因素，若是將其改成 NM0S增益電晶體或是達靈頓對電路的話，則可降低此不穩 張尺度適用中國國家標準（CNS)A4規格（21G x 297公爱） 一 -- (請先閱讀背面之注意事項再填寫本頁) --------^---------線- 556070 A7 B7 五、發明說明（4 疋的因素。 但第六圖所示的習知定電流源電路在低電源電壓的應 用上疋相當觉限的，例如針對右側電流鏡電路的最低工作 電壓加以分析’此電壓至少要大於VtH· VBEG+ VDSR，這 ；· 3 V以下的工作電壓而言是一大考驗，因此亟須尋 求另種電路實行的方式來解決此問題。另外此電路的輸 出電流亦會隨著輸出電流導通的數目改變而受到些微的影 響，其原因是因為增益電晶體的壓降Vbeg會隨著所須要的 土木電/;IL而改變（若用M0S來做增益電晶體的話，其變化 ^為明顯），因而影響到Vdsr，另外基極電流本身也會消耗 邛伤的參考電流Ir等因素交互作用，這些都會造成輸出電 流隨著輸出端導通的數目增加而降低。 +要根本解決第六圖習知電路所產生的問題須從幾個方 面著手，一方面是要讓Vdsr成為一固定值，即不受輸出電 流導通的數目所影響，一方面則是要降低或消除V咖及^ ’另一方面參考電流不可受到輸出電流導通數目的影響， 即參考電流須與基極電流隔開。 ^故本發明主要目的在提供一種令參考電流源與輸出電 机間可為任何放大比例，且多組電源流同時工作 獨立而不致相互干擾之定電流電路。 、各個 為達成别述目的採取的主要技術手段係令一參考電泣 源與-電流鏡分開，並在其間加入一控制電路，該控制： 路包括-個運算放大器、電晶體及傳輸閘等電路，該 電路利用運算放大器將參考電流源的輸出電壓v⑽與㈣ --------1T---------^· (請先閱讀背面之注意事項再填寫本頁) 556070 A7 ~~ _____E__ —_ 五、發明說明（7) 制電路内部或外部產生參考電壓做比較，進而控制輸入/ 輸出端電晶體的基極電壓（yBER及vBE())及基極電流； 又傳輸閘除了作為電流源的控制開關之外，同時亦可 用以控制甚至消除電流源輸出端開集極（办的一 Col lector)應用時所產生的耗電及干擾問題，故該控制電 路不僅可工作於極低的電源電壓，且亦會大幅降低或消除 傳、”充單個Bipolar或M0S電晶體所產生的額外電壓降， 而參考電流源的輸出電壓yCER亦不受輸出電流的影響，且 運算放大器亦不會影響參考電流源的電流Ir，因而可完全 解決傳統Bipolar電流源電路所產生的問題。 為使貴審查委員進一步瞭解前述目的及本發明之技 術特徵，茲附以圖式詳細說明如后： (一）圖式部分： 第一圖A、B :係習用Bip〇iar電晶體電流鏡電路之電路 圖。 第二圖A、B :係習用CM0S電晶體電流鏡電路之電路圖 第二圖A、B :係習用具增益的Bip〇iar電晶體電流鏡電 路之電路圖。 第四圖A、B :係習用具M0S增益電晶體的Bip〇lar電晶 體電流鏡電路之電路圖。 第五圖·係習用具開關的B i po 1 ar電晶體電流鏡電路之電 路圖。 第六圖：係習用定電流源電路之電路圖。 (請先閱讀背面之注意事項再填寫本頁) -裝--------訂---------線秦 9 556070 A7 '-------21_—__ 五、發明說明（f ) —" 第七圖（A) (B) ·係本發明之電路方塊圖。 第八圖（A)〜（L):係本發明定電流源電路之不同實施例圖 第九圖：係本發明定電流源電路之又一實施例圖。 第十圖：係本發明定電流源電路之再一實施例圖。 第十一圖〜第十六圖：係本發明定電流源電路之其他實施 例圖。 (二）圖號部分： (1 〇 )運算放大器 （2 0 )傳輸閘 第七圖為本發明的方塊圖，包含了電流鏡電路及控制 電路，圖中包含兩種型態的電流源電路，第七圖（A)為流 入型（Sink-Type)電流源電路，第七圖（B)為流出型 (Source-Type)電流源電路，其二者均將傳統電流鏡電路 的輸入（左側參考電流源）及輸出端（電流鏡右侧）分開，並 在中央加入一控制電路，該控制電路不同於以往的電路那 樣直接連接的單一個Bip〇lar電晶體或是M〇s電晶體或者 甚至是達靈頓對（Darlint〇n pair)電路，請參閱第八圖 (A)所示，其包括一個op運算放大器、電晶體及傳輸閘等 電路，該控制電路利用〇p運算放大器將參考電流源的輸 出電壓VcER與該控制電路内部或外部產生參考電壓做比較 ’進而控制輸入/輸出端電晶體的基極電壓（VBER及VBE。）及 基極電流，又傳輸閘除了作為電流源的控制開關之外，同 時亦可用以控制甚至消除電流源輸出端開集極（Qpen 一 Collector)應用時所產生的耗電及干擾問題，故該控制電 _____ 10 本紙張尺度朝巾關家標準(CNS)A4規格（210 X 297公爱1 " (請先閱讀背面之注意事項再填寫本頁) --------tr---------線， 556070 五、發明說明（ 路不僅可工作於極低的電源電壓，而且它也會大幅降低或 消除傳統單一個Bipolar或是M0S電晶體所產生的額外電 壓降’而參考電流源的輸出電壓VcER也不會受到輸出電流 的影響，且0P運算放大器也不會影響參考電流源的電流 h，因此可完全解決傳統Bip〇lar電流源電路所產生的問 題。而輸出端可由一組延伸成N組，所有輸出電流均由一 組共同的參考輸入所產生，故可大幅消除各個輸出電流之 間的誤差，而且輸出的數目可隨應用任意調整。 第八圖（A)至（L)係本發明不同實施態樣的定電流源電 路，其中前述的控制電路已分別由〇p運算放大器（1 〇 )，M0S或Bipolar電晶體及傳輸閘（2 〇 )所取代（其分 別以虛線框區隔控制電路與電流鏡）。其中，運算放大器 (1 〇 )之一輸入端固定連接接於參考電流源的輸出端（ 即NPN電晶體的集極），其另一端點的接線法則有許多的 變化，例如： 第八圖（A)及第八圖（B)所示電路係連接於的源極 (Source)，此一接線方法可讓M〇s的源極（s〇urce)電壓等 於參考電流源的輸出端，其可使電路具有增加一 M〇s電晶 體所產生的優點，又不致產生一額外臨界電壓（Thresh〇id Voltage)降。 第八圖（C)及第八圖（D)所示電路中，運算放大琴（1 〇 )另一端點係連接於一外部的，，固定，，電壓，該電壓可 任忍選定及調整以符合各種電路的需求。當然此電麼不宜 過高或過低，或是容易受到其他因素的影響，否則會大大 本紙張尺㈣財陶家辟（CNS)A4祕⑵G X 297公爱） 556070 A7 五、發明說明（，〇 ) 減低此電路的優點。 第八圖（E)及第八圖（F)所示電路則將運算放大器（丄 0 )接成一正向放大器，並且控制M〇s電晶體，因此參考 電流源的輸出端會比M0S電晶體的源極（s〇UIXe)電壓還要 低，此一正向放大器的放大倍率亦可自由選定，放大倍率 越大則可工作的電壓越低，惟應注意電晶體是否已進入飽 和區及運算放大器（i 〇 )是否仍工作在正常的共模區。 第八圖（G)及第八圖（H)所示電路則是令參考電流源的 電壓4於NPN電晶體的基極（Base)電壓，其令NPN (或 PNP)電晶體的基極（Base)與集極（c〇iiector)產生虛短路 (Virtual Short)的現象，其效果相當於傳統電流鏡電路 直接將NPN電晶體的基極（Base)與集極（c〇llect〇r)連接 在一起。 第八圖（I)及第八圖（J)所示電路則是將第八圖（⑺及 第八圖（H)的電路中的NM0S(或PM〇s)電晶體換成了 NpN(或 PNP)電晶體，事實上，第八圖（A)至八（F)的電路中的 NM0S(或PM0S)均可由NPN(PNP)來取代。 第八圖（K)及第八圖（L)所示電路是將第八圖（A)及第 八圖（B)的電路改成兩個輸出，藉以說明如何將本發明延 伸成多組輸出。 第九圖為本發明定電流源電路之另一實施例，其係將 本發明的電路（第八圖（A))應用於第六圖所示的定電流源 電路中。此一組合可解決圖所示電路所有問題，該電路除 完全消除增益電晶體所須的額外壓降以外（讓壓降僅變為 12 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) -裝--------訂---------線赢 A7 556070 五、發明說明（"） 運算放大器（1 〇 )的輸入抵補電壓，〇ffset v〇ltage) ，也讓VdSR成為一固定值。而且運算放大器（丄〇)本身 不需要輸入偏壓電流，因此也不會影響參考電流IR。運算 放大器（1 0 )和電晶體的大小及電流驅動能力均可單獨 5周整’以因應不同輸出端數目（8 Bit或16 Bit)所需要的 電流’此將簡化不同產品及應用上的電路修正時間。圖中 傳輸閘（2 0 )僅使用NM0S電路來實現，而無須同時使 用PM0S+ NM0S，如此可令電路更為簡化，該NM0S傳輸閘 (2 0 )除做為各個輸出端的開關之外，同時亦可用以限 制輸出端浮接所產生的大電源電流及不同輸出端之間相互 干擾等問題。 當然NM0S傳輸閘（2 0 )亦可由PM0S電晶體來取代 。如第十圖所示，如是的改變將使得輸出端浮接所產生的 大電源電流及不同輸出端相互干擾等問題完全消除。而且 可使得該電路可工作電壓範圍更為寬廣，其原因謹分析如 下： 由第九圖中可發現NM0S傳輸閘（2 0 )之閘極是接 到電源電壓，當電源電壓改變時，NM0S傳輸閘（2 〇 )的 等效阻抗隨之改變，NM0S傳輸閘（2 0 )的壓降yTG也會 不同，而且電源電壓若是降低的話，NM0S傳輸閘（2 〇 ) 的壓降Vtg反而增加，因此造成低電源電壓應用時的不利 因素。然當採用PM0S傳輸閘（2 0 )時，由於pm〇s傳輸 閘（2 0 )的閘極是接到地電位（Ground)，其電壓差不會 隨著電源電壓而改變，因此PM0S傳輸閘（2 〇 )的等效 (請先閱讀背面之注意事項再填寫本頁) -------訂---------線- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 556070 A7 五、發明說明（P) ^ 阻抗不會隨著電壓而改變，PM0S傳輸問（2 〇 )的麼降 Vn;亦為固定值，故可工作的電壓範圍自然可增大。V. Description of the invention (f) Bulk current mirror circuit 'In the third figure, the gain transistor composed of NPN < PNP transistor is replaced by NMOS or transistor. Such a change will make the transistor on both sides of the current mirror The base current of the whisker is completely provided by the _s transistor (pM0s transistor). The supply will not affect the current at the input terminal at all, so it is completely unaffected by changes in ㈣, and it is completely unaffected by process drift and X operating temperature. It is sensitive, so as long as the current driving ability of the M0S gain transistor is large enough, the output current 12 can be amplified without limit. However, of course, the circuit design in Figure w also has problems such as the large power supply current generated when the output terminals are floating or operating in the saturation region (Saturation Region), and all output terminals are affected by the abnormal operation of a single output terminal at the same time. In addition, because an additional gain transistor is added, the voltage drop required at the input must be at least vBE + Vbe or Vbe + Vgs to ensure normal operation. This additional voltage drop Vb " Go Vcs limits the current mirror. Application of the circuit at low supply voltage. The fifth figure is a conventional bipolar transistor current mirror circuit with a switch, wherein the switch circuit can be implemented by a MOS, PMOS, or CMOS Trans-mission Gate. The TG must be exactly the same between each transmission (including the geometric size W / L 'geometry and bias, etc.) to ensure the normal function of the current mirror. The transmission at the input end is only used to balance the load at the input and output ends, so it is always In the open state, each output terminal has a transmission gate TG for individual switching and switching control, so the switching state of the output terminal current can be easily controlled. 'If the output terminal can be predicted or detected ^ connection or working status , You can control or switch for each output terminal. If there is no such circuit, the transmission itself is actually applicable to the Chinese national standard (CNS) A4 specification (210 X 297 mm) 556070 A7 Γ —_____ Β7 5. Invention description (Ai) The impedance and voltage drop will also reduce and limit such abnormal large currents, so it will also reduce the influence and interference between the output terminals. If the magnification ratio of the output terminal is greater than 1, the transmission gate and the Bipolar transistor must be amplified at the same ratio. For example, if the current magnification is three times, the transmission gate size (W / L) is doubled and Bipolar The transistor is also doubled at the same time (the original size is repeated three times), so as to ensure that the voltage drop Vtg on the transmission gate TG is exactly the same (the base voltage of the NPN transistor will also be the same). However, the base current IB of this type of current mirror is completely provided by the input current h. Therefore, the function of the current mirror has a great influence with the change of cold. To improve this problem, you can use the same as the third and fourth figures. Gain transistor or Darlington pair to improve. In addition, the voltage drop VTG generated by the transmission gate will also make this type of current mirror circuit require additional voltage to work properly, so it is more disadvantageous for applications with low operating voltage. The sixth figure is a conventional constant current source circuit. Its composition includes the reference current source circuit on the left and the current mirror circuit on the right (separated by a dashed line). The number of output current sources is usually 8 B it or 16 B i ΐ . The reference current source circuit is composed of a band-gap voltage generator and a PM0S current mirror (all M0S circuits can be replaced by components corresponding to Bi po 1 ar), so the effect on temperature changes It is quite small, so the reference current it generates is extremely insensitive to temperature changes. The current mirror circuit on the right uses NPN gain transistors to provide the base current at all output terminals. This in turn causes sensitivity to temperature and process factors. If it is changed to NM0S gain transistor or Darlington pair circuit, this instability scale can be reduced. Applicable to China National Standard (CNS) A4 specification (21G x 297 public love). I-(Please read the back first Please note this page before filling in this page) -------- ^ --------- line- 556070 A7 B7 V. Description of the invention (4 factors). The constant current source circuit is quite limited in the application of low power supply voltage. For example, the minimum operating voltage of the right current mirror circuit is analyzed. 'This voltage must be at least greater than VtH · VBEG + VDSR, which; · The operating voltage below 3 V and Speak is one The test, therefore, it is urgent to find another way to implement this circuit to solve this problem. In addition, the output current of this circuit will be slightly affected as the number of output current conduction changes. The reason is that the voltage drop of the gain transistor Vbeg It will change with the required civil power / IL (if M0S is used as the gain transistor, the change is obvious), thus affecting Vdsr, and the base current itself will consume the reference current Ir These factors interact with each other, which will cause the output current to decrease as the number of output terminal conduction increases. + To fundamentally solve the problem caused by the conventional circuit of the sixth figure, we must start from several aspects, on the one hand, let Vdsr become a Fixed value, which is not affected by the number of output current conduction, on the one hand, it is necessary to reduce or eliminate Vc and ^ 'On the other hand, the reference current cannot be affected by the number of output current conduction, that is, the reference current must be separated from the base current ^ The main purpose of the present invention is to provide an amplification ratio between the reference current source and the output motor. Constant current circuits that do not interfere with each other. Each of the main technical measures taken to achieve the other purposes is to separate a reference source from the current mirror and add a control circuit in between. The control includes: a calculation Circuits such as amplifiers, transistors, and transmission gates. This circuit uses an op amp to convert the output voltages v⑽ and 参考 of the reference current source -------- 1T --------- ^ · (Please read the back first Please pay attention to this page before filling in this page) 556070 A7 ~~ _____E__ —_ V. Description of the invention (7) The reference voltage generated inside or outside the control circuit is compared for controlling the base voltage of the input / output transistor (yBER and vBE ( )) And the base current; In addition to being used as a control switch for the current source, the transmission gate can also be used to control or even eliminate the power consumption and interference generated when the collector of the current source is turned on (a collector). Problem, so the control circuit can not only work at extremely low power voltage, but also greatly reduce or eliminate the extra voltage drop generated by charging a single Bipolar or M0S transistor, and the output voltage yCER of the reference current source is also Affected output current, and will not affect the operational amplifier reference current Ir a current source, which can completely solve problems of the conventional current source circuit Bipolar generated. In order to make your reviewers better understand the foregoing objectives and the technical features of the present invention, the detailed description is attached as follows: (A) Schematic part: The first picture A, B: is a conventional Bipoiar transistor current mirror circuit Circuit diagram. The second picture A and B are the circuit diagrams of the conventional CM0S transistor current mirror circuit. The second picture A and B are the circuit diagrams of the Bipoiar transistor current mirror circuit of the gain of the custom appliances. The fourth figure A, B: circuit diagram of the Bipolar transistor current mirror circuit of the M0S gain transistor. The fifth figure is the circuit diagram of the Bi po 1 ar transistor current mirror circuit of the switch of the appliance. Figure 6: Circuit diagram of the conventional constant current source circuit. (Please read the precautions on the back before filling this page) -install -------- order --------- line Qin 9 556070 A7 '------- 21 _—__ five Description of the invention (f) — &#; The seventh diagram (A) (B) · is a circuit block diagram of the present invention. Eighth diagrams (A) to (L): diagrams of different embodiments of the constant current source circuit of the present invention. Ninth diagram: diagrams of another embodiment of the constant current source circuit of the present invention. The tenth figure is a diagram of still another embodiment of the constant current source circuit of the present invention. Figures 11 to 16 are diagrams of other embodiments of the constant current source circuit of the present invention. (II) Figure number part: (10) Operational amplifier (20) Transmission gate The seventh figure is a block diagram of the present invention, which includes a current mirror circuit and a control circuit. The figure includes two types of current source circuits. The seventh diagram (A) is a sink-type current source circuit, and the seventh diagram (B) is a source-type current source circuit. Both of them use the input of a conventional current mirror circuit (left reference The current source) and the output (right side of the current mirror) are separated, and a control circuit is added in the center. This control circuit is different from the single circuit directly connected to a single Bip〇lar transistor or M0s transistor or even It is a Darlington pair circuit. Please refer to Figure 8 (A). It includes an op operational amplifier, transistor, and transmission gate. The control circuit uses an op operational amplifier to reference the current. The output voltage VcER of the source is compared with the reference voltage generated internally or externally by the control circuit, and then the base voltage (VBER and VBE.) And base current of the transistor at the input / output side are controlled, and the transmission gate is controlled in addition to the current source. open In addition, it can also be used to control or even eliminate the power consumption and interference problems caused by the application of Qpen-Collector at the output end of the current source. Therefore, the control power _____ ) A4 specification (210 X 297 Public Love 1 " (Please read the precautions on the back before filling this page) -------- tr --------- line, 556070 V. Invention Description (The circuit can not only work at extremely low power supply voltages, but it will also significantly reduce or eliminate the extra voltage drop generated by a traditional single Bipolar or M0S transistor, and the output voltage VcER of the reference current source will not be affected by the output current. , And the 0P op amp will not affect the current h of the reference current source, so it can completely solve the problems caused by the traditional Bipolar current source circuit. The output end can be extended from one group into N groups, and all output currents are determined by It is generated by a common set of reference inputs, so the errors between the output currents can be largely eliminated, and the number of outputs can be arbitrarily adjusted according to the application. The eighth figures (A) to (L) are the determination of different implementation aspects of the present invention. Current source circuit, The aforementioned control circuits have been replaced by 0p operational amplifiers (10), M0S or Bipolar transistors and transmission gates (20) (these control circuits and current mirrors are separated by dashed boxes respectively). Among them, the operational amplifier (1) One input terminal is fixedly connected to the output terminal of the reference current source (that is, the collector of the NPN transistor), and the wiring of the other terminal terminal has many changes, for example: Figure 8 (A) and The circuit shown in Figure 8 (B) is connected to the source. This wiring method can make the source voltage of MOS equal to the output of the reference current source, which can increase the circuit. The advantages of a Mos transistor do not cause an additional threshold voltage drop. In the circuits shown in Figures 8 (C) and 8 (D), the other end of the operational amplifier (10) is connected to an external, fixed, and voltage. This voltage can be selected and adjusted to Meet the needs of various circuits. Of course, this electricity should not be too high or too low, or easily affected by other factors, otherwise it will greatly reduce the size of this paper (CNS) A4 secret G X 297 public love) 556070 A7 5. Description of the invention (, 〇) Reduce the advantages of this circuit. The circuits shown in Figures 8 (E) and 8 (F) connect the operational amplifier (丄 0) as a forward amplifier and control the Mos transistor, so the output of the reference current source will be better than the M0S transistor. The source (sUIXe) voltage is even lower. The amplification factor of this forward amplifier can also be selected freely. The larger the amplification factor, the lower the operating voltage. However, it should be noted whether the transistor has entered the saturation region and the calculation. Whether the amplifier (i) is still operating in the normal common mode region. The circuits shown in Figure 8 (G) and Figure 8 (H) are to make the voltage of the reference current source 4 to the base voltage of the NPN transistor, which makes the base of the NPN (or PNP) transistor ( Base) and the collector (coiector) produce a virtual short (Virtual Short) phenomenon, the effect is equivalent to the traditional current mirror circuit directly connects the base (Base) of the NPN transistor and the collector (collect〇r) Together. The circuits shown in Figure 8 (I) and Figure 8 (J) are replaced by NpS (or PM0s) transistors in the circuits of Figure 8 (⑺ and Figure 8 (H) with NpN (or PNP) transistors, in fact, the NMOS (or PM0S) in the circuits of the eighth (A) to eight (F) can be replaced by NPN (PNP). The eighth (K) and eighth (L) The circuit shown is to change the circuit of the eighth figure (A) and the eighth figure (B) into two outputs, so as to explain how to extend the invention into multiple sets of outputs. The ninth figure is another of the constant current source circuit of the invention An embodiment is to apply the circuit of the present invention (eighth figure (A)) to the constant current source circuit shown in the sixth figure. This combination can solve all the problems of the circuit shown in the figure, except that the circuit is completely eliminated In addition to the extra voltage drop required for the gain transistor (let the pressure drop only be 12) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page ) -Install -------- order --------- line win A7 556070 V. Description of the invention (") Input offset voltage of the operational amplifier (10), ffset v〇ltage) And also let V dSR becomes a fixed value. Moreover, the operational amplifier (丄 〇) itself does not need to input a bias current, so it does not affect the reference current IR. The size of the operational amplifier (1 0) and the transistor and the current driving capability can be 5 weeks independently. It adjusts the current required by the number of different output terminals (8 Bit or 16 Bit). This will simplify the circuit correction time on different products and applications. The transmission gate (20) in the figure is only implemented by the NM0S circuit, without the need At the same time, PM0S + NM0S is used, which can simplify the circuit. In addition to serving as a switch for each output terminal, the NM0S transmission gate (20) can also be used to limit the large power supply current and different output terminals generated by floating output terminals. Problems such as mutual interference between them. Of course, the NM0S transmission gate (20) can also be replaced by a PM0S transistor. As shown in the tenth figure, if the change is made, the large power supply current generated by the output terminals floating and the different output terminals are mutually The interference and other problems are completely eliminated, and the circuit can be operated with a wider range of voltages. The reasons are as follows: From the ninth figure, the gate of the NM0S transmission gate (2 0) can be found. It is connected to the power supply voltage. When the power supply voltage changes, the equivalent impedance of the NM0S transmission gate (20) changes accordingly. The voltage drop yTG of the NM0S transmission gate (2 0) will also be different, and if the power supply voltage decreases, NM0S The voltage drop Vtg of the transmission gate (20) increases instead, thus causing disadvantages in the application of low power supply voltage. However, when the PM0S transmission gate (20) is used, the gate of the pm0s transmission gate (20) is Connected to the ground (Ground), the voltage difference will not change with the power supply voltage, so the PM0S transmission gate (20) is equivalent (please read the precautions on the back before filling this page) ------ -Order --------- Line- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 556070 A7 V. Description of the invention (P) ^ Impedance does not change with voltage The PM0S transmission asks (2) for the drop Vn; it is also a fixed value, so the working voltage range can naturally be increased.
第十一圖至第十六圖為本發明定電流源電路的其他實 施例，其係分別將第八圖（〇、第八圖（£)及第八圖'((?)應 用纟帛六圖的定電流源祕中。帛十一圖及第十二圖是採 用第八圖（C)所示發明，其係將運算放大器（丄〇 )的一 輸入端接到參考電壓源，若採用能帶間隙參考電壓源 (Band-Gap Voltage Reference)，則該點電壓約為 125V 左右而且溫度係數極低，如此接法可讓Vdsr更臻固定，完 全不文溫度、輸入參考電流及輸出端導通數目的影響。 第十三圖及第十四圖是採用第八圖（幻所示發明，只 要運算放大器（1 〇 )及NPN電晶體能保持在正常的工作 區域内，正向放大的倍率可隨意調整。第十五圖及第十六 圖是採用第八圖（G)所示發明，係將NPN電晶體集極及基 極端虛短路，此端點電壓通常只有0·7ν左右，因此可工 作的電源電壓範圍最大，但須注意運算放大器的共模區 (Common Mode Range)是否仍然正常。 i 由上述說明可看出本發明不同實施例之電路構造及其 工作原理，其主要係經由控制電路之控制，使其不僅可工 作於極低的電源電壓，同時可大幅降低或消除習用定電流 源電源中單一 Bipolar或M0S電晶體所產生的額外電壓降 | 問通’又參考電流源的輸出電壓yCER不受輸出電流的影響 ，且運算放大器亦不會影響參考電流源的電流，因而可完 全解決習用電流源電路所產生的問題；故以前述設計已具 _ _ 14 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱) -- --------IT---------線- (請先閱讀背面之注意事項再填寫本頁) A7 556070 _ B7 五、發明說明（Λ3 ) 備顯著的實用性、新穎性與進步性，並符合發明專利要件 ，爰依法提起申請。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------------------訂---------i^w— (請先閱讀背面之注意事項再填寫本頁)The eleventh to the sixteenth diagrams are other embodiments of the constant current source circuit of the present invention. They are the eighth diagram (0, the eighth diagram (£), and the eighth diagram '((?) Applied to 26). The constant current source in the figure is shown in Figure 11. Figure 11 and Figure 12 adopt the invention shown in Figure 8 (C), which connects an input terminal of the operational amplifier (丄 〇) to a reference voltage source. Band-Gap Voltage Reference, then the voltage at this point is about 125V and the temperature coefficient is very low. This connection can make Vdsr more fixed, completely unknown temperature, input reference current and output terminal conduction The thirteenth and fourteenth diagrams are the eighth (the invention shown in the magic picture), as long as the operational amplifier (10) and the NPN transistor can be maintained in the normal working area, the positive magnification can be Adjust at will. Figures 15 and 16 adopt the invention shown in Figure 8 (G), which virtually short-circuits the NPN transistor collector and base extremes. This terminal voltage is usually only about 0 · 7ν, so it can be adjusted. The operating power supply voltage range is the largest. Whether the Common Mode Range is still normal. From the above description, we can see the circuit structure and working principle of different embodiments of the present invention, which are mainly controlled by the control circuit, so that it can not only work at extremely low power supply voltages. At the same time, it can greatly reduce or eliminate the extra voltage drop generated by a single Bipolar or M0S transistor in the conventional constant current source power supply. Ask about the output voltage yCER of the reference current source is not affected by the output current, and the operational amplifier will not Affects the current of the reference current source, so it can completely solve the problems caused by the conventional current source circuit; therefore, the aforementioned design already has _ _ 14 This paper size applies to the Chinese National Standard (CNS) A4 specification (21〇X 297 public love)- --------- IT --------- Line- (Please read the precautions on the back before filling out this page) A7 556070 _ B7 V. Description of the invention (Λ3) has outstanding practicality , Novelty and progress, and meet the requirements of the invention patent, and filed an application in accordance with the law. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------- ------- Order --------- i ^ w— (Please read first Note to fill out the back of this page)