JP4751295B2 - Digital protection control device - Google Patents

Description

  The present invention relates to a digital protection control device for protecting a power system.

  The digital type protection control device that protects the power system inputs the amount of electricity and state of the power system, converts it into a digital amount, performs a predetermined protection control calculation using this digital amount, and according to this calculation result By controlling the circuit breaker and the like, protection control of the power system is performed.

  In general, an automatic monitoring function is incorporated in a digital protection control apparatus. This automatic monitoring function monitors the state of the apparatus so that the protection control function of the system, which is the responsibility of the digital protection control apparatus, operates normally, and outputs an alarm if there is an abnormality. Since this automatic monitoring function is well known (for example, Non-Patent Document 1), detailed description thereof is omitted.

  By the way, in the conventional digital protection control device, when a failure of the protection control function is detected by the automatic monitoring function, the time is added to the monitoring failure information detected by the automatic monitoring function in order to clarify the monitoring failure occurrence time. There is a configuration in which the information is stored in a non-volatile memory or a backup memory, and then the stored information can be read by a display operation means or an analysis tool by an operator (for example, Patent Document 1).

  In addition, when these protection control systems are large in scale or when a protection control calculation with a large amount of processing is performed, a plurality of calculation processing boards are used, each of which processes the protection control function and the monitoring failure detection means separately. (For example, Patent Document 2).

  FIG. 7 is a block diagram showing an example of a digital protection control device that constitutes a general multi-CPU. The digital protection control device 1 naturally has a protection control function unit (not shown), but the description thereof is omitted here.

  In FIG. 7, the protection control device 1 inputs an electric quantity of a power system and converts it into an analog-digital converter (A / D) 2 that converts it into a digital quantity, and an input circuit (ON / OFF information for power equipment) ( DI) 3, an output circuit (DO) 4 for outputting protection control calculation results to an external device, and a plurality of calculation processing boards 5-1 to 5-n. Includes monitoring failure detection means 7-1 to 7-n for detecting failures of a plurality of various monitoring targets 6-1 to 6-n inside and outside the protection control device, and these arithmetic processing boards 5-1 to 5-n. They are connected by a system bus 8 that exchanges data.

  At least one of the arithmetic processing boards 5-1 to 5-n, here, the current time acquisition means 9 using a clock IC circuit or the like for the arithmetic processing board 5-n, and the arithmetic processing boards 6-1 to 6-1. 6-n, the failure information collection means 10 that collects the monitoring failure information detected by the monitoring failure detection means 7-1 to 7-n using the system bus 8, and the current time acquisition means 9 in the collected monitoring failure information. The time adding means 11 for adding the current time given from the above and the defect information recording means 12 for recording the defect information to which the time is added in a nonvolatile memory or a backup memory are provided, and the defect recorded in the defect information recording means 12 is provided. Is generated and displayed on the external display means 13.

In this case, the display means 13 may be realized by attaching a display device to the protection control device, or may be realized by connecting a personal computer to the protection control device via RS232C or Ethernet (registered trademark).
Japanese Patent Application Laid-Open No. 09-056051 Japanese Patent Laid-Open No. 08-163766 January 1986 Issued by Electric Cooperative Research Association "Electric Cooperative Research" Vol. 41 No. 4 Chapter 5 (Page 59)

  Incidentally, in the protection control device as described above, typical monitoring targets inside and outside the protection control device detected by the monitoring failure detection means 7-1 to 7-n include items as shown in FIG. .

  As shown in FIG. 8, analog / digital converter (A / D) accuracy monitoring, instrument transformer (PT) monitoring, instrument current transformer (CT) monitoring, RAM monitoring, ROM monitoring, output circuit Monitoring.

  In order to prevent erroneous detection due to noise, each monitoring item is provided with a confirmation timer for the purpose of confirming that a defect has occurred for a predetermined time, as shown in FIG. Here, it is assumed that the time limit Tad of the “A / D accuracy monitoring” confirmation timer and the time limit Tot of the “output circuit monitoring” confirmation timer are in a relationship of Tad <Tot.

  Moreover, the example of a display of the monitoring result by a monitoring item is shown in FIG. After confirming the monitoring results, the operator identified and replaced the defective part.

  In the digital type protection control device configured by the multi-CPU described above, except for the monitoring items such as “RAM monitoring” and “ROM monitoring”, which are not monitored items for monitoring defects in each processing board, Share and configure. An example of this is shown in FIG.

In the case of such a configuration, when “RAM failure” is displayed due to a simple failure, for example, a failure of the RAM, the operator can specify that the detected RAM of the arithmetic processing board is defective and can be replaced. However, when a complicated failure aspect, for example, an A / D converter becomes defective, an “A / D accuracy monitoring” failure is detected, but an analog input becomes invalid and the relay malfunctions to detect an “output circuit monitoring” failure . There is a possibility, and in such a case, it is difficult to specify a defective part, but it is possible to estimate a defective part from the time relationship of the occurrence of the defect as follows.

  For example, when an A / D converter failure occurs, if an “output circuit monitoring” failure is detected after detecting an “A / D accuracy monitoring” failure from the relationship of the confirmation timer, the “output circuit monitoring” failure is When it is determined that the fault has occurred due to a fault in the A / D converter and an "A / D accuracy monitoring" fault is detected after detecting an "output circuit monitoring" fault, not only in the A / D converter but also in the output circuit It can be identified that some defect has occurred.

  However, in the arithmetic processing board 5-n for display operation, the failure information collecting means 10 that collects data of other arithmetic processing boards shows the failure state of each arithmetic processing board and the display operation arithmetic board in FIG. Thus, for example, at the timing shown in FIG. 13, a defect 1 occurs in the arithmetic processing board 5-1, after the processing of the arithmetic processing board 5-1, for example, and then the arithmetic processing board 5-2. When the defect 2 occurs, the current processing time is stored in the defect 2 by reading the arithmetic processing board 5-2, and then the current time is stored in the defect 1 by the reading process in the arithmetic processing board 5-1. The collection of defect information is not necessarily in the order in which defects occur, and an accurate defect occurrence time cannot be added, so the time relationship of defect occurrence cannot be accurately grasped. For this reason, there is a problem that it becomes difficult to identify the cause of the defect.

  The present invention has been made to solve the above-described problem, and even when a plurality of arithmetic processing units detect a plurality of defects at the same time, the time relationship of the occurrence of the defect is accurately grasped, and the occurrence of the defect. It is an object of the present invention to provide a digital protection control device having a multi-CPU configuration capable of accurately specifying the state.

In order to achieve the above object, the present invention provides a digital protection control device comprising a plurality of arithmetic processing units that divide and process protection control of an electric power system. A monitoring failure detection means for detecting the time, a clock means, and a current time adding means for adding the current time by the clock means to the monitoring failure information detected by the monitoring failure detection means, and at least a plurality of the arithmetic processing units and defect information collecting means for collecting the failure information obtained by adding time at time adding means of each processing unit using the system bus to one record for defect information recorded more collected defect information in the defect information acquisition means Means , recording means for recording the monitoring failure information added by the respective arithmetic processing units, and reading of failure information for reading the monitoring failure information recorded by the recording means Providing means .
Further, in order to achieve the above object, the present invention provides a digital protection control device including a plurality of arithmetic processing units that divide and process protection control of an electric power system. A plurality of arithmetic processing units, including a monitoring failure detecting means for detecting a failure of the clock, a clock means, and a current time adding means for adding the current time by the clock means to the monitoring failure information detected by the monitoring failure detection means. Defect information collecting means for collecting defect information to which time is added by time adding means of each arithmetic processing unit using at least one of the system bus, and defect information for recording defect information collected by the defect information collecting means A recording means and a time synchronization means for synchronizing with the time of the clock means are provided, and an arithmetic processing unit as a time reference is assigned from among the arithmetic processing units, and the operation of the time reference is performed. The time obtained from the clock means of the other arithmetic processing section is synchronized with the time obtained from the clock means of the arithmetic processing section.

According to the present invention, in case plural arithmetic processing unit detects a plurality of defective similar time, and even if such a failure occurs can not collect fault conditions, accurate time relationship failure It is possible to accurately grasp the occurrence state of defects.
Further, according to the present invention, it is possible to prevent a time lag due to an error of each clock circuit in a plurality of arithmetic processing boards, and synchronization of time information at the time of occurrence of failure stored together with failure data at the time of occurrence of failure makes each arithmetic processing. Since it can be taken between the substrates, it becomes possible to grasp a plurality of defects occurring on different arithmetic processing substrates in a time series, and it is possible to easily determine a temporal relationship between a plurality of events that have occurred.

(First embodiment)
Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a first embodiment of a digital protection control apparatus according to the present invention. The same parts as those in FIG. Although the protection control function unit is naturally included, since it is not directly related to the present invention, description and explanation thereof are omitted.

  In FIG. 1, a protection control device 1 receives an electric quantity of an electric power system, an analog / digital converter (A / D) 2 for converting the electric quantity into a digital quantity, and an input circuit for inputting ON / OFF information of electric power equipment ( DI) 3, an output circuit (DO) 4 for outputting protection control calculation results to an external device, and a plurality of calculation processing boards 5-1 to 5-n. Includes monitoring failure detection means 7-1 to 7-n for detecting failures of a plurality of various monitoring targets 6-1 to 6-n inside and outside the protection control device, and these arithmetic processing boards 5-1 to 5-n. They are connected by a system bus 8 that exchanges data.

  Each arithmetic processing board 5-1 to 5-n is provided with current time acquisition means 9-1 to 9-n and time addition means 11-1 to 11-n using a clock IC circuit or the like, Obtained by the current time acquisition means 9-1 to 9-n into the monitoring failure information detected by the monitoring failure detection means 7-1 to 7-n by the time addition means 11-1 to 11-n in each arithmetic processing board. The current time is given. In this case, the time of the clock IC circuit is set in advance by the operator for each board individually or collectively.

  Further, at least one of the arithmetic processing boards 5-1 to 5-n, here, the arithmetic processing board 5-n is connected to the time adding means 11-1 to 11-n of each arithmetic processing board using a system bus. The defect information collecting means 10 for collecting the defect information to which the time is added and the defect information recording means 12 for recording the collected defect information in a nonvolatile memory or a backup memory are provided, and the defect recorded in the defect information recording means 12 is provided. Is generated and displayed on the external display means 13.

  In this case, the display means 13 may be realized by attaching a display device to the protection control device, or may be realized by connecting a personal computer to the protection control device via RS232C or Ethernet.

  With the digital protection control device having such a configuration, the current time is obtained from the failure information detected by the monitoring failure detection means 7-1 to 7-n provided on the respective arithmetic processing boards 5-1 to 5-n. Since the time of failure occurrence given by the means 9-1 to 9-n is added by the time adding means 11-1 to 11-n, for example, the reading processing of the arithmetic processing board 5-1 is performed at the timing shown in FIG. Even if the defect 1 occurs later on the arithmetic processing board 5-1, and then the defect 2 occurs on the arithmetic processing board 5-2, the defect information is collected by the defect information collecting means 10 in the arithmetic processing board 5-n. Regardless of the timing, it is possible to time the defect information in the order in which defects occurred.

  Therefore, in the multi-CPU digital protection control device, even when a plurality of substrates detect a plurality of defects at the same time, it is possible to accurately grasp the time relationship of the occurrence of the defect, Analysis becomes easy.

(Second Embodiment)
FIG. 3 is a block diagram showing a second embodiment of the digital protection control apparatus according to the present invention. The same parts as those in FIG. To do.

  In the second embodiment, as shown in FIG. 3, a non-volatile memory or the like that records the failure information with the time added by the time adding means 11-1 to 11-n on each of the arithmetic processing boards 5-1 to 5-n. And a personal computer in which defect information stored in the recording means 12-1 to 12-n of each arithmetic processing board 5-1 to 5-n is connected to the outside by RS232C or the like. 14 to which defect information reading means 15-1 to 15-n to be read are added.

  In the digital protection control device having such a configuration, since the failure information with the time added is stored in the recording means 12-1 to 12-n of each arithmetic processing board, a personal computer or the like is connected to the board. As a result, it is possible to read out defective data.

  Therefore, in addition to obtaining the same operational effects as those of the first embodiment, even when a failure occurs in the system bus 8 and a failure in a mode in which a failure state cannot be collected occurs, a failure by the operator Information can be read out, the time-causal relationship of occurrence of defects can be accurately grasped, and the state of occurrence of defects can be accurately identified.

(Third embodiment)
FIG. 4 is a block diagram showing a third embodiment of the digital protection control apparatus according to the present invention. The same parts as those in FIG. 1 or FIG. The part will be described.

  In the third embodiment, as shown in FIG. 4, among the plurality of arithmetic processing boards 5-1 to 5-n mounted on the protection control device 1, an arithmetic processing board as a time reference is assigned. A time reference is assigned to the board 5-n, and each of the arithmetic processing boards 5-1 to 5-n is provided with a time synchronization means 16 for synchronizing the time of a clock circuit between the arithmetic boards.

  In the arithmetic processing boards 5-1 to 5-n, the monitoring failure detecting means 7-1 to 7-n, the time adding means 11-1 to 11-n, and the arithmetic processing board 5-n shown in FIGS. In FIG. 2, the constituent elements such as the defect information collecting means 10 and the recording means 12 are omitted for the sake of simplicity of illustration and description.

  Here, the configuration of the time synchronization means 16 of the arithmetic processing board 5-n as the time reference is the current date (year / month) acquired from the current time acquisition means 9-n at a preset time (hour / minute / second). The correction time output means 16a for outputting the correction time to which (day) is added, the correction time output by the correction time output means 16a and the current time of the current time acquisition means 9-n are compared, and a correction trigger is output when they match. And the time synchronization means 16 of the arithmetic processing boards 5-1 to 5- (n-1) includes a corrected time output means 16a of the time synchronization means 16 of the arithmetic processing board 5-n. The correction time input means 16c for inputting the correction time output from the input terminal and the correction trigger output from the trigger output means 16b of the time synchronization means 16 of the arithmetic processing board 5-n are input to detect the timing of time correction. And a trigger detection unit 16d for.

  FIG. 5 is a diagram showing a data flow from the time-based computation processing board 5-n to each of the computation processing boards 5-1 to 5- (n-1), and FIG. 6 is a flowchart showing time correction processing. is there.

  Here, the timing and cycle for performing the time correction are performed at an arbitrary timing and cycle set in advance. The trigger detection means 16d sets the time of the clock circuit to the time input by the correction time input means at the timing when the trigger output by the trigger output means 16b is detected.

  According to the digital protection control device having such a configuration, time-based operation processing boards (time reference units) 5-n are allocated and time synchronization is performed on the operation processing boards 5-1 to 5-n (each unit). Means 16 is provided to compare the correction time output by the correction time output means 16a from the time base unit to another unit and the current time of the current time acquisition means 9-n, and when they match, the trigger output means 16b generates a correction trigger. Since the time of the clock circuit is set to the time inputted by the correction time input means 16c at the timing when the trigger is detected by the trigger detection means 16d by the time synchronization means 16 of the other unit, the arithmetic processing board 5 The error of the clock circuit can be corrected every −1 to 5-n.

  Therefore, in addition to obtaining the same operational effects as those of the first or second embodiment, it is possible to prevent a time shift due to an error of each clock circuit in the plurality of arithmetic processing boards mounted on the protection control device. The time information at the time of failure that is saved with the failure data can be synchronized between each processing board when a failure occurs, so it is possible to grasp multiple faults that occurred on different processing boards in a time series. It is possible to easily determine the temporal relationship between the events that have occurred.

  In addition, you may allocate to the arithmetic processing board used as a time reference to another arithmetic processing board.

1 is a system configuration diagram showing a first embodiment of a digital protection control apparatus according to the present invention. FIG. The figure which shows the flow from the defect generation | occurrence | production to preservation | save in the embodiment. The system block diagram which shows 2nd Embodiment of the digital type protection control apparatus by this invention. The system block diagram which shows 3rd Embodiment of the digital type protection control apparatus by this invention. The figure which shows the flow of the data in the embodiment. The flowchart which shows the time correction process of the embodiment. The system block diagram which shows the conventional digital type | mold protection control apparatus. The figure which shows the typical monitoring item currently performed with a digital relay. The figure which shows the confirmation process in a monitoring item. The figure which shows the example of a display of a monitoring result. The figure which shows the sharing example of the monitoring item in a multi CPU structure. The flowchart which shows defect information collection processing. The figure which shows the flow from the conventional defect generation to preservation | save.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Protection control apparatus, 2 ... Analog-digital converter (A / D), 3 ... Input circuit (DI), 4 ... Output circuit (DO), 5-1 to 5-n ... Arithmetic processing board, 6-1 6-n: various monitoring targets, 7-1 to 7-n: monitoring failure detection means, 8: system bus, 9, 9-1 to 9-n: current time acquisition means, 10 ... failure information collection means, 11, 11-1 to 11-n ... current time adding means 12, 12-1 to 12-n ... recording means, 13 ... display means, 14 ... externally connected personal computer, 15-1 to 15-n ... failure information reading hand Stage 16 ... Time synchronization means 16a ... Correction time output means 16b ... Trigger output means 16c ... Correction time input means 16d ... Trigger detection means

Claims (2)

In the digital type protection control device composed of a plurality of arithmetic processing units that divide and process the protection control of the power system,
Each arithmetic processing unit includes monitoring failure detection means for detecting failures of various monitoring targets, clock means, and current time adding means for adding the current time by the clock means to monitoring failure information detected by the monitoring failure detection means And a defect information collecting means for collecting defect information in which time is added by a time adding means of each arithmetic processing unit using a system bus for at least one of the plurality of arithmetic processing units, and the defect information collecting means more and defect information recording means for recording the collected defect information, recording means for recording the monitoring defect information time added by the arithmetic processing unit, the defect information reading for reading the monitor defect information recorded by the recording means digital protective control apparatus characterized in that a means. In the digital type protection control device composed of a plurality of arithmetic processing units that divide and process the protection control of the power system,
Each arithmetic processing unit includes monitoring failure detection means for detecting failures of various monitoring targets, clock means, and current time adding means for adding the current time by the clock means to monitoring failure information detected by the monitoring failure detection means And a defect information collecting means for collecting defect information in which time is added by a time adding means of each arithmetic processing unit using a system bus for at least one of the plurality of arithmetic processing units, and the defect information collecting means A defect information recording means for recording the defect information collected by the above and a time synchronization means for synchronizing with the time of the clock means, and assigning an arithmetic processing section as a time reference from these arithmetic processing sections. A digital protection control device for synchronizing a time obtained from the clock means of another arithmetic processing section with a time obtained from the clock means of the arithmetic processing section. Place.

Images